Semiconductor memory device and method for manufacturing a semiconductor memory device

Abstract

To provide a semiconductor memory device that can improve operational reliability. [Solution] According to one embodiment, in a semiconductor memory device, the charge storage film has a plurality of first protrusions and a plurality of second protrusions. The plurality of first protrusions are arranged in a first region between a plurality of first conductive layers and a semiconductor film and are continuous with each other in the stacking direction. Each of the plurality of first protrusions projects toward the first conductive layer at a stacking position corresponding to the first conductive layer. The plurality of second protrusions are arranged in a second region between a plurality of second conductive layers and a semiconductor film and are separated from each other in the stacking direction. Each of the plurality of second protrusions projects toward the second conductive layer at a stacking position corresponding to the second conductive layer. The thickness of the first insulating layer is greater than the thickness of the second insulating layer.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device and a method for manufacturing a semiconductor memory device.

Background Art

[0002] There is known a three-dimensional semiconductor memory device in which a semiconductor film extends in the stacking direction within a stack body in which a plurality of conductive layers are stacked via insulating layers, and a portion where each conductive layer and the semiconductor film are in proximity functions as a memory cell. In this semiconductor memory device, it is desired to improve the operational reliability.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment aims to provide a semiconductor memory device capable of improving operational reliability and a method for manufacturing a semiconductor memory device.

Means for Solving the Problems

[0005] According to one embodiment, a semiconductor memory device is provided having a laminate, a semiconductor film, an insulating film, and a charge storage film. The laminate has a first region and a second region. The second region is located above the first region in the stacking direction. In the first region, a plurality of first conductive layers are stacked via a first insulating layer. In the second region, a plurality of second conductive layers are stacked via a second insulating layer. The semiconductor film extends in the stacking direction through the first and second regions. The charge storage film has a plurality of first protrusions and a plurality of second protrusions. The plurality of first protrusions are arranged in the first region between a plurality of first conductive layers and the semiconductor film and are continuous with each other in the stacking direction. Each of the plurality of first protrusions projects toward the first conductive layer at a stacking position corresponding to the first conductive layer. Multiple second protrusions are positioned in the second region between multiple second conductive layers and the semiconductor film, and are separated from each other in the stacking direction. Each of the multiple second protrusions projects toward the second conductive layer at the stacking position corresponding to the second conductive layer. The thickness of the first insulating layer is greater than the thickness of the second insulating layer. [Brief explanation of the drawing]

[0006] [Figure 1] A perspective view showing the overall configuration of a semiconductor memory device according to an embodiment. [Figure 2] A block diagram showing the overview configuration of a semiconductor memory device according to an embodiment. [Figure 3] A circuit diagram showing the configuration of a memory cell array in an embodiment. [Figure 4] A cross-sectional view showing the configuration of the memory cell array in the embodiment. [Figure 5] A plan view showing the configuration of the memory cell in the embodiment. [Figure 6] An enlarged cross-sectional view showing the configuration near the memory cell in the embodiment. [Figure 7] A cross-sectional view showing the configuration of a memory cell array in a first modified example of the embodiment. [Figure 8] An enlarged cross-sectional view showing the configuration near the memory cell in a first modified example of the embodiment. [Figure 9]A cross-sectional view showing a method for manufacturing a semiconductor memory device according to a second modified example of the embodiment. [Figure 10] A cross-sectional view showing a method for manufacturing a semiconductor memory device according to a second modified example of the embodiment. [Figure 11] A cross-sectional view showing a method for manufacturing a semiconductor memory device according to a second modified example of the embodiment. [Figure 12] A cross-sectional view showing a method for manufacturing a semiconductor memory device according to a second modified example of the embodiment. [Figure 13] A cross-sectional view showing a method for manufacturing a semiconductor memory device according to a second modified example of the embodiment. [Modes for carrying out the invention]

[0007] The semiconductor memory device according to the embodiment will be described in detail below with reference to the attached drawings. However, the present invention is not limited to these embodiments.

[0008] (Embodiment) The semiconductor memory device according to this embodiment has a three-dimensional structure in which a semiconductor film extends in the stacking direction within a stack in which multiple conductive layers are stacked with an insulating layer in between, and the portions in close proximity between each conductive layer and the semiconductor film function as memory cells. However, measures are taken to improve its operational reliability.

[0009] The semiconductor memory device 1 may be configured as shown in Figure 1. Figure 1 is a schematic perspective view showing the configuration of a memory cell array 2 included in the semiconductor memory device 1 according to an embodiment. The semiconductor memory device 1 is a NAND-type non-volatile memory including three-dimensionally arranged memory cells. Hereinafter, the direction perpendicular to the surface of the substrate SUB will be defined as the Z direction, and the two mutually orthogonal directions in the plane perpendicular to the Z direction will be defined as the X direction and the Y direction.

[0010] As shown in FIG. 1, the semiconductor memory device 1 includes a source line SL, a select gate SGS, a word line WL, and a select gate SGD. The source line SL is laminated on the +Z side of the substrate SUB via an insulating layer 7 with an interlayer insulating film 81 interposed therebetween. The select gate SGS is laminated on the source line SL via the insulating layer 7. In the example of FIG. 1, three layers of select gates SGS are provided. The word line WL is laminated on the uppermost select gate SGS via the insulating layer 7. In the example of FIG. 1, a plurality of layers of word lines WL are provided. The select gate SGD is laminated on the uppermost word line WL via the insulating layer 7. In the example of FIG. 1, three layers of select gates SGD are provided. The select gate SGD means a plurality of select gates included and divided in the same layer. In the example of FIG. 1, select gates SGD0 and SGD1 divided in the Y direction are shown. The select gate SGD is laminated on the uppermost word line WL via the insulating layer 7. The source line SL, the select gate SGS, the word line WL, and the select gate SGD are each plate-shaped and extend in the X direction and the Y direction.

[0011] In the example of FIG. 1, the select gate SGD, the word line WL, and the select gate SGS are divided and insulated in the Y direction by a slit ST. The slit ST is provided in the substrate SUB and extends in the X direction and the Z direction.

[0012] The select gate SGD is, for example, divided in the Y direction by an insulating film SHE. The insulating film SHE is provided above (+Z side) the word line WL and extends in the X direction and the Z direction. For this reason, the select gate SGD0 and the select gate SGD1 are arranged side by side in the Y direction on the word line WL. In the example of FIG. 1, three layers of select gates SGD0 and SGD1 are provided respectively.

[0013] The substrate SUB can be formed of a material mainly composed of a semiconductor such as silicon. The select gate SGS, the word line WL, and the select gate SGD can each be formed of a material mainly composed of a metal such as tungsten (W). The interlayer insulating film 7 and the insulating film SHE can each be formed of an insulator such as silicon oxide.

[0014] The semiconductor memory device 1 further includes a plurality of columnar bodies 4. The columnar bodies 4 penetrate through the select gate SGS, the word line WL, and the select gate SGD, and extend in the Z direction, which is the stacking direction thereof. The semiconductor memory device 1 further includes a plurality of bit lines BL provided above the select gate SGD.

[0015] The columnar bodies 4 are each electrically connected to the bit line BL via a contact plug BC. The contact plug BC is a contact plug for the bit line BL. In FIG. 1, a configuration is illustrated in which one of the columnar bodies 4 sharing the select gate SGD0 and one of the columnar bodies 4 sharing the select gate SGD1 are electrically connected to one bit line BL via the contact plug BC.

[0016] In the case of a semiconductor memory device (memory) having a three-dimensional structure such as the semiconductor memory device 1, a portion where the word line WL and the columnar body 4 intersect is configured to function as a memory cell, and a memory cell array 2 in which a plurality of memory cells are three-dimensionally arranged is configured. Also, a portion where the select gate SGS and the columnar body 4 intersect functions as a select gate on the source side, and portions where the select gates SGD0 and SGD1 and the columnar body 4 intersect serve as select gates on the drain side. In the semiconductor memory device 1, by increasing the number of stacked word lines WL in the stacked body, it is possible to increase the memory capacity without using a finer patterning technique.

[0017] Note that in FIG. 1, for simplicity of illustration, the interlayer insulating film provided between the select gate SGD and the bit line BL is omitted. Also, in FIG. 如何翻译“如何翻译”?1, a configuration is illustrated in which the substrate SUB is arranged on the opposite side of the bit line BL with respect to the memory cell array 2, but a configuration in which the substrate SUB is arranged on the opposite side of the memory cell array 2 with respect to the bit line BL may also be used.

[0018] FIG. 2 is a block diagram showing the configuration of the semiconductor memory device 1.

[0019] As shown in Figure 2, the semiconductor memory device 1 has a memory cell array 2, peripheral circuits 10, and an interface 20. The peripheral circuits 10 include a WL drive circuit 11, an SGS drive circuit 12, an SGD drive circuit 13, an SL drive circuit 14, and a sense amplifier circuit 15.

[0020] The WL drive circuit 11 controls the voltage applied to the word line WL, and the SGS drive circuit 12 controls the voltage applied to the selection gate SGS. The SGD drive circuit 13 controls the voltage applied to the selection gate SGD, and the SL drive circuit 14 controls the voltage applied to the source line SL. The sense amplifier circuit 15 determines the data read out according to the signal from the selected memory cell.

[0021] The peripheral circuit 10 controls the operation of the semiconductor memory device 1 based on instructions input from an external source (for example, the memory controller of the memory system to which the semiconductor memory device 1 is applied) via the interface 20. For example, when the peripheral circuit 10 receives a write instruction, it selects the memory cell at the address to be written using the SGS drive circuit 12, the SGD drive circuit 13, and the WL drive circuit 11, and writes the data by applying a voltage corresponding to the data to the selected memory cell. Also, when the peripheral circuit 10 receives a read instruction, it selects the memory cell at the address to be written in the memory cell array 2 using the SGS drive circuit 12, the SGD drive circuit 13, and the WL drive circuit 11, determines the data read from the selected memory cell using the sense amplifier circuit 15, and outputs that data to an external source (memory controller) via the interface 20.

[0022] Next, the configuration of the memory cell array 2 will be explained using Figure 3. Figure 3 is a circuit diagram showing the configuration of the memory cell array 2 included in the semiconductor memory device 1.

[0023] The memory cell array 2 has multiple blocks BLK, each of which is a collection of multiple memory cells MT. Memory cells MT are also called memory cell transistors.

[0024] Each block BLK has multiple string units SU0, SU1, SU2, SU3, which are sets of memory cells MT associated with word lines WL and bit lines BL. Each string unit SU0 to SU3 has multiple memory strings MST, in which memory cells MT are connected in series. The number of memory strings MST within each string unit SU0 to SU3 is arbitrary.

[0025] Multiple string units SU0, SU1, SU2, and SU3 correspond to multiple selected gate lines SGD0, SGD1, SGD3, and SGD4, and share a selected gate line SGS, functioning as multiple drive units in block BLK. Each string unit SU can be driven by its corresponding selected gate line SGD and selected gate line SGS. Each string unit SU also contains multiple memory strings MST.

[0026] Each memory string MST contains, for example, 11 memory cells MT (MT0 to MT10) and selection transistors DGT and SGT. Each memory cell MT has a control gate and a charge storage layer to hold data non-volatile. The 11 memory cells MT (MT0 to MT10) are connected in series between the source of the selection transistor DGT and the drain of the selection transistor SGT. Note that the number of memory cells MT in a memory string MST is not limited to 11.

[0027] The gates of the selection transistors DGT in each string unit SU are connected to the selection gate line SGD. In contrast, the gates of the selection transistors SGT in each string unit SU are connected to a common selection gate line SGS, for example.

[0028] The drains of the selection transistor DGT of each memory string MST within each string unit SU are connected to different bit lines BL0 to BLk (where k is any integer greater than or equal to 2). Furthermore, the bit lines BL0 to BLk connect a single memory string MST within each string unit SU across multiple blocks BLK. Additionally, the sources of each selection transistor SGT are commonly connected to the source line SL.

[0029] In other words, a string unit SU is a collection of memory strings MST connected to different bit lines BL0~BLk and the same selection gate line SGD. A block BLK is a collection of multiple string units SU0~SU3 that share a common word line WL. And memory cell array 2 is a collection of multiple block BLKs that share a common bit line BL0~BLk.

[0030] If we refer to a group of memory cells (MTs) that share a word line (WL) as a "memory cell group (MCG)," then a memory cell group (MCG) is the smallest unit of a collection of memory cells to which a predetermined voltage (e.g., write voltage, read voltage) can be applied collectively via the word line (WL).

[0031] Next, the specific configuration of the memory cell array 2 will be explained using Figures 4 and 5. Figure 4 is a ZY cross-sectional view showing the configuration of the memory cell array 2. Figure 5 is an XY plan view showing the configuration of the memory cell MT, and shows the XY plane when Figure 4 is cut along line AA.

[0032] As shown in Figures 1, 4, and 5, the memory cell array 2 is configured on the +Z side of the substrate SUB, with columnar bodies 4 arranged two-dimensionally in the XY direction, and multiple layers of word lines WL passing through the columnar bodies 4 to form a three-dimensional array of memory cells MT.

[0033] In the memory cell array 2, a laminated structure SST is formed by alternately stacking conductive layers 6 and insulating layers 7. In the laminated structure SST, each conductive layer 6 may be made of a material mainly composed of a conductor (e.g., a metal such as tungsten). Each insulating layer 7 may be made of a material mainly composed of an insulator (e.g., a semiconductor oxide such as silicon oxide). Most of the conductive layers 6 function as word lines WL. The conductive layers 6 on the +Z side function as selected gate lines SGD. The conductive layers 6 on the -Z side function as selected gate lines SGS.

[0034] Multiple memory holes MH (see Figure 4) are formed in the laminated SST. Each memory hole MH extends in the Z direction within the laminated SST. Each memory hole MH may penetrate the laminated SST in the Z direction. Multiple memory holes MH are arranged two-dimensionally in the XY direction. A columnar body 4 is placed inside each memory hole MH. This creates a two-dimensional arrangement of multiple columnar bodies 4 corresponding to multiple memory holes MH.

[0035] In the memory cell array 2, multiple memory cells MT are configured at multiple locations where multiple word lines WL intersect with multiple columnar bodies 4. Multiple selection transistors DGT are configured at multiple locations where selection gate lines SGD intersect with multiple columnar bodies 4. Multiple selection transistors SGT are configured at multiple locations where selection gate lines SGS intersect with multiple columnar bodies 4. As shown in Figure 5, the columnar bodies 4 include a core insulating film 41, a semiconductor film 42, and an insulating film 43. The core insulating film 41, semiconductor film 42, and insulating film 43 are arranged within the memory holes MH. The core insulating film 41 may be formed from a material mainly composed of an insulator (e.g., silicon oxide). The core insulating film 41 includes a substantially cylindrical shape extending along the central axis of the columnar body 4. The semiconductor film 42 is arranged to surround the core insulating film 41 from the outside and includes a substantially cylindrical shape extending along the central axis of the columnar body 4. The insulating film 43 is arranged to surround the semiconductor film 42 from the outside and includes a substantially cylindrical shape that extends along the central axis of the columnar body 4.

[0036] The semiconductor film 42 includes the channel region (active region) in the memory string MST and can be formed from a material mainly composed of a semiconductor (e.g., polysilicon).

[0037] The insulating film 43 is positioned between the conductive layer 6 and the semiconductor film 42, and surrounds the semiconductor film 42 in a plan view. The insulating film 43 covers the sides of the semiconductor film 42. The insulating film 43 is configured to have charge storage capability in the portion positioned between the conductive layer 6 and the semiconductor film 42.

[0038] As shown in Figure 5, the insulating film 43 may consist of a three-layer structure: tunnel insulating film 431, charge storage film 432, and block insulating film 433, in that order from the semiconductor film 42 side. That is, within the memory hole MH, the core insulating film 41, semiconductor film 42, tunnel insulating film 431, charge storage film 432, and block insulating film 433 may be arranged in that order from the center side. The tunnel insulating film 431 may be formed from a material mainly composed of oxides (e.g., silicon oxide). The charge storage film 432 may be formed from a material mainly composed of nitrides (e.g., silicon nitride). The block insulating film 433 may be formed from a material mainly composed of oxides (e.g., silicon oxide, metal oxide, or a stack thereof).

[0039] In other words, the insulating film 43 may have an ONO-type three-layer structure in the portion (memory cell MT) located between the conductive layer 6 (word line WL) and the semiconductor film 42, where the charge storage film is sandwiched between a pair of insulating films (tunnel insulating film, block insulating film). Alternatively, the insulating film 43 may consist of a single-layer structure of a gate insulating film in the portion (selection transistor DGT) located between the conductive layer 6 (selection gate line SGD) and the semiconductor film 42. The gate insulating film can be formed from a material mainly composed of an oxide (for example, silicon oxide).

[0040] In the semiconductor memory device 1, increasing the number of stacked conductive layers 6 increases the aspect ratio of the columnar body 4 (= (dimension in the stacking direction) / (dimension in the planar direction)), which may increase the difficulty of processing.

[0041] Alternatively, the columnar body 4 that penetrates the laminated SST can be made into a structure with multiple layers stacked together. For example, the laminated SST can be divided into multiple laminates corresponding to multiple layers, and accordingly, the memory hole MH into which the columnar body 4 is to be embedded can be divided into multiple memory holes. Since the aspect ratio of each of the multiple memory holes is lower than the aspect ratio of the memory hole MH before division, the difficulty of processing can be reduced.

[0042] In Figure 4, each memory hole MH consists of memory hole MH1 and memory hole MH2 stacked in that order. Each columnar body 4 consists of tier T1 and tier T2 stacked in that order. The laminated body SST consists of laminated body SST1 and laminated body SST2 stacked in that order.

[0043] The stacked structure SST1 has regions RG11 and RG12. Region RG12 is located on the +Z side relative to region RG11. The memory hole MH1 extends through the stacked structure SST1 in the Z direction. The memory hole MH1 may penetrate through the stacked structure SST1 in the Z direction. The tier T1 is located within the memory hole MH1. The tier T1 extends through the stacked structure SST1 in the Z direction. The tier T1 may penetrate through the stacked structure SST1 in the Z direction.

[0044] The average planar width of memory holes MH1 in region RG11 is smaller than the average planar width of memory holes MH1 in region RG12. The average planar width is the average of the maximum dimensions in the XY directions with respect to the Z direction within a given region. If the memory hole MH1 is approximately cylindrical, the average planar width of memory holes MH1 in region RG11 is the average of the diameters of memory holes MH1 in region RG11 with respect to the Z direction. The average planar width of memory holes MH1 in region RG12 is the average of the diameters of memory holes MH1 in region RG12 with respect to the Z direction. If the memory hole MH1 is approximately rectangular prism-shaped, the average planar width of memory holes MH1 in region RG11 is the average of the diagonal lengths of the rectangular cross-section of memory holes MH1 in region RG11 with respect to the Z direction. The average planar width of memory holes MH1 in region RG12 is the average of the diagonal lengths of the rectangular cross-section of memory holes MH1 in region RG12 with respect to the Z direction.

[0045] Accordingly, the average planar width of tier T1 in region RG11 is smaller than the average planar width of tier T1 in region RG12.

[0046] In the laminate SST1, in region RG11, conductive layer 6 (selection gate line SGS), conductive layer 6 (word line WL0), conductive layer 6 (word line WL1), and conductive layer 6 (word line WL2) are laminated with an insulating layer 7 in between.

[0047] In region RG11, the areas where conductive layer 6 (selection gate line SGS), conductive layer 6 (word line WL0), conductive layer 6 (word line WL1), conductive layer 6 (word line WL2) intersect with tier T1 function as selection transistor SGT, memory cell MT0, memory cell MT1, and memory cell MT2, respectively.

[0048] The charge storage film 432 of tier T1 has a plurality of protrusions 4321 and connecting portions 4325 in region RG11. The plurality of protrusions 4321 are arranged in region RG11 between a plurality of conductive layers 6 and a semiconductor film 42. The plurality of protrusions 4321 are continuous with each other in the Z direction via the connecting portions 4325. The connecting portions 4325 cover the inner surface of the memory hole MH1 and connect the plurality of adjacent protrusions 4321 in the Z direction.

[0049] The multiple protrusions 4321 correspond to the conductive layer 6 (selected gate line SGS), conductive layer 6 (word line WL0), conductive layer 6 (word line WL1), and conductive layer 6 (word line WL2). Each protrusion 4321 projects outwards from the corresponding conductive layer 6 at the Z position of the corresponding conductive layer 6.

[0050] As shown in Figure 6(b), each protrusion 4321 has a concave surface 4321a1 in the central part in the Z direction on the semiconductor film side surface 4321a. Figure 6 is an enlarged cross-sectional view showing the configuration near the memory cell MT. Figure 6(b) is an enlarged cross-sectional view of portion C in Figure 4.

[0051] In the memory cell MT0, the convex portion 4321 has a semiconductor film side surface 4321a which includes a concave surface 4321a1, a flat surface 4321a2, and a flat surface 4321a3.

[0052] The flat surface 4321a2 is located on the +Z side of surface 4321a. The flat surface 4321a2 is generally flat. The flat surface 4321a2 is continuous with surface 4325a on the semiconductor film side of the connection portion 4325 on the +Z side. Surface 4325a is generally flat.

[0053] The flat surface 4321a3 is located on the -Z side of surface 4321a. The flat surface 4321a3 is generally flat. The flat surface 4321a3 is continuous with surface 4325a on the semiconductor film side of the connection portion 4325 on the -Z side. Surface 4325a is generally flat.

[0054] The concave surface 4321a1 is located in the center of the surface 4321a in the Z direction. The concave surface 4321a1 is positioned between the flat surfaces 4321a2 and 4321a3 in the Z direction. The concave surface 4321a1 is recessed toward the conductive layer 6 (word line WL0) from each of the flat surfaces 4321a2 and 4321a3. The concave surface 4321a1 may also be curved toward the conductive layer 6 (word line WL0).

[0055] The protrusion 4321 in memory cell MT1 is the same as the protrusion 4321 in memory cell MT0.

[0056] In region RG11, the selection transistor SGT, memory cell MT0, memory cell MT1, and memory cell MT2 are capable of accumulating charge on the protrusion 4321.

[0057] In the laminate SST1, in region RG12, conductive layer 6 (word line WL2), conductive layer 6 (word line WL3), conductive layer 6 (word line WL4), and conductive layer 6 (word line WL5) are laminated with an insulating layer 7 in between.

[0058] In region RG12, the areas where conductive layer 6 (word line WL2), conductive layer 6 (word line WL3), conductive layer 6 (word line WL4), conductive layer 6 (word line WL5) intersect with tier T1 function as memory cells MT2, MT3, MT4, and MT5, respectively.

[0059] The charge storage film 432 of tier T1 has a plurality of protrusions 4322 in region RG12. The plurality of protrusions 4322 are arranged in region RG12 between a plurality of conductive layers 6 and a semiconductor film 42. The plurality of protrusions 4322 are separated from each other in the Z direction.

[0060] The multiple protrusions 4322 correspond to conductive layer 6 (word line WL2), conductive layer 6 (word line WL3), conductive layer 6 (word line WL4), and conductive layer 6 (word line WL5). Each protrusion 4322 projects outwards from the corresponding conductive layer 6 at the Z position of the corresponding conductive layer 6.

[0061] As shown in Figure 6(a), each protrusion 4322 has a surface 4322a on the semiconductor film 42 side that includes concave surfaces 4322a2 and 4322a3 at both ends in the Z direction. Figure 6(a) is an enlarged cross-sectional view of portion B in Figure 4.

[0062] In memory cell MT3, the protrusion 4322 has a semiconductor film side surface 4322a which includes a flat surface 4322a1, a concave surface 4322a2, and a concave surface 4322a3.

[0063] The flat surface 4322a1 is located in the center of surface 4322a in the Z direction. The flat surface 4322a1 is positioned between concave surfaces 4322a2 and 4322a3 in the Z direction. The flat surface 4322a1 is generally flat.

[0064] The concave surface 4322a2 is located on the +Z side of surface 4322a. The concave surface 4322a2 is recessed toward the conductive layer 6 (word line WL3) from the flat surface 4322a1. The concave surface 4322a2 may also be recessed in a curved shape toward the conductive layer 6 (word line WL3).

[0065] The concave surface 4322a3 is located on the -Z side of surface 4322a. The concave surface 4322a3 is recessed toward the conductive layer 6 (word line WL3) from the flat surface 4322a1. The concave surface 4322a3 may also be recessed in a curved shape toward the conductive layer 6 (word line WL3).

[0066] The protrusion 4322 in memory cell MT4 is the same as the protrusion 4322 in memory cell MT3.

[0067] Memory cells MT2, MT3, MT4, and MT5 in region RG12 can store charge on the protrusion 4322.

[0068] Here, multiple protrusions 4321 in region RG11 are continuous with each other in the Z direction via connecting portion 4325, while multiple protrusions 4322 in region RG12 are separated from each other in the Z direction. For this reason, the selection transistor SGT, memory cell MT0, memory cell MT1, and memory cell MT2 in region RG11 may be more prone to charge leakage in the Z direction compared to memory cells MT2, MT3, MT4, and MT5 in region RG12. In other words, the selection transistor SGT, memory cell MT0, memory cell MT1, and memory cell MT2 in region RG11 may have lower information retention characteristics compared to memory cells MT2, MT3, MT4, and MT5 in region RG12.

[0069] In contrast, as shown in Figure 6, the film thickness W1 of the insulating layer 7 in region RG11 is thicker than the film thickness W2 of the insulating layer 7 in region RG12. Accordingly, the Z-spacing of the protrusions 4321 in region RG11 can be made wider than the Z-spacing of the protrusions 4322 in region RG12. This makes it possible to suppress charge leakage in the Z direction in the selection transistor SGT, memory cell MT0, memory cell MT1, and memory cell MT2 in region RG11. In other words, the information retention characteristics of the selection transistor SGT, memory cell MT0, memory cell MT1, and memory cell MT2 in region RG11 can be made closer to the information retention characteristics of the memory cells MT2, memory cell MT3, memory cell MT4, and memory cell MT5 in region RG12.

[0070] The stacked structure SST2 has regions RG21 and RG22. Region RG22 is located on the +Z side relative to region RG21. The memory hole MH2 extends through the stacked structure SST2 in the Z direction. The memory hole MH2 may penetrate through the stacked structure SST2 in the Z direction. The tier T2 is located within the memory hole MH2. The tier T2 extends through the stacked structure SST2 in the Z direction. The tier T2 may penetrate through the stacked structure SST2 in the Z direction.

[0071] The average planar width of memory holes MH2 in region RG21 is smaller than the average planar width of memory holes MH2 in region RG22. The average planar width of tier T2 in region RG21 is smaller than the average planar width of tier T2 in region RG22.

[0072] In the laminate SST2, in region RG21, conductive layer 6 (word line WL6), conductive layer 6 (word line WL7), and conductive layer 6 (word line WL8) are laminated with an insulating layer 7 in between.

[0073] The charge storage film 432 of tier T2 has a plurality of protrusions 4323 and connecting portions 4325 in region RG21. The plurality of protrusions 4323 are arranged in region RG21 between a plurality of conductive layers 6 and a semiconductor film 42. The plurality of protrusions 4323 are continuous with each other in the Z direction via the connecting portions 4325. The connecting portions 4325 cover the inner surface of the memory hole MH2 and connect the plurality of adjacent protrusions 4323 in the Z direction.

[0074] The multiple protrusions 4323 correspond to conductive layer 6 (word line WL6), conductive layer 6 (word line WL7), and conductive layer 6 (word line WL8). Each protrusion 4323 projects toward the corresponding conductive layer 6 at the Z position of the corresponding conductive layer 6.

[0075] Each protrusion 4323 has a concave surface 4323a1 in the center of the semiconductor film side surface 4323a in the Z direction (see Figure 6(b)).

[0076] In the memory cell MT6, the convex portion 4323 has a semiconductor film side surface 4323a which includes a concave surface 4323a1, a flat surface 4323a2, and a flat surface 4323a3.

[0077] The flat surface 4323a2 is located on the +Z side of surface 4323a. The flat surface 4323a2 is generally flat. The flat surface 4323a2 is continuous with surface 4325a on the semiconductor film side of the connection portion 4325 on the +Z side. Surface 4325a is generally flat.

[0078] The flat surface 4323a3 is located on the -Z side of surface 4323a. The flat surface 4323a3 is generally flat. The flat surface 4323a3 is continuous with surface 4325a on the semiconductor film side of the connection portion 4325 on the -Z side. Surface 4325a is generally flat.

[0079] The concave surface 4323a1 is located in the center of the surface 4323a in the Z direction. The concave surface 4323a1 is positioned between the flat surfaces 4323a2 and 4323a3 in the Z direction. The concave surface 4323a1 is recessed toward the conductive layer 6 (word line WL6) from each of the flat surfaces 4323a2 and 4323a3. The concave surface 4323a1 may also be recessed in a curved shape toward the conductive layer 6 (word line WL6).

[0080] The protrusion 4323 in memory cell MT7 is the same as the protrusion 4323 in memory cell MT6.

[0081] Memory cells MT6, MT7, and MT8 in region RG21 can store charge on the protrusion 4323.

[0082] In the laminate SST2, in region RG22, conductive layer 6 (word line WL9), conductive layer 6 (word line WL10), and conductive layer 6 (selection gate line SGD) are laminated via an insulating layer 7.

[0083] The charge storage film 432 of tier T2 has a plurality of protrusions 4324 in region RG22. The plurality of protrusions 4324 are arranged between a plurality of conductive layers 6 and a semiconductor film 42 in region RG22. The plurality of protrusions 4324 are separated from each other in the Z direction.

[0084] The multiple protrusions 4324 correspond to conductive layer 6 (word line WL9), conductive layer 6 (word line WL10), and conductive layer 6 (selection gate line SGD). Each protrusion 4324 projects toward the corresponding conductive layer 6 at the Z position of the corresponding conductive layer 6.

[0085] Each protrusion 4324 has a surface 4324a on the semiconductor film 42 side that includes concave surfaces 4324a2 and 4324a3 at both ends in the Z direction (see Figure 6(a)).

[0086] In the memory cell MT9, the protrusion 4324 has a semiconductor film side surface 4324a which includes a flat surface 4324a1, a concave surface 4324a2, and a concave surface 4324a3.

[0087] The flat surface 4324a1 is located in the center of surface 4324a in the Z direction. The flat surface 4324a1 is positioned between concave surfaces 4324a2 and 4324a3 in the Z direction. The flat surface 4324a1 is generally flat.

[0088] The concave surface 4324a2 is located on the +Z side of surface 4324a. The concave surface 4324a2 is recessed toward the conductive layer 6 (word line WL9) from the flat surface 4324a1. The concave surface 4324a2 may also be recessed in a curved shape toward the conductive layer 6 (word line WL9).

[0089] The concave surface 4324a3 is located on the -Z side of surface 4324a. The concave surface 4324a3 is recessed toward the conductive layer 6 (word line WL9) from the flat surface 4324a1. The concave surface 4324a3 may also be recessed in a curved shape toward the conductive layer 6 (word line WL9).

[0090] The protrusion 4324 in memory cell MT10 is the same as the protrusion 4324 in memory cell MT9.

[0091] In region RG22, memory cells MT9 and MT10, and the selection transistor DGT can store charge on the protrusion 4324.

[0092] Here, multiple protrusions 4323 in region RG21 are continuous with each other in the Z direction via connecting portion 4326, while multiple protrusions 4324 in region RG22 are separated from each other in the Z direction. For this reason, memory cells MT6, MT7, and MT8 in region RG21 may be more prone to charge leakage in the Z direction compared to memory cells MT9, MT10, and selection transistor DGT in region RG22. In other words, memory cells MT6, MT7, and MT8 in region RG21 may have lower information retention characteristics compared to memory cells MT9, MT10, and selection transistor DGT in region RG22.

[0093] In contrast, the film thickness W1 of the insulating layer 7 in region RG21 is thicker than the film thickness W2 of the insulating layer 7 in region RG22 (see Figure 6). Accordingly, the Z-spacing of the protrusions 4323 in region RG21 can be made wider than the Z-spacing of the protrusions 4324 in region RG22. This suppresses charge leakage in the Z direction in memory cells MT6, MT7, and MT8 in region RG21. In other words, the information retention characteristics of memory cells MT6, MT7, and MT8 in region RG21 can be made closer to the information retention characteristics of memory cells MT9, MT10, and the selection transistor DGT in region RG22.

[0094] As described above, in this embodiment, in the semiconductor memory device 1, the film thickness W1 of the insulating layer 7 in regions RG11 and R21 where the protrusions 4321 and 4323 are continuous in the Z direction is thicker than the film thickness W2 of the insulating layer 7 in regions RG12 and R22 where the protrusions 4322 and 4324 are separated in the Z direction. This makes it possible to bring the information retention characteristics of memory cells MT6, MT7, and MT8 in region RG21 closer to the information retention characteristics of memory cells MT9, MT10, and the selection transistor DGT in region RG22. In other words, the information retention characteristics can be equalized among multiple memory cells MT and selection transistors aligned in the Z direction, thereby improving the operational reliability of the semiconductor memory device 1.

[0095] As a first modification of the embodiment, in the semiconductor memory device 1i, the film thickness of the insulating layer 7i in each stack SST1i and SST2i of the stack SSTi may change in multiple steps. As the film thickness of the charge storage film 432 increases from the +Z side to the -Z side of each stack SST1i and SST2i, the film thickness of the insulating layer 7i may increase in multiple steps. That is, the configuration shown in Figure 4 may be modified so that the film thickness of the insulating layer 7 in regions RG11 and RG21 increases in two or more steps from the +Z side to the -Z side.

[0096] For example, if the memory cell array 2i is modified to thicken in two stages, it may be configured as shown in Figures 7 and 8. Figure 7 is a YZ cross-sectional view showing the configuration of the memory cell array 2i in a first modified example of the embodiment. Figure 8 is an enlarged YZ cross-sectional view showing the configuration near the memory cell MT in a first modified example of the embodiment. Figures 8(a), 8(b), and 8(c) are enlarged YZ cross-sectional views of portions D, E, and F of Figure 7, respectively.

[0097] The laminate SST1i has regions RG111 and RG112 instead of region RG11 (see Figure 4). Regions RG111 and RG112 correspond to regions obtained by dividing region RG11 into two parts. Region RG112 is located on the +Z side relative to region RG111. Region RG12 is located on the +Z side relative to region RG112.

[0098] The average planar width of memory holes MH1 in region RG111 is smaller than the average planar width of memory holes MH1 in region RG112. The average planar width of tier T1 in region RG111 is smaller than the average planar width of tier T1 in region RG112.

[0099] The average planar width of memory holes MH1 in region RG112 is smaller than the average planar width of memory holes MH1 in region RG12. The average planar width of tier T1 in region RG112 is smaller than the average planar width of tier T1 in region RG112.

[0100] In region RG111, the selection transistor SGT and memory cell MT0 can store charge on the protrusion 4321.

[0101] Memory cells MT1 and MT2 in region RG112 can store charge on the protrusion 4321.

[0102] Memory cells MT2, MT3, MT4, and MT5 in region RG12 can store charge on the protrusion 4322.

[0103] Here, as shown in Figures 8(b) and 8(c), the film thickness D12 of the connection portion 4325 in region RG112 is thinner than the film thickness D11 of the connection portion 4325 in region RG111. For this reason, the memory cells MT1 and MT2 in region RG112 may be less prone to charge leakage in the Z direction compared to the selection transistor SGT and memory cell MT0 in region RG111. In other words, the memory cells MT1 and MT2 in region RG112 may have higher information retention characteristics compared to the selection transistor SGT and memory cell MT0 in region RG111.

[0104] On the other hand, the multiple protrusions 4321 in region RG112 are continuous with each other in the Z direction via the connecting portion 4325, while the multiple protrusions 4322 in region RG12 are separated from each other in the Z direction. For this reason, memory cells MT1 and MT2 in region RG112 may be more prone to charge leakage in the Z direction compared to memory cells MT2, MT3, MT4, and MT5 in region RG12. In other words, memory cells MT1 and MT2 in region RG112 may have lower information retention characteristics compared to memory cells MT2, MT3, MT4, and MT5 in region RG12.

[0105] In contrast, as shown in Figures 8(a) to 8(c), the film thickness W12 of the insulating layer 7i in region RG112 is thicker than the film thickness W2 of the insulating layer 7i in region RG12, and thinner than the film thickness of the insulating layer 7i in region RG111. Accordingly, the Z spacing of the protrusions 4321 in region RG112 can be made wider than the Z spacing of the protrusions 4322 in region RG12 and narrower than the Z spacing of the protrusions 4321 in region RG111. As a result, charge leakage in the Z direction from memory cells MT1 and MT2 in region RG112 can be suppressed to the same extent as in region RG111. That is, the information retention characteristics of memory cells MT1 and MT2 in region RG112 can be made closer to the information retention characteristics of memory cells MT2, MT3, MT4, and MT5 in region RG12, and closer to the information retention characteristics of the selection transistor SGT and memory cell MT0 in region RG111.

[0106] The laminate SST2i has regions RG211 and RG212 instead of region RG21 (see Figure 4). Regions RG211 and RG212 correspond to the two divided regions of region RG21. Region RG212 is located on the +Z side relative to region RG211. Region RG22 is located on the +Z side relative to region RG212.

[0107] The average planar width of memory holes MH2 in region RG211 is smaller than the average planar width of memory holes MH2 in region RG212. The average planar width of tier T2 in region RG211 is smaller than the average planar width of tier T2 in region RG212.

[0108] The average planar width of memory holes MH2 in region RG212 is smaller than the average planar width of memory holes MH2 in region RG22. The average planar width of tier T2 in region RG212 is smaller than the average planar width of tier T2 in region RG212.

[0109] Memory cells MT6 and MT7 in region RG211 can store charge on the protrusion 4323.

[0110] Memory cells MT8 and MT9 in region RG212 can store charge on the protrusion 4323.

[0111] In region RG22, the memory cell MT10 and the selection transistor DGT can store charge on the protrusion 4324.

[0112] Here, the film thickness D12 of the connection portion 4326 in region RG212 is thinner than the film thickness D11 of the connection portion 4326 in region RG211 (see Figures 8(b) and 8(c)). Therefore, memory cells MT8 and MT9 in region RG212 may be less prone to charge leakage in the Z direction compared to memory cells MT6 and MT7 in region RG211. In other words, memory cells MT8 and MT9 in region RG212 may have higher information retention characteristics compared to memory cells MT6 and MT7 in region RG211.

[0113] On the other hand, multiple protrusions 4323 in region RG212 are continuous with each other in the Z direction via connecting portion 4326, while multiple protrusions 4324 in region RG22 are separated from each other in the Z direction. For this reason, memory cells MT8 and MT9 in region RG212 may be more prone to charge leakage in the Z direction compared to memory cell MT10 and selection transistor DGT in region RG22. In other words, memory cells MT8 and MT9 in region RG212 may have lower information retention characteristics compared to memory cell MT10 and selection transistor DGT in region RG22.

[0114] In contrast, the film thickness W12 of the insulating layer 7i in region RG212 is thicker than the film thickness W2 of the insulating layer 7i in region RG22, but thinner than the film thickness of the insulating layer 7i in region RG211 (see Figures 8(a) to 8(c)). Accordingly, the Z spacing of the protrusions 4323 in region RG212 can be made wider than the Z spacing of the protrusions 4324 in region RG22 and narrower than the Z spacing of the protrusions 4323 in region RG211. As a result, charge leakage in the Z direction from memory cells MT8 and MT9 in region RG212 can be suppressed to the same extent as in region RG211. That is, the information retention characteristics of memory cells MT8 and MT9 in region RG212 can be made closer to the information retention characteristics of memory cell MT10 and selection transistor DGT in region RG22, and closer to the information retention characteristics of memory cells MT6 and MT7 in region RG211.

[0115] Thus, in the semiconductor memory device 1i, the thickness of the insulating layer 7i in each stack SST1i and SST2i of the stack SSTi is varied in multiple steps. This allows for more equalization of the information retention characteristics between multiple memory cells MT and selection transistors aligned in the Z direction, further improving the operational reliability of the semiconductor memory device 1.

[0116] Alternatively, as a second modification of the embodiment, the semiconductor memory device 1 may be manufactured as shown in Figures 9 to 13. Figures 9(a), 9(b), 10(a), 10(b), 11(a) to 11(h), 12(a) to 12(h), and 13(a) to 13(f) are YZ cross-sectional views showing a method for manufacturing the semiconductor memory device 1. Figures 11(a), 11(c), 11(e), 11(g), 12(a), 12(c), 12(e), 12(g), 13(a), 13(c), and 13(e) are enlarged YZ cross-sectional views of portion G in Figure 10(b). Figures 11(b), 11(d), 11(f), 11(h), 12(b), 12(d), 12(f), 12(h), 13(b), 13(d), and 13(f) are enlarged YZ cross-sectional views of the H portion of Figure 10(b).

[0117] In the process shown in FIG. 9(a), a transistor is formed on the substrate SUB, and contact plugs, wiring films, via plugs, etc. are formed on the substrate SUB, and an interlayer insulating film is formed around them. Thereby, the peripheral circuit 100 is formed. Then, an interlayer insulating film 81 is deposited on the +Z side of the substrate SUB. The interlayer insulating film 81 can be formed of a material mainly composed of an insulator (for example, a semiconductor oxide such as silicon oxide) (see FIG. 1). A plurality of insulating layers 7a and sacrificial layers 5 are alternately deposited on the +Z side of the interlayer insulating film 81 to form a laminate SST1a. The insulating layer 7a can be formed of a material mainly composed of an oxide (for example, silicon oxide). The sacrificial layer 5 can be formed of a material mainly composed of a nitride (for example, silicon nitride).

[0118] At this time, at the Z position corresponding to the region RG11, the insulating layer 7a is deposited with a film thickness W1, and at the Z position corresponding to the region RG12, the insulating layer 7a is deposited with a film thickness W2 (<W1). The sacrificial layer 5 may be deposited with a substantially constant film thickness.

[0119] In the process shown in FIG. 9(b), a resist pattern RG1 with an opening at the formation position of the memory hole MH1 is formed on the laminate SST1a. Anisotropic dry etching is performed using the resist pattern RG1 as a mask to form a memory hole MH1 that reaches the sacrificial layer 5 on the most -Z side. The memory hole MH1 can be formed such that the average planar width of the region RG11 is smaller than the average planar width of the region RG12.

[0120] In the process shown in FIG. 10(a), a plurality of insulating layers 7a and sacrificial layers 5 are alternately deposited on the +Z side of the laminate SST1b to form a laminate SST2a. The insulating layer 7a can be formed of a material mainly composed of an oxide (for example, silicon oxide). The sacrificial layer 5 can be formed of a material mainly composed of a nitride (for example, silicon nitride).

[0121] At this time, at the Z position corresponding to the region RG21, the insulating layer 7a is deposited with a film thickness W1, and at the Z position corresponding to the region RG22, the insulating layer 7a is deposited with a film thickness W2 (<W1). The sacrificial layer 5 may be deposited with a substantially constant film thickness.

[0122] In the process shown in Figure 10(b), a resist pattern RG2 with openings for the formation of memory holes MH2 is formed on the laminate SST2a. Anisotropic dry etching is performed using the resist pattern RG2 as a mask to form memory holes MH2 that reach memory holes MH1. Memory holes MH2 may be formed such that the average planar width of region RG21 is smaller than the average planar width of region RG22.

[0123] At this time, the inner surfaces of each memory hole MH1, MH2 are generally flat, as shown in Figures 11(a) and 11(b). In each of the regions RG11 shown in Figure 11(b) and RG12 shown in Figure 11(a), the surfaces 7a1 of the adjacent insulating layer 7a and the surface 51 of the sacrificial layer 5 form a continuous, generally flat surface in the ZY cross-section.

[0124] Note that while Figures 11(a) and 11(b) illustrate memory hole MH1, the cross-sectional shape of memory hole MH2 is generally similar to that of memory hole MH1. The following explanation will mainly focus on memory hole MH1, but the same explanation applies to memory hole MH2.

[0125] In the process shown in Figures 11(c) and 11(d), an inhibitor treatment is applied to the inner surface of the memory hole MH1. During the inhibitor treatment, a first treatment gas, which has high reactivity with the material of the sacrificial layer 5 and low reactivity with the material of the insulating layer 7a, is supplied to the inner surface of the memory hole MH1. As a result, an insulating film 91 is selectively grown on the surface 51 of the sacrificial layer 5 in the region RG11 shown in Figure 11(d) and the region RG12 shown in Figure 11(c), respectively. The insulating film 91 can be formed from a material mainly composed of an insulator (e.g., silicon oxide). At this time, both ends of the insulating film 91 in the Z direction slightly cover the surface 7a1 of the insulating layer 7a.

[0126] In the process shown in Figures 11(e) and 11(f), a selective growth treatment is applied to the inner surface of the memory hole MH1. In the selective growth treatment, a second treatment gas, which has high reactivity with the insulating layer 7a material and low reactivity with the sacrificial layer 5 material, is supplied to the inner surface of the memory hole MH1. As a result, an insulating film 92 is selectively grown on the surface 7a1 of the insulating layer 7a in region RG11 shown in Figure 11(f) and region RG12 shown in Figure 11(e), respectively. The insulating film 92 is selectively grown to be thicker than the insulating film 91. The insulating film 92 can be formed from a material mainly composed of an insulator (e.g., silicon oxide). At this time, both ends of the insulating film 92 in the Z direction slightly cover the insulating film 91. A step is formed between the Z-direction ends of the insulating film 92 and the surface of the insulating film 91, thereby forming a recess 93 on the inner surface of the memory hole MH1. The recess 93 is recessed toward the sacrificial layer 5 side from the surface of the insulating film 92.

[0127] In the process shown in Figures 11(g) and 11(h), isotropic dry etching or wet etching is performed using the insulating film 92 as a mask. The isotropic dry etching or wet etching is performed until the surface 51 of the sacrificial layer 5 is exposed. As a result, the surface 51 of the sacrificial layer 5 is exposed on the bottom surface of the recess 93 in both the region RG11 shown in Figure 11(h) and the region RG12 shown in Figure 11(g). At this time, the insulating layer 7a and the remaining insulating films 91 and 92 after etching can be integrated as the insulating layer 7.

[0128] In the process shown in Figures 12(a) and 12(b), a tunnel insulating film 433 is deposited on the inner surface and bottom surface of the memory hole MH1. The tunnel insulating film 433 can be formed from a material mainly composed of oxide (for example, silicon oxide). At this time, the tunnel insulating film 433 covers the side and bottom surfaces of the recess 93 and also covers the surface 71 of the insulating layer 7.

[0129] In the process shown in Figures 12(c) and 12(d), a charge storage film 432 is deposited on the inner surface and bottom surface of the memory hole MH1. The charge storage film 432 may be formed from a material mainly composed of nitride (for example, silicon nitride). At this time, the charge storage film 432 covers the side and bottom surfaces of the recess 93 and also covers the surface 71 of the insulating layer 7 via the tunnel insulating film 433.

[0130] As a result, a protrusion 4321 and a connecting portion 4325 of the charge storage film 432 are formed in region RG11 shown in Figure 12(d). The protrusion 4321 is formed to protrude toward the sacrificial layer 5 from the connecting portion 4325. A concave surface is formed in the center in the Z direction on the surface of the protrusion 4321 facing the memory hole MH1. The connecting portion 4325 is formed to extend generally flat in the Z direction.

[0131] Similarly, in the region RG12 shown in Figure 12(c), the convex portion 4322 and the connecting portion 4327 of the charge storage film 432 are formed. The convex portion 4322 is formed to protrude toward the sacrificial layer 5 from the connecting portion 4325. A concave surface is formed in the center in the Z direction on the surface of the convex portion 4322 facing the memory hole MH1. The connecting portion 4327 is formed to extend generally flat in the Z direction.

[0132] In the process shown in Figures 12(e) and 12(f), a sacrificial film 94 is deposited on the inner surface and bottom surface of the memory hole MH1. The sacrificial film 94 can be formed from any material that has etching resistance to the etchant of the charge storage film 432. The sacrificial film 94 can be formed from amorphous silicon. In this case, the sacrificial film 94 covers the charge storage film 432 from the inside in the XY direction.

[0133] As a result, in the region RG11 shown in Figure 12(f), a protrusion 941 and a connecting portion 945 of the sacrificial film 94 are formed. The protrusion 941 is formed to protrude toward the sacrificial layer 5 from the connecting portion 945. A concave surface is formed in the center in the Z direction on the surface of the protrusion 941 facing the memory hole MH1. The connecting portion 945 is formed to extend generally flat in the Z direction.

[0134] Similarly, in the region RG12 shown in Figure 12(e), a protrusion 942 and a connecting portion 947 of the sacrificial film 94 are formed. The protrusion 942 is formed to project toward the sacrificial layer 5 from the connecting portion 945. A concave surface is formed in the center in the Z direction on the surface of the protrusion 942 facing the memory hole MH1. The connecting portion 947 is formed to extend generally flat in the Z direction.

[0135] In the process shown in Figures 12(g) and 12(h), a slimming treatment is performed on the sacrificial film 94. In the slimming treatment, the sacrificial film 94 is selectively thickened by isotropic dry etching or wet etching. At this time, the isotropic dry etching or wet etching is performed under etching conditions such that the connecting portion 427 is properly removed in the region RG12 shown in Figure 12(g) and the protrusion 942 selectively remains on the concave surface of the protrusion 4322.

[0136] Here, the average planar width of the memory holes MH1 in region RG11 is smaller than the average planar width of the memory holes MH1 in region RG12. Accordingly, the etching rate of the sacrificial film 94 in region RG11 may be smaller than the etching rate of the sacrificial film 94 in region RG12.

[0137] As a result, in the region RG11 shown in Figure 12(h), the connecting portion 945 remains in addition to the protrusion 941 of the sacrificial film 94, and cannot be completely removed.

[0138] Therefore, in the process shown in Figures 13(a) and 13(b), wet etching is performed using the etchant of the charge storage film 432 and the sacrificial film 94 as a mask. However, in the region RG11 shown in Figure 13(b), the connection portion 4325 of the charge storage film 432 is covered by the connection portion 945 of the sacrificial film 94, making it difficult to remove.

[0139] On the other hand, in region RG12 shown in Figure 13(a), the protrusions 942 of the sacrificial film 94 selectively cover the protrusions 4322 of the charge storage film 432, so that the connection portion 4237 of the charge storage film 432 can be etched and removed. As a result, the protrusions 4322 of the charge storage film 432 can be made into an isolated pattern in the Z direction in region RG12. At this time, concave surfaces are formed at both ends in the Z direction on the surface of the protrusion 4322 facing the memory hole MH1.

[0140] In the process shown in Figures 13(c) and 13(d), wet etching is performed using an etchant for the sacrificial film 94. As a result, the sacrificial film 94 is removed in the region RG11 shown in Figure 13(d) and the region RG12 shown in Figure 13(c), respectively.

[0141] In the process shown in Figures 13(e) and 13(f), a block insulating film 431 is deposited on the side and bottom surfaces of the memory hole MH1. Anisotropic dry etching selectively removes the tunnel insulating film 433, charge storage film 432, and block insulating film 431 from the bottom surface of the memory hole MH1. Subsequently, a semiconductor film 42 and a core insulating film 41 are deposited sequentially on the side and bottom surfaces of the memory hole MH1. This can form a columnar body 4 (see Figure 4).

[0142] Subsequently, the sacrificial layer 5 is removed, and gaps are formed between the multiple insulating layers 7. Conductive material is then embedded in these gaps to form a conductive layer 6. This completes the formation of the laminates SST1 and SST2.

[0143] As described above, the semiconductor memory device 1 can be manufactured using the manufacturing process shown in Figures 9 to 13.

[0144] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0145] 1 Semiconductor memory device, 6 Conductive layer, 7 Insulating layer, 42 Semiconductor film, 431 Block insulating film, 432 Charge storage film, 433 Tunnel insulating film, 4321, 4322, 4323, 4324 Protrusions, 4325, 4326 Connection parts.

Claims

1. A laminate having a first region and a second region located above the first region in the stacking direction, wherein a plurality of first conductive layers are stacked in the first region via a first insulating layer, and a plurality of second conductive layers are stacked in the second region via a second insulating layer, The first region and the second region are semiconductor films extending in the stacking direction, A charge storage film having a plurality of first protrusions and a plurality of second protrusions, Equipped with, The plurality of first protrusions are arranged in the first region between the plurality of first conductive layers and the semiconductor film, and are continuous with each other in the stacking direction. Each of the plurality of first protrusions protrudes toward the first conductive layer at the lamination position corresponding to the first conductive layer, The plurality of second protrusions are arranged in the second region between the plurality of second conductive layers and the semiconductor film, and are separated from each other in the stacking direction. Each of the plurality of second protrusions protrudes toward the second conductive layer at the lamination position corresponding to the second conductive layer, The thickness of the first insulating layer is thicker than the thickness of the second insulating layer. Semiconductor memory device.

2. The semiconductor film and the charge storage film are arranged in the stacked structure within memory holes extending in the stacking direction. The average planar width of the memory holes in the first region is smaller than the average planar width of the memory holes in the second region. The semiconductor memory device according to claim 1.

3. The charge storage film further has first connecting portions in the first region, each extending in the stacking direction and connecting the plurality of first protrusions. The semiconductor memory device according to claim 1.

4. Each of the plurality of first protrusions has a concave surface in the central part in the stacking direction on the side of the semiconductor film. Each of the plurality of second protrusions has a side surface facing the semiconductor film that includes concave surfaces at both ends in the stacking direction. The semiconductor memory device according to claim 1.

5. The laminate has a third region between the first region and the second region in the lamination direction, and in the third region, a plurality of third conductive layers are laminated via a third insulating layer. The charge storage film is disposed between the plurality of third conductive layers and the semiconductor film in the third region, and is separated from each other in the stacking direction, and each has a plurality of third protrusions that project toward the plurality of third conductive layers at the stacking position corresponding to the third conductive layer. The thickness of the third insulating layer is thinner than the thickness of the first insulating layer and thicker than the thickness of the second insulating layer. The semiconductor memory device according to claim 1.

6. The charge storage film is A first connecting portion extending in the stacking direction in the first region and connecting the plurality of first protrusions, A second connecting portion extending in the stacking direction in the third region and connecting the plurality of third protrusions, It further possesses, The film thickness of the second connection is thinner than the film thickness of the first connection. The semiconductor memory device according to claim 5.

7. In the laminate, the thickness of the second insulating layer increases in steps from top to bottom as the thickness of the charge storage film increases in the second region. The semiconductor memory device according to claim 1.

8. A laminate is formed by alternately laminating a first conductive layer and a first insulating layer having a first thickness multiple times, and by alternately laminating a second conductive layer and a second insulating layer having a second thickness multiple times, thereby forming a laminate having a first region in which a plurality of the first conductive layers are laminated via the first insulating layer, and a second region located above the first region in the lamination direction in which a plurality of the second conductive layers are laminated via the second insulating layer. The first region and the second region are formed to create a memory hole having a first recess extending in the stacking direction and whose inner circumferential surface is recessed toward the first conductive layer at a position corresponding to the first conductive layer, and a second recess being recessed toward the second conductive layer at a position corresponding to the second conductive layer. The memory holes are used to deposit a charge storage film and a sacrificial film, Etching the sacrificial film to selectively leave it in the first recess and the second recess to form a sacrificial pattern, Etching the charge storage film using the aforementioned sacrificial pattern so as to selectively leave it in the first recess and the second recess, To eliminate the aforementioned sacrifice pattern, Depositing a semiconductor film in the aforementioned memory hole, Includes, The thickness of the first insulating layer is thicker than the thickness of the second insulating layer. A method for manufacturing semiconductor memory devices.

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