Semiconductor integrated circuits

Abstract

It suppresses malfunctions caused by voltage drops. [Solution] The semiconductor integrated circuit of the present disclosure comprises a plurality of power supply paths that supply a power supply voltage, a plurality of circuit blocks to which the power supply voltage is supplied from the plurality of power supply paths, a switch for switching the connection between the plurality of power supply paths, a shared wiring provided so as to be connectable to the plurality of power supply paths via the switch, and a control circuit for controlling the switch.

Description

Technical Field

[0001] This disclosure relates to a semiconductor integrated circuit.

Background Art

[0002] Patent Document 1 discloses a semiconductor integrated circuit including a first power supply wiring and a second power supply wiring for supplying power to a plurality of blocks, and a power supply path switching means capable of switching a path for supplying power to the plurality of blocks from the first power supply wiring to the second power supply wiring. When it is found that an undesired voltage drop has occurred in a target block among the plurality of blocks, the semiconductor integrated circuit stops supplying power from the first power supply wiring to the target block and supplies power to the target block from the second power supply wiring.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When a difference in power supply voltage occurs among a plurality of circuit blocks, there is a risk of malfunction or the like. An object of this disclosure is to provide a semiconductor integrated circuit capable of reducing the difference in power supply voltage between a plurality of circuit blocks.

Means for Solving the Problems

[0005] The semiconductor integrated circuit of this disclosure is characterized by including a plurality of power supply paths for supplying a power supply voltage, a plurality of circuit blocks to which the power supply voltage is supplied from the plurality of power supply paths, a switch for switching the connection with the plurality of power supply paths, a shared wiring provided so as to be connectable to the plurality of power supply paths via the switch, and a control circuit for controlling the switch.

Effects of the Invention

[0006] The semiconductor integrated circuit described herein can reduce the difference in power supply voltage between multiple circuit blocks. [Brief explanation of the drawing]

[0007] [Figure 1] This is a circuit diagram showing a semiconductor integrated circuit according to the first embodiment. [Figure 2] This is a circuit diagram showing a switch according to the first embodiment. [Figure 3] This figure shows an example of an operation table held by the control circuit according to the first embodiment. [Figure 4] This figure shows the change in operating state in the first circuit block and the third circuit block according to the first embodiment. [Figure 5] This figure shows the control table held by the control circuit according to the first embodiment. [Figure 6] This is a circuit diagram showing a semiconductor integrated circuit according to the second embodiment. [Figure 7] This figure shows an example of voltage values ​​over time in multiple circuit blocks. [Figure 8] This is a circuit diagram showing a semiconductor integrated circuit according to a modified example of the first embodiment. [Modes for carrying out the invention]

[0008] The embodiments for implementing this disclosure will be described in detail below with reference to the drawings. However, this disclosure is not limited to the embodiments described below and can be modified as appropriate without departing from its essence. Furthermore, in the drawings described below, components having the same function will be denoted by the same reference numerals, and their descriptions may be omitted or simplified.

[0009] (First Embodiment) Figure 1 is a circuit diagram showing a semiconductor integrated circuit 1 according to the first embodiment. The semiconductor integrated circuit 1 constitutes, for example, an image processing device, a signal processing device, an imaging device, etc., and includes a potential difference adjustment circuit 100, a first circuit block 120, a second circuit block 130, a third circuit block 140, a first power supply wiring 150P, a first ground wiring 150G, a second power supply wiring 160P, a second ground wiring 160G, a third power supply wiring 170P, a third ground wiring 170G, a first input section 181, a second input section 182, and a third input section 183.

[0010] Furthermore, a power supply regulator 200 is provided outside the semiconductor integrated circuit 1. The regulator 200 is connected to the semiconductor integrated circuit 1 via substrate power wiring 200P and substrate ground wiring 200G. The semiconductor integrated circuit 1 and the regulator 200 are housed in an enclosure (not shown) and constitute an electronic device.

[0011] In this embodiment, the board power wiring 200P and the board ground wiring 200G are branched into three externally from the semiconductor integrated circuit 1. The board power wiring 200P and the board ground wiring 200G are connected to the first input section 181, the second input section 182, and the third input section 183 of the semiconductor integrated circuit 1, respectively. Power voltage is supplied to the semiconductor integrated circuit 1 from the regulator 200 via the first input section 181, the second input section 182, and the third input section 183, respectively.

[0012] Furthermore, the potential difference adjustment circuit 100 includes a control circuit 101, a first shared wiring 102, a second shared wiring 103, a first switch 104, a second switch 105, and a third switch 106.

[0013] The control circuit 101 has the function of controlling the first switch 104, the second switch 105, and the third switch 106, respectively, by control signals generated based on the control rules and operation tables described later. The control circuit 101 is connected to the first switch 104 via signal line SG1. The control circuit 101 is connected to the second switch 105 via signal line SG2. The control circuit 101 is connected to the third switch 106 via signal line SG3.

[0014] The first shared wiring 102 is connected to the first switch 104 via wiring 107P, and the second shared wiring 103 is connected to the first switch 104 via wiring 107G. Furthermore, the first shared wiring 102 is connected to the second switch 105 via wiring 108P, and the second shared wiring 103 is connected to the second switch 105 via wiring 108G. Additionally, the first shared wiring 102 is connected to the third switch 106 via wiring 109P, and the second shared wiring 103 is connected to the third switch 106 via wiring 109G. The first and second shared wirings 102 and 103 are provided across multiple power supply paths corresponding to multiple circuit blocks, and are configured to be connectable to multiple power supply paths via switches.

[0015] The first circuit block 120 has a first signal pass circuit 121 and a signal output circuit 122. The second circuit block 130 has a second signal pass circuit 131. The third circuit block 140 has a third signal pass circuit 141 and a signal input circuit 124. The first signal pass circuit 121, the second signal pass circuit 131, and the third signal pass circuit 141 are composite circuits composed of, for example, buffer circuits, inverter circuits, AND circuits, etc.

[0016] In this embodiment, the signal output circuit 122 is located inside the first circuit block 120. The signal input circuit 124 is located inside the third circuit block 140. However, this arrangement is just an example, and the signal output circuit 122 and the signal input circuit 124 can be located anywhere within the semiconductor integrated circuit 1.

[0017] The first signal passing circuit 121 is connected to the first power supply wiring 150P via the wiring 110P. Also, the first signal passing circuit 121 is connected to the first ground wiring 150G via the wiring 110G. Thereby, a power supply voltage is supplied to the first signal passing circuit 121 by the first power supply wiring 150P and the first ground wiring 150G.

[0018] The second signal passing circuit 131 is connected to the second power supply wiring 160P via the wiring 111P. The second signal passing circuit 131 is connected to the first ground wiring 150G via the wiring 111G. Thereby, a power supply voltage is supplied to the second signal passing circuit 131 by the second power supply wiring 160P and the second ground wiring 160G.

[0019] The third signal passing circuit 141 is connected to the third power supply wiring 170P via the wiring 112P. The third signal passing circuit 141 is connected to the third ground wiring 170G via the wiring 112G. Thereby, a power supply voltage is supplied to the third signal passing circuit 134 by the third power supply wiring 170P and the third ground wiring 170G.

[0020] The signal output circuit 122 is connected to the first signal passing circuit 121 via the signal line SG11. The first signal passing circuit 121 is connected to the second signal passing circuit 131 via the signal line SG12. The second signal passing circuit 131 is connected to the third signal passing circuit 141 via the signal line SG13. The third signal passing circuit 141 is connected to the signal input circuit 142 via the signal line SG14. Thereby, the operation signal output from the signal output circuit 122 sequentially passes through the first signal passing circuit 121, the second signal passing circuit 131, and the third signal passing circuit 141 and is input to the signal input circuit 142.

[0021] Furthermore, in the potential difference adjustment circuit 100, the first switch 104 is connected to the first signal pass circuit 121 and the first power supply wiring 150P via wiring 110P. Also, the first switch 104 is connected to the first signal pass circuit 121 and the first ground wiring 150G via wiring 110G.

[0022] Similarly, in the potential difference adjustment circuit 100, the second switch 105 is connected to the second signal pass circuit 131 and the second power supply wiring 160P via wiring 111P. Furthermore, the second switch 105 is connected to the second signal pass circuit 131 and the second ground wiring 160G via wiring 111G.

[0023] In the potential difference adjustment circuit 100, the third switch 106 is connected to the third signal pass circuit 141 and the third power supply wiring 170P via wiring 112P. Furthermore, the third switch 106 is connected to the third signal pass circuit 141 and the third ground wiring 170G via wiring 112G.

[0024] The first switch 104 switches the connection between wiring 107P and wiring 110P, and between wiring 107G and wiring 110G, based on the control signal input from the control circuit 101. In other words, the first switch 104 switches the connection between the power supply path of the first circuit block 120 and the first shared wiring 102 and the second shared wiring 103.

[0025] The second switch 105 switches the connection and disconnection between wiring 108P and wiring 111P, and between wiring 108G and wiring 111G, based on the control signal input from the control circuit 101. In other words, the second switch 105 switches the connection and disconnection between the power supply path of the second circuit block 130 and the first shared wiring 102 and the second shared wiring 103.

[0026] The third switch 106 switches the connection between wiring 109P and wiring 112P, and between wiring 109G and wiring 112G, based on the control signal input from the control circuit 101. In other words, the third switch 106 switches the connection between the power supply path of the third circuit block 140 and the first shared wiring 102 and the second shared wiring 103.

[0027] Next, we will explain the switches with reference to Figure 2. Here, the first switch 104 will be explained as an example of a switch. The configuration of the second switch 105 and the third switch 106 is the same as that of the first switch 104.

[0028] The first switch 104 shown in Figure 2 is realized by an NMOS (Negative-channel Metal-Oxide-Semiconductor Transistor) transistor 104a, a PMOS (Positive-channel Metal-Oxide-Semiconductor Transistor) transistor 104b, and an inverter circuit 104c.

[0029] The NMOS transistor 104a is a type of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with a metal-oxide-semiconductor structure. Because the NMOS transistor 104a operates using electrons as carriers, it can operate at high speeds and is used in many electronic circuits. The operation of the NMOS transistor 104a is controlled by the voltage applied to the gate. When the input to the gate (applied voltage) is HIGH, the source and drain of the NMOS transistor 104a are conducting. Conversely, when the input to the gate (applied voltage) is LOW, the resistance between the source and drain of the NMOS transistor becomes high, resulting in an open circuit. Here, HIGH indicates that the applied voltage to the gate exceeds a predetermined value, and LOW indicates that the applied voltage is below a predetermined value.

[0030] The PMOS transistor 104b is a type of MOSFET. The PMOS transistor 104b uses holes as a carrier and operates when a negative voltage is applied to the gate. The PMOS transistor 104b is mainly used in CMOS circuits in combination with NMOS transistors. When the input to the gate of the PMOS transistor 104b is LOW, the source and drain conduct, and when it is HIGH, the resistance between the source and drain becomes high and it is disconnected.

[0031] A control signal is input to the gate of the NMOS transistor 104a via the signal line SG1. Additionally, a control signal is input to the gate of the PMOS transistor 104b via both the signal line SG1 and the inverter circuit 203.

[0032] The inverter circuit 104c is a digital circuit that inverts the logic state of the input signal. The inverter circuit outputs HIGH when LOW is input and LOW when HIGH is input. Therefore, when the control signal is HIGH, the gate of NMOS transistor 201 is HIGH and the gate of PMOS transistor 202 is LOW. As a result, wire 107P conducts to wire 110P, and wire 107G conducts to wire 110G.

[0033] Furthermore, when the control signal is LOW, the gate of NMOS transistor 104a is LOW and the gate of PMOS transistor 104b is HIGH. This disconnects wires 107G and 110G.

[0034] Next, the switch control by the control circuit 101 will be explained with reference to Figures 3 to 5. Figure 3 is a diagram showing an example of an operation table held by the control circuit 101. Figure 4 is a diagram showing the changes in the operating state in the first circuit block 120 and the third circuit block 140, and is a representation of the operation table in Figure 3 as a timing chart. Figure 4(a) shows the operating state in the first circuit block 120 and the third circuit block 140, and Figure 4(b) shows the operating state in the third circuit block 140. Figure 5 is a diagram showing the control table held by the control circuit.

[0035] As shown in Figure 3, the operation table of the control circuit 101 maintains the operating state of each of the multiple circuit blocks over time. The operating states of the circuit blocks include at least a stopped state, normal operation at the first power supply voltage, and low-power operation at a second power supply voltage lower than the first power supply voltage. By referring to the operation table, the control circuit 101 can determine which circuit block is in what state at a given time.

[0036] In this embodiment, the second circuit block 130 and the third circuit block 140 are circuit blocks that have low tolerance to dynamic voltage drops generated in the first circuit block 120 and are prone to malfunction. Therefore, they need to be controlled to avoid being affected by dynamic voltage drops caused by the first shared wiring 102 and the second shared wiring 103 conducting to the power supply path when other circuit blocks are operating.

[0037] Therefore, in this embodiment, the control circuit 101 holds a predefined control rule that describes the relationship between the combination of operating states of each of the multiple circuit blocks and the ON / OFF switching control of the switches (first switch 104, second switch 105, third switch 106).

[0038] The control rules are described below. Here, it is assumed that when the operating state of the first circuit block 120 is low-power operation, the dynamic voltage drop effect on other blocks due to the conduction of the first shared wiring 102 and the second shared wiring 103 is low and no malfunction occurs. In this case, the control rules may be defined to include, for example, the following rules 1 to 4.

[0039] • Specific examples of control rules (1) Rule 1: Of the first circuit block 120 and the third circuit block 140, the circuit block whose operating state is stopped is connected to the first shared wiring 102 and the second shared wiring 103. Rule 2: If the operation state of the first circuit block 120 and the third circuit block 140 is stopped, the first circuit block 120 and the third circuit block 140 are connected to the first shared wiring 102 and the second shared wiring 103. Rule 3: When the first circuit block 120, the second circuit block 130, and the third circuit block 140 are operating in normal operation or low power operation mode, the circuit block among the multiple circuit blocks that is operating in low power operation mode is connected to the first shared wiring 102 and the second shared wiring 103. Rule 4: The third circuit block 140 is not connected to the first shared wiring 102 and the second shared wiring 103, even in the low power consumption state.

[0040] The control rules may also be defined as shown in the following specific examples (2), (3), and (4). The content and number of control rules can be arbitrarily changed considering the configuration of the circuit block.

[0041] • Specific examples of control rules (2) Rule 1: Of the first circuit block 120 and the third circuit block 140, the circuit block whose operating state is stopped is connected to the first shared wiring 102 and the second shared wiring 103. Rule 2: When the first circuit block and the third circuit block are in a stopped state, the first circuit block 120 and the third circuit block 140 are not connected to the first shared wiring 102 and the second shared wiring 103. Rule 3: When the first circuit block 120, the second circuit block 130, and the third circuit block 140 are operating in normal operation or low power operation mode, the circuit block among the multiple circuit blocks that is operating in low power operation mode is connected to the first shared wiring 102 and the second shared wiring 103. Rule 4: The third circuit block 140 is not connected to the first shared wiring 102 and the second shared wiring 103, even in the low power consumption state. Specific example (2) differs from specific example (1) in its approach to Rule 2.

[0042] • Specific examples of control rules (3) Rule 1: Of the first circuit block 120 and the third circuit block 140, the circuit block whose operating state is stopped is connected to the first shared wiring 102 and the second shared wiring 103. Rule 2: When all of the operating states of multiple circuit blocks are in a stopped state, do not connect all of the multiple circuit blocks (first circuit block 120, second circuit block 130, third circuit block 140) to the first shared wiring 102 and the second shared wiring 103. Rule 3: When the first circuit block 120, the second circuit block 130, and the third circuit block 140 are operating in normal operation or low power operation mode, the circuit block among the multiple circuit blocks that is operating in low power operation mode is connected to the first shared wiring 102 and the second shared wiring 103. Specific example (3) differs from specific example (1) in that rule 2 has been modified and rule 4 has been removed.

[0043] • Specific examples of control rules (4) Rule 1: Of the first circuit block 120 and the third circuit block 140, the circuit block whose operating state is stopped is connected to the first shared wiring 102 and the second shared wiring 103. Rule 2: When all of the operating states of multiple circuit blocks are in a stopped state, do not connect all of the multiple circuit blocks (first circuit block 120, second circuit block 130, third circuit block 140) to the first shared wiring 102 and the second shared wiring 103. Specific example (4) differs from specific example (1) in that rule 2 has been modified and rules 3 and 4 have been removed.

[0044] The control circuit 101 generates and maintains the control table shown in Figure 5 based on the control rules described above and the operation table shown in Figure 4. Then, according to the control table, the control circuit 101 transmits LOW and HIGH control signals to the first switch 104, the second switch 105, and the third switch 106, respectively. As a result, the control circuit 101 lowers the potential of at least one of the multiple circuit blocks, or raises the potential of at least one of the multiple circuit blocks.

[0045] Next, the operation of the control circuit 101 at times t1 to t10 will be explained with reference to Figures 3 and 5. Here, control rules 1 to 4 from the specific example (1) described above will be used. In Figure 5, ON indicates that the switch corresponding to the circuit block is conductive and the power supply path of the circuit block is connected to the shared wiring. OFF indicates that the switch corresponding to the circuit block is disconnected and the power supply path of the circuit block is not connected to the shared wiring. In this embodiment, the initial state of the first switch 104 to the third switch 106 is all OFF.

[0046] Referring to the operation table in Figure 3, at time t1, the operating states of both the first circuit block 120 and the third circuit block 140 are in the stopped state. In this case, according to rule 2 of the control rules, the control circuit 101 determines the ON / OFF states of the first switch 104, the second switch 105, and the third switch 106 in the control table shown in Figure 5 to be {ON,ON,ON} at time t1. Then, the control circuit 101 transmits a control signal to conduct all power switches.

[0047] At time t2, the operating state of the first circuit block 120 is normal operation, and the operating state of the third circuit block 140 is stopped. In this case, according to rule 1 of the control rules, the control circuit 101 determines the ON / OFF states of the first switch 104, the second switch 105, and the third switch 106 in the control table to {OFF, ON, ON} at time t2. Then, the control circuit 101 disconnects the first switch 104 and transmits a control signal to open the second switch 105 and the third switch 106.

[0048] At time t3, both the first circuit block 120 and the third circuit block 140 are operating normally. In this case, according to control rules 1 and 3, the control circuit 101 determines the ON / OFF states of the first switch 104, the second switch 105, and the third switch 106 in the control table to {OFF, OFF, OFF} at time t3. Then, the control circuit 101 sends control signals to disconnect the first switch 104, the second switch 105, and the third switch 106.

[0049] At time t4, the operating state of the first circuit block 120 is stopped, and the operating state of the third circuit block 140 is normal operation. In this case, according to rule 1 of the control rules, the control circuit 101 determines the ON / OFF states of the first switch 104, the second switch 105, and the third switch 106 in the control table to {ON, ON, OFF} at time t4. Then, the control circuit 101 transmits a control signal to connect the first switch 104 and the second switch 105, and disconnect the third switch 106.

[0050] At time t5, the operating state of both the first circuit block 120 and the third circuit block 140 is stopped. In this case, according to rule 2 of the control rules, the control circuit 101 determines the ON / OFF state of the first switch 104, the second switch 105, and the third switch 106 in the control table to {ON, ON, ON} at time t5. Then, the control circuit 101 transmits a control signal to make all power switches conduct.

[0051] At time t6, the operating state of the first circuit block 120 is low-power operation, and the operating state of the third circuit block 140 is stopped. In this case, according to rule 3 of the control rules, the control circuit 101 determines the ON / OFF states of the first switch 104, the second switch 105, and the third switch 106 in the control table to {OFF, ON, ON} at time t6. Then, the control circuit 101 disconnects the first switch 104 and transmits a control signal to open the second switch 105 and the third switch 106.

[0052] At time t7, the operating state of the first circuit block 120 is low-power operation, and the operating state of the third circuit block 140 is normal operation. In this case, according to control rules 1 and 3, the control circuit 101 determines the ON / OFF states of the first switch 104, the second switch 105, and the third switch 106 in the control table to {ON, ON, OFF} at time t7. Then, the control circuit 101 transmits a control signal to conduct to the first switch 104 and the second switch 105, and to disconnect the third switch 106.

[0053] At time t8, the operating state of the first circuit block 120 is stopped, and the operating state of the third circuit block 140 is normal operation. In this case, according to rule 1 of the control rules, the control circuit 101 determines the ON / OFF states of the first switch 104, the second switch 105, and the third switch 106 in the control table to {ON, ON, OFF} at time t8. Then, the control circuit 101 transmits a control signal to connect the first switch 104 and the second switch 105, and to disconnect the third switch 106.

[0054] At time t9, both the first circuit block 120 and the third circuit block 140 are operating normally. In this case, according to control rules 1 and 3, the control circuit 101 determines the ON / OFF states of the first switch 104, the second switch 105, and the third switch 106 in the control table to {OFF, OFF, OFF} at time t9. Then, the control circuit 101 sends control signals to disconnect the first switch 104, the second switch 105, and the third switch 106.

[0055] At time t10, the operating state of the first circuit block 120 is normal operation, and the operating state of the third circuit block 140 is low-power operation. In this case, according to control rules 3 and 4, the control circuit 101 determines the ON / OFF states of the first switch 104, the second switch 105, and the third switch 106 in the control table to {OFF,OFF,OFF} at time t10. Then, the control circuit 101 transmits a control signal to connect the first switch 104 and the second switch 105, and to disconnect the third switch 106.

[0056] According to the semiconductor integrated circuit 1 of this embodiment, the first switch 104 to the third switch 106 are controlled by referring to a predefined control rule and operation table. This reduces the difference in power supply voltage between multiple circuit blocks, even if a voltage drop occurs in any of the multiple circuit blocks. As a result, malfunctions in the semiconductor integrated circuit 1 can be suppressed.

[0057] (Second Embodiment) The following describes a semiconductor integrated circuit according to the second embodiment. The semiconductor integrated circuit according to the second embodiment differs from the first embodiment in that it has a function to control a switch based on the voltage value detected in each of the multiple circuit blocks.

[0058] Figure 6 is a circuit diagram showing a semiconductor integrated circuit 2 according to the second embodiment. The semiconductor integrated circuit 2 further includes a first voltage extraction circuit 125 in the first circuit block 120, a second voltage extraction circuit 135 in the second circuit block 130, and a third voltage extraction circuit 145 in the third circuit block 140. The other configurations are the same as in the first embodiment.

[0059] The first voltage extraction circuit 125 extracts the voltage value of the first circuit block 120. The second voltage extraction circuit 135 extracts the voltage value of the second circuit block 130. The third voltage extraction circuit 145 extracts the voltage value of the third circuit block 140.

[0060] The first voltage extraction circuit 125, the second voltage extraction circuit 135, and the third voltage extraction circuit 145 each input the extracted voltages to the control circuit 101. The control circuit 101 calculates the voltage difference between the circuit blocks from the voltages input from each of the first, second, and third voltage extraction circuits 125, 135, and 145. The control circuit 101 also has a threshold value for determining whether or not there is a problem with the voltage difference between the circuit blocks.

[0061] In this embodiment, the control circuit 101 has a first threshold for determining whether there is a problem with the voltage difference between the first circuit block 120 and the second circuit block 130, and a second threshold for determining whether there is a problem with the voltage difference between the second circuit block 130 and the third circuit block 140. "A problem with the voltage difference" means that the voltage difference can affect the signals transmitted between the circuit blocks.

[0062] In this embodiment, a problem is determined if the voltage difference between the first circuit block 120 and the second circuit block 130 is 0.4V or more, which is the first threshold, and a problem is determined if the voltage difference between the second circuit block 130 and the third circuit block 140 is 0.5V or more, which is the second threshold.

[0063] If the control circuit 101 determines that there is a problem with the voltage difference, it sends a control signal to turn on a switch so that the power supplies between the circuit blocks become conductive via the first shared wiring 102 and the second shared wiring 103, thereby reducing the voltage difference between the circuits.

[0064] Furthermore, if no problem is detected, the control circuit 101 sends a control signal to turn off the switch so that the power supplies between the circuit blocks do not conduct through the first shared wiring 102 and the second shared wiring 103.

[0065] Next, the specific operation of the semiconductor integrated circuit 2 according to the second embodiment will be explained using Figure 7. Figure 7 is a diagram showing an example of voltage values ​​over time in multiple circuit blocks. In this embodiment, the initial state of the first switch 104 to the third switch 106 is all OFF.

[0066] At time T1, the voltage extraction results from the first voltage extraction circuit 125, the second voltage extraction circuit 135, and the third voltage extraction circuit 145 are all 1.2V, and the voltage difference between the circuit blocks is 0V. Therefore, the control circuit 101 determines that there is no problem with the voltage difference and does not send control signals to the first switch 104 to the third switch 106.

[0067] At time T2, the voltage difference between the first circuit block 120 and the second circuit block 130 is 0.4V, so the control circuit 101 determines that there is a problem with the voltage difference between the first circuit block 120 and the second circuit block 130. Also, the voltage difference between the second circuit block 130 and the third circuit block 140 is 0.4V, so the control circuit 101 determines that there is no problem with the voltage difference between the second circuit block 130 and the third circuit block 140. Therefore, the control circuit 101 sends ON control signals to the first switch 104 and the second switch 105, causing them to conduct. As a result, the control circuit 101 reduces the voltage difference between the first circuit block 120 and the second circuit block 130.

[0068] At time T3, the voltage difference between the first circuit block 120 and the second circuit block 130 is 0.5V, so the control circuit 101 determines that there is a problem with the voltage difference between the first circuit block 120 and the second circuit block 130. Also, the voltage difference between the second circuit block 130 and the third circuit block 140 is 0.2V, so the control circuit 101 determines that there is no problem with the voltage difference between the second circuit block 130 and the third circuit block 140. Therefore, the control circuit 101 sends ON control signals to the first switch 104 and the second switch 105, causing them to conduct. As a result, the control circuit 101 reduces the voltage difference between the first circuit block 120 and the second circuit block 130.

[0069] At time T4, the voltage difference between the first circuit block 120 and the second circuit block 130 is 0.1V, so the control circuit 101 determines that there is no problem with the voltage difference between the first circuit block 120 and the second circuit block 130. Also, the voltage difference between the second circuit block 130 and the third circuit block 140 is 0.5V, so the control circuit 101 determines that there is a problem with the voltage difference between the second circuit block 130 and the third circuit block 140. Therefore, the control circuit 101 sends ON control signals to the second switch 105 and the third switch 106, causing them to conduct. As a result, the control circuit 101 reduces the voltage difference between the second circuit block 130 and the third circuit block 140.

[0070] At time T5, the voltage difference between the first circuit block 120 and the second circuit block 130 is 0.2V, so the control circuit 101 determines that there is no problem with the voltage difference between the first circuit block 120 and the second circuit block 130. Also, the voltage difference between the second circuit block 130 and the third circuit block 140 is 0.4V, so the control circuit 101 determines that there is no problem with the voltage difference between the second circuit block 130 and the third circuit block 140. Therefore, the control circuit 101 sends OFF control signals to the first switch 104 to the third switch 106, respectively, and disconnects the connection to the shared wiring.

[0071] According to the semiconductor integrated circuit 2 of this embodiment, the switch is controlled based on the voltage values ​​extracted from multiple circuit blocks. This reduces the difference in power supply voltage between multiple circuit blocks. As a result, malfunctions in the semiconductor integrated circuit 2 can be suppressed.

[0072] [Modified Embodiment] This disclosure is not limited to the embodiments described above and can be modified in various ways. For example, an example in which some components of one embodiment are added to another embodiment, or in which some components of another embodiment are replaced, is also an embodiment of this disclosure. Furthermore, the effects described in the embodiments are merely a list of the most preferred effects that result from this disclosure, and the effects of this disclosure are not limited to those described in the embodiments.

[0073] In the first embodiment, a configuration was described in which the semiconductor integrated circuit 1 has multiple input sections, and the regulator 200 provided externally is connected to the multiple input sections in a one-to-many relationship via branch wiring. However, the semiconductor integrated circuit may also have a configuration in which only one input section is provided. Figure 8 is a circuit diagram showing a semiconductor integrated circuit 3 according to a modified example of the first embodiment. Here, the substrate power wiring 200P and the substrate ground wiring 200G are connected by a single input section 180 provided on the semiconductor integrated circuit 1. In addition, inside the semiconductor integrated circuit 3, wirings 185P and 185G are provided, each branching into three at one end. Wiring 185P connects the input section 180 to the first power wiring 150P, the second power wiring 160P, and the third power wiring 170P. Wiring 185G connects the input section 180 to the first ground wiring 150G, the second ground wiring 160G, and the third ground wiring 170G.

[0074] Furthermore, in the second embodiment, switch control based on actual voltage values ​​in the circuit block was described without using the control rules described in the first embodiment. The configuration for extracting voltage values ​​may be used in conjunction with the control rules and operation tables to control the ON / OFF state of each switch.

[0075] Furthermore, in the second embodiment, the control circuit 101 performed switch control and voltage adjustment by comparing the difference between the voltage value of the first circuit block 120 and the voltage value of the second circuit block 130, and the difference between the voltage value of the second circuit block 130 and the voltage value of the third circuit block 140, with thresholds. However, instead of comparing the voltage difference between blocks, the control circuit 101 may perform switch control and voltage adjustment by comparing the voltage value in each circuit block with a predetermined threshold. That is, the control circuit 101 may be configured to raise the potential of circuit blocks whose voltage value is below a threshold among a plurality of circuit blocks. Alternatively, the control circuit 101 may be configured to lower the potential of circuit blocks whose voltage value exceeds a threshold among a plurality of circuit blocks.

[0076] This disclosure includes the following components: (Composition 1) Multiple power supply paths that supply power voltage, Multiple circuit blocks from which the power supply voltage is supplied from the multiple power supply paths, A switch for switching connections to the aforementioned multiple power supply paths, A shared wiring is provided that can be connected to the multiple power supply paths via the aforementioned switch, A control circuit for controlling the switch, A semiconductor integrated circuit characterized by comprising the following features. (Configuration 2) The semiconductor integrated circuit according to configuration 1, further comprising a plurality of input sections provided corresponding to each of the plurality of power supply paths, to which the power supply voltage is supplied from a power supply means provided outside the semiconductor integrated circuit. (Composition 3) The semiconductor integrated circuit further comprises an input section to which the power supply voltage is supplied from a power supply means provided outside the semiconductor integrated circuit, The aforementioned multiple power supply paths are connected to the input unit. A semiconductor integrated circuit according to configuration 1, characterized by the features described above. (Composition 4) The control circuit controls the switch based on the operating state of each of the plurality of circuit blocks. A semiconductor integrated circuit according to any one of configurations 1 to 3, characterized by the above. (Composition 5) The semiconductor integrated circuit according to any one of configurations 1 to 4, characterized in that the control circuit lowers the potential of at least one of the plurality of circuit blocks. (Composition 6) The semiconductor integrated circuit according to any one of configurations 1 to 4, characterized in that the control circuit raises the potential of at least one of the plurality of circuit blocks. (Composition 7) The semiconductor integrated circuit according to any one of configurations 1 to 4, characterized in that the control circuit holds a control rule that pre-defines the relationship between the combination of operating states of each of the plurality of circuit blocks and the ON / OFF switching control of the switch. (Composition 8) The semiconductor integrated circuit according to configuration 7, characterized in that the control circuit maintains the operating state of each of the plurality of circuit blocks over time. (Composition 9) The control circuit controls the switch at intervals based on the control rule and the operating state. A semiconductor integrated circuit according to configuration 8, characterized by the above. (Composition 10) The aforementioned operating states include at least a stopped state, normal operation operating at a first power supply voltage, and low-power operation operating at a second power supply voltage lower than the first power supply voltage. A semiconductor integrated circuit according to configuration 9, characterized by the features described therein. (Composition 11) The system further includes a voltage extraction circuit that extracts voltage values ​​from each of the aforementioned multiple circuit blocks. The control circuit controls the switch based on the extracted voltage value. A semiconductor integrated circuit according to any one of configurations 1 to 3, characterized by the above. (Composition 12) The control circuit lowers the potential of the circuit block whose voltage value exceeds the threshold among the plurality of circuit blocks. A semiconductor integrated circuit according to configuration 11, characterized by the features described above. (Composition 13) The control circuit raises the potential of the circuit block whose voltage value is below a threshold among the plurality of circuit blocks. A semiconductor integrated circuit according to configuration 11 or 12, characterized by the above. (Composition 14) The aforementioned plurality of circuit blocks consist of a first circuit block, a second circuit block, and a third circuit block. The control circuit connects the circuit block whose operating state is the stopped state among the first and third circuit blocks to the shared wiring. A semiconductor integrated circuit according to configuration 10, characterized by the above. (Composition 15) The aforementioned plurality of circuit blocks consist of a first circuit block, a second circuit block, and a third circuit block. The control circuit connects the first circuit block and the third circuit block to the shared wiring when the operating state of the first circuit block and the third circuit block is the stopped state. A semiconductor integrated circuit according to configuration 10, characterized by the above. (Composition 16) The aforementioned plurality of circuit blocks consist of a first circuit block, a second circuit block, and a third circuit block. The control circuit, when the operating state of the first circuit block, the second circuit block, and the third circuit block is the normal operation or the low-power operation, connects the circuit block among the plurality of circuit blocks whose operating state is the low-power operation to the shared wiring. A semiconductor integrated circuit according to configuration 10, characterized by the above. (Composition 17) The aforementioned plurality of circuit blocks consist of a first circuit block, a second circuit block, and a third circuit block. The control circuit, when the first circuit block and the third circuit block are in the stopped state, does not connect the first circuit block and the third circuit block to the shared wiring. A semiconductor integrated circuit according to configuration 10, characterized by the above. (Composition 18) The aforementioned plurality of circuit blocks consist of a first circuit block, a second circuit block, and a third circuit block. The control circuit, when the operating state of all of the plurality of circuit blocks is the stopped state, does not connect all of the plurality of circuit blocks to the shared wiring. A semiconductor integrated circuit according to configuration 10, characterized by the above. (Composition 19) The aforementioned switch is composed of an NMOS transistor and a PMOS transistor. A semiconductor integrated circuit according to any one of configurations 1 to 18, characterized by the above. (Composition 20) A semiconductor integrated circuit as described in any of configurations 1 to 19, A regulator that supplies the power supply voltage to the semiconductor integrated circuit, An electronic device characterized by having the following features. [Explanation of symbols]

[0077] 1,2,3 Semiconductor integrated circuits 100 Potential difference adjustment circuit 101 Control circuit 102 1st shared wiring 103 2nd shared wiring 104 Switch 1 105 Second switch 106 Third switch 120 First Circuit Block 121 1st signal passing circuit 122 Signal Output Circuit 130 Second Circuit Block 131 2nd signal passing circuit 140 Third Circuit Block 141 Third signal passing circuit 142 Signal Input Circuit 150P 1st power wiring 150G 1st Ground Wiring 160P 2nd power wiring 160G Second Ground Wiring 170P 3rd power supply wiring 170G Third Ground Wiring 180 Input section 181 First Input Section 182 Second Input Section 183 Third Input Section 200 Regulator 200P PCB power wiring 200G PCB ground wiring

Claims

1. Multiple power supply paths that supply power voltage, Multiple circuit blocks from which the power supply voltage is supplied from the multiple power supply paths, A switch for switching connections to the aforementioned multiple power supply paths, A shared wiring is provided that can be connected to the multiple power supply paths via the aforementioned switch, A control circuit for controlling the switch, A semiconductor integrated circuit characterized by comprising the following features.

2. The semiconductor integrated circuit according to claim 1, further comprising a plurality of input sections provided corresponding to each of the plurality of power supply paths, to which the power supply voltage is supplied from a power supply means provided outside the semiconductor integrated circuit.

3. The semiconductor integrated circuit further comprises an input section to which the power supply voltage is supplied from a power supply means provided outside the semiconductor integrated circuit, The aforementioned multiple power supply paths are connected to the input unit. The semiconductor integrated circuit according to feature 1.

4. The control circuit controls the switch based on the operating state of each of the plurality of circuit blocks. The semiconductor integrated circuit according to feature 1.

5. The semiconductor integrated circuit according to claim 1, characterized in that the control circuit lowers the potential of at least one of the plurality of circuit blocks.

6. The semiconductor integrated circuit according to claim 1, characterized in that the control circuit raises the potential of at least one of the plurality of circuit blocks.

7. The semiconductor integrated circuit according to claim 1, characterized in that the control circuit holds a control rule that pre-defines the relationship between the combination of operating states of each of the plurality of circuit blocks and the ON / OFF switching control of the switch.

8. The semiconductor integrated circuit according to claim 7, characterized in that the control circuit maintains the operating state of each of the plurality of circuit blocks over time.

9. The control circuit controls the switch at intervals based on the control rule and the operating state. The semiconductor integrated circuit according to feature 8.

10. The aforementioned operating states include at least a stopped state, normal operation operating at a first power supply voltage, and low-power operation operating at a second power supply voltage lower than the first power supply voltage. The semiconductor integrated circuit according to feature 9.

11. The system further includes a voltage extraction circuit that extracts voltage values ​​from each of the aforementioned multiple circuit blocks. The control circuit controls the switch based on the extracted voltage value. The semiconductor integrated circuit according to feature 1.

12. The control circuit lowers the potential of the circuit block whose voltage value exceeds the threshold among the plurality of circuit blocks. The semiconductor integrated circuit according to feature 11.

13. The control circuit raises the potential of the circuit block whose voltage value is below a threshold among the plurality of circuit blocks. The semiconductor integrated circuit according to feature 11.

14. The aforementioned plurality of circuit blocks consist of a first circuit block, a second circuit block, and a third circuit block. The control circuit connects the circuit block whose operating state is the stopped state among the first and third circuit blocks to the shared wiring. The semiconductor integrated circuit according to feature 10.

15. The aforementioned plurality of circuit blocks consist of a first circuit block, a second circuit block, and a third circuit block. The control circuit connects the first circuit block and the third circuit block to the shared wiring when the operating state of the first circuit block and the third circuit block is the stopped state. The semiconductor integrated circuit according to feature 10.

16. The aforementioned plurality of circuit blocks consist of a first circuit block, a second circuit block, and a third circuit block. The control circuit, when the operating state of the first circuit block, the second circuit block, and the third circuit block is the normal operation or the low-power operation, connects the circuit block among the plurality of circuit blocks whose operating state is the low-power operation to the shared wiring. The semiconductor integrated circuit according to feature 10.

17. The aforementioned plurality of circuit blocks consist of a first circuit block, a second circuit block, and a third circuit block. The control circuit, when the first circuit block and the third circuit block are in the stopped state, does not connect the first circuit block and the third circuit block to the shared wiring. The semiconductor integrated circuit according to feature 10.

18. The aforementioned plurality of circuit blocks consist of a first circuit block, a second circuit block, and a third circuit block. The control circuit, when the operating state of all of the plurality of circuit blocks is the stopped state, does not connect all of the plurality of circuit blocks to the shared wiring. The semiconductor integrated circuit according to feature 10.

19. The aforementioned switch is composed of an NMOS transistor and a PMOS transistor. The semiconductor integrated circuit according to feature 1.

20. A semiconductor integrated circuit according to any one of claims 1 to 19, A regulator that supplies the power supply voltage to the semiconductor integrated circuit, An electronic device characterized by having the following features.

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