Semiconductor device and method for manufacturing a semiconductor device

JP2026131278APending Publication Date: 2026-08-14FUJITSU LTD
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Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
Filing Date
2025-02-03
Publication Date
2026-08-14

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【0007】 本開示によれば、オン時の電気抵抗を低減することができる。

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Abstract

The present invention provides a semiconductor device and a method for manufacturing a semiconductor device that can reduce electrical resistance when the device is turned on. [Solution] The semiconductor device comprises a barrier layer and a channel layer, an anode electrode that makes Schottky contact with the channel layer, and a cathode electrode that makes ohmic contact with the channel layer, wherein the channel layer is located between the barrier layer and the anode electrode, and the channel layer comprises an n-type first region, an n-type second region located between the first region and the anode electrode and in contact with the first region and the anode electrode, and a p-type third region located between the first region and the anode electrode and in contact with the first region, the second region and the anode electrode.
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Claims

1. Barrier layer and channel layer, The anode electrode that makes Schottky contact with the channel layer, A cathode electrode that makes ohmic contact with the channel layer, It has, The channel layer is located between the barrier layer and the anode electrode. The aforementioned channel layer is n-type first region, An n-type second region is located between the first region and the anode electrode and is in contact with the first region and the anode electrode, A p-type third region is located between the first region and the anode electrode and is in contact with the first region, the second region and the anode electrode, Semiconductor device.

2. The channel layer has a plurality of the second region and the third region, The semiconductor device according to claim 1, wherein the second region and the third region are arranged alternately in a plan view.

3. The semiconductor device according to claim 1 or 2, wherein the surface of the barrier layer facing the channel layer has nitrogen polarity.

4. The aforementioned barrier layer is Al x Ga 1-x It is an N-layer structure (0 < x ≤ 1), The semiconductor device according to claim 1 or 2, wherein the channel layer is a GaN layer.

5. Having a substrate, The semiconductor device according to claim 1 or 2, wherein the barrier layer is located between the substrate and the channel layer.

6. The semiconductor device according to claim 1 or 2, wherein the channel layer is located between the anode electrode and the cathode electrode in a plan view and has a p-type termination region that contacts the third region.

7. The semiconductor device according to claim 6, wherein the thickness of the termination region is smaller than the thickness of the third region.

8. A process of forming a barrier layer on a substrate, The steps include forming an n-type channel layer on the barrier layer, A step of forming an anode electrode that makes Schottky contact with the channel layer, A step of forming a cathode electrode that makes ohmic contact with the channel layer, It has, Between the step of forming the channel layer and the step of forming the anode electrode, By ion implanting p-type impurities into the channel layer, n-type first region, An n-type second region is located between the first region and the anode electrode and is in contact with the first region and the anode electrode, A p-type third region is located between the first region and the anode electrode and is in contact with the first region, the second region and the anode electrode, The process of forming, A step of activating the aforementioned p-type impurity, A method for manufacturing a semiconductor device having [a certain feature].

9. Between the step of forming the first region, the second region, and the third region, and the step of activating the p-type impurity, The method for manufacturing a semiconductor device according to claim 8, further comprising the step of ion implanting p-type impurities into the channel layer to form a p-type termination region in the channel layer that is located between the anode electrode and the cathode electrode in a plan view and in contact with the third region.

Citation Information

Patent Citations

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  • Vertical gallium nitride schottky diode

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