Semiconductor device and method for manufacturing a semiconductor device

Abstract

The objective is to provide a semiconductor device in which trenches can be filled with an interlayer insulating film. [Solution] The semiconductor device according to the present disclosure comprises a semiconductor substrate having a cell portion and an outer peripheral portion outside the cell portion; a gate electrode provided inside a trench formed on the upper surface of the cell portion; a cell portion interlayer film provided on the gate electrode inside the trench; an outer peripheral portion interlayer film provided on the upper surface of a mesa portion adjacent to the trench in the outer peripheral portion; and a main electrode provided on the cell portion interlayer film and the outer peripheral portion interlayer film, and in contact with the cell portion interlayer film and the outer peripheral portion interlayer film, wherein the cell portion interlayer film comprises a first cell portion interlayer film provided on the gate electrode and a second cell portion interlayer film provided on the first cell portion interlayer film and in contact with the main electrode, and one of the first cell portion interlayer film and the second cell portion interlayer film contains an impurity.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device.

Background Art

[0002] Patent Document 1 discloses a semiconductor device having a trench gate structure. In the trench gate structure, a gate electrode is disposed in a trench via a gate insulating film. Further, the trench is filled with an interlayer insulating film.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In order to reduce the on-resistance of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or the like, it is desirable to reduce the cell pitch. However, in a semiconductor device with a narrow cell pitch, it may be difficult to fill the trench with an interlayer insulating film as in Patent Document 1.

[0005] This disclosure has been made to solve the above-described problems, and an object thereof is to provide a semiconductor device in which a trench can be filled with an interlayer insulating film.

Means for Solving the Problems

[0006] A semiconductor device according to this disclosure comprises a semiconductor substrate having a cell portion and an outer peripheral portion outside the cell portion; a gate electrode provided inside a trench formed on the upper surface of the cell portion; a cell portion interlayer film provided on the gate electrode inside the trench; an outer peripheral portion interlayer film provided on the upper surface of a mesa portion adjacent to the trench in the outer peripheral portion; and a main electrode provided on the cell portion interlayer film and the outer peripheral portion interlayer film, and in contact with the cell portion interlayer film and the outer peripheral portion interlayer film, wherein the cell portion interlayer film has a first cell portion interlayer film provided on the gate electrode and a second cell portion interlayer film provided on the first cell portion interlayer film and in contact with the main electrode, and one of the first cell portion interlayer film and the second cell portion interlayer film contains an impurity.

[0007] The semiconductor device according to this disclosure comprises a semiconductor substrate having a cell portion and an outer peripheral portion outside the cell portion; a gate electrode provided inside a trench formed on the upper surface of the cell portion; a cell portion interlayer film provided on the gate electrode inside the trench; an outer peripheral interlayer film provided on the upper surface of a mesa portion adjacent to the trench in the outer peripheral portion; and a main electrode provided on the cell portion interlayer film and the outer peripheral interlayer film, in contact with the cell portion interlayer film and the outer peripheral interlayer film, wherein the cell portion interlayer film contains impurities, and the outer peripheral interlayer film has a first outer peripheral interlayer film and a second outer peripheral interlayer film provided on the first outer peripheral interlayer film and in contact with the main electrode, wherein the portion of the upper surface of the outer peripheral interlayer film directly above the mesa portion and the end face of the outer peripheral interlayer film above the mesa portion are formed of the same type of interlayer film.

[0008] A method for manufacturing a semiconductor device according to the present disclosure, comprising a semiconductor substrate having a cell portion and an outer peripheral portion outside the cell portion, wherein a trench is formed on the upper surface of the cell portion, a gate electrode is formed inside the trench, a first interlayer film is formed on the upper surface of the semiconductor substrate extending from the cell portion to the outer peripheral portion, the first interlayer film is etched so that the first interlayer film remains inside the trench, a second interlayer film is formed on the upper surface of the semiconductor substrate extending from the cell portion to the outer peripheral portion after etching the first interlayer film, a second interlayer film is formed on the upper surface of the semiconductor substrate extending from the cell portion to the outer peripheral portion so that a second interlayer film is formed on the first interlayer film inside the trench, the second interlayer film is etched so that the second interlayer film remains inside the trench and on the outer peripheral portion, and a main electrode is formed on the second interlayer film in contact with the second interlayer film after etching the second interlayer film, and one of the first and second interlayer films contains an impurity. [Effects of the Invention]

[0009] In the semiconductor device and method for manufacturing the semiconductor device according to this disclosure, the trench is filled with an interlayer film containing impurities and having high embedding properties. Therefore, the inside of the trench can be filled with an interlayer insulating film. [Brief explanation of the drawing]

[0010] [Figure 1] This is a cross-sectional view of the semiconductor device according to Embodiment 1. [Figure 2] This is a cross-sectional view showing the semiconductor device according to Embodiment 1 with the main electrode provided. [Figure 3A] This is a diagram illustrating the manufacturing method of a semiconductor device according to Embodiment 1. [Figure 3B] This is a diagram illustrating the manufacturing method of a semiconductor device according to Embodiment 1. [Figure 3C] This is a diagram illustrating the manufacturing method of a semiconductor device according to Embodiment 1. [Figure 3D] This is a diagram illustrating the manufacturing method of a semiconductor device according to Embodiment 1. [Figure 4] This is a flowchart showing the method for manufacturing a semiconductor device according to Embodiment 1. [Figure 5] Cross-sectional view of a semiconductor device according to a modified example of Embodiment 1. [Figure 6] Cross-sectional view of a semiconductor device according to Embodiment 2. [Figure 7] Cross-sectional view showing a state where a main electrode is provided in the semiconductor device according to Embodiment 2. [Figure 8A] Diagram for explaining a method of manufacturing a semiconductor device according to Embodiment 2. [Figure 8B] Diagram for explaining a method of manufacturing a semiconductor device according to Embodiment 2. [Figure 8C] Diagram for explaining a method of manufacturing a semiconductor device according to Embodiment 2. [Figure 8D] Diagram for explaining a method of manufacturing a semiconductor device according to Embodiment 2. [Figure 9] Diagram for explaining a method of manufacturing a semiconductor device according to a first modified example of Embodiment 2. [Figure 10] Cross-sectional view of a semiconductor device according to a second modified example of Embodiment 2. [Figure 11] Cross-sectional view of a semiconductor device according to Embodiment 3. [Figure 12] Planar view of a semiconductor device according to Embodiment 3. [Figure 13] Cross-sectional view of a semiconductor substrate according to Embodiment 4.

Embodiments for Carrying Out the Invention

[0011] The semiconductor devices and the methods of manufacturing the semiconductor devices according to each embodiment will be described with reference to the drawings. The same or corresponding components may be denoted by the same reference numerals, and the repeated description may be omitted.

[0012] Embodiment 1. FIG. 1 is a cross-sectional view of a semiconductor device 100 according to Embodiment 1. FIG. 2 is a cross-sectional view showing a state in which a main electrode 80 is provided on the semiconductor device 100 according to Embodiment 1. The semiconductor device 100 includes a semiconductor substrate 60 having a cell portion 10 which is an active region through which a main current flows, and an outer peripheral portion 30 outside the cell portion 10. The outer peripheral portion 30 is also called a termination region. In FIG. 1, various semiconductor layers and a back surface electrode provided on the semiconductor substrate 60 are omitted. FIGS. 1 and 2 show a boundary portion between the cell portion 10 and the outer peripheral portion 30.

[0013] A trench 12 is formed on the upper surface of the cell portion 10. That is, the trench 12 shown in FIGS. 1 and 2 is the trench 12 on the outermost peripheral portion 30 side among the plurality of trenches 12 formed in the cell portion 10. A mesa portion 18 is a portion between adjacent trenches 12 in the cell portion 10. A gate electrode 16 is provided inside the trench 12. The gate electrode 16 is formed of, for example, polysilicon. Inside the trench 12, a cell interlayer film 20 is provided on the gate electrode 16. The inner wall of the trench 12 is covered with a gate oxide film 14. The gate electrode 16 and the cell interlayer film 20 are in contact with the semiconductor substrate 60 through the gate oxide film 14.

[0014] A mesa portion 38 adjacent to the trench 12 of the cell portion 10 is provided in the outer peripheral portion 30. An outer peripheral interlayer film 40 is provided on the upper surface of the mesa portion 38. The outer peripheral interlayer film 40 is, for example, a single layer.

[0015] An outer peripheral trench 32 is formed on the upper surface of the outer peripheral portion 30 of the semiconductor substrate 60. A gate oxide film 34 is provided inside the outer peripheral trench 32. The inner wall of the outer peripheral trench 32 is covered with the gate oxide film 34. An outer peripheral gate electrode 36 is provided on top of the gate oxide film 34 inside the outer peripheral trench 32. The outer peripheral gate electrode 36 is formed from, for example, polysilicon. An outer peripheral interlayer film 40 is provided on top of the outer peripheral gate electrode 36. In other words, the outer peripheral gate electrode 36 and the outer peripheral interlayer film 40 are in contact with the semiconductor substrate 60 via the gate oxide film 34. The outer peripheral interlayer film 40 is formed so as to ride up from inside the outer peripheral trench 32 onto the mesa portion 38. By forming a trench in the outer peripheral portion 30, irregularities within the wafer surface can be reduced. Therefore, stress caused by steps and other uneven surfaces can be alleviated, improving reliability.

[0016] A main electrode 80 is provided on the cell portion interlayer film 20 and the peripheral portion interlayer film 40, in contact with the cell portion interlayer film 20 and the peripheral portion interlayer film 40. The main electrode 80 is, for example, a source electrode or an emitter electrode. The peripheral portion interlayer film 40 is provided so as to expose a part of the mesa portion 38. The main electrode 80 is in contact with the semiconductor substrate 60 at the exposed portion 39, which is a part of the mesa portion 38 that is exposed from the peripheral portion interlayer film 40. This ensures the contact between the mesa portion 38 and the main electrode 80 required at the boundary between the cell portion 10 and the peripheral portion 30.

[0017] The cell interlayer membrane 20 has a first cell interlayer membrane 21 provided on the gate electrode 16 and a second cell interlayer membrane 22 provided on the first cell interlayer membrane 21 and in contact with the main electrode 80. One of the first cell interlayer membrane 21 and the second cell interlayer membrane 22 contains impurities. In this embodiment, as an example, the first cell interlayer membrane 21 contains impurities, and the second cell interlayer membrane 22 has a lower impurity concentration than the first cell interlayer membrane 21. The second cell interlayer membrane 22 does not have to contain impurities.

[0018] The outer periphery interlayer 40 is formed of an interlayer with a lower impurity concentration than the first cell interlayer 21. The outer periphery interlayer 40 does not need to contain impurities. If the outer periphery interlayer 40 is formed of multiple layers, it is sufficient that the uppermost surface of the outer periphery interlayer 40 that contacts the main electrode 80 is formed of an interlayer with a lower impurity concentration than the first cell interlayer 21. Furthermore, the interlayer forming the uppermost surface of the outer periphery interlayer 40 does not need to contain impurities.

[0019] In this embodiment, two interlayer films are embedded in the trench 12 in the cell portion 10. On the other hand, the outer peripheral interlayer film 40 that overlaps the mesa portion 38 is a single layer. The first cell portion interlayer film 21, the second cell portion interlayer film 22, and the outer peripheral interlayer film 40 are, for example, oxide films. Specifically, the first cell portion interlayer film 21 is, for example, a BPSG (Boron Phosphorus Silicon Glass) film. The second cell portion interlayer film 22 and the outer peripheral interlayer film 40 are, for example, TEOS (Tetra Ethoxy Silane) films.

[0020] Next, a method for manufacturing the semiconductor device 100 will be described. Figures 3A to 3D illustrate the method for manufacturing the semiconductor device 100 according to Embodiment 1. Figure 4 is a flowchart illustrating the method for manufacturing the semiconductor device 100 according to Embodiment 1. For example, an N-type silicon carbide substrate is used as the semiconductor substrate 60. The semiconductor device 100 is formed on a base material on which a silicon carbide epitaxial layer is formed on the silicon carbide substrate. First, impurities are implanted into the epitaxial layer to form a semiconductor layer of any conductive type. For example, Al can be implanted to form a P-type semiconductor layer, and N can be implanted to form an N-type semiconductor layer.

[0021] After impurities are injected, a trenching process is performed to form the trench 12 (Step 1). In the trenching process, first, an oxide film is deposited on the semiconductor substrate 60, and then a resist is deposited. Next, the resist is patterned along the shape of the trench 12. Next, the oxide film is etched using the resist pattern. This allows a hard mask to be formed in the oxide film for forming trenches in the epitaxial layer. Next, silicon carbide is etched through the hard mask. This allows the trench 12 to be formed on the upper surface of the cell portion 10. The trench 12 extends perpendicularly to the semiconductor substrate 60. The outer periphery trench 32 can be formed in the same manner as the trench 12, or simultaneously with the trench 12.

[0022] After the trenching process, impurities may be injected into the bottom of the trench 12 to form a P-type field relaxation layer. By using a hard mask in the trenching process, a P-type field relaxation layer can be selectively formed at the bottom of the trench 12. Providing a field relaxation layer can improve gate reliability. A trench 12 that is substantially perpendicular to the semiconductor substrate 60 allows for more stable formation of the field relaxation layer.

[0023] Next, the hard mask is removed. Then, an impurity implantation process may be performed to further form an N-type or P-type impurity layer in the portion of the trench 12's sidewall perpendicular to the semiconductor substrate 60. In particular, in semiconductor devices with an electric field relaxation layer at the bottom of the trench, it is desirable to form a P-layer on the sidewall of the trench 12 in order to make the potential of the electric field relaxation layer common with the P-layer in the middle of the trench 12.

[0024] In addition, in the cell section 10, an injection process is performed to change a portion of the semiconductor layer that contacts the metal electrode from N-type to P-type. At this time, the gate pull-up portion, in particular, which is surrounded by gate wiring, can cause an increase in leakage current. For this reason, it is desirable to implant impurities so that the gate pull-up portion, including the portion that does not contact the gate wiring, becomes P-type. The reason why N-type semiconductors have a large leakage current is presumed to be because the excess of highly mobile electrons makes them prone to increased leakage current.

[0025] After all impurity implantation steps have been completed, a heat treatment is performed to activate the implanted impurity layer. Following the heat treatment, the desired insulating film formation step and gate oxide film formation step are carried out, respectively. In the gate oxide film formation step, gate oxide films 14 and 34 are formed.

[0026] Next, the gate wiring process is carried out. In the gate wiring process, after depositing polysilicon, gate wiring is obtained by patterning it into an arbitrary shape. This gate wiring includes the gate electrode 16 inside the trench 12 and the outer gate electrode 36 inside the outer trench 32 (Step 2). In the process of patterning the gate wiring, the portion of the gate wiring embedded in the trench 12 of the cell portion 10 is etched. In other words, the gate wiring that overlaps the upper part of the trench 12 in the cell portion 10 is etched back. After that, if necessary, an oxide film may be formed on the gate wiring by thermal oxidation or the like.

[0027] Next, a first interlayer film is formed on the upper surface of the semiconductor substrate 60, extending from the cell portion 10 to the outer peripheral portion 30 (Step 3). The first interlayer film corresponds to the first cell portion interlayer film 21. In this step, as shown in Figure 3A, two or more interlayer films may be formed as the interlayer film. Alternatively, only one interlayer film may be formed.

[0028] As two interlayer films, for example, a first cell interlayer film 21 containing impurity elements and having high fluidity, which allows for high embedding of the trenches 12, and a highly reliable interlayer film 23 that does not contain impurity elements are used. Impurity elements include, for example, boron (B) or phosphorus (P). The first cell interlayer film 21 is, for example, a BPSG film, and the interlayer film 23 is, for example, a TEOS film. When using two interlayer films, it is desirable to first fill the trenches 12 and the outer periphery trenches 32 with the first cell interlayer film 21 containing impurity elements, and then cover the entire structure with the interlayer film 23 that does not contain impurity elements.

[0029] When forming a single interlayer film, a first cell interlayer film 21 containing impurity elements is used to improve its ability to fill the trench 12. Alternatively, an interlayer film free of impurity elements may be formed as a base layer before forming the first cell interlayer film 21.

[0030] Next, as shown in Figure 3B, the first cell interlayer 21 and the interlayer 23 are etched so that the first cell interlayer 21 remains inside the trench 12 (step 4). In other words, by etching back the entire wafer surface, the first cell interlayer 21 remains only inside the trench 12. The interlayers of the cell portion 10 and the mesa portion 38 of the outer peripheral portion 30 are all etched, except inside the trench 12.

[0031] Next, as shown in Figure 3C, after etching the first cell interlayer film 21, a second interlayer film is formed on the upper surface of the semiconductor substrate 60, extending from the cell portion 10 to the outer peripheral portion 30 (Step 5). The second interlayer film corresponds to the second cell interlayer film 22, which does not contain impurity elements. At this time, the second cell interlayer film 22 is formed on top of the first cell interlayer film 21 inside the trench 12.

[0032] Next, as shown in Figure 3D, the second cell interlayer film 22 is etched so that it remains inside the trench 12 and around the outer periphery 30 (step 6). Specifically, the portion of the mask covering the cell portion 10 is patterned using photogravure to form an opening in the mask, and then etching back is performed. As a result, the second cell interlayer film 22 inside the trench 12 is thinned, and the upper surface of the semiconductor substrate 60 in the cell portion 10 is exposed from the second cell interlayer film 22. In other words, only the inside of the trench 12 in the cell portion 10 can be filled with the interlayer film. Through this process, the second cell interlayer film 22 becomes thinner than the outer periphery interlayer film 40. The amount of etching back in step 6 is adjusted so that the amount of the second cell interlayer film 22 remaining inside the trench 12 is adjusted. The portion of the second cell interlayer film 22 remaining around the outer periphery 30 becomes the outer periphery interlayer film 40.

[0033] Subsequently, the main electrode 80 is formed in a surface metallization process (step 7). The main electrode 80 is formed on the second cell interlayer film 22 and the outer peripheral interlayer film 40, in contact with the second cell interlayer film 22 and the outer peripheral interlayer film 40.

[0034] Next, the semiconductor device 100 is manufactured through processes such as passivation film formation, protective film formation, grinding, back surface metallization, dicing, and testing. The semiconductor device 100 is then modularized and ultimately forms an inverter circuit or the like.

[0035] In this embodiment, the trenches 12 are filled with the first cell interlayer film 21, which contains impurities and has high embedding properties. Therefore, even when the cell pitch is narrow, the inside of the trenches 12 can be filled with the interlayer insulating film. This makes it possible to reduce on-resistance by reducing the cell pitch, i.e., to reduce energy loss.

[0036] Furthermore, if the main electrode 80 comes into contact with the interlayer film containing impurity elements, the insulating properties may decrease when a high voltage is applied, potentially leading to a decrease in reliability due to leakage current. In contrast, in this embodiment, the second cell portion interlayer film 22 and the outer peripheral portion interlayer film 40 that come into contact with the main electrode 80 are formed from interlayer films that do not contain impurity elements. Therefore, the reliability of the device can be improved.

[0037] Furthermore, the interlayer membrane 22 of the second cell section and the interlayer membrane 40 of the outer periphery section may contain some impurities. For example, the interlayer membrane 22 of the second cell section and the interlayer membrane 40 of the outer periphery section only need to have a lower impurity concentration than the interlayer membrane 21 of the first cell section.

[0038] Furthermore, the stacking order of the first cell interlayer film 21 and the second cell interlayer film 22 is not limited. In other words, an interlayer film containing impurities may be provided on top of an interlayer film that does not contain impurities. Also, an interlayer film containing impurities may be applied to the outer periphery interlayer film 40.

[0039] In this embodiment, an example was described in which the semiconductor substrate 60 is formed of a wide-bandgap semiconductor. The wide-bandgap semiconductor may be a gallium nitride-based material or diamond, in addition to the silicon carbide mentioned above. The semiconductor substrate 60 may also be a silicon substrate. In any case, it is possible to stably form the interlayer film and improve reliability.

[0040] The semiconductor device 100 of this embodiment can be applied to any semiconductor device such as a MOSFET or IGBT (Insulated Gate Bipolar Transistor).

[0041] Figure 5 is a cross-sectional view of a semiconductor device 100 according to a modified example of Embodiment 1. During the etch-back in step 6, the edges of the outer peripheral interlayer film 40 adjacent to the trench 12 may be etched in a tapered shape. This improves the embedding performance in the metallization process.

[0042] The modifications described above can be appropriately applied to the semiconductor device and method for manufacturing the semiconductor device according to the following embodiments. Since the semiconductor device and method for manufacturing the semiconductor device according to the following embodiments have many similarities with Embodiment 1, the differences from Embodiment 1 will be the focus of this explanation.

[0043] Embodiment 2. Figure 6 is a cross-sectional view of the semiconductor device 200 according to Embodiment 2. Figure 7 is a cross-sectional view showing the semiconductor device 200 according to Embodiment 2 with the main electrode 80 provided. In this embodiment, the outer peripheral interlayer film 40 provided on the upper surface of the mesa portion 38 has a first outer peripheral interlayer film 41, a second outer peripheral interlayer film 42, and an interlayer film 43 provided between the first outer peripheral interlayer film 41 and the second outer peripheral interlayer film 42. The second outer peripheral interlayer film 42 is provided on the first outer peripheral interlayer film 41 and is in contact with the main electrode 80.

[0044] The interlayer film 43 may be the same type of film as the second outer layer interlayer film 42, or a different type of film. The interlayer film 43 may be omitted. In other words, the outer layer interlayer film 40 that overlaps the mesa portion 38 only needs to be formed by two or more interlayer films. The first outer layer interlayer film 41 contains impurities. The second outer layer interlayer film 42 and interlayer film 43 have lower impurity concentrations than the first outer layer interlayer film 41. The second outer layer interlayer film 42 and interlayer film 43 do not need to contain impurities. The first outer layer interlayer film 41, the second outer layer interlayer film 42, and interlayer film 43 are, for example, oxide films. Specifically, the first outer layer interlayer film 41 is, for example, a BPSG film. The second cell layer interlayer film 22 and interlayer film 43 are, for example, TEOS films.

[0045] In this embodiment, the upper surface of the outer peripheral interlayer film 40, specifically the portion 40a directly above the mesa portion 38 and the upper end face 40b of the mesa portion 38, is formed of the same type of interlayer film. This same type of interlayer film is either the second outer peripheral interlayer film 42 or the interlayer film 43. The portion of the outer peripheral interlayer film 40 directly above the mesa portion 38 may be entirely covered with either the second outer peripheral interlayer film 42 or the interlayer film 43.

[0046] The structure of the cell interlayer membrane 20 is the same as that of Embodiment 1. Of the cell interlayer membrane 20, the uppermost surface that contacts the main electrode 80, i.e., the second cell interlayer membrane 22, is formed of an interlayer membrane with a lower impurity concentration than the first outer peripheral interlayer membrane 41. The second cell interlayer membrane 22, which forms the uppermost surface of the cell interlayer membrane 20, does not need to contain impurities. In this embodiment, the cell interlayer membrane 20 only needs to be formed of one or more interlayer membranes. The cell interlayer membrane 20 contains impurities. This improves the embedding ability into the trench 12.

[0047] Figures 8A to 8D illustrate the manufacturing method of the semiconductor device 200 according to Embodiment 2. The manufacturing method is the same as in Embodiment 1 up to the step of forming the first cell interlayer film 21 and the interlayer film 23 in step 3.

[0048] In step 4, the portion of the mask covering the cell portion 10 is patterned using photogravure to form an opening. Etching back is then performed using this mask. As a result, as shown in Figure 8B, the first cell portion interlayer 21 can be left only within the trench 12 in the cell portion 10. Also, a portion of the mesa portion 38 in the outer peripheral portion 30 is exposed from the interlayer. Of the first cell portion interlayer 21 and interlayer 23, the portions remaining in the outer peripheral portion 30 become the first outer peripheral interlayer 41 and interlayer 43. Through this process, the first cell portion interlayer 21 is formed to be thinner than the first outer peripheral interlayer 41.

[0049] Next, as shown in Figure 8C, a second cell interlayer film 22 is formed as the second interlayer film (step 5). Then, as shown in Figure 8D, the entire wafer surface is etched back (step 6). As a result, in the cell portion 10, only the inside of the trench 12 is filled with the second cell interlayer film 22. Also, an exposed portion 39 is formed in the mesa portion 38. The portion of the second cell interlayer film 22 remaining on the outer periphery 30 becomes the second outer periphery interlayer film 42. In step 6, the amount of etch back is adjusted so that the amount of the second interlayer film remains on the wafer surface in the cell portion 10 and the outer periphery 30. The subsequent steps are the same as those in Embodiment 1.

[0050] Figure 9 illustrates a method for manufacturing a semiconductor device 200 according to a first modification of Embodiment 2. In step 6, instead of etching the entire wafer, only the interlayer film 22 of the second cell portion of the cell portion 10 may be etched. In this case, the same mask as in step 4 may be used. This makes it possible to leave a thicker interlayer film on the outer periphery 30, thereby improving reliability.

[0051] Figure 10 is a cross-sectional view of a semiconductor device 200 according to a second modified example of Embodiment 2. The end of the first outer peripheral interlayer film 41 adjacent to the trench 12 may be tapered. That is, during the etch-back in step 4, the end of the first outer peripheral interlayer film 41 may be etched in a tapered shape. This makes it easier for the second outer peripheral interlayer film 42 to adhere to the end face of the first outer peripheral interlayer film 41 in step 5. Therefore, the first outer peripheral interlayer film 41 is less likely to be exposed, and reliability can be improved.

[0052] In this embodiment, the portion of the outer peripheral interlayer film 40 that overlaps with the mesa portion 38 is formed of two or more types of interlayer films. An interlayer film containing impurity elements remains inside the overlapping portion, while the surface is covered with an interlayer film that does not contain impurity elements. With this structure, only the interlayer film that does not contain impurity elements comes into contact with the main electrode 80. Therefore, the reliability of the device can be ensured. Also, similar to Embodiment 1, since the trench 12 is filled with the first cell portion interlayer film 21 which contains impurities and has high embedding properties, the inside of the trench 12 can be filled with an interlayer insulating film even when the cell pitch is narrow.

[0053] Furthermore, in this embodiment, the portion of the outer peripheral interlayer film 40 that overlaps with the mesa portion 38 is thicker, which allows for a smaller leakage current than in Embodiment 1. On the other hand, in Embodiment 1, the flatness of the electrode can be improved compared to Embodiment 2, thus improving resistance to stress and the like.

[0054] Embodiment 3. Figure 11 is a cross-sectional view of the semiconductor device according to Embodiment 3. Figure 12 is a plan view of the semiconductor device according to Embodiment 3. Multiple trenches 12 are formed in a stripe pattern in the semiconductor device 300. Figures 1 and 6 are cross-sectional views obtained by cutting Figure 12 along the line AB. Figure 11 is a cross-sectional view obtained by cutting Figure 12 along the line CD. In other words, Figure 11 shows the gate pull-out portion at the longitudinal end of the trench 12.

[0055] The gate oxide film 34 and the outer peripheral gate electrode 36 are formed so as to ride up onto the upper surface of the semiconductor substrate 60 of the cell portion 10 from inside the outer peripheral trench 32. In this case, the portion 34a of the gate oxide film 34 provided on the upper surface of the semiconductor substrate 60 of the cell portion 10 may be thicker than the portion of the gate oxide film 14 provided inside the trench 12. This improves reliability in the portion where the gate wiring rides up onto the corners of the trench 12. The portion of the gate oxide film 34 provided inside the outer peripheral trench 32 may be the same thickness as portion 34a, or the same thickness as the gate oxide film 14. The features of this embodiment may be combined with either Embodiment 1 or Embodiment 2.

[0056] Embodiment 4. Figure 13 is a cross-sectional view of the semiconductor substrate 60 according to Embodiment 4. The corners of the semiconductor substrate 60 that form the opening of the trench 12 may be obtuse or curved. This improves the embedding of the gate electrode 16 and the cell interlayer film 20 into the trench 12.

[0057] The trench 12 shown in Figure 13 can be formed by adding a step to form an inclined portion or curvature at the upper corner of the trench 12 after forming the vertical portion of the trench 12. Specifically, after forming the vertical portion of the trench 12, a mask reduction step is performed to reduce the hard mask forming the trench 12 by, for example, wet etching, by an arbitrary dimension. As a result, a portion of the upper surface of the semiconductor substrate 60 around the trench 12 is exposed from the hard mask. By performing dry etching, such as reactive ion etching, on this exposed portion, an inclined portion or curved surface can be formed at the corner of the trench 12. After this, the hard mask is removed. The features of this embodiment may be combined with either Embodiment 1 or 2.

[0058] The technical features described in each embodiment may be used in combination as appropriate.

[0059] The various aspects of this disclosure are summarized below as an appendix. (Note 1) A semiconductor substrate having a cell portion and an outer peripheral portion outside the cell portion, A gate electrode is provided inside a trench formed on the upper surface of the cell portion, Inside the trench, the interlayer film of the cell portion provided on the gate electrode, An outer peripheral interlayer membrane provided on the upper surface of the mesa portion adjacent to the trench, A main electrode is provided on the interlayer membrane of the cell portion and the interlayer membrane of the outer periphery, and is in contact with the interlayer membrane of the cell portion and the interlayer membrane of the outer periphery, Equipped with, The cell portion interlayer film comprises a first cell portion interlayer film provided on the gate electrode and a second cell portion interlayer film provided on the first cell portion interlayer film and in contact with the main electrode. A semiconductor device characterized in that one of the interlayer films of the first cell portion and the interlayer film of the second cell portion contains an impurity. (Note 2) The interlayer film of the first cell contains impurities. The interlayer membrane of the second cell portion has a lower impurity concentration than the interlayer membrane of the first cell portion. The semiconductor device according to Appendix 1, characterized in that the uppermost surface of the outer peripheral interlayer film that contacts the main electrode is formed of an interlayer film with a lower impurity concentration than the interlayer film of the first cell portion. (Note 3) The semiconductor device according to Appendix 2, characterized in that the interlayer film of the second cell portion and the interlayer film forming the uppermost surface of the outer peripheral interlayer film do not contain impurities. (Note 4) The semiconductor device according to any one of the appendices 1 to 3, characterized in that the outer peripheral interlayer film is a single layer. (Note 5) The semiconductor device according to any one of the appendices 1 to 4, characterized in that the interlayer film of the second cell portion is thinner than the interlayer film of the outer peripheral portion. (Note 6) The semiconductor device according to any one of claims 1 to 5, characterized in that the end of the outer peripheral interlayer film adjacent to the trench is tapered. (Note 7) A semiconductor substrate having a cell portion and an outer peripheral portion outside the cell portion, A gate electrode is provided inside a trench formed on the upper surface of the cell portion, Inside the trench, the interlayer film of the cell portion provided on the gate electrode, An outer peripheral interlayer membrane provided on the upper surface of the mesa portion adjacent to the trench, A main electrode is provided on the interlayer membrane of the cell portion and the interlayer membrane of the outer periphery, and is in contact with the interlayer membrane of the cell portion and the interlayer membrane of the outer periphery, Equipped with, The interlayer film of the cell portion contains impurities. The outer peripheral interlayer film comprises a first outer peripheral interlayer film and a second outer peripheral interlayer film provided on the first outer peripheral interlayer film and in contact with the main electrode. A semiconductor device characterized in that the portion of the upper surface of the outer peripheral interlayer film directly above the mesa portion and the end face of the outer peripheral interlayer film above the mesa portion are formed of the same type of interlayer film. (Note 8) The first outer interlayer film contains impurities, The second outer interlayer film has a lower impurity concentration than the first outer interlayer film. The aforementioned interlayer film of the same type is the second outer periphery interlayer film, The semiconductor device according to Appendix 7, characterized in that the uppermost surface of the interlayer film in the cell portion that contacts the main electrode is formed of an interlayer film with a lower impurity concentration than the first outer peripheral interlayer film. (Note 9) The semiconductor device according to Appendix 8, characterized in that the second outer peripheral interlayer film and the interlayer film forming the uppermost surface of the cell interlayer film do not contain impurities. (Note 10) The cell portion interlayer film comprises a first cell portion interlayer film provided on the gate electrode and a second cell portion interlayer film provided on the first cell portion interlayer film and in contact with the main electrode. The semiconductor device according to any one of appendices 7 to 9, characterized in that the interlayer film of the first cell portion is thinner than the interlayer film of the first outer periphery portion. (Note 11) The semiconductor device according to any one of appendices 7 to 10, characterized in that the end of the first outer peripheral interlayer film adjacent to the trench is tapered. (Note 12) The outer peripheral interlayer film is provided so as to expose a part of the mesa portion. The semiconductor device according to any one of appendices 1 to 11, characterized in that the main electrode is in contact with the semiconductor substrate in a portion of the mesa portion that is exposed from the outer peripheral interlayer film. (Note 13) The semiconductor device according to any one of appendices 1 to 12, characterized in that an outer peripheral trench is formed on the upper surface of the outer peripheral portion of the semiconductor substrate. (Note 14) The semiconductor device according to Appendix 13, characterized in that the outer peripheral interlayer film is formed to ride up from the inside of the outer peripheral trench onto the mesa portion. (Note 15) The gate oxide film provided inside the trench and inside the outer peripheral trench, Inside the outer peripheral trench, an outer peripheral gate electrode is provided on the gate oxide film, Equipped with, The gate electrode is provided inside the trench on the gate oxide film, The gate oxide film and the peripheral gate electrode are formed so as to ride up onto the upper surface of the semiconductor substrate in the cell portion from inside the peripheral trench. The semiconductor device according to Appendix 13 or 14, characterized in that the portion of the gate oxide film provided on the upper surface of the semiconductor substrate in the cell portion is thicker than the portion provided inside the trench. (Note 16) The semiconductor device according to any one of appendices 1 to 15, characterized in that the corner of the semiconductor substrate forming the opening of the trench is formed at an obtuse angle or a curved surface. (Note 17) The semiconductor device according to any one of appendices 1 to 16, characterized in that the semiconductor substrate is formed of a wide-bandgap semiconductor. (Note 18) The semiconductor device according to Appendix 17, characterized in that the wide-bandgap semiconductor is silicon carbide, gallium nitride-based material, or diamond. (Note 19) In a semiconductor substrate having a cell portion and an outer peripheral portion outside the cell portion, a trench is formed on the upper surface of the cell portion. A gate electrode is formed inside the trench. A first interlayer film is formed on the upper surface of the semiconductor substrate, extending from the cell portion to the outer peripheral portion. The first interlayer film is etched so that it remains inside the trench. After etching the first interlayer film, the second interlayer film is formed on the upper surface of the semiconductor substrate from the cell portion to the outer periphery, such that the second interlayer film is formed on the first interlayer film inside the trench. The second interlayer film is etched so that it remains inside the trench and on the outer periphery. After etching the second interlayer film, a main electrode is formed on the second interlayer film so as to be in contact with the second interlayer film. A method for manufacturing a semiconductor device, characterized in that one of the first interlayer film and the second interlayer film contains an impurity. [Explanation of symbols]

[0060] 10 Cell section, 12 Trench, 14 Gate oxide film, 16 Gate electrode, 20 Interlayer film of cell section, 21 Interlayer film of first cell section, 22 Interlayer film of second cell section, 23 Interlayer film, 30 Outer periphery, 32 Outer periphery trench, 34 Gate oxide film, 36 Outer periphery gate electrode, 38 Mesa section, 39 Exposed section, 40 Interlayer film of outer periphery, 41 Interlayer film of first outer periphery, 42 Interlayer film of second outer periphery, 43 Interlayer film, 60 Semiconductor substrate, 80 Main electrode, 100, 200, 300 Semiconductor device

Claims

1. A semiconductor substrate having a cell portion and an outer peripheral portion outside the cell portion, A gate electrode is provided inside a trench formed on the upper surface of the cell portion, Inside the trench, the interlayer film of the cell portion provided on the gate electrode, An outer peripheral interlayer membrane provided on the upper surface of the mesa portion adjacent to the trench, A main electrode is provided on the interlayer membrane of the cell portion and the interlayer membrane of the outer periphery, and is in contact with the interlayer membrane of the cell portion and the interlayer membrane of the outer periphery, Equipped with, The cell portion interlayer film comprises a first cell portion interlayer film provided on the gate electrode and a second cell portion interlayer film provided on the first cell portion interlayer film and in contact with the main electrode. A semiconductor device characterized in that one of the interlayer films of the first cell portion and the interlayer film of the second cell portion contains an impurity.

2. The interlayer film of the first cell contains impurities. The interlayer film of the second cell portion has a lower impurity concentration than the interlayer film of the first cell portion. The semiconductor device according to claim 1, characterized in that the uppermost surface of the outer peripheral interlayer film that contacts the main electrode is formed of an interlayer film with a lower impurity concentration than the first cell interlayer film.

3. The semiconductor device according to claim 2, characterized in that the interlayer film of the second cell portion and the interlayer film of the outer peripheral portion that forms the uppermost surface do not contain impurities.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that the outer peripheral interlayer film is a single layer.

5. The semiconductor device according to any one of claims 1 to 3, characterized in that the interlayer film of the second cell portion is thinner than the interlayer film of the outer peripheral portion.

6. The semiconductor device according to any one of claims 1 to 3, characterized in that the end of the outer peripheral interlayer film adjacent to the trench is tapered.

7. A semiconductor substrate having a cell portion and an outer peripheral portion outside the cell portion, A gate electrode is provided inside a trench formed on the upper surface of the cell portion, Inside the trench, the interlayer film of the cell portion provided on the gate electrode, An outer peripheral interlayer membrane provided on the upper surface of the mesa portion adjacent to the trench, A main electrode is provided on the interlayer membrane of the cell portion and the interlayer membrane of the outer periphery, and is in contact with the interlayer membrane of the cell portion and the interlayer membrane of the outer periphery, Equipped with, The interlayer film of the cell portion contains impurities. The outer peripheral interlayer film comprises a first outer peripheral interlayer film and a second outer peripheral interlayer film provided on the first outer peripheral interlayer film and in contact with the main electrode. A semiconductor device characterized in that the portion of the upper surface of the outer peripheral interlayer film directly above the mesa portion and the end face of the outer peripheral interlayer film above the mesa portion are formed of the same type of interlayer film.

8. The first outer interlayer film contains impurities. The second outer interlayer film has a lower impurity concentration than the first outer interlayer film. The interlayer film of the same type mentioned above is the second outer periphery interlayer film, The semiconductor device according to claim 7, characterized in that the uppermost surface of the interlayer film in the cell portion that contacts the main electrode is formed of an interlayer film with a lower impurity concentration than the first outer peripheral interlayer film.

9. The semiconductor device according to claim 8, characterized in that the second outer peripheral interlayer film and the interlayer film forming the uppermost surface of the cell interlayer film are free of impurities.

10. The cell portion interlayer film comprises a first cell portion interlayer film provided on the gate electrode and a second cell portion interlayer film provided on the first cell portion interlayer film and in contact with the main electrode. The semiconductor device according to any one of claims 7 to 9, characterized in that the interlayer film of the first cell portion is thinner than the interlayer film of the first outer periphery portion.

11. The semiconductor device according to any one of claims 7 to 9, characterized in that the end of the first outer peripheral interlayer film adjacent to the trench is tapered.

12. The outer peripheral interlayer film is provided so as to expose a part of the mesa portion. The semiconductor device according to any one of claims 1, 2, 3, 7, 8, or 9, characterized in that the main electrode is in contact with the semiconductor substrate in a portion of the mesa that is exposed from the outer peripheral interlayer film.

13. The semiconductor device according to any one of claims 1, 2, 3, 7, 8, or 9, characterized in that an outer peripheral trench is formed on the upper surface of the outer peripheral portion of the semiconductor substrate.

14. The semiconductor device according to claim 13, characterized in that the outer peripheral interlayer film is formed to ride up from the inside of the outer peripheral trench onto the mesa portion.

15. The gate oxide film provided inside the trench and inside the outer peripheral trench, Inside the outer peripheral trench, an outer peripheral gate electrode is provided on the gate oxide film, Equipped with, The gate electrode is provided inside the trench on the gate oxide film, The gate oxide film and the peripheral gate electrode are formed so as to ride up onto the upper surface of the semiconductor substrate in the cell portion from inside the peripheral trench. The semiconductor device according to claim 13, characterized in that the portion of the gate oxide film provided on the upper surface of the semiconductor substrate in the cell portion is thicker than the portion provided inside the trench.

16. The semiconductor device according to any one of claims 1, 2, 3, 7, 8, or 9, characterized in that the corners of the semiconductor substrate that form the opening of the trench are formed at an obtuse angle or a curved surface.

17. The semiconductor device according to any one of claims 1, 2, 3, 7, 8, or 9, characterized in that the semiconductor substrate is formed of a wide-bandgap semiconductor.

18. The semiconductor device according to claim 17, characterized in that the wide bandgap semiconductor is silicon carbide, gallium nitride-based material, or diamond.

19. In a semiconductor substrate having a cell portion and an outer peripheral portion outside the cell portion, a trench is formed on the upper surface of the cell portion. A gate electrode is formed inside the trench. A first interlayer film is formed on the upper surface of the semiconductor substrate, extending from the cell portion to the outer peripheral portion. The first interlayer film is etched so that it remains inside the trench. After etching the first interlayer film, the second interlayer film is formed on the upper surface of the semiconductor substrate from the cell portion to the outer periphery, such that the second interlayer film is formed on the first interlayer film inside the trench. The second interlayer film is etched so that it remains inside the trench and on the outer periphery. After etching the second interlayer film, a main electrode is formed on the second interlayer film so as to be in contact with the second interlayer film. A method for manufacturing a semiconductor device, characterized in that one of the first interlayer film and the second interlayer film contains an impurity.

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