Semiconductor device and its manufacturing method

Abstract

This invention provides a technology to suppress the tilting of fins in a semiconductor device having fins. [Solution] The semiconductor device comprises a semiconductor substrate, a gate electrode, and a gate insulating film. The semiconductor substrate has a support layer and a plurality of first fins that protrude from the upper surface of the support layer, extend along a first direction, and are spaced apart in a second direction intersecting the first direction, and second fins that protrude from the upper surface of the support layer, are spaced within the corresponding intervals, and extend along the second direction. The second fins connect two first fins located on either side thereof. Inside the semiconductor substrate are a first n-type region distributed across the support layer and each first fin, a body region provided on each first fin and located above the first n-type region, and a second n-type region provided on each first fin and located above the body region. The upper end of the second fin is located above the interface between the first n-type region and the body region.

Description

Technical Field

[0001] The technology disclosed in this specification relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] The semiconductor device disclosed in Patent Document 1 has a semiconductor substrate. The semiconductor substrate has a support layer and fins. The fins protrude from the upper surface of the support layer. Gate electrodes are disposed on both sides of the fins. Each gate electrode faces the side surface of the fin through a gate insulating film. A body region is provided inside the fin. When a gate-on potential is applied to each gate electrode, channels are formed along both side surfaces of the fin in the body region. Since the channels on both sides are coupled inside the fin, the entire fin becomes a channel. Therefore, the on-resistance of this semiconductor device is low.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The width of the fin of the semiconductor device of Patent Document 1 is extremely narrow. Therefore, in the manufacturing process of this semiconductor device, the fin may fall over. In this specification, a technology for suppressing the fall of the fin in a semiconductor device having a fin is provided.

Means for Solving the Problems

[0005] A semiconductor device disclosed herein may include a semiconductor substrate. The semiconductor substrate may have a support layer, a plurality of first fins, and second fins. The plurality of first fins may protrude from the upper surface of the support layer and extend along a first direction on the upper surface, and be spaced apart in a second direction intersecting the first direction. The second fins may protrude from the upper surface of the support layer, be spaced within the corresponding intervals, and extend along the second direction on the upper surface. The second fins may also connect two of the first fins located on either side of them. A first n-type region, a p-type body region, and a second n-type region may be provided inside the semiconductor substrate. The first n-type region may be distributed across the support layer and each of the first fins. The body region may be provided on each of the first fins and located above the first n-type region. The second n-type region may be provided on each of the first fins and located above the body region, and may be separated from the first n-type region by the body region. The semiconductor device may have a gate electrode and a gate insulating film. The gate insulating film may be provided within the gap and in contact with the body region on the side surface of the first fin. The gate electrode may be provided within the gap and insulated from the semiconductor substrate by the gate insulating film. The upper end of the second fin may be positioned above the interface between the first n-type region and the body region.

[0006] In the semiconductor device described above, the second fin connects the two first fins located on either side of it. Therefore, during the manufacturing process of this semiconductor device, the tilting of the first fins can be suppressed. [Brief explanation of the drawing]

[0007] [Figure 1] This is a perspective view of a semiconductor device. [Figure 2] This is a top view of a semiconductor device. [Figure 3] This is a cross-sectional view taken along line III-III in Figure 2. [Figure 4] This is a cross-sectional view taken along line IV-IV in Figure 2. [Figure 5] Figure 3 is a cross-sectional view of the VV section. [Figure 6] This is a diagram illustrating the manufacturing method of the semiconductor device in the example (a cross-sectional view corresponding to Figure 3). [Figure 7] This is a diagram illustrating the manufacturing method of the semiconductor device in the example. [Figure 8] This is a diagram illustrating the manufacturing method of the semiconductor device in the example (a cross-sectional view corresponding to Figure 3). [Figure 9] This is a diagram illustrating the manufacturing method of the semiconductor device in the embodiment (a cross-sectional view corresponding to Figure 4). [Figure 10] This is a diagram illustrating the manufacturing method of the semiconductor device in the example (a cross-sectional view corresponding to Figure 5). [Figure 11] This is a diagram illustrating the manufacturing method of the semiconductor device in the example (a cross-sectional view corresponding to Figure 3). [Figure 12] This is a diagram illustrating the manufacturing method of the semiconductor device in the embodiment (a cross-sectional view corresponding to Figure 4). [Figure 13] This is a diagram illustrating the manufacturing method of the semiconductor device in the example (a cross-sectional view corresponding to Figure 5). [Figure 14] This is a diagram illustrating the manufacturing method of the semiconductor device in the example (a cross-sectional view corresponding to Figure 3). [Figure 15] This is a diagram illustrating the manufacturing method of the semiconductor device in the embodiment (a cross-sectional view corresponding to Figure 4). [Figure 16] This is a diagram illustrating the manufacturing method of the semiconductor device in the example (a cross-sectional view corresponding to Figure 5). [Figure 17] This is a top view of a modified semiconductor device. [Figure 18] This is a top view of a modified semiconductor device. [Modes for carrying out the invention]

[0008] In one example semiconductor device disclosed herein, the upper end of the second fin may be positioned above the interface between the body region and the second n-type region.

[0009] In a semiconductor device disclosed in this specification, the upper end of the second fin may be disposed below the upper end of the first fin or at the same height as the upper end of the first fin.

[0010] In a semiconductor device disclosed in this specification, a plurality of gate electrodes may be arranged at intervals such that a second fin is positioned between the plurality of gate electrodes. The semiconductor device may further include a wiring layer disposed above the second fin and electrically connecting the gate electrodes on both sides of the second fin.

Example

[0011] (Structure of Semiconductor Device 100) The semiconductor device 100 shown in FIGS. 1 to 5 is a MOSFET (Metal - Oxide - Semiconductor Field Effect Transistor). The semiconductor device 100 has a semiconductor substrate 10. The semiconductor substrate 10 is a SiC substrate. The semiconductor substrate 10 may be made of other semiconductor materials such as silicon and gallium nitride.

[0012] As shown in FIG. 1, the semiconductor substrate 10 has a support layer 12. The support layer 12 has a plate shape. Hereinafter, the thickness direction of the support layer 12 is referred to as the z - direction, one direction parallel to the upper surface 12a of the support layer 12 is referred to as the x - direction, and a direction parallel to the upper surface 12a of the support layer 12 and orthogonal to the x - direction is referred to as the y - direction.

[0013] The semiconductor substrate 10 has a plurality of first fins 14 and a plurality of second fins 16. The fin is a convex portion protruding from the upper surface 12a of the support layer 12, linearly extending on the upper surface 12a, and having a height higher than the width.

[0014] Multiple first fins 14 protrude from the upper surface 12a of the support layer 12. On the upper surface 12a, the multiple first fins 14 extend along the y-direction. Also, on the upper surface 12a, the multiple first fins 14 are spaced apart in the x-direction. The width of each first fin 14 in the x-direction is, for example, 200 nm or less. In the following, the space between the multiple first fins 14 will be referred to as the spacing 18.

[0015] Multiple second fins 16 protrude from the upper surface 12a of the support layer 12. Each second fin 16 is positioned within a corresponding interval 18. On the upper surface 12a, the multiple second fins 16 extend along the x-direction. Also on the upper surface 12a, the multiple second fins 16 are spaced apart in the y-direction. Furthermore, each second fin 16 connects two first fins 14 located on either side of it. The upper end 16a of each second fin 16 is positioned at the same height as the upper end 14a of the first fin 14. In this embodiment, within each interval 18, the second fins 16 are positioned at the same location in the y-direction.

[0016] Next, the internal structure of the semiconductor substrate 10 will be described. As shown in Figure 1, the semiconductor substrate 10 has a source region 30 and a body region 32. The source region 30 and the body region 32 are provided on each of the first fins 14.

[0017] The source region 30 is an n-type region with a high concentration of n-type impurities. The source region 30 is located in a range that includes the upper end 14a of the first fin 14 (i.e., the upper surface of the first fin 14).

[0018] The body region 32 is a p-type region. The body region 32 is in contact with the lower surface of the source region 30. The lower surface of the body region 32 is located above the support layer 12.

[0019] The semiconductor substrate 10 has a drift region 34 and a drain region 36. The drift region 34 is an n-type region having a lower n-type impurity concentration than the source region 30. The drift region 34 is distributed across multiple first fins 14 and the support layer 12. The drift region 34 is in contact with the lower surface of each body region 32. The drift region 34 is separated from the source region 30 by the body regions 32.

[0020] The drain region 36 is an n-type region having a higher n-type impurity concentration than the drift region 34. The drain region 36 is provided in the support layer 12. The drain region 36 is in contact with the lower surface of the drift region 34. The drain region 36 is provided in a range that includes the lower surface 12b of the support layer 12 (i.e., the lower surface of the semiconductor substrate 10).

[0021] As shown in Figures 3 to 5, the semiconductor device 100 has a gate insulating film 40 and a plurality of gate electrodes 50. As shown in Figures 3 and 5, the gate insulating film 40 is provided within a gap 18. The gate insulating film 40 covers the side surfaces of the first fin 14 and the second fin 16. The gate insulating film 40 also covers the upper surface 12a of the support layer 12. On the side surfaces of the first fin 14, the gate insulating film 40 is in contact with the source region 30, the body region 32, and the drift region 34. On the upper surface 12a of the support layer 12, the gate insulating film 40 is in contact with the drift region 34.

[0022] As shown in Figures 3 and 5, each gate electrode 50 is located within a gap 18. As shown in Figure 5, within each gap 18, the gate electrodes 50 are positioned on both sides of the second fin 16. In other words, the second fin 16 is positioned between the two gate electrodes 50. Each gate electrode 50 is insulated from the semiconductor substrate 10 by a gate insulating film 40.

[0023] As shown in Figures 3 to 5, the semiconductor device 100 has a wiring layer 52. As shown in Figure 3, the wiring layer 52 is provided above each gate electrode 50. As shown in Figures 4 and 5, the wiring layer 52 extends linearly in the y direction through the top of each second fin 16. The wiring layer 52 electrically connects each of the gate electrodes 50 below it to each other. The wiring layer 52 is also connected to electrode pads (not shown). The potential of each gate electrode 50 is controlled by an external circuit via the electrode pads.

[0024] The semiconductor device 100 has an upper insulating film 42 and a lower insulating film 44. The upper insulating film 42 covers the upper surface of the gate electrode 50, the sides of the wiring layer 52, and the upper surface of the wiring layer 52. The lower insulating film 44 is located between the wiring layer 52 and the second fin 16. The lower insulating film 44 covers the lower surface of the wiring layer 52. The wiring layer 52 is insulated from the semiconductor substrate 10 (in this case, the second fin 16) by the lower insulating film 44.

[0025] The semiconductor device 100 has an upper electrode 60 and a lower electrode 62. As shown in Figures 3 and 4, the upper electrode 60 covers the upper end 14a of the first fin 14 (i.e., the upper surface of the first fin 14). The upper electrode 60 also covers the upper end 16a of the second fin 16 (i.e., the upper surface of the second fin 16) where the wiring layer 52 is not provided. The upper electrode 60 is in ohmic contact with the source region 30. The semiconductor substrate 10 also has a p-type contact region in a position not shown that is in ohmic contact with the upper electrode 60. The upper electrode 60 is connected to the body region 32 via the contact region.

[0026] The lower electrode 62 is in contact with the lower surface 12b of the support layer 12 (i.e., the lower surface of the semiconductor substrate 10). The lower electrode 62 is in ohmic contact with the drain region 36.

[0027] When a gate-on potential (a potential higher than the gate threshold) is applied to each gate electrode 50, a channel is formed in the body region 32 near the gate insulating film 40. Because the width of the first fin 14 is narrow, the channels formed on both sides of the first fin 14 are coupled to each other, forming a channel throughout the entire body region 32. This results in low channel resistance. Once the channel is formed, electrons flow from the drain region 36 to the source region 30 through the drift region 34 and the channel.

[0028] (Method of manufacturing semiconductor device 100) Next, a method for manufacturing the semiconductor device 100 will be described. First, epitaxial growth, ion implantation, etc., are performed on a semiconductor substrate 10 made of SiC to form a source region 30, a body region 32, a drift region 34, and a drain region 36 inside the semiconductor substrate 10, as shown in Figure 6. The source region 30 is exposed on the upper surface 10a of the semiconductor substrate 10.

[0029] Next, as shown in Figure 7, a plurality of recesses 70 are formed by selectively etching the upper surface 10a of the semiconductor substrate 10. The plurality of recesses 70 are formed on the upper surface 10a with gaps in both the x and y directions. Furthermore, the plurality of recesses 70 are formed so as to penetrate from the upper surface 10a through the source region 30 and the body region 32 to reach the drift region 34. As a result, a support layer 12, a plurality of first fins 14, and a plurality of second fins 16 are formed on the semiconductor substrate 10. When the recesses 70 are formed in this way, the upper end 16a of the second fins 16 is positioned at the same height as the upper end 14a of the first fins 14. The upper surface 10a of the semiconductor substrate 10 becomes the upper end 14a of the first fins 14 and the upper end 16a of the second fins 16. Also, the bottom surface of the recesses 70 becomes the upper surface 12a of the support layer 12.

[0030] On the upper surface 12a, multiple first fins 14 are formed to extend along the y-direction. Furthermore, two first fins 14 located on either side are connected to each other by a second fin 16 that extends along the x-direction. As a result, tilting of each first fin 14 is suppressed during the manufacturing process of the semiconductor device 100. In particular, since the upper end 16a of the second fin 16 is positioned above the interface 38 between the body region 32 and the drift region 34, and the height of the second fin 16 is high, tilting of each first fin 14 can be effectively suppressed.

[0031] Next, as shown in Figures 8 to 10, an insulating film 46 is formed on the inner surfaces of the upper end 14a, the upper end 16a, and the gap 18, for example, by CVD. This forms an insulating film 46 around the first fin 14 and around the second fin 16. An insulating film 46 is also formed on the upper surface 12a of the support layer 12. After forming the insulating film 46, electrodes 54 are formed on the insulating film 46. Here, the electrodes 54 are formed such that their upper surfaces are located above the upper end 14a and the upper end 16a.

[0032] Next, as shown in Figures 11 to 13, a mask 72 is formed on the electrode 54. Here, the mask 72 is formed in the area where the wiring layer 52 is formed.

[0033] Next, as shown in Figures 14 to 16, the electrodes 54 are etched through the mask 72. This forms the gate electrodes 50 and the wiring layer 52. Here, the gate electrodes 50 are formed such that their upper surface is located below the upper end 14a of the first fin 14. Even after forming the gate electrodes 50 in this way, they are connected to each other by the wiring layer 52. After that, the mask 72 is removed.

[0034] Next, as shown in Figures 3 to 5, the gate insulating film 40, the upper insulating film 42, and the lower insulating film 44 are formed. Then, as shown in Figures 3 to 5, the upper electrode 60 is formed on the upper end 14a of the first fin 14 and the upper end 16a of the second fin 16. Here, the upper electrode 60 is formed by reacting a metal with the upper surface 10a of the semiconductor substrate 10 (i.e., the upper end 14a and the upper end 16a) to form a silicide layer. After that, the semiconductor device 100 is completed by forming the lower electrode 62 on the lower surface 12b of the support layer 12 (i.e., the lower surface of the semiconductor substrate 10).

[0035] As described above, according to this embodiment, the tilting of the first fin 14 can be suppressed by the second fin 16 during the manufacturing process of the semiconductor device 100. However, if the height of the second fin 16 is low, the first fin 14 may tilt. In contrast, in this embodiment, the tilting of each first fin 14 is effectively suppressed by raising the height of the second fin 16 such that its upper end 16a is positioned above the interface 38 between the body region 32 and the drift region 34. In this configuration, the body region 32 does not function as a channel in the area of ​​the side surface of the first fin 14 where the second fin 16 is present. As a result, the channel density decreases. Thus, by raising the second fin 16 to a height where a part of the body region 32 cannot function as a channel, the tilting of the first fin 14 can be suppressed.

[0036] In the embodiment described above, when the semiconductor device 100 is viewed from above, the second fins 16 were arranged at the same position in the y-direction in each interval 18. However, as shown in Figure 17, intervals 18 with the second fins 16 and intervals 18 without the second fins 16 may be arranged alternately. Also, in adjacent intervals 18a and 18b, the second fin 16 in interval 18b may be positioned offset in the y-direction relative to the second fin 16 in interval 18a. That is, as shown in Figure 18, the second fin 16 in interval 18b does not need to be provided at a position adjacent in the x-direction to the second fin 16 in interval 18a.

[0037] In the embodiment described above, the source region 30 was in contact with the body region 32. However, the source region 30 may be separated from the body region 32.

[0038] In the embodiment described above, the upper end 16a of each second fin 16 was positioned at the same height as the upper end 14a of the first fin 14. However, the upper end 16a of each second fin 16 only needs to be positioned above the boundary surface 38 between the drift region 34 and the body region 32.

[0039] In the embodiment described above, the upper end 16a of each second fin 16 was positioned at the same height as the upper end 14a of the first fin 14. However, the upper end 16a of each second fin 16 only needs to be positioned above the interface between the body region 32 and the source region 30.

[0040] In the embodiment described above, the upper end 16a of each second fin 16 was positioned at the same height as the upper end 14a of the first fin 14. However, the upper end 16a of each second fin 16 does not need to be positioned lower than the upper end 14a of the first fin 14.

[0041] The configuration of the semiconductor device and its manufacturing method disclosed herein is described below. (Composition 1) A semiconductor device comprising a semiconductor substrate, a gate electrode, and a gate insulating film, The aforementioned semiconductor substrate Supporting layer and A plurality of first fins protrude from the upper surface of the support layer, extend along a first direction on the upper surface, and are spaced apart in a second direction intersecting the first direction, A second fin protrudes from the upper surface of the support layer, is positioned within the corresponding interval, and extends along the second direction on the upper surface, It has, The second fin connects the two first fins located on either side thereof. Inside the aforementioned semiconductor substrate, A first n-type region distributed across the support layer and each of the first fins, A p-shaped body region is provided on each of the first fins and positioned above the first n-shaped region, A second n-type region is provided on each of the first fins, positioned above the body region, and separated from the first n-type region by the body region. A system is in place, The gate insulating film is provided within the gap and is in contact with the body region on the side surface of the first fin. The gate electrode is provided within the aforementioned interval and is insulated from the semiconductor substrate by the gate insulating film. The upper end of the second fin is positioned above the interface between the first n-type region and the body region. Semiconductor equipment. (Configuration 2) The semiconductor device according to configuration 1, wherein the upper end of the second fin is positioned above the interface between the body region and the second n-type region. (Composition 3) The semiconductor device according to configuration 1 or 2, wherein the upper end of the second fin is positioned below the upper end of the first fin or at the same height as the upper end of the first fin. (Composition 4) Multiple gate electrodes are arranged at the aforementioned interval, and the second fin is positioned between the multiple gate electrodes. It further has a wiring layer positioned on top of the second fin, which electrically connects the gate electrodes on both sides of the second fin. A semiconductor device as described in any of configurations 1 to 3. (Composition 5) A method for manufacturing a semiconductor device, A step of preparing a semiconductor substrate having a first n-type region, a p-type body region located above the first n-type region, and a second n-type region located above the body region, A step of etching the upper surface of the semiconductor substrate, wherein the following conditions are met: The semiconductor substrate after etching has a support layer, a plurality of first fins, and a second fin. • Multiple first fins protrude from the upper surface of the support layer, and are arranged at intervals along the first direction and intersecting the first direction on the upper surface of the support layer. The second fin protrudes from the upper surface of the support layer, is positioned within the corresponding interval, and extends along the second direction on the upper surface of the support layer. The second fin connects the two first fins located on either side thereof. The first n-type region is distributed across the support layer and each of the first fins. The body region is located within each of the first fins and above the first n-type region. The second n-type region is located within each of the first fins and above the body region, and is separated from the first n-type region by the body region. The upper end of the second fin is positioned above the interface between the first n-type region and the body region. The process involves etching in a manner that satisfies the following conditions, A step of forming a gate insulating film that contacts the body region on the side surface of the first fin and a gate electrode that is insulated from the semiconductor substrate by the gate insulating film within the aforementioned interval, A manufacturing method having the following characteristics.

[0042] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of Symbols]

[0043] 10: Semiconductor substrate, 12: Support layer, 12a: Top surface, 14: First fin, 16: Second fin, 16a: Top edge, 30: Source region, 32: Body region, 34: Drift region, 38: Interface, 40: Gate insulating film, 42: Upper insulating film, 44: Lower insulating film, 50: Gate electrode, 52: Wiring layer, 100: Semiconductor device

Claims

1. A semiconductor device comprising a semiconductor substrate, a gate electrode, and a gate insulating film, The aforementioned semiconductor substrate Support layer (12) and A plurality of first fins (14) protrude from the upper surface (12a) of the support layer, extend along a first direction on the upper surface, and are spaced apart in a second direction intersecting the first direction, A second fin (16) protrudes from the upper surface of the support layer, is positioned within the corresponding interval, and extends along the second direction on the upper surface, It has, The second fin connects the two first fins located on either side thereof. Inside the aforementioned semiconductor substrate, A first n-type region (34) distributed across the support layer and each of the first fins, A p-shaped body region (32) is provided on each of the first fins and is positioned above the first n-shaped region, A second n-type region (30) is provided on each of the first fins, positioned above the body region, and separated from the first n-type region by the body region. A system is in place, The gate insulating film is provided within the gap and is in contact with the body region on the side surface of the first fin. The gate electrode is provided within the aforementioned interval and is insulated from the semiconductor substrate by the gate insulating film. The upper end (16a) of the second fin is positioned above the interface (38) between the first n-type region and the body region. Semiconductor equipment.

2. The semiconductor device according to claim 1, wherein the upper end of the second fin is positioned above the interface between the body region and the second n-type region.

3. The semiconductor device according to claim 1 or 2, wherein the upper end of the second fin is positioned below the upper end of the first fin or at the same height as the upper end of the first fin.

4. Multiple gate electrodes are arranged at the aforementioned interval, and the second fin is positioned between the multiple gate electrodes. The second fin further comprises a wiring layer (52) positioned on the upper part of the second fin, which electrically connects the gate electrodes on both sides of the second fin. The semiconductor device according to claim 3.

5. A method for manufacturing a semiconductor device, A step of preparing a semiconductor substrate having a first n-type region (34), a p-type body region (32) located above the first n-type region, and a second n-type region (30) located above the body region, A step of etching the upper surface of the semiconductor substrate, wherein the following conditions are met: - The semiconductor substrate after etching has a support layer (12), a plurality of first fins (14), and a second fin (16). - A plurality of the first fins protrude from the upper surface of the support layer, and are arranged at intervals along the first direction and intersecting the first direction on the upper surface of the support layer. - The second fin protrudes from the upper surface of the support layer, is positioned within the corresponding interval, and extends along the second direction on the upper surface of the support layer. - The second fin connects the two first fins located on either side thereof. - The first n-type region is distributed across the support layer and each of the first fins. - The body region is located within each of the first fins and above the first n-type region. - The second n-type region is located within each of the first fins and above the body region, and is separated from the first n-type region by the body region. - The upper end (16a) of the second fin is positioned above the interface (38) between the first n-type region and the body region. The process involves etching in a manner that satisfies the following conditions, A step of forming a gate insulating film that contacts the body region on the side surface of the first fin and a gate electrode that is insulated from the semiconductor substrate by the gate insulating film within the aforementioned interval, A manufacturing method having

Images