Wiring board

Abstract

This technology is useful for reducing the likelihood of short-circuit and open-circuit failures, as well as shortening the distance between post electrodes. [Solution] The terminal 14 of the wiring board is made of copper and comprises a post electrode 141 which is tapered at least at the top, a diffusion prevention layer 142 which is provided on the upper surface of the post electrode 141 and has a diameter R2 which is larger than the diameter R1 of the upper surface of the post electrode 141, and a solder layer 143 which covers the upper surface of the diffusion prevention layer 142.

Description

[Technical Field]

[0001] This invention relates to a wiring board. [Background technology]

[0002] In recent years, research and development in artificial intelligence and communication networks has been flourishing. Consequently, semiconductor packages used in these technologies are required to be faster and more functional.

[0003] One example of a semiconductor package designed for higher speed and functionality is one in which a semiconductor chip containing a logic integrated circuit (IC) and a semiconductor chip containing a memory IC are mounted on a single interposer. In such semiconductor packages, there are usually many terminals connecting the semiconductor chip to the wiring board such as the interposer, and the distance between these terminals is short.

[0004] To shorten the distance between these terminals, it is useful to adopt a structure for the terminals of a wiring board in which a solder layer is provided on a copper post electrode (or pillar electrode) with a diffusion-preventing layer such as a nickel layer in between, as described in Patent Document 1. However, in the manufacture of wiring boards employing such a structure for terminals, during the solder reflow process, the solder may wet and spread to the sides of the post electrode, and in some cases, it may flow off the post electrode, potentially causing a short circuit between adjacent terminals.

[0005] Regarding this problem, Patent Document 2 describes a method in which the peripheral edge of the diffusion prevention layer protrudes outward in a flange-like manner relative to the side surface of the post electrode. By adopting this structure, the wetting and spreading of solder to the side surface of the post electrode can be suppressed. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2020-188139 [Patent Document 2] Japanese Patent Publication No. 2022-189275 [Overview of the project] [Problems that the invention aims to solve]

[0007] The present invention aims to provide a useful technique for reducing the likelihood of short-circuit and open-circuit failures, as well as for shortening the distance between post electrodes. [Means for solving the problem]

[0008] According to one aspect of the present invention, a terminal for a wiring board is provided, comprising a post electrode made of copper and tapering at least at its upper end; a diffusion prevention layer provided on the upper surface of the post electrode and having a diameter R2 that is larger than the diameter R1 of the upper surface of the post electrode; and a solder layer covering the upper surface of the diffusion prevention layer.

[0009] According to another aspect of the present invention, the maximum diameter R of the post electrode max The terminal on the side is provided such that the ratio ΔR / H of the difference ΔR between the diameter R1 of the upper surface of the post electrode and the height H of the post electrode is within the range of 0.05 or more and 0.2 or less.

[0010] According to yet another aspect of the present invention, a terminal is provided relating to any of the above aspects, wherein the ratio R2 / R1 of the diameter R2 of the diffusion-preventing layer to the diameter R1 of the upper surface of the post electrode is within the range of 1.1 or more and 1.5 or less.

[0011] According to yet another aspect of the present invention, the solder layer provides a terminal relating to any of the above aspects, further covering the end face of the diffusion prevention layer.

[0012] According to yet another aspect of the present invention, the diameter of the solder layer is the maximum diameter R of the post electrode. max A terminal relating to any of the above-mentioned aspects is provided.

[0013] According to still another aspect of the present invention, the post electrode is provided with a terminal related to any one of the side surfaces whose arithmetic mean roughness Ra of the side surface is in the range of 90 nm or more and 200 nm or less.

[0014] According to still another aspect of the present invention, the post electrode is provided with a terminal related to any one of the side surfaces whose diameter is reduced downward at the lower part thereof.

[0015] According to still another aspect of the present invention, the post electrode further includes a lower conductor layer provided on the lower surface of the post electrode, and a laminate of the post electrode and the lower conductor layer is provided with a terminal related to any one of the side surfaces having a constriction at the position of the interface between the post electrode and the lower conductor layer.

[0016] According to still another aspect of the present invention, the lower conductor layer is provided with a terminal related to the side surface including a first conductor layer and a second conductor layer interposed between the first conductor layer and the post electrode.

[0017] According to still another aspect of the present invention, there is provided a terminal of a wiring board, which includes a post electrode made of copper and having an arithmetic mean roughness Ra of the side surface in the range of 90 nm or more and 200 nm or less, a diffusion prevention layer provided on the upper surface of the post electrode, and a solder layer covering the upper surface of the diffusion prevention layer.

[0018] According to still another aspect of the present invention, the post electrode is provided with a terminal related to the side surface whose diameter is reduced downward at the lower part thereof.

[0019] According to still another aspect of the present invention, the post electrode further includes a lower conductor layer provided on the lower surface of the post electrode, and a laminate of the post electrode and the lower conductor layer is provided with a terminal related to any one of the side surfaces having a constriction at the position of the interface between the post electrode and the lower conductor layer.

[0020] According to still another aspect of the present invention, the lower conductor layer is provided with a terminal related to the side surface at least a part of which in contact with the post electrode is made of copper.

[0021] According to still another aspect of the present invention, there is provided a wiring board including a terminal according to any of the above aspects, a conductor pattern, and an insulating layer, and a composite layer in which the terminal is joined to the conductor pattern such that the post electrode is positioned between the solder layer and the conductor pattern.

[0022] According to still another aspect of the present invention, there is provided a method for manufacturing a terminal of a wiring board, the method including forming a columnar post electrode made of copper, forming a diffusion prevention layer on the post electrode, forming a solder layer so as to cover the upper surface of the diffusion prevention layer, and then etching the side surface of the post electrode.

[0023] According to still another aspect of the present invention, there is provided a method for manufacturing a wiring board, the method including forming a composite layer including a conductor pattern and an insulating layer, forming a columnar post electrode made of copper on the conductor pattern, forming a diffusion prevention layer on the post electrode, forming a solder layer so as to cover the upper surface of the diffusion prevention layer, and then etching the side surface of the post electrode.

[0024] According to still another aspect of the present invention, prior to the formation of the post electrode, a seed layer is formed on the composite layer; prior to the formation of the post electrode, a resist layer having a through hole at a position where the post electrode is to be formed is provided on the seed layer; after the formation of the solder layer and prior to etching the side surface of the post electrode, the resist layer is removed; and after the removal of the resist layer, a portion of the seed layer that is not sandwiched between the post electrode and the conductor pattern is removed by etching. The post electrode is formed by electrolytic plating, and there is provided a method for manufacturing a wiring board according to the above aspect.

[0025] According to still another aspect of the present invention, there is provided a method for manufacturing a wiring board according to any of the above aspects, in which a layer made of copper is formed as the seed layer by a sputtering method. [Effects of the Invention]

[0026] According to the present invention, a technique is provided that is useful for reducing the likelihood of short-circuit and open-circuit failures, as well as for shortening the distance between post electrodes. [Brief explanation of the drawing]

[0027] [Figure 1] Figure 1 is a cross-sectional view showing a part of a wiring board according to an embodiment of the present invention. [Figure 2] Figure 2 is a magnified cross-sectional view showing the terminals included in the wiring board shown in Figure 1. [Figure 3] Figure 3 is a cross-sectional view showing the first step in the manufacturing method of the terminal shown in Figure 2. [Figure 4] Figure 4 is a cross-sectional view showing the second step in the manufacturing method of the terminal shown in Figure 2. [Figure 5] Figure 5 is a cross-sectional view showing the third step in the manufacturing method of the terminal shown in Figure 2. [Figure 6] Figure 6 is a cross-sectional view showing the fourth step in the manufacturing method of the terminal shown in Figure 2. [Figure 7] Figure 7 is a cross-sectional view showing an example of a semiconductor package including the wiring board shown in Figure 1. [Figure 8] Figure 8 is an enlarged cross-sectional view showing the terminals related to the first comparative example. [Figure 9] Figure 9 is an enlarged cross-sectional view showing the terminals related to the second comparative example. [Figure 10] Figure 10 is a cross-sectional view showing an enlarged view of the terminals related to a modified example. [Figure 11] Figure 11 is an electron microscope image of the post electrode before etching. [Figure 12] Figure 12 is an electron microscope image of a terminal according to an example of the present invention. [Modes for carrying out the invention]

[0028] Embodiments of the present invention will be described below with reference to the drawings. The embodiments described below are more specific to any of the above aspects. The matters described below can be incorporated into each of the above aspects, individually or in combination.

[0029] Furthermore, the embodiments shown below illustrate configurations for realizing the technical concept of the present invention, and the technical concept of the present invention is not limited by the material, shape, and structure of the components described below. Various modifications can be made to the technical concept of the present invention within the technical scope defined by the claims described in the claims.

[0030] Elements with similar or identical functions are given the same reference numerals in the drawings referenced below, and redundant explanations are omitted. Furthermore, the drawings are schematic, and the relationships between dimensions in one direction and those in another, and the relationships between the dimensions of one component and those of other components, may differ from reality.

[0031] Furthermore, in the following, the terms "upper" and "lower" are used to indicate the position in the thickness direction of the layer, and correspond to the upper and lower parts of the cross-sectional view, respectively. Also, the terms "upper surface" and "lower surface" used below refer to the upper and lower main surfaces of the two main surfaces of a layer in which the cross-section is drawn with the thickness direction as the vertical direction, respectively.

[0032] <1> Wiring board Figure 1 is a cross-sectional view showing a part of a wiring board according to an embodiment of the present invention. Figure 2 is a close-up cross-sectional view showing the terminals included in the wiring board of Figure 1.

[0033] The wiring board 10 shown in Figure 1 is an interposer that mediates the bonding between a semiconductor chip and a flip-chip ball grid array (FC-BGA) substrate. The wiring board 10 includes insulating layers 11A to 11C, conductor patterns 12A to 12C, bonding conductors 13, and terminals 14. Although the wiring board 10 is a coreless interposer, it may also include a core substrate.

[0034] Each of the insulating layers 11A to 11C is provided with multiple through-holes. The insulating layers 11B are stacked on top of each other. The insulating layers 11A and 11C face each other with these insulating layers 11B in between. The average distance between the centers of the through-holes in the insulating layers increases sequentially from insulating layer 11A to insulating layer 11C. In this example, the number of insulating layers 11B included in the wiring board 10 is 4, but the number of insulating layers 11B included in the wiring board 10 may be 3 or less, or 5 or more.

[0035] Each of the insulating layers 11A to 11C is, for example, an organic insulating layer containing a cured resin. The cured resin may be a cured photosensitive resin or a cured non-photosensitive resin. As the non-photosensitive resin, for example, polyimide resin, benzocyclobutene resin, epoxy resin, or modified versions thereof can be used. Non-photosensitive resins such as polyimide have excellent insulating and mechanical properties, as well as high heat resistance. In addition, inorganic particles such as silica, alumina, and zirconia may be added to the resin as fillers. For example, insulating layer 11A is a layer containing a cured epoxy resin.

[0036] Each of the insulating layers 11A to 11C may have a single-layer structure or a multi-layer structure.

[0037] The conductor pattern 12A includes through electrodes that fill the through holes in the insulating layer 11A.

[0038] Each conductor pattern 12B includes a via portion that fills a through-hole in the insulating layer 11B, a land portion and a wiring portion interposed between the insulating layer 11B and the insulating layer located below it. Each wiring portion has one end connected to a via portion and the other end connected to a land portion. The via portions included in the uppermost conductor pattern 12B are each connected to the through-electrodes included in the conductor pattern 12A. The via portions included in other conductor patterns 12B are each connected to the land portions included in the conductor pattern 12B of that information. Here, the number of conductor patterns 12B included in the wiring board 10 is 4, but the number of conductor patterns 12B included in the wiring board 10 may be 3 or less, or 5 or more.

[0039] The conductor pattern 12C includes via portions that fill through holes in the insulating layer 11C and pad portions located on the underside of the insulating layer 11C. These pad portions are connected to the via portions of the conductor pattern 12C, respectively. The via portions of the conductor pattern 12C are connected to the land portions included in the bottommost conductor pattern 12B, respectively.

[0040] Each of the conductor patterns 12A to 12C includes a lead layer. The lead layer is made of, for example, copper. Each of the conductor patterns 12A to 12C may further include one or more other layers. For example, one or more of the conductor patterns 12A to 12C may further include a seed layer, or a seed layer and an adhesion layer.

[0041] A seed layer is provided when the conductor pattern is formed by electroplating. The material of the seed layer is appropriately selected from the group consisting of, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi (aluminum-silicon alloy), AlSiCu (aluminum-silicon-copper alloy), AlCu (aluminum-copper alloy), NiFe (nickel-iron alloy), ITO (indium tin oxide), IZO (indium-doped zinc oxide), AZO (aluminum-doped zinc oxide), ZnO (zinc oxide), PZT (lead zirconate titanate), TiN (titanium nitride), and Cu3N4. The thickness of the seed layer is preferably in the range of 100 nm to 1000 nm, and more preferably in the range of 100 nm to 500 nm.

[0042] An adhesion layer can be provided between the insulating layer and the seed layer to improve their adhesion. The adhesion layer is a thin metal layer formed, for example, by sputtering or electroless plating. Titanium is preferred as the material for the adhesion layer. The thickness of the adhesion layer is preferably in the range of 5 nm to 100 nm, considering the formation of a continuous film and productivity.

[0043] The bonding conductor 13 is a bonding material for bonding and electrical connection between the wiring board 10 and the FC-BGA board. Here, the bonding conductor 13 is a solder bump provided on the pad portion of the conductor pattern 12C. The bonding conductor 13 may further include one or more other layers between the conductor pattern 12C and the solder bump. One or more other layers are provided, for example, for the purpose of preventing diffusion, preventing oxidation of the conductor pattern 12C, or improving the wettability of the solder to the conductor pattern 12C.

[0044] Each terminal 14 is provided on a through electrode included in the conductor pattern 12A. These terminals 14 are for joining and electrically connecting the wiring board 10 and the semiconductor chip.

[0045] As shown in Figure 2, terminal 14 includes a post electrode 141, a diffusion prevention layer 142, a solder layer 143, and a lower conductor layer 144.

[0046] The post electrodes 141 are each located above the through electrodes included in the conductor pattern 12A. The post electrodes 141 are made of copper.

[0047] Each post electrode 141 has a shape that extends in the thickness direction of the wiring board 10. Each post electrode 141 is tapered at least at the top. Here, each post electrode 141 has a roughly frustoconical shape. Also, here, each post electrode 141 is tapered downwards at its lower part. Each post electrode 141 does not have to be tapered downwards at its lower part.

[0048] By tapering the upper part of the post electrode 141, a flange-like portion can be created in the diffusion prevention layer 142 without excessively increasing the diameter R2 of the diffusion prevention layer 142. Therefore, by adopting this structure, solder wetting and spreading to the sides of the post electrode 141 becomes less likely, thereby reducing the occurrence of short-circuit and open-circuit defects described later, and shortening the distance between the post electrodes 141.

[0049] The height H of the post electrode 141 is preferably in the range of 10.0 μm to 50.0 μm, and more preferably in the range of 20.0 μm to 40.0 μm.

[0050] Maximum diameter R of post electrode 141 max The maximum diameter R is preferably within the range of 10.0 μm to 30.0 μm, and more preferably within the range of 15.0 μm to 25.0 μm. max Reducing the maximum diameter R will decrease the strength of terminal 14. max Increasing the size of the terminals makes it difficult to arrange the terminals 14 at a high density.

[0051] Post electrode 141 has the maximum diameter R maxThe position having it is preferably within a range where the height based on the lower surface of the post electrode 141 is 1000 nm or less, and more preferably 500 nm or less.

[0052] The ratio R1 / R of the diameter R1 of the upper surface of the post electrode 141 to the maximum diameter R of the post electrode 141 max is preferably within a range of 0.80 or more and 0.95 or less, and more preferably within a range of 0.85 or more and 0.90 or less. Without making the diameter R2 of the diffusion prevention layer 142 excessively large, in order to form a flange-like portion on the diffusion prevention layer 142, it is advantageous to increase the ratio R1 / R max However, increasing the ratio R1 / R max will reduce the strength of the terminal 14.

[0053] The maximum diameter R of the post electrode 141 max The ratio ΔR / H of the difference ΔR between the maximum diameter R of the post electrode 141 and the diameter R1 of the upper surface of the post electrode 141 to the height H of the post electrode 141 is preferably within a range of 0.05 or more and 0.2 or less, more preferably within a range of 0.065 or more and 0.13 or less, and still more preferably within a range of 0.07 or more and 0.12 or less. Without making the diameter R2 of the diffusion prevention layer 142 excessively large, in order to form a flange-like portion on the diffusion prevention layer 142, it is advantageous to increase the ratio ΔR / H. However, increasing the ratio ΔR / H will reduce the strength of the terminal 14.

[0054] The shortest distance D2 between the post electrodes 141 is preferably within a range of 10.0 μm or more and 30.0 μm or less, and more preferably within a range of 15.0 μm or more and 20.0 μm or less.

[0055] ​​The post electrode 141 may have an uneven surface on its side. This uneven surface can be created, for example, by etching the post electrode 141 to give it a tapered shape. This uneven surface can prevent solder from flowing off the post electrode 141 when solder reflow is performed during the manufacturing of the wiring board 10 and the solder wets and spreads to the side of the post electrode 141. Furthermore, this uneven surface can improve the adhesion between the post electrode 141 and the underfill layer, making it less likely for the underfill layer to peel off. The arithmetic mean roughness Ra (according to JIS B0601:2013) of the side surface of the post electrode 141 is preferably in the range of 90 nm to 200 nm, and preferably in the range of 100 nm to 150 nm.

[0056] The diffusion prevention layer 142 is provided on the upper surface of each post electrode 141. The diffusion prevention layer 142 is made of, for example, one or more of nickel, titanium, chromium, tungsten, and alloys obtained by doping these with at least one of copper and zinc.

[0057] The thickness of the diffusion prevention layer 142 is preferably in the range of 2000 nm to 5000 nm, and more preferably in the range of 3000 nm to 4500 nm.

[0058] Each of the diffusion-blocking layers 142 has a diameter R2 that is larger than the diameter R1 of the upper surface of the post electrode 141 located below it. Each of the diffusion-blocking layers 142 has a portion located directly above the post electrode 141 and a flange-shaped portion surrounding this portion. Preferably, the orthogonal projection of the diffusion-blocking layer 142 onto a plane perpendicular to the thickness direction of the wiring substrate 10 has a shape similar to the upper surface of the post electrode 141. For example, the above orthogonal projection is approximately circular. Also preferably, the position of the centroid of the orthogonal projection of the diffusion-blocking layer 142 onto the plane perpendicular to the thickness direction of the wiring substrate 10 coincides with the position of the centroid of the orthogonal projection of the upper surface of the post electrode 141 onto the above plane.

[0059] The ratio R2 / R1 between the diameter R2 of the diffusion prevention layer 142 and the diameter R1 of the upper surface of the post electrode 141 is preferably in the range of 1.1 to 1.5, and more preferably in the range of 1.2 to 1.4. The ratio R2 / R1 may also be 1.3 or less. Increasing the ratio R2 / R1 reduces the possibility of solder wetting and spreading to the side surface of the post electrode 141 when solder reflow processing is performed during the manufacturing of the wiring board 10. However, increasing the ratio R2 / R1 reduces the strength of the terminal 14.

[0060] The shortest distance D1 between the diffusion-preventing layers 142 is preferably within the range of 10.0 μm to 30.0 μm, and more preferably within the range of 15.0 μm to 20.0 μm.

[0061] The solder layer 143 covers the upper surface of the diffusion prevention layer 142. Here, the solder layer 143 covers the entire upper surface of the diffusion prevention layer 142. Also, here, the upper surface of the solder layer 143 is a convex curved surface that protrudes upward. The solder layer 143 is made of, for example, lead-free solder containing tin and silver.

[0062] The height of the solder layer 143 is preferably in the range of 8.0 μm to 20.0 μm, and more preferably in the range of 10.0 μm to 15.0 μm.

[0063] The lower conductor layers 144 are provided on the lower surface of each post electrode 141. That is, each lower conductor layer 144 is located between the post electrode 141 and the through electrode included in the conductor pattern 12A. Preferably, at least the portion of the lower conductor layer 144 that is in contact with the post electrode 141 is made of copper.

[0064] The lower conductor layer 144 here includes a first conductor layer 144A and a second conductor layer 144B.

[0065] The first conductor layer 144A is interposed between the post electrode 141 and the through electrode included in the conductor pattern 12A. The first conductor layer 144A is part of an adhesion layer formed to improve the adhesion of the seed layer, for example, when electroplating is used to form the post electrode 141. The first conductor layer 144A can be formed, for example, by film deposition by sputtering or electroless plating and patterning by etching.

[0066] As the material for the first conductor layer 144A, for example, the materials exemplified for the adhesion layer included in the conductor patterns 12A to 12C can be used. The thickness of the first conductor layer 144A is preferably within the range described above for the adhesion layer included in the conductor patterns 12A to 12C. The first conductor layer 144A may be omitted.

[0067] The second conductor layer 144B is interposed between the first conductor layer 144A and the post electrode 141. The second conductor layer 144B is part of a seed layer used as a power supply layer, for example, when electroplating is used to form the post electrode 141. The second conductor layer 144B is made of a metallic material such as copper. The second conductor layer 144B can be formed, for example, by film deposition by sputtering and patterning by etching.

[0068] As the material for the second conductor layer 144B, for example, the materials exemplified for the seed layers included in the conductor patterns 12A to 12C can be used. The second conductor layer 144B is preferably made of copper. The thickness of the second conductor layer 144B is preferably within the range described above for the seed layers included in the conductor patterns 12A to 12C.

[0069] The laminate of the post electrode 141 and the lower conductor layer 144 has a constricted portion C at the interface between the post electrode 141 and the lower conductor layer 144. The constricted portion C can prevent solder from flowing off the post electrode 141 if, for example, solder reflow processing is performed during the manufacturing of the wiring board 10 and the solder wets and spreads to the side surface of the post electrode 141. This laminate does not necessarily have to have the constricted portion C.

[0070] The minimum diameter R of the laminate at the position of the constricted portion C min And the maximum diameter R of the post electrode 141 max R ratio min / R max It is preferable that the value is within the range of 0.85 or more and less than 1.00, and more preferably within the range of 0.90 or more and 0.98 or less.

[0071] The dimensions of the constricted portion C in the thickness direction of the wiring board 10 are, for example, equal to the thickness of the second conductor layer 144B, or slightly larger than the thickness of the second conductor layer 144B. The ratio W / T of the dimensions W of the constricted portion C in the thickness direction of the wiring board 10 to the thickness T of the lower conductor layer 144 is preferably in the range of 0.5 to 0.86, and more preferably in the range of 0.7 to 0.82.

[0072] <2> Manufacturing method of wiring boards In the manufacturing of the wiring board 10 shown in Figure 1, the insulating layer 11A and the conductor pattern 12A can be formed, for example, by forming a seed layer by sputtering or electroless plating, forming a resist pattern with openings at the positions of the through-electrodes of the conductor pattern 12A, forming the conductor pattern 12A by electroplating, removing the resist pattern, embedding the conductor pattern 12A with resin as the material for the insulating layer 11A, and polishing the resin layer by chemical mechanical polishing (CMP).

[0073] A laminate consisting of an insulating layer 11B and a conductor pattern 12B can be formed, for example, by repeating a cycle that includes forming an insulating layer 11B having through holes at positions corresponding to via portions of the conductor pattern 12B, forming an adhesion layer and a seed layer by sputtering or electroless plating, forming a resist pattern with openings at positions corresponding to wiring portions and land portions, forming the conductor pattern 12B by electroplating, removing the resist pattern, and removing exposed portions of the adhesion layer and seed layer by etching.

[0074] The insulating layer 11C, the conductor pattern 12C, and the bonding conductor 13 can be formed, for example, by forming a resist pattern with openings at positions corresponding to the pad portions, forming the conductor pattern 12C and the bonding conductor 13 by electroplating, removing the resist pattern, removing exposed portions of the adhesion layer and seed layer by etching, forming the insulating layer 11C having through holes at positions corresponding to the via portions of the conductor pattern 12, forming the adhesion layer and seed layer by sputtering or electroless plating, and performing a reflow process.

[0075] Terminal 14 can be formed, for example, by the following method. Figures 3 to 6 are cross-sectional views showing the manufacturing method of the terminal shown in Figure 2. Here, as an example, the first conductor layer 144A is made of titanium, the post electrode 141 and the second conductor layer 144B are made of copper, and the diffusion prevention layer 142 is made of nickel.

[0076] In this method, as shown in Figure 3, a first conductor layer 144A and a second conductor layer 144B are formed as a continuous film on the insulating layer 11A side of the laminate. The first conductor layer 144A is formed, for example, by sputtering or electroless plating. The second conductor layer 144B is formed, for example, by sputtering. Next, a resist pattern 19 is formed on the second conductor layer 144B, each having through holes at the positions of the through electrodes of the conductor pattern 12A. Subsequently, a post electrode 141, a diffusion prevention layer 142, and a solder layer 143 are formed in this order on the upper surface of the second conductor layer 144B at the positions of the through holes of the resist pattern 19 by electroplating.

[0077] Next, as shown in Figure 4, the resist pattern 19 is removed. Then, the exposed portion of the second conductor layer 144B, that is, the portion of the second conductor layer 144B that is not sandwiched between the post electrode 141 and the through electrode of the conductor pattern 12A, is removed by wet etching. This wet etching is continued for a sufficient amount of time even after the exposed portion of the second conductor layer 144B has been removed. This etches the side surface of the post electrode 141 and creates a structure corresponding to the constricted portion C described above in the laminate of the post electrode 141 and the second conductor layer 144B at the location of the second conductor layer 144B. In this way, the structure shown in Figure 5 is obtained.

[0078] Next, as shown in Figure 6, the exposed portion of the first conductor layer 144A, that is, the portion of the first conductor layer 144A that is not sandwiched between the second conductor layer 144B and the through-electrode of the conductor pattern 12A, is removed. After that, solder reflow processing is performed. In this way, terminal 14 is obtained.

[0079] <3> Semiconductor packages Figure 7 is a cross-sectional view showing an example of a semiconductor package including the wiring board shown in Figure 1.

[0080] The semiconductor package 1 shown in Figure 7 includes a wiring substrate 10, semiconductor chips 20A and 20B, an underfill layer 30A, and a molded resin layer 30B.

[0081] The semiconductor chip 20A is, for example, a semiconductor chip with a built-in logic IC. The semiconductor chip 20B is, for example, a semiconductor chip with a built-in memory IC or a semiconductor chip with a built-in logic IC. The semiconductor chip 20B consists of multiple stacks, and these stacks and the semiconductor chip 20A are bonded to the wiring board 10 via terminals 14. The semiconductor chip 20B can be omitted.

[0082] The underfill layer 30A is interposed between the gap between the semiconductor chip 20A and the wiring substrate 10, and between the laminate consisting of the semiconductor chip 20B and the wiring substrate 10. The mold resin layer 30B, together with the underfill layer 30A, constitutes the sealing resin layer 30. The sealing resin layer 30 embeds the semiconductor chips 20A and 20B.

[0083] <4> effect Figure 8 is an enlarged cross-sectional view showing the terminals of the first comparative example. Figure 9 is an enlarged cross-sectional view showing the terminals of the second comparative example.

[0084] In the structures shown in Figures 8 and 9, the insulating layer 11 and the conductor pattern 12 correspond to the insulating layer 11A and the conductor pattern 12A, respectively. In terminal 14X shown in Figure 8 and terminal 14Y shown in Figure 9, the portion of the post electrode 141 that protrudes upward from the upper surface of the insulating layer 11 has a cylindrical shape. In terminal 14X, the diameter of the diffusion prevention layer 142 is equal to the diameter of the upper surface of the post electrode 141. In terminal 14Y, the diameter of the diffusion prevention layer 142 is larger than the diameter of the upper surface of the post electrode 141.

[0085] In wiring boards having terminals 14X, solder wetting and spreading occurs on the sides of the post electrode 141 during solder reflow processing or when joining semiconductor chips during manufacturing, and furthermore, the solder tends to flow off the post electrode 141. If the solder that flows off the post electrode 141 spreads on the insulating layer 11, it can cause a short circuit (short fault) between adjacent terminals 14X. Also, if the amount of solder that flows off the diffusion prevention layer 142 increases, the variation in the height of the solder layer 143 increases. As a result, terminals 14X with a high solder layer 143 are more likely to be joined to the semiconductor chip terminals, while terminals 14X with a low solder layer 143 are more likely to be joined to the semiconductor chip terminals, resulting in a joining fault, i.e., an open fault.

[0086] A wiring board having terminal 14Y is less prone to solder wetting and spreading to the side of the post electrode 141 compared to a wiring board having terminal 14X. Therefore, a wiring board having terminal 14Y is less prone to the aforementioned short-circuit and open-circuit defects compared to a wiring board having terminal 14X.

[0087] However, if the shortest distance D2 between post electrodes 141 is the same, the shortest distance D1 is smaller in a wiring board with terminal 14Y compared to a wiring board with terminal 14X. Reducing the shortest distance D1 makes it easier for short-circuit defects to occur, for example, when joining the wiring board and the semiconductor chip.

[0088] As described above, terminal 14 employs a structure in which the upper part of the post electrode 141 is tapered. By tapering the upper part of the post electrode 141, a flange-like portion can be created in the diffusion prevention layer 142 without making the diameter R2 of the diffusion prevention layer 142 excessively large. This flange-like portion makes it difficult for solder to spread to the sides of the post electrode 141. When solder spreading to the sides of the post electrode 141 is reduced, short-circuit failures caused by this are less likely to occur.

[0089] Furthermore, since a flange-like portion can be created in the diffusion prevention layer 142 without excessively increasing the diameter R2 of the diffusion prevention layer 142, the shortest distance D1 does not become excessively small. Therefore, short-circuit failures caused by an excessively small shortest distance D1 are less likely to occur.

[0090] Furthermore, when solder wetting and spreading to the sides of the post electrode 141 becomes less likely, variations in the height of the solder layer 143 decrease, and open-circuit defects caused by these height variations become less likely.

[0091] Therefore, by adopting the above structure, short-circuit and open-circuit failures are less likely to occur, and the distance between post electrodes can be shortened.

[0092] Furthermore, if irregularities are provided on the side surface of the post electrode 141, these irregularities can prevent the solder from flowing off the post electrode 141 when the solder wets and spreads to the side surface of the post electrode 141. Therefore, these irregularities make it less likely for short-circuit defects to occur and can reduce variations in the height of the solder layer 143. Thus, when this structure is adopted, it is less likely for short-circuit and open-circuit defects to occur and the distance between post electrodes can be shortened.

[0093] Thus, both the structure in which the upper part of the post electrode 141 is tapered and the structure in which irregularities are provided on the side surface of the post electrode 141 make it difficult for short-circuit and open-circuit failures to occur, and also make it possible to shorten the distance between post electrodes. Therefore, this effect can be obtained even if the terminal 14 does not have one of these structures. However, the combination of these structures is particularly effective in making short-circuit and open-circuit failures difficult to occur and shortening the distance between post electrodes.

[0094] <5> Variation The techniques described above can be modified in various ways.

[0095] Figure 10 is a cross-sectional view showing an enlarged view of the terminals related to a modified example. The terminal 14 shown in Figure 10 is the same as the terminal 14 described with reference to Figure 2, except that the solder layer 143 further covers not only the upper surface of the diffusion prevention layer 142 but also the end face of the diffusion prevention layer 142. Thus, the solder layer 143 may further cover not only the upper surface of the diffusion prevention layer 142 but also the end face of the diffusion prevention layer 142. Furthermore, the wiring board 10 may have the solder layer 143 covering only the upper surface of the diffusion prevention layer 142 for all terminals 14, or the solder layer 143 covering both the upper surface and end face of the diffusion prevention layer 142 for all terminals 14, or the solder layer 143 covering only the upper surface of the diffusion prevention layer 142 for some terminals 14 and covering both the upper surface and end face of the diffusion prevention layer 142 for the rest of the terminals 14. [Examples]

[0096] The tests conducted in connection with the present invention are described below.

[0097] (Manufacturing of Sample A) Sample A was manufactured using the following method. First, a substrate was prepared in which copper layers were provided on both sides of an insulating substrate. Next, an insulating layer 11A, a conductor pattern 12A, and terminals 14 were formed on this substrate using the same method as described above.

[0098] Specifically, epoxy resin was used for the insulating layer 11A, and copper was used for the conductor pattern 12A.

[0099] For the first conductive layer 144A, a titanium layer with a thickness of 50 nm was formed by sputtering. For the second conductive layer 144B, a copper layer with a thickness of 200 nm was formed by sputtering.

[0100] A copper post with a height H of 30.0 μm was formed as the post electrode 141. A nickel layer with a thickness of 3.0 μm was formed as the diffusion prevention layer 142. The diffusion prevention layer 142 was formed so that its orthogonal projection perpendicular to its thickness direction was a circle with a diameter of 20.0 μm. Lead-free solder containing tin and silver was used for the solder layer 143.

[0101] For etching the second conductor layer 144B and the post electrode 141, Meltex's E-Process-WL etchant bath was used as the etching solution. Etching of the post electrode 141 was performed at a temperature of 30.0°C for 40 seconds starting from the point when the exposed portion of the second conductor layer 144B was completely removed.

[0102] (Manufacturing of Sample B) Sample B was prepared using the same method as described above for Sample A, except that the etching time for post-electrode 141 was changed from 40 seconds to 50 seconds.

[0103] (Manufacturing of Sample C) Sample C was prepared using the same method as described above for Sample A, except that the etching time for post-electrode 141 was changed from 40 seconds to 60 seconds.

[0104] (Manufacturing of Sample D) Sample D was prepared using the same method as described above for Sample A, except that the etching time for post-electrode 141 was changed from 40 seconds to 70 seconds.

[0105] (Manufacturing of Sample E) Sample E was prepared using the same method as described above for Sample A, except that the etching time for post-electrode 141 was changed from 40 seconds to 80 seconds.

[0106] (Manufacturing of Sample F) Sample F was prepared using the same method as described above for Sample A, except that the etching time for post-electrode 141 was changed from 40 seconds to 90 seconds.

[0107] (Manufacturing of Sample G) Sample G was prepared using the same method as described above for Sample A, except that etching of the post electrode 141 was omitted.

[0108] (Measurement and evaluation) For each of samples A through G, dimensional measurements and visual inspections were performed using a metallurgical microscope and a scanning electron microscope, surface texture measurements were performed using a laser microscope, and the presence or absence of short-circuit defects was checked using a four-terminal, four-probe high-precision resistivity meter.

[0109] Furthermore, semiconductor chips were bonded to each of samples A through G. For each of these samples, the presence or absence of short-circuit and open-circuit defects was checked using a four-terminal, four-probe high-precision resistivity meter.

[0110] Furthermore, an underfill layer was formed on each of samples A through G, which had semiconductor chips bonded to them. Each of these samples was then subjected to durability tests, including thermal cycling tests from -55.0°C to 125.0°C. Afterward, the presence or absence of delamination of the underfill layer was confirmed by cross-sectional observation using a scanning electron microscope. The results are shown in Table 1 below. Images obtained for samples E and A are shown in Figures 11 and 12, respectively.

[0111] [Table 1]

[0112] As shown in Table 1, sample G exhibited solder dripping, open circuit failure, and underfill layer delamination. In contrast, samples A through F did not exhibit any of these issues. Furthermore, samples E and F exhibited pillar collapse (post electrode collapse), while samples A through C did not. [Explanation of symbols]

[0113] 1...Semiconductor package, 10...Wiring board, 11...Insulating layer, 11A...Insulating layer, 11B...Insulating layer, 11C...Insulating layer, 12...Conductor pattern, 12A...Conductor pattern, 12B...Conductor pattern, 12C...Conductor pattern, 13...Bonding conductor, 14...Terminal, 14X...Terminal, 14Y...Terminal, 20A...Semiconductor chip, 20B...Semiconductor chip, 30...Sealing resin layer, 30A...Underfill layer, 30B...Molding resin layer, 141...Post electrode, 142...Diffusion prevention layer, 143...Solder layer, 144...Lower conductor layer, 144A...First conductor layer, 144B...Second conductor layer, C...Narrowed part, D1...Shortest distance, D2...Shortest distance, R1...Diameter, R2...Diameter, H...Height.

Claims

1. Terminals on a wiring board, A post electrode made of copper, with at least the top part tapering, A diffusion prevention layer is provided on the upper surface of the post electrode and has a diameter R2 that is larger than the diameter R1 of the upper surface of the post electrode, A solder layer covering the upper surface of the diffusion prevention layer and Terminals that are provided.

2. The maximum diameter R of the post electrode ｍａｘ The terminal according to claim 1, wherein the ratio ΔR / H of the difference ΔR between the diameter R1 of the upper surface of the post electrode and the height H of the post electrode is within the range of 0.05 or more and 0.2 or less.

3. The terminal according to claim 1, wherein the ratio R2 / R1 of the diameter R2 of the diffusion prevention layer to the diameter R1 of the upper surface of the post electrode is within the range of 1.1 or more and 1.5 or less.

4. The terminal according to claim 1, wherein the solder layer further covers the end face of the diffusion prevention layer.

5. The diameter of the solder layer is the maximum diameter R of the post electrode. ｍａｘ The terminal according to claim 1, which is as follows:

6. The terminal according to claim 1, wherein the post electrode has an arithmetic mean roughness Ra of the side surface in the range of 90 nm to 200 nm.

7. The terminal according to claim 1, wherein the post electrode is tapered downwards at its lower part.

8. The post electrode further comprises a lower conductive layer provided on the lower surface of the post electrode, The terminal according to claim 1, wherein the laminate of the post electrode and the lower conductor layer has a constricted portion at the interface between the post electrode and the lower conductor layer.

9. The terminal according to claim 8, wherein the lower conductor layer includes a first conductor layer and a second conductor layer interposed between the first conductor layer and the post electrode.

10. Terminals on a wiring board, A post electrode made of copper, with an arithmetic mean roughness Ra of the side surface in the range of 90 nm to 200 nm, A diffusion prevention layer provided on the upper surface of the post electrode, A solder layer covering the upper surface of the diffusion prevention layer and Terminals that are provided.

11. The terminal according to claim 10, wherein the post electrode is tapered downwards at its lower part.

12. The post electrode further comprises a lower conductive layer provided on the lower surface of the post electrode, The terminal according to claim 10, wherein the laminate of the post electrode and the lower conductor layer has a constricted portion at the interface between the post electrode and the lower conductor layer.

13. The terminal according to claim 12, wherein the lower conductor layer is made of copper in at least the portion in contact with the post electrode.

14. A terminal according to any one of claims 1 to 13, A composite layer comprising a conductor pattern and an insulating layer, wherein the terminal is bonded to the conductor pattern such that the post electrode is located between the solder layer and the conductor pattern. A wiring board equipped with [a specific feature].

15. A method for manufacturing terminals of a wiring board, Forming a columnar post electrode made of copper, Forming a diffusion prevention layer on the post electrode, A solder layer is formed so as to cover the upper surface of the diffusion prevention layer, Subsequently, the side surface of the post electrode is etched. A method for manufacturing terminals that include [a specific component].

16. Forming a composite layer including a conductor pattern and an insulating layer, Forming a columnar post electrode made of copper on the aforementioned conductor pattern, Forming a diffusion prevention layer on the post electrode, A solder layer is formed so as to cover the upper surface of the diffusion prevention layer, Subsequently, the side surface of the post electrode is etched. A method for manufacturing a wiring board that includes [the specified component].

17. Prior to the formation of the post electrode, a seed layer is formed on the composite layer, Prior to the formation of the post electrode, a resist layer having through holes at the position where the post electrode is to be formed is provided on the seed layer, After forming the solder layer, and prior to etching the side surface of the post electrode, the resist layer is removed. After removing the resist layer, the portion of the seed layer that is not sandwiched between the post electrode and the conductor pattern is removed by etching. It further includes, The method for manufacturing a wiring board according to claim 16, wherein the post electrode is formed by electroplating.

18. The method for manufacturing a wiring board according to claim 17, wherein a layer made of copper is formed as the seed layer by a sputtering method.

Images