Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same that can suppress parasitic capacitance between wirings to a low level. [Solution] The semiconductor device according to this embodiment comprises a plurality of first wirings and a plurality of second wirings. The plurality of first wirings are provided in a first direction relative to the first insulating film, extend in a second direction intersecting the first direction, and are arranged in a third direction intersecting the first and second directions. The plurality of second wirings are provided in the first direction of the plurality of first wirings. The plurality of first contacts electrically connect the plurality of first wirings and the plurality of second wirings, respectively. The second insulating film is filled between the plurality of first wirings in a first region that includes the region where the plurality of first contacts are formed when viewed from the first direction. The air gap insulating film has an air gap between the plurality of first wirings in a second region other than the first region when viewed from the first direction.

Description

Technical Field

[0001] This embodiment relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] A semiconductor memory device such as a NAND type flash memory may have a three-dimensional memory cell array in which a plurality of memory cells are three-dimensionally arranged. As the memory cell array is miniaturized, the interval between a plurality of adjacent wirings becomes narrow. Thereby, there is a risk that the parasitic capacitance between the wirings increases.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Provided are a semiconductor device and a method for manufacturing the same that can suppress the parasitic capacitance between wirings to a low level.

Means for Solving the Problems

[0005] The semiconductor device according to this embodiment includes a plurality of first wirings and a plurality of second wirings. The plurality of first wirings are provided in a first direction with respect to a first insulating film, extend in a second direction intersecting the first direction, and are arranged in a third direction intersecting the first and second directions. The plurality of second wirings are provided in the first direction of the plurality of first wirings. The plurality of first contacts electrically connect between the plurality of first wirings and the plurality of second wirings, respectively. The second insulating film is filled between the plurality of first wirings in a first region including a region where the plurality of first contacts are formed when viewed from the first direction. The air gap insulating film has an air gap between the plurality of first wirings in a second region other than the first region when viewed from the first direction. [Brief explanation of the drawing]

[0006] [Figure 1] This is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to the first embodiment. [Figure 2] This is a schematic plan view showing a laminate. [Figure 3] This is a schematic cross-sectional view illustrating a three-dimensional memory cell structure. [Figure 4] This is a schematic cross-sectional view illustrating a three-dimensional memory cell structure. [Figure 5] This is a schematic plan view showing an example of the configuration of the bit line and surrounding area according to the first embodiment. [Figure 6] This is a plan view showing an example of the arrangement of bit lines and via contacts in the via formation region. [Figure 7] This is a cross-sectional view showing an example of the configuration of the bit line and its surroundings in the air gap region. [Figure 8] This is a cross-sectional view showing an example of the configuration of the bit line and its surroundings in the embedded region. [Figure 9] This is a cross-sectional view showing an example of the configuration of the surrounding area. [Figure 10] This is a cross-sectional view showing an example of a semiconductor memory device manufacturing method according to the first embodiment. [Figure 11] Figure 10 is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 12] Figure 11 is followed by a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 13] Figure 12 is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 14] Figure 13 is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 15] Figure 14 is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 16] Figure 15 is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 17]It is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device following FIG. 16. [Figure 18] It is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device following FIG. 17. [Figure 19] It is a cross-sectional view showing an example of a configuration of a bit line and its periphery in an air gap region of a semiconductor memory device according to the second embodiment. [Figure 20] It is a cross-sectional view showing an example of a configuration of a bit line and its periphery in an air gap region of a semiconductor memory device according to the second embodiment. [Figure 21] It is a cross-sectional view showing an example of a configuration of a peripheral region of a semiconductor memory device according to the second embodiment. [Figure 22] It is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device according to the second embodiment. [Figure 23] It is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device following FIG. 22. [Figure 24] It is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device following FIG. 23. [Figure 25] It is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device following FIG. 24. [Figure 26] It is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device following FIG. 25. [Figure 27] It is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device following FIG. 26. <​​​​​​​​​​​​​​​​ [Figure 34] Figure 33 is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 35] Figure 34 is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 36] This is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to a modification of the fourth embodiment. [Figure 37] This is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to a modification of the fourth embodiment. [Figure 38] This is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to a modification of the fourth embodiment. [Figure 39] This is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to a modification of the fourth embodiment. [Figure 40] This is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to the fifth embodiment. [Figure 41] This is a cross-sectional view showing an example of a semiconductor memory device manufacturing method according to the fifth embodiment. [Figure 42] Figure 41 is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 43] Figure 42 is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 44] Figure 43 is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 45] Figure 44 is a cross-sectional view showing an example of a semiconductor memory device manufacturing method. [Figure 46] This is a block diagram showing an example configuration of a semiconductor memory device using an array chip. [Figure 47] This is a circuit diagram showing an example of a memory cell array circuit configuration. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will be described below with reference to the drawings. These embodiments are not limiting to the present invention. The drawings are schematic or conceptual. The same elements are denoted by the same reference numerals in the specification and the drawings.

[0008] (First Embodiment) Figure 1 is a cross-sectional view showing an example of the configuration of a semiconductor memory device 1 according to the first embodiment. Hereinafter, the stacking direction of the stacked body 20 will be referred to as the Z direction. One direction that intersects the Z direction, for example, is orthogonal to it, will be referred to as the Y direction. One direction that intersects both the Z direction and the Y direction, for example, is orthogonal to them, will be referred to as the X direction. In this specification, the -Z direction is an example of the first direction. The ±X directions are examples of second directions that intersect (for example, are orthogonal to) the first direction, and the ±Y directions are examples of third directions that intersect both the first and second directions. In Figure 1, "up" refers to the +Z direction. However, in Figure 2 and subsequent figures, "up" may refer to the -Z direction.

[0009] The semiconductor memory device 1 comprises an array chip 2 having a memory cell array and a CMOS chip 3 having a CMOS circuit. The array chip 2 and the CMOS chip 3 are bonded together on a bonding surface B1 and are electrically connected to each other via wiring joined on the bonding surface. Figure 1 shows the array chip 2 mounted on the CMOS chip 3.

[0010] The CMOS chip 3 comprises a substrate 30, a transistor 31, a via contact 32, wiring 33 and 34, and an interlayer insulating film 35.

[0011] The substrate 30 is, for example, a semiconductor substrate such as a silicon substrate. The transistor 31 is an NMOS or PMOS transistor provided on the substrate 30. The transistor 31 constitutes a CMOS circuit that controls the memory cell array of the array chip 2, for example. Multiple transistors 31 constitute logic circuits such as a sense amplifier, a row decoder, and a column decoder. Semiconductor elements other than transistors 31, such as resistors and capacitive elements, may be formed on the substrate 30.

[0012] The via contact 32 electrically connects the transistor 31 to the wiring 33, or to the wiring 33 and the wiring 34. The wirings 33 and 34 form a multilayer wiring structure within the interlayer insulating film 35. The wiring 34 is embedded within the interlayer insulating film 35 and is exposed almost flush with the surface of the interlayer insulating film 35. The wirings 33 and 34 are electrically connected to the transistor 31, etc. Metals such as copper and tungsten are used for the via contact 32, wirings 33 and 34. The interlayer insulating film 35 covers and protects the transistor 31, via contact 32, wirings 33 and 34. An insulating film such as a silicon oxide film is used for the interlayer insulating film 35.

[0013] The array chip 2 comprises a laminate 20, a columnar body CL, a slit ST(LI), a source layer BSL, a metal layer 40, a contact plug CCw, a contact plug 29, a bonding pad 50, and an interlayer insulating film 25.

[0014] The laminate 20 is located above the transistor 31 and is positioned in the +Z direction relative to the substrate 30. The laminate 20 is constructed by alternately stacking a plurality of electrode films 21 and a plurality of insulating films 22 along the Z direction. The laminate 20 constitutes a memory cell array. For example, a conductive metal such as tungsten is used for the electrode films 21. For example, an insulating film such as a silicon oxide film is used for the insulating films 22. The insulating films 22 insulate the electrode films 21 from each other. That is, the plurality of electrode films 21 are stacked in an insulated state from each other. The number of stacks of each electrode film 21 and insulating film 22 is arbitrary. The insulating film 22 may be, for example, a porous insulating film or an air gap.

[0015] One or more electrode films 21 at the upper and lower ends of the stacked body 20 in the Z direction function as a source-side selection gate SGS and a drain-side selection gate SGD, respectively. The electrode film 21 between the source-side selection gate SGS and the drain-side selection gate SGD functions as a word line WL. The word line WL is the gate electrode of the memory cell MC. The source-side selection gate SGS is the gate electrode of the source-side selection transistor. The drain-side selection gate SGD is the gate electrode of the drain-side selection transistor. The source-side selection gate SGS is located in the upper region of the stacked body 20. The drain-side selection gate SGD is located in the lower region of the stacked body 20. The upper region refers to the region of the stacked body 20 that is farther from the CMOS chip 3 (closer to the metal layer 40), and the lower region refers to the region of the stacked body 20 that is closer to the CMOS chip 3.

[0016] The semiconductor memory device 1 has multiple memory cells MC connected in series between a source-side selection transistor and a drain-side selection transistor. The structure in which the source-side selection transistor, memory cells MC, and drain-side selection transistor are connected in series is called a “memory string” or “NAND string”. The memory string is connected to a bit line BL via, for example, a via contact 28. The bit line BL is a wiring 23 located below the stack 20 and extending in the X direction (plane-of-paper direction in Figure 1).

[0017] Multiple columnar bodies CL are provided within the laminate 20. The columnar bodies CL extend through the laminate 20 in the stacking direction (Z direction) and are provided from the via contact 28 connected to the bit line BL to the source layer BSL. The internal structure of the columnar bodies CL will be described later. In this embodiment, the columnar bodies CL are formed in two stages in the Z direction. However, it is not a problem if the columnar bodies CL are in one stage. Alternatively, the columnar bodies CL may be formed in three or more stages.

[0018] Although not shown in Figure 1, multiple slits ST (see Figure 2) are provided within the laminate 20. The slits ST extend in the Y direction and penetrate the laminate 20 in the stacking direction (Z direction). The slits ST are filled with an insulating film such as a silicon oxide film, and the insulating film is configured in a plate shape. The slits ST electrically isolate the electrode film 21 of the laminate 20. Alternatively, the inner walls of the slits ST may be coated with an insulating film such as a silicon oxide film, and a conductive material may be embedded inside the insulating film. In this case, the conductive material can also function as source wiring that reaches the source layer BSL.

[0019] A source layer BSL is provided on the laminate 20. The source layer BSL is provided in correspondence with the laminate 20. The source layer BSL has a first surface F1 and a second surface F2 opposite to the first surface F1. The laminate 20 (memory cell array) is provided on the first surface F1 side of the source layer BSL, and a metal layer 40 is provided on the second surface F2 side. The metal layer 40 includes a source line 41 and a power line 42. The source layer BSL is commonly connected to one end of a plurality of columnar bodies CL and provides a common source potential to a plurality of columnar bodies CL in the same memory cell array 2m. That is, the source layer BSL functions as a common source electrode for the memory cell array 2m. For example, a conductive material such as doped polysilicon is used for the source layer BSL. For the metal layer 40, a metal material with lower resistance than the source layer BSL is used, such as copper, aluminum, or tungsten. 2s is a stepped portion of the electrode film 21 provided for connecting the contact plug CCw to each electrode film 21. The stepped portion 2s will be described later with reference to Figure 2.

[0020] On the other hand, a bonding pad 50 is provided in the region above the stacked body 20 where the source layer BSL is not provided. The bonding pad 50 is connected to a metal wire or the like (not shown) and receives power or signals from outside the semiconductor memory device 1. The bonding pad 50 is provided so as to be connected to one end of the contact plug 29 in the Z direction. The bonding pad 50 is connected to the transistor 31 of the CMOS chip 3 via the contact plug 29, wiring 24 and wiring 34. Therefore, the external power supplied from the bonding pad 50 is supplied to the transistor 31. Alternatively, a signal is supplied to the transistor 31 or the memory cell array 2m via the bonding pad 50.

[0021] The contact plug CCw is provided on the outer edge of the laminate 20 and extends in the Z direction within the interlayer insulating film 25. The contact plug CCw is electrically connected between the electrode film 21 (word line WL) and the wiring 24. The contact plug CCw is provided on the stepped portion 2s formed in a stepped shape at the end of the laminate 20 and is electrically connected to each electrode film 21. The contact plug CCw is provided to transmit the word line voltage from the CMOS chip 3 to each electrode film 21. For example, metals such as copper and tungsten can be used for the contact plug CCw.

[0022] The contact plug 29 is provided in the peripheral region PD of the laminate 20 and extends the interlayer insulating film 25 in the Z direction. The contact plug 29 is a contact plug provided from the wiring 24 to the bonding pad 50. The contact plug 29 is formed simultaneously in the same process as the contact plug CCw connected to the word line WL.

[0023] The contact plug 29 is electrically connected between the bonding pad 50 and the wiring 24. The contact plug 29 is used to supply power voltage or signals from the bonding pad 50 to the array chip 2 or CMOS chip 3. The contact plug 29 is made of a metal such as copper or tungsten. The power voltage is, for example, the power voltage VDD, or a reference voltage (e.g., ground voltage) VSS that is lower than the power voltage VDD. The signal may be an external control signal, or it may be write data or read data.

[0024] In this embodiment, the array chip 2 and the CMOS chip 3 are formed individually and bonded together at the bonding surface B1. Therefore, no transistors 31 are provided within the array chip 2. Also, no stacked structure 20 (memory cell array) is provided within the CMOS chip 3. Both the transistors 31 and the stacked structure 20 are located on the first surface F1 side of the source layer BSL. The transistors 31 are on the opposite side from the second surface F2 where the metal layer 40 is located.

[0025] Below the laminate 20, via contacts 28, wiring 23, and wiring 24 are provided. Wirings 23 and 24 are embedded in the interlayer insulating film 25. Wiring 24 is exposed almost flush with the surface of the interlayer insulating film 25. Wirings 23 and 24 are electrically connected to the semiconductor body 210 of the columnar body CL, etc. Metals such as copper and tungsten are used for the via contacts 28, wiring 23, and wiring 24. The interlayer insulating film 25 covers and protects the laminate 20, via contacts 28, wiring 23, and wiring 24. An insulating film such as a silicon oxide film is used for the interlayer insulating film 25.

[0026] The interlayer insulating film 25 and the interlayer insulating film 35 are bonded together at the bonding surface B1, and consequently, the wiring 24 and the wiring 34 are joined almost flush at the bonding surface B1. As a result, the array chip 2 and the CMOS chip 3 are electrically connected via the wiring 24 and the wiring 34.

[0027] Figure 2 is a schematic plan view showing the stacked structure 20. The stacked structure 20 includes a stepped portion 2s and a memory cell array 2m. The stepped portion 2s is provided, for example, at the end of the stacked structure 20. The memory cell array 2m is sandwiched or surrounded by the stepped portion 2s. The slit ST(LI) is provided from the stepped portion 2s at one end of the stacked structure 20, through the memory cell array 2m, to the stepped portion 2s at the other end of the stacked structure 20. The slit SHE is provided at least in the memory cell array 2m. The slit SHE is shallower in the Z direction than the slit ST(LI) and extends substantially parallel to the slit ST(LI). The slit SHE electrically isolates the electrode film 21 for each drain-side selection gate SGD. Note that the slit ST may be a source wiring LI that is electrically isolated from the electrode film 21 of the stacked structure 20 and electrically connected to the source layer BSL. In other words, the slit ST may be a source wiring LI that is electrically isolated from the electrode film 21 of the stacked body 20 constituting the memory cell array and electrically connected to the source layer BSL.

[0028] The portion of the laminate 20 sandwiched between the two slits ST shown in Figure 2 is called a block. A block constitutes, for example, the smallest unit of data erasure. Slit SHE is located within the block. The laminate 20 between slit ST and slit SHE is called a finger. The drain-side selection gate SGD is separated for each finger. Therefore, during data writing and reading, the drain-side selection gate SGD can select one finger within the block.

[0029] Figures 3 and 4 are schematic cross-sectional views illustrating a three-dimensional memory cell structure. Each of the multiple columnar bodies CL is located within a memory hole MH provided within a stack 20. Each columnar body CL extends from one end of the stack 20 along the Z direction, through the stack 20, and is located within the stack 20 and within the source layer BSL. Each of the multiple columnar bodies CL includes a semiconductor body 210, a memory film 220, and a core layer 230. The columnar body CL includes a core layer 230 located in its center, a semiconductor body (semiconductor member) 210 located around the core layer 230, and a memory film 220 located around the semiconductor body 210. The semiconductor body 210 extends in the stacking direction (Z direction) within the stack 20. The semiconductor body 210 is electrically connected to the source layer BSL. The memory film 220 is located between the semiconductor body 210 and the electrode film 21 and has a charge trapping portion. Multiple columnar bodies CL, one selected from each finger, are connected in common to a single bit line BL via via contacts 28 in Figure 1. Each of the columnar bodies CL is located, for example, in the region of the memory cell array 2m.

[0030] As shown in Figure 4, the shape of the memory hole MH in the XY plane is, for example, a circle or an ellipse. A block insulating film 221a, which constitutes part of the memory film 220, may be provided between the electrode film 21 and the insulating film 22. The block insulating film 221a is, for example, silicon oxide or a metal oxide. One example of a metal oxide is aluminum oxide. A barrier film 21b may be provided between the electrode film 21 and the insulating film 22, and between the electrode film 21 and the memory film 220. The barrier film 21b is, for example, a multilayer film of titanium nitride and titanium when the electrode film 21 is tungsten. The block insulating film 221a suppresses back tunneling of charge from the electrode film 21 to the memory film 220. The barrier film 21b improves the adhesion between the electrode film 21 and the block insulating film 221a.

[0031] The semiconductor body 210 has a cylindrical shape, for example, with a bottom. For example, polysilicon is used for the semiconductor body 210. For example, the semiconductor body 210 is undoped silicon. Alternatively, the semiconductor body 210 may be p-type silicon. The semiconductor body 210 serves as the channel for the drain-side selection transistor, the memory cell MC, and the source-side selection transistor. That is, multiple memory cell MCs have a storage area between the semiconductor body 210 and the electrode film 21 which becomes the word line WL, and are stacked in the Z direction. One end of multiple semiconductor bodies 210 within the same memory cell array 2m is electrically connected in common to the source layer BSL.

[0032] The memory film 220 includes, for example, a cover insulating film 221, a charge trapping film 222, a tunnel insulating film 223, and a block insulating film 221a. The portion of the memory film 220 other than the block insulating film 221a is provided between the inner wall of the memory hole MH and the semiconductor body 210. The shape of the memory film 220 is, for example, cylindrical. The charge trapping film 222 and the tunnel insulating film 223 are each stretched in the Z direction.

[0033] The cover insulating film 221 is provided between the insulating film 22 and the charge trapping film 222, and between the block insulating film 221a and the charge trapping film 222. The cover insulating film 221 includes, for example, silicon oxide. The cover insulating film 221 protects the charge trapping film 222 from etching when a sacrificial film (not shown) is replaced with the electrode film 21 (replacement step). If the replacement step is not used to form the electrode film 21, the cover insulating film 221 may be omitted.

[0034] The charge trapping film 222 is provided between the cover insulating film 221 and the tunnel insulating film 223. The charge trapping film 222 contains, for example, silicon nitride and has trapping sites that trap charges within the film. The portion of the charge trapping film 222 sandwiched between the electrode film 21, which becomes the word line WL, and the semiconductor body 210 constitutes the memory area of ​​the memory cell MC as a charge trapping section. The threshold voltage of the memory cell MC changes depending on the presence or absence of charge in the charge trapping section, or the amount of charge trapped in the charge trapping section. As a result, the memory cell MC retains information.

[0035] The tunnel insulating film 223 is provided between the semiconductor body 210 and the charge trapping film 222. The tunnel insulating film 223 includes, for example, silicon oxide, or silicon oxide and silicon nitride. The tunnel insulating film 223 is a potential barrier between the semiconductor body 210 and the charge trapping film 222. For example, when electrons are injected from the semiconductor body 210 to the charge trapping film 222 (writing operation), and when holes are injected from the semiconductor body 210 to the charge trapping film 222 (erasing operation), the electrons and holes pass through the potential barrier of the tunnel insulating film 223 (tunneling).

[0036] The core layer 230 fills the internal space of the cylindrical semiconductor body 210. The shape of the core layer 230 is, for example, columnar. An insulating material such as silicon oxide is used for the core layer 230.

[0037] Figure 5 is a schematic plan view showing an example of the configuration of the bit line BL and surrounding region PD according to the first embodiment. Figure 6 is a plan view showing an example of the arrangement relationship between the bit line BL and via contact 28v in the via formation region Rvia. Hereinafter, the -Z direction may be referred to as upward.

[0038] Multiple bit lines BL extend in the X direction and are arranged in the Y direction. No bit lines BL are provided in the peripheral region PD. Via contact 28v is connected between bit line BL and the wiring above it (-Z direction) (for example, 24w in Figure 8).

[0039] The via formation region Rvia in Figure 5 is the region where the via contact 28v is formed. Specifically, the via formation region Rvia is a region that, when viewed from the Z direction, includes at least the surface that is in contact with the bit line BL at the via contact 28v.

[0040] As shown in Figure 6, for example, two via contacts 28v are provided for each bit line BL, electrically connecting multiple bit lines BL to different wirings 24. The via contacts 28v are offset from each other in the direction of extension of the bit lines BL (X direction) to prevent short circuits between multiple bit lines BL. The via formation region Rvia in Figure 5 is set to encompass all of these via contact 28v formation locations when viewed from the Z direction. Furthermore, the via formation region Rvia is a region with a margin added from the via contacts 28v located at the upper, lower, right, and left ends of the multiple via contacts 28v when viewed from the Z direction.

[0041] Multiple via formation regions Rvia each extend in the Y direction and are arranged in the X direction. Therefore, multiple via formation regions Rvia have a stripe shape. Multiple via formation regions Rvia are connected and continuous in the peripheral region PD. When viewed from the Z direction, only one via formation region Rvia may be provided as long as it encompasses the formation location of the via contact 28v. However, the via formation region Rvia partially covers the bit line BL but does not cover the entire bit line BL.

[0042] The embedded region Rbr in Figure 5 coincides with the via-forming region Rvia where the via contact 28v is formed, when viewed from the Z direction. The embedded region Rbr is a region where insulating material is provided between adjacent bit lines BL. In the embedded region Rbr, the insulating material is substantially embedded between adjacent bit lines BL, and there is almost no air gap. In the X direction, the length of the embedded region Rbr of the laminate 20 is, for example, approximately 30% of the length of the bit lines BL. Also, in the XY plane, the area of ​​the embedded region Rbr of the laminate 20 is, for example, approximately 30% of the area of ​​the region where the bit lines BL of the laminate 20 are formed.

[0043] On the other hand, the air gap region Rag is the region of the bit line BL that is not the via formation region Rvia, when viewed from the Z direction. The air gap region Rag is the region where an air gap AG is provided between adjacent bit lines BL. In the air gap region Rag, insulating material is not embedded between adjacent bit lines BL, and the air gap AG remains. In the X direction, the length of the air gap region Rag of the laminate 20 is, for example, approximately 70% of the length of the bit line BL. Also, in the XY plane, the area of ​​the air gap region Rag of the laminate 20 is, for example, approximately 70% of the area of ​​the region where the bit lines BL of the laminate 20 are formed.

[0044] Figure 7 is a cross-sectional view showing an example configuration of the bit line BL and its surroundings in the air gap region Rag. Figure 7 is a cross-sectional view along line 7-7 in Figure 5. Figure 8 is a cross-sectional view showing an example configuration of the bit line BL and its surroundings in the embedded region Rbr. Figure 8 is a cross-sectional view along line 8-8 in Figure 5.

[0045] The semiconductor memory device 1 according to this embodiment comprises a first insulating film 25_1, a via contact 28vy, a bit line BL, a second insulating film 25_2, a third insulating film 25_3, a fourth insulating film 25_4, a fifth insulating film 25_5, a via contact 28v, wiring 24w, and an air gap AG.

[0046] For the first insulating film 25_1, an insulating material such as silicon oxide is used. Below the first insulating film 25_1 (in the +Z direction), the laminate 20 shown in Figure 1 is provided.

[0047] The via contact 28vy is provided within the first insulating film 25_1. The via contact 28vy is electrically connected between the semiconductor body 210 of the columnar body CL and the bit line BL. As a result, the semiconductor body 210 of each columnar body CL is electrically connected to one of the bit lines BL via the via contact 28vy. Conductive materials such as tungsten or copper are used for the via contact 28vy.

[0048] Multiple bit lines BL are provided in the -Z direction relative to the first insulating film 25_1. As described above, the multiple bit lines BL extend in the X direction and are arranged in the Y direction. Conductive materials such as tungsten and copper are used for the bit lines BL. In the air gap region Rag of Figure 7, the multiple bit lines BL are electrically isolated from each other by the third insulating film 25_3 and the air gap AG. In the embedded region Rbr of Figure 8, the multiple bit lines BL are electrically isolated from each other by the second insulating film 25_2.

[0049] The second insulating film 25_2 is filled between multiple bit lines BL in the embedded region Rbr shown in Figure 8. No air gap AG is intentionally formed or provided within the second insulating film 25_2. Furthermore, the second insulating film 25_2 is not provided between bit lines BL in the air gap region Rag. For example, an insulating material such as silicon oxide is used for the second insulating film 25_2.

[0050] The third insulating film 25_3, acting as an air gap insulating film, is provided on the bit line BL in the air gap region Rag of Figure 7. Furthermore, the third insulating film 25_3 is provided around the air gap AG and encloses the air gap AG. That is, the third insulating film 25_3 is provided between multiple bit lines BL and has the air gap AG inside it. In the embedded region Rbr of Figure 8, the third insulating film 25_3 is provided on the bit line BL and the second insulating film 25_2. For example, an insulating material such as silicon nitride is used for the third insulating film 25_3.

[0051] The fourth insulating film 25_4 is provided in the air gap region Rag of Figure 7, connecting the ends of adjacent bit lines BL between the first insulating film 25_1 and the third insulating film 25_3. Furthermore, the fourth insulating film 25_4 is provided in the embedded region Rbr of Figure 8, connecting the ends of adjacent bit lines BL between the first insulating film 25_1 and the second insulating film 25_2. The fourth insulating film 25_4 later functions as an etching stopper when removing the second insulating film 25_2. For example, an insulating material such as silicon nitride is used for the fourth insulating film 25_4.

[0052] The fifth insulating film 25_5 is provided on the third insulating film 25_3. For example, an insulating material such as silicon oxide is used for the fifth insulating film 25_5.

[0053] The via contact 28v is formed in the via formation region Rvia within the embedded region Rbr in Figure 8. The via contact 28v electrically connects the bit line BL and the wiring 24w. The via contact 28v extends in the Z direction within the fifth insulating film 25_5. Each via contact 28v connects one bit line BL to one wiring 24w without electrically short-circuiting multiple bit lines BL. Conductive materials such as tungsten or copper are used for the via contact 28v.

[0054] The wiring 24w is located above (-Z direction) multiple bit lines BL and is situated on via contact 28v. One of the wirings 24w is electrically connected to the corresponding bit line BL via via contact 28v. Conductive materials such as tungsten or copper are used for the wiring 24w.

[0055] The air gap AG is provided between adjacent bit lines BL in the air gap region Rag shown in Figure 7. The air gap AG is not provided between bit lines BL in the embedded region Rbr shown in Figure 8. The upper end of the air gap AG in the -Z direction is located closer to the wiring 24w than the upper ends of the multiple bit lines BL in the -Z direction. In other words, the upper end of the air gap AG in the -Z direction is formed at a higher position than the upper ends of the multiple bit lines BL in the -Z direction. Also, the lower end of the air gap AG in the +Z direction is located closer to the first insulating film 25_1 than the lower ends of the multiple bit lines BL in the +Z direction. That is, the air gap AG is longer than the bit lines BL in the ±Z direction and is provided over the entire length of the bit lines BL.

[0056] A third insulating film 25_3 is provided on the side walls of the bit lines BL. Therefore, the third insulating film 25_3 is provided between the side walls of multiple bit lines BL and the air gap AG. In addition, the third insulating film 25_3 is also provided between the side and bottom surfaces of the first insulating film 25_1 and the air gap AG. That is, the air gap AG is surrounded by the third insulating film 25_3. This effectively reduces parasitic capacitance between the bit lines BL.

[0057] Figure 9 is a cross-sectional view showing an example of the configuration of the peripheral region PD. In the peripheral region PD, the interior of the third insulating film 25_3 is filled with the material of the third insulating film 25_3 (e.g., silicon nitride film) and does not have an air gap AG. Wiring 55 formed in the same layer as the bit line BL is provided on the first insulating film 25_1. The second insulating film 25_2 is provided so as to penetrate the wiring 55. The interior of the second insulating film 25_2 is also filled with the material of the second insulating film 25_2 (e.g., silicon oxide film) and does not have an air gap AG. In other words, the space between adjacent wirings 55 is filled with the second insulating film 25_2 and no air gap AG is provided. The fourth insulating film 25_4 is provided so as to connect the ends of adjacent wirings 55 between the first insulating film 25_1 and the second insulating film 25_2. The fourth insulating film 25_4 in the peripheral region PD is formed at the same timing as the fourth insulating film 25_4 in the laminate 20. In the peripheral region PD, a fourth insulating film 25_4 is formed by nitriding a portion of the first insulating film 25_1 before providing the second insulating film 25_2. The third insulating film 25_3 is provided on the wiring 55 and the second insulating film 25_2. The fifth insulating film 25_5 is provided on the third insulating film 25_3. The via contact 29v penetrates the fifth insulating film 25_5 and the third insulating film 25_3 in the Z direction and electrically connects either of the wirings 24w to the wiring 55.

[0058] In the data read operation, data from the selected memory cell of the memory cell array 2m in Figure 1 is transmitted to the bit line BL via the semiconductor body 210 and via contact 28vy of the columnar body CL. This data is further transmitted through the wiring 24w via via contact 28v and detected by a sense amplifier (not shown). In the data write operation, data from an external decoder is transmitted to the bit line BL via the wiring 24w and via contact 28v. This data is transmitted to the semiconductor body 210 of the columnar body CL via via contact 28vy and written to the selected memory cell of the memory cell array 2m.

[0059] Thus, according to this embodiment, in the air gap region Rag where via contacts 28v are not formed, an air gap region Rag is provided between multiple bit lines BL. This reduces parasitic capacitance between multiple bit lines BL. As a result, data disturbance between bit lines BL can be suppressed. Furthermore, data reliability can be maintained even if the bit lines BL are made longer.

[0060] On the other hand, in the embedded region Rbr, which includes the via formation region Rvia where the via contact 28v is formed, there is no air gap AG between the multiple bit lines BL, and the second insulating film 25_2 is embedded. Therefore, as shown in Figure 8, even if the position of the via contact 28v is shifted somewhat, the second insulating film 25_2 prevents the via contact 28v from connecting to an unintended bit line BL.

[0061] If an air gap AG is provided between bit lines BL, and the via contact 28v is misaligned during its formation, the conductive material of the via contact 28v may enter the air gap AG and connect to an unintended bit line BL.

[0062] In contrast, in this embodiment, in the embedded region Rbr, no air gap AG is provided between the multiple bit lines BL, and a third insulating film 25_3 is embedded. Therefore, the third insulating film 25_3 can suppress the via contact 28v from electrically short-circuiting the multiple bit lines BL or connecting to unintended bit lines BL.

[0063] Next, a method for manufacturing the semiconductor memory device 1 according to this embodiment will be described.

[0064] Figures 10 to 18 are cross-sectional views showing an example of a method for manufacturing a semiconductor memory device 1 according to the first embodiment. Note that the upward direction (-Z direction) is an example of the first direction.

[0065] As shown in Figure 10, the first insulating film 25_1 is deposited on top of a laminate 20 (not shown) to form via contacts 28vy within the first insulating film 25_1. Next, the material for the bit line BL (e.g., tungsten) is deposited on the first insulating film 25_1 and the via contacts 28vy. Next, the material for the third insulating film 25_3 (e.g., silicon nitride) is deposited on the bit line BL material. Next, the material for the hard mask HM1 (e.g., silicon oxide) is deposited on the third insulating film 25_3 material. This results in the structure shown in Figure 10.

[0066] Next, the material for the hard mask HM1 is processed into a layout pattern for the bit lines BL using lithography and etching techniques. At this time, the mask pattern may be formed using the side walls formed on both sides of the pattern. Next, as shown in Figure 11, the material for the third insulating film 25_3 and the material for the bit lines BL are etched using etching techniques such as RIE (Reactive Ion Etching) with the hard mask HM1 as a mask. Trench TR1 between the bit lines BL is formed so as to penetrate the third insulating film 25_3 and the bit lines BL and reach the first insulating film 25_1. The first insulating film 25_1 is exposed at the bottom of the trench TR1. This forms the bit lines BL. The bit lines BL and the third insulating film 25_3 on top of them are stretched in the X direction and arranged in the Y direction. The third insulating film 25_3 is provided in the -Z direction of the bit lines BL, corresponding to each of the multiple bit lines BL.

[0067] Next, the surface of the first insulating film 25_1 exposed at the bottom of the trench TR1 is nitrided to form the fourth insulating film 25_4. The fourth insulating film 25_4 is formed, for example, by plasma treatment of the surface of the first insulating film 25_1 to modify its surface. The fourth insulating film 25_4 later functions as an etching stopper when removing the second insulating film 25_2.

[0068] Next, the material for the second insulating film 25_2 (e.g., silicon oxide) is deposited in the trench TR1 and on the hard mask HM1. The second insulating film 25_2 and the hard mask HM1 are polished using the CMP (Chemical Mechanical Polishing) method until the upper surface of the third insulating film 25_3 is exposed. As a result, the second insulating film 25_2 fills the trench TR1 between the bit lines BL, as shown in Figure 12. At this time, no air gap AG is provided within the second insulating film 25_2.

[0069] Next, the material for the hard mask HM2 is deposited on the second and third insulating films 25_2 and 25_3. The material for the hard mask HM2 is a material that can be selectively etched with respect to the second and third insulating films 25_2 and 25_3.

[0070] Next, using lithography and etching techniques, the material of the hard mask HM2 in the air gap region Rag is removed, as shown in Figure 13, leaving the hard mask HM2 in the embedding region Rbr. At this time, in a plan view from the Z direction, the hard mask HM2 remains on the embedding region Rbr, as shown in Figure 14.

[0071] Next, as shown in Figure 15, the hard mask HM2 is used as a mask to selectively etch the second insulating film 25_2 in the trench TR1 in the air gap region Rag. The second insulating film 25_2 in the trench TR1 in the embedded region Rbr is left intact. That is, when viewed from the Z direction, the insulating film 25_2 in the air gap region Rag other than the embedded region Rbr is selectively removed, and trench TR1 is formed between multiple bit lines BL in the air gap region Rag.

[0072] Next, after removing the hard mask HM2, as shown in Figure 16, the material for the third insulating film 25_3 (e.g., silicon nitride) is further deposited on the second insulating film 25_2 and the third insulating film 25_3 from the -Z direction. At this time, the material for the third insulating film 25_3 is deposited using a method such as plasma CVD (Chemical Vapor Deposition) under conditions that reduce step coverage. As a result, in the air gap region Rag, the material for the third insulating film 25_3 blocks the opening of the trench TR1, leaving an air gap AG inside. A thin layer of the material for the third insulating film 25_3 is formed on the inner wall and bottom surface of the trench TR1. Since the fourth insulating film 25_4 is formed at the bottom of the trench TR1 in the air gap region Rag, the third insulating film 25_3 in the air gap region Rag is formed on top of the fourth insulating film 25_4. Therefore, a third insulating film 25_3 is provided between the bit line BL and the air gap AG, and between the first insulating film 25_1 and the air gap AG. On the other hand, in the embedded region Rbr, since the second insulating film 25_2 is embedded in the trench TR1, the air gap AG does not remain within the third insulating film 25_3.

[0073] Next, the material for the fifth insulating film 25_5 (for example, silicon oxide) is deposited on the third insulating film 25_3. This results in the structure shown in Figure 16.

[0074] Next, using lithography and etching techniques, a contact hole CH_28v is formed at the location of the via contact 28v, as shown in Figure 17. The contact hole CH_28v is formed in the via formation region Rvia within the embedded region Rbr. The contact hole CH_28v penetrates the fifth insulating film 25_5 and the third insulating film 25_3 to reach the corresponding bit line BL. At this time, in the embedded region Rbr, no air gap AG is formed between the bit lines BL, and the second insulating film 25_2 fills the space between the bit lines BL. Therefore, even if the contact hole CH_28v is misaligned in the Y direction by the width of the second insulating film 25_2, the contact hole CH_28v will not reach any other adjacent bit lines BL. In other words, because the second insulating film 25_2 fills the space between the bit lines BL, a margin equal to the width of the second insulating film 25_2 is ensured for the alignment misalignment of the contact hole CH_28v.

[0075] On the other hand, in the air gap region Rag, an air gap AG is formed between multiple bit lines BL. Therefore, parasitic capacitance between multiple bit lines BL can be reduced. This suppresses data disturbance between bit lines BL.

[0076] Next, as shown in Figure 18, the material for the via contact 28v (e.g., tungsten) is embedded in the contact hole CH_28v. At this time, after depositing the material for the via contact 28v on the fifth insulating film 25_5 and in the contact hole CH_28v, the material for the via contact 28v is polished using a CMP method or the like until the fifth insulating film 25_5 is exposed. This fills the contact hole CH_28v with the via contact 28v.

[0077] Subsequently, as shown in Figure 8, wiring 24w and other components are formed, and the array chip 2 is completed.

[0078] A CMOS chip 3, formed separately from the array chip 2, is bonded to the array chip 2. This completes the semiconductor memory device 1 according to the first embodiment, as shown in Figure 1.

[0079] According to this embodiment, an air gap AG is provided between multiple bit lines BL in the air gap region Rag. Therefore, parasitic capacitance between multiple bit lines BL can be reduced. This suppresses data disturbance between bit lines BL and improves the reliability of the semiconductor memory device 1. Furthermore, the bit lines BL can be made even longer in the X direction while maintaining the parasitic capacitance between bit lines BL.

[0080] On the other hand, in the embedded region Rbr, the second insulating film 25_2 fills the space between the bit lines BL. Therefore, even if the via contact 28v is displaced in the Y direction by the width of the second insulating film 25_2, the via contact 28v will not come into contact with any other adjacent bit lines BL. In other words, the fact that the second insulating film 25_2 fills the space between the bit lines BL ensures a certain margin of error in the position of the via contact 28v.

[0081] (Second Embodiment) Figures 19 and 20 are cross-sectional views showing an example configuration of the bit line BL and its surroundings in the air gap region Rag of a semiconductor memory device according to the second embodiment. Figure 19 corresponds to a cross-section along line 7-7 in Figure 5. Figure 20 corresponds to a cross-section along line 8-8 in Figure 5. Figure 21 is a cross-sectional view showing an example configuration of the peripheral region PD of a semiconductor memory device according to the second embodiment.

[0082] In the second embodiment, the third insulating film 25_3 is not provided, and the fifth insulating film 25_5, acting as an air gap insulating film, covers the bit line BL, the second insulating film 25_2, and the air gap AG.

[0083] The fifth insulating film 25_5, acting as an air gap insulating film, is provided on the bit line BL in the air gap region Rag. Furthermore, the fifth insulating film 25_5 is provided around the air gap AG and encloses the air gap AG. That is, the fifth insulating film 25_5 is provided between multiple bit lines BL and has the air gap AG inside it. The fifth insulating film 25_5 is provided on the bit line BL and the second insulating film 25_2 in the embedded region Rbr. For example, an insulating material such as silicon oxide is used for the fifth insulating film 25_5.

[0084] A fifth insulating film 25_5 is provided on the sidewalls of the bit lines BL. Therefore, a fifth insulating film 25_5 is provided between the sidewalls of multiple bit lines BL and the air gap AG. Furthermore, a fifth insulating film 25_5 is also provided between the side and bottom surfaces of the first insulating film 25_1 and the air gap AG. In other words, the air gap AG is surrounded by the fifth insulating film 25_5. This effectively reduces parasitic capacitance between the bit lines BL.

[0085] Other configurations of the second embodiment may be the same as those of the first embodiment. Therefore, the second embodiment can obtain the same effects as the first embodiment.

[0086] Next, a method for manufacturing the semiconductor memory device 1 according to the second embodiment will be described.

[0087] Figures 22 to 29 are cross-sectional views showing an example of a method for manufacturing a semiconductor memory device 1 according to the second embodiment.

[0088] The material formation process for the first insulating film 25_1, via contact 28vy, and bit line BL shown in Figure 22 may be the same as the material formation process for the first embodiment.

[0089] Next, the material of the bit lines BL is etched using a hard mask, lithography, and etching techniques. Trench TR1 between the bit lines BL is formed so as to penetrate the bit lines BL and reach the first insulating film 25_1. The bottom of the trench TR1 exposes the first insulating film 25_1. This forms the bit lines BL. The bit lines BL are extended in the X direction and arranged in the Y direction.

[0090] Next, the surface of the first insulating film 25_1 exposed at the bottom of the trench TR1 is nitrided to form a fourth insulating film 25_4. The fourth insulating film 25_4 later functions as an etching stopper when removing the second insulating film 25_2.

[0091] Next, the material for the second insulating film 25_2 (e.g., silicon oxide) is deposited in the trench TR1. Using the CMP method, the insulating film 25_2 is polished until the upper surface of the second insulating film 25_2 and the bit line BL are exposed. As a result, the second insulating film 25_2 fills the trench TR1 between the bit lines BL, as shown in Figure 24. At this time, no air gap AG is provided within the second insulating film 25_2.

[0092] Next, the material for the hard mask HM2 is deposited on the second insulating film 25_2 and the bit line BL.

[0093] Next, using lithography and etching techniques, the material of the hard mask HM2 in the air gap region Rag is removed, as shown in Figure 25, leaving the hard mask HM2 in the embedded region Rbr.

[0094] Next, as shown in Figure 26, the hard mask HM2 is used as a mask to selectively etch the second insulating film 25_2 in the trench TR1 in the air gap region Rag. The second insulating film 25_2 in the trench TR1 in the embedded region Rbr is left intact.

[0095] Next, after removing the hard mask HM2, as shown in Figure 27, the material for the fifth insulating film 25_5 is further deposited on the second insulating film 25_2 and the bit line BL from the -Z direction. At this time, the material for the fifth insulating film 25_5 is deposited using CVD or the like under conditions that reduce step coverage. As a result, in the air gap region Rag, the material for the fifth insulating film 25_5 blocks the opening of the trench TR1, leaving an air gap AG inside. A thin layer of the material for the fifth insulating film 25_5 is formed on the inner wall and bottom surface of the trench TR1. Therefore, the fifth insulating film 25_5 is provided between the bit line BL and the air gap AG, and between the first insulating film 25_1 and the air gap AG. On the other hand, in the embedded region Rbr, since the second insulating film 25_2 is embedded in the trench TR1, no air gap AG remains in the fifth insulating film 25_5.

[0096] Next, using lithography and etching techniques, a contact hole CH_28v is formed at the location of the via contact 28v, as shown in Figure 28. The contact hole CH_28v is formed in the via formation region Rvia within the embedded region Rbr. The contact hole CH_28v penetrates the fifth insulating film 25_5 and reaches the corresponding bit line BL. At this time, in the embedded region Rbr, no air gap AG is formed between the bit lines BL, and the second insulating film 25_2 fills the space between the bit lines BL. Therefore, even if the contact hole CH_28v is misaligned in the Y direction by the width of the second insulating film 25_2, the contact hole CH_28v will not reach any other adjacent bit lines BL. In other words, because the second insulating film 25_2 fills the space between the bit lines BL, a margin equal to the width of the second insulating film 25_2 is ensured for the alignment misalignment of the contact hole CH_28v.

[0097] On the other hand, in the air gap region Rag, an air gap AG is formed between multiple bit lines BL. Therefore, parasitic capacitance between multiple bit lines BL can be reduced. This suppresses data disturbance between bit lines BL.

[0098] Next, as shown in Figure 29, the material for via contact 28v (e.g., tungsten) is embedded in the contact hole CH_28v.

[0099] After that, wiring 24w and other components are formed, and the array chip 2 is completed.

[0100] A CMOS chip 3, formed separately from the array chip 2, is bonded to the array chip 2. This completes the semiconductor memory device 1 shown in Figure 1.

[0101] In the second embodiment, although the third insulating film 25_3 is omitted, the other configurations are almost the same as in the first embodiment. Therefore, the second embodiment can obtain the same effects as the first embodiment.

[0102] (Third embodiment) Figure 30 is a plan view showing an example of the configuration of a semiconductor memory device according to the third embodiment. Figure 30 shows a plan view of a part of the stacked body 20. Figure 31 is a plan view showing further details of a part of Figure 30. The peripheral region PD may be the same as that of the first embodiment.

[0103] In the third embodiment, when viewed from the Z direction, the embedded region Rbr is provided corresponding to one or more via contacts 28v connected to each bit line BL, and is provided in an island-like manner corresponding to each bit line BL.

[0104] For example, as shown in Figure 31, two via contacts 28v are connected to each bit line BL. In this case, each embedded region Rbr is provided corresponding to the two via contacts 28v, and is provided around the two via contacts 28v and their vicinity when viewed from the Z direction.

[0105] Similar to the first embodiment, the space between the bit lines BL in the embedded region Rbr is filled with a second insulating film 25_2. However, in the third embodiment, multiple embedded regions Rbr are provided in an island-like manner within the via formation region Rvia, and an air gap AG is provided between the bit lines BL between adjacent embedded regions Rbr. In other words, an air gap AG is partially formed even within the via formation region Rvia. This further reduces the capacitance between the bit lines BL.

[0106] It is preferable that the embedded regions Rbr are arranged substantially evenly within the via formation regions Rvia. This ensures that the capacitance between multiple bit lines BL does not vary and remains substantially uniform.

[0107] Similar to the first embodiment, an air gap AG is provided between the bit lines BL in the air gap region Rag. Thus, although the third embodiment differs from the first embodiment in the planar layout of the embedded region Rbr and the air gap region Rag, the other configurations may be the same as those of the first embodiment. As a result, the third embodiment can also obtain the same effects as the first embodiment. Furthermore, the third embodiment may be combined with the second embodiment.

[0108] (Fourth Embodiment) Figure 32 is a plan view showing an example of the configuration of a semiconductor memory device according to the fourth embodiment. Figure 32 shows a plan view of a part of the stacked body 20. A more detailed plan of the via formation region Rvia may be the same as that of Figure 31. The peripheral region PD may be the same as that of the first embodiment.

[0109] In the fourth embodiment, when viewed from the Z direction, the embedded regions Rbr are provided corresponding to one or more via contacts 28v connected to each bit line BL, and are provided in an island-like manner corresponding to each bit line BL. In this respect, the fourth embodiment is the same as the third embodiment. The embedded region Rbr provided within the via formation region Rvia is conveniently referred to as embedded region Rbr1.

[0110] Furthermore, in the fourth embodiment, multiple embedded regions Rbr2 are provided within a portion of the air gap region Rag. The embedded region Rbr2, as the third region, is a region in which the second insulating film 25_2 is filled between the bit lines BL, similar to the embedded region Rbr1, but differs from the embedded region Rbr1 in that it is provided within the air gap region Rag. No via contacts 28v are formed in the embedded region Rbr2. Therefore, no contact holes CH_28v are formed in the embedded region Rbr2 during the manufacturing process.

[0111] For example, as shown in Figure 32, when viewed from the Z direction, the embedded region Rbr2 is provided in an island-like manner within the air gap region Rag, corresponding to one or more bit lines BL. The planar layout of the embedded region Rbr2 may be the same as the planar layout of the embedded region Rbr1.

[0112] According to the fourth embodiment, an embedded region Rbr2 is provided within the air gap region Rag. This allows the embedded region Rbr2 to support the third and fifth insulating films 25_3 and 25_5 during the CMP process, such as the via contact 28v formation process, thereby suppressing collapse or cracking of the air gap region Rag.

[0113] On the other hand, the embedded region Rbr2 is provided in a part of the air gap region Rag, while the air gap AG is provided in the other air gap region Rag. Therefore, the effect of reducing parasitic capacitance between bit lines BL can also be obtained.

[0114] Next, a method for manufacturing the semiconductor memory device 1 according to the fourth embodiment will be described.

[0115] Figures 33 to 35 are cross-sectional views showing an example of a semiconductor memory device manufacturing method according to the fourth embodiment. After the steps described with reference to Figures 10 to 12, the material for the hard mask HM2 is deposited on the second and third insulating films 25_2 and 25_3.

[0116] Next, using lithography and etching techniques, the material of the hard mask HM2 in areas other than the embedded area Rbr2 within the air gap area Rag is removed, as shown in Figure 33, leaving the hard mask HM2 in the embedded areas Rbr1 and Rbr2. At this time, the mask pattern in the lithography process differs from that of the first embodiment.

[0117] Next, as shown in Figure 34, the hard mask HM2 is used as a mask to selectively etch the second insulating film 25_2 in the trench TR1 in areas other than the embedded areas Rbr1 and Rbr2. The second insulating film 25_2 in the trench TR1 in the embedded areas Rbr1 and Rbr2 is left intact. That is, when viewed from the Z direction, the second insulating film 25_2 in areas other than the embedded areas Rbr1 and Rbr2 is selectively removed, and trench TR1 is formed between multiple bit lines BL in the air gap area Rag.

[0118] Subsequently, following the steps described with reference to Figures 15 to 18, the structure shown in Figure 35 is obtained. At this time, via contacts 28v are formed in the embedded region Rbr1, but no contact holes CH_28v and via contacts 28v are formed in the embedded region Rbr2, and third and fifth insulating films 25_3 and 25_5 are provided on the bit line BL.

[0119] Subsequently, the semiconductor memory device 1 according to the fourth embodiment is completed through the same process as in the first embodiment.

[0120] According to the fourth embodiment, an embedded region Rbr2 is provided within the air gap region Rag. This allows the embedded region Rbr2 to support the third and fifth insulating films 25_3 and 25_5 during the CMP process, such as the via contact 28v formation process, thereby suppressing collapse or cracking of the air gap region Rag.

[0121] It is preferable that the embedded regions Rbr1 and Rbr2 are arranged substantially evenly within the bit line BL formation region. This results in substantially uniform mechanical strength and further suppresses cracking during the CMP process. In addition, the capacitance between multiple bit lines BL does not vary from location to location and becomes substantially uniform.

[0122] Other configurations of the fourth embodiment may be the same as those of the first embodiment. Therefore, the fourth embodiment can obtain the same effects as the first embodiment. Furthermore, the fourth embodiment may be combined with the second embodiment. In addition, the planar layout of the embedded area Rbr1 in the fourth embodiment may be the same as that of the first or second embodiment. That is, in the fourth embodiment, the planar layout of the embedded area Rbr1 may be a stripe shape.

[0123] (modified version) Figures 36 to 39 are cross-sectional views showing examples of semiconductor memory device configurations according to modifications of the fourth embodiment. In these modifications, the layout of the embedded region Rbr2 within the air gap region Rag, as viewed from the Z direction, is different. Other configurations of these modifications may be the same as those of the fourth embodiment.

[0124] In Figure 36, the embedded region Rbr2 has a striped layout that extends in the Y direction and is arranged in the X direction.

[0125] In Figure 37, the embedded region Rbr2 extends in the X direction and has a stripe-shaped layout arranged in the X direction.

[0126] In Figure 38, the embedded region Rbr2 has an island-shaped layout arranged in the X and Y directions.

[0127] In Figure 39, the embedded regions Rbr2 are arranged in the Y direction and have an island-shaped layout with each bit line BL offset in the X direction.

[0128] The layout of the embedded region Rbr2 may be the same as the layout of the embedded region Rbr1, but the arrangement of the embedded region Rbr2 may be arbitrarily changed as shown in these modifications. Furthermore, the area ratio of the embedded region Rbr2 to the air gap region Rag should be such that it can suppress the collapse of the air gap region Rag and cracking of the substrate. Even if the area ratio of the embedded region Rbr2 to the air gap region Rag differs to some extent from the area ratio of the embedded region Rbr1 to the via formation region Rvia, the effect of suppressing the collapse of the air gap region Rag and cracking of the substrate can still be obtained. In addition, in the modifications of the fourth embodiment, the planar layout of the embedded region Rbr1 may be the same as that of the first and second embodiments. That is, in the modifications of the fourth embodiment, the planar layout of the embedded region Rbr1 may be a stripe shape.

[0129] Furthermore, in order to reduce the capacitance between bit lines BL, the areas of the embedded regions Rbr1 and Rbr2 should be as small as possible. On the other hand, in order to suppress cracks during the CMP process, a certain amount of area is necessary for the embedded regions Rbr1 and Rbr2. Therefore, it is preferable to set the areas of the embedded regions Rbr1 and Rbr2 to be as small as possible while suppressing cracks during the CMP process.

[0130] (Fifth embodiment) Figure 40 is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to the fifth embodiment. The embedded region Rbr in the fifth embodiment may have the same structure as that of the first embodiment. On the other hand, in the air gap region Rag of the fifth embodiment, the third insulating film 25_3 is removed, and an air gap AG is provided within the fifth insulating film 25_5. The other configurations of the fifth embodiment may be the same as those of the first embodiment.

[0131] Next, a method for manufacturing the semiconductor memory device 1 according to the fifth embodiment will be described.

[0132] Figures 41 to 45 are cross-sectional views showing an example of a semiconductor memory device manufacturing method according to the fifth embodiment. After the steps described with reference to Figures 10 to 12, the material for the third insulating film 25_3 is further deposited on the second insulating film 25_2.

[0133] Next, the material for the hard mask HM2 is deposited on the third insulating film 25_3. Using lithography and etching techniques, the material for the hard mask HM2 in the air gap region Rag is removed, as shown in Figure 42, leaving the hard mask HM2 in the embedded region Rbr.

[0134] Next, as shown in Figure 43, the hard mask HM2 is used as a mask to selectively etch the third insulating film 25_3 and the second insulating film 25_2 in the air gap region Rag. At this time, the fourth insulating film 25_4 functions as an etching stopper in the air gap region Rag. Therefore, the trench TR1 is formed up to the fourth insulating film 25_4. On the other hand, the second insulating film 25_2 in the embedded region Rbr is left intact, and the trench TR1 is not formed there.

[0135] Next, after removing the hard mask HM2, as shown in Figure 44, the material for the fifth insulating film 25_5 (e.g., silicon nitride) is deposited on the third insulating film 25_3, the bit line BL, and the trench TR1 from the -Z direction. At this time, the material for the fifth insulating film 25_5 is deposited using a CVD method or the like under conditions that reduce step coverage. As a result, in the air gap region Rag, the material for the fifth insulating film 25_5 blocks the opening of the trench TR1, leaving an air gap AG inside. A thin layer of the material for the fifth insulating film 25_5 is formed on the inner wall and bottom surface of the trench TR1. Therefore, the fifth insulating film 25_5 is provided between the bit line BL and the air gap AG, and between the first insulating film 25_1 and the air gap AG. On the other hand, in the embedded region Rbr, since the second insulating film 25_2 is embedded in the trench TR1, no air gap AG is formed.

[0136] Next, using lithography and etching techniques, a contact hole CH_28v is formed at the location of the via contact 28v, as shown in Figure 45. The contact hole CH_28v is formed in the via formation region Rvia within the embedded region Rbr. The contact hole CH_28v penetrates the fifth insulating film 25_5 and the third insulating film 25_3 to reach the corresponding bit line BL. At this time, in the embedded region Rbr, no air gap AG is formed between the bit lines BL, and the second insulating film 25_2 fills the space between the bit lines BL. Therefore, a margin equal to the width of the second insulating film 25_2 is secured for the alignment misalignment of the contact hole CH_28v.

[0137] On the other hand, in the air gap region Rag, an air gap AG is formed between multiple bit lines BL. Therefore, parasitic capacitance between multiple bit lines BL can be reduced. This suppresses data disturbance between bit lines BL.

[0138] Subsequently, by embedding via contact 28v within contact hole CH_28v, the structure shown in Figure 40 is obtained.

[0139] As in the fifth embodiment, in the air gap region Rag, a fifth insulating film 25_5 is provided instead of the third insulating film 25_3, and an air gap AG is provided in the fifth insulating film 25_5. Even with a configuration like that of the fifth embodiment, the same effects as in the first embodiment can be obtained.

[0140] The fifth embodiment may be combined with the third or fourth embodiment. The planar layout of the fifth embodiment may be any of the above modifications.

[0141] Figure 46 is a block diagram showing an example configuration of a semiconductor memory device to which one of the array chips of the above embodiment is applied. The semiconductor memory device 1 is, for example, a memory 100a such as a NAND flash memory capable of storing data non-volatilely, and is controlled by an external memory controller 1002. Communication between the memory 100a and the memory controller 1002 conforms to, for example, the NAND interface standard.

[0142] As shown in Figure 46, the memory 100a includes, for example, a memory cell array MCA(2m), a command register 1011, an address register 1012, a sequencer 1013, a driver module 1014, a row decoder module 1015, and a sense amplifier module 1016.

[0143] A memory cell array (MCA) contains multiple blocks BLK(0) to BLK(n) (where n is an integer greater than or equal to 1). A block BLK is a collection of multiple memory cells capable of storing data non-volatilely, and is used, for example, as a data erasure unit. The memory cell array (MCA) is also provided with multiple bit lines and multiple word lines. Each memory cell is associated with, for example, one bit line and one word line. The detailed configuration of the memory cell array (MCA) will be described later.

[0144] The command register 1011 holds the command CMD received by memory 100a from the memory controller 1002. The command CMD includes instructions that cause the sequencer 1013 to perform read operations, write operations, erase operations, etc.

[0145] The address register 1012 holds the address information ADD received by memory 100a from the memory controller 1002. The address information ADD includes, for example, the block address BA, the page address PA, and the column address CA. For example, the block address BA, the page address PA, and the column address CA are used for selecting the block BLK, the word line, and the bit line, respectively.

[0146] The sequencer 1013 controls the operation of the entire memory 100a. For example, based on the command CMD held in the command register 1011, the sequencer 1013 controls the driver module 1014, the row decoder module 1015, the sense amplifier module 1016, etc., to perform read operations, write operations, erase operations, etc.

[0147] The driver module 1014 generates voltages used in read operations, write operations, erase operations, etc. Then, the driver module 1014 applies the generated voltage to the signal line corresponding to the selected word line, for example, based on the page address PA held in the address register 1012.

[0148] The row decoder module 1015 comprises multiple row decoders. The row decoder selects one block BLK in the corresponding memory cell array MCA based on the block address BA held in the address register 1012. The row decoder then transfers, for example, the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0149] During a write operation, the sense amplifier module 1016 applies a desired voltage to each bit line according to the write data DAT received from the memory controller 1002. During a read operation, the sense amplifier module 1016 determines the data stored in the memory cell based on the voltage of the bit line and transfers the determination result as read data DAT to the memory controller 1002.

[0150] The memory 100a and memory controller 1002 described above may be combined to form a single semiconductor memory device. Examples of such semiconductor memory devices include memory cards such as SD™ cards and SSDs (solid state drives).

[0151] Figure 47 is a circuit diagram showing an example of the circuit configuration of a memory cell array (MCA). One block BLK is extracted from among several block BLKs included in the memory cell array (MCA). As shown in Figure 47, the block BLK contains multiple string units SU(0) to SU(k) (where k is an integer greater than or equal to 1).

[0152] Each string unit SU contains multiple NAND strings NS, each associated with a bit line BL(1) to BL(m) (where m is an integer greater than or equal to 1). Each NAND string NS includes, for example, memory cells MC(0) to MC(15), as well as selection transistors ST(1) and ST(2). The memory cell MC includes a control gate and a charge trapping layer to hold data non-volatile. The selection transistors ST(1) and ST(2) are used to select the string unit SU during various operations.

[0153] In each NAND string NS, memory cells MC(0) to MC(15) are connected in series. The drain of selection transistor ST(1) is connected to the associated bit line BL, and the source of selection transistor ST(1) is connected to one end of the series-connected memory cells MC(0) to MC(15). The drain of selection transistor ST(2) is connected to the other end of the series-connected memory cells MC(0) to MC(15). The source of selection transistor ST(2) is connected to the source line SL.

[0154] In the same block BLK, the control gates of memory cells MC(0) to MC(15) are commonly connected to the word lines WL(0) to WL(15), respectively. The gates of each selection transistor ST(1) in string units SU(0) to SU(k) are commonly connected to the selection gate lines SGD(0) to SGD(k), respectively. The gate of selection transistor ST(2) is commonly connected to the selection gate line SGS.

[0155] In the circuit configuration of the memory cell array MCA described above, the bit line BL is shared by the NAND string NS, each of which the same column address is assigned in each string unit SU. The source line SL is shared, for example, between multiple block BLKs.

[0156] A collection of multiple memory cells MC connected to a common word line WL within a single string unit SU is referred to, for example, as a cell unit CU. For instance, the storage capacity of a cell unit CU containing memory cells MC, each storing 1 bit of data, is defined as "1 page of data." A cell unit CU may have a storage capacity of 2 pages of data or more, depending on the number of bits of data stored in the memory cells MC.

[0157] Furthermore, the memory cell array MCA provided in the memory 100a according to this embodiment is not limited to the circuit configuration described above. For example, the number of memory cells MC and selection transistors ST(1) and ST(2) included in each NAND string NS can be designed to any number. The number of string units SU included in each block BLK can also be designed to any number.

[0158] The above embodiment is applicable not only to memory array chips but also to the wiring and via contacts of logic circuits such as CMOS chips.

[0159] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0160] 1. Semiconductor memory 28vy via contact BL bit line 25_1 First insulating film 25_2 Second insulating film 25_3 Third insulating film 25_4 Fourth insulating film 25_5 Fifth insulating film 28V via contacts 24W wiring AG Air Gap

Claims

1. A plurality of first wirings are provided in a first direction relative to the first insulating film, extend in a second direction intersecting the first direction, and are arranged in a third direction intersecting the first and second directions. A plurality of second wirings provided in the first direction of the plurality of first wirings, A plurality of first contacts that electrically connect the plurality of first wirings and the plurality of second wirings, In the first region, which includes the region where the plurality of first contacts are formed when viewed from the first direction, a second insulating film is filled between the plurality of first wirings, A semiconductor device comprising: an air-gap insulating film having an air gap between the plurality of first wirings in a second region other than the first region when viewed from the first direction.

2. The semiconductor device according to claim 1, wherein the end of the air gap in the first direction is located closer to the plurality of second wirings than the end of the plurality of first wirings in the first direction.

3. The semiconductor device according to claim 1, wherein the end of the air gap in the direction opposite to the first direction is located closer to the first insulating film than the ends of the plurality of first wirings in the direction opposite to the first direction.

4. The semiconductor device according to claim 1, wherein the second insulating film is filled between the plurality of third wirings in the peripheral region of the plurality of first wirings.

5. The semiconductor device according to claim 1, wherein in the second region, the air gap insulating film is provided between the side walls of the plurality of first wirings and the air gap.

6. The semiconductor device according to claim 1, wherein in the second region, the air gap insulating film is provided between the first insulating film and the air gap.

7. The semiconductor device according to claim 1, wherein in the first region, a fourth insulating film is provided between the first insulating film and the second insulating film, connecting adjacent first wirings.

8. The semiconductor device according to claim 1, wherein, in the vicinity of the region containing the plurality of first wirings, a fourth insulating film is provided between the first insulating film and the second insulating film, connecting adjacent plurality of third wirings.

9. The first region includes an embedded region in which the second insulating film is filled between the plurality of first wirings, The semiconductor device according to claim 1, wherein, when viewed from the first direction, the embedded region extends in the third direction and is arranged in a stripe pattern in the second direction.

10. The first region includes an embedded region in which the second insulating film is filled between the plurality of first wirings, The semiconductor device according to claim 1, wherein, when viewed from the first direction, the embedded region is provided corresponding to one or more first contacts connected to each first wiring.

11. The semiconductor device according to claim 10, wherein, when viewed from the first direction, the embedded region is provided in an island shape corresponding to the first contact.

12. The semiconductor device according to claim 1, further comprising a third region provided in a part of the second region, wherein the second insulating film is filled between the first wirings.

13. The semiconductor device according to claim 12, wherein, when viewed from the first direction, the third region has a stripe shape that extends in the third direction and is arranged in the second direction.

14. The semiconductor device according to claim 12, wherein, when viewed from the first direction, the third region is provided in an island-like manner corresponding to one or more first wirings.

15. The semiconductor device according to claim 12, wherein, when viewed from the first direction, the third region has a stripe shape that extends in the second direction and is arranged in the third direction.

16. A laminate comprising a plurality of first conductive films and a plurality of sixth insulating films stacked alternately one by one in the first direction, A plurality of columnar bodies including a first semiconductor portion extending in the first direction within the laminate, and a first insulating portion provided between the first semiconductor portion and the laminate, The semiconductor device according to claim 1, further comprising a second contact that penetrates the first insulating film and connects the plurality of columnar bodies and the first wiring.

17. A plurality of first wirings are formed, which are provided in a first direction relative to the first insulating film, extend in a second direction intersecting the first direction, and are arranged in a third direction intersecting the first and second directions. A second insulating film is filled between the plurality of first wirings. When viewed from the first direction, the second insulating film in the second region other than the first region where a plurality of first contacts electrically connected to each of the plurality of first wirings are to be formed is selectively removed to form a plurality of first trenches between the plurality of first wirings in the second region. The air gap insulating film material is deposited from the first direction of the plurality of first trenches, thereby sealing the openings of the plurality of first trenches while leaving an air gap between the plurality of first wirings in the second region. In the second region, a contact hole is formed that reaches one of the plurality of first wirings from the first direction of the air gap insulating film. A method for manufacturing a semiconductor device, comprising forming a first contact in the contact hole in the second region.

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