Circuit board and its manufacturing method

Abstract

To provide a circuit board and a method for manufacturing the same that overcome process constraints and meet high-density circuit design requirements. [Solution] The circuit board of the present invention comprises an insulating layer having via holes penetrating in a first direction; a through via including a through portion having a hollow portion extending in the first direction and configured to cover the inner wall of the via hole, and a land portion extending from the through portion in a second direction perpendicular to the first direction; a circuit layer disposed on the insulating layer, separated from the land portion of the through via; and a plug including a plug body that fills the hollow portion of the through via and protrudes to the outside of the surface of the insulating layer, and a plug head that extends from the plug body in a second direction and is disposed on the land portion.

Description

Technical Field

[0001] The present invention relates to a circuit board and a method for manufacturing the same.

Background Art

[0002] As electronic devices, particularly IT devices such as mobile phones, are miniaturized and lightweight, high-density circuit design is an essential requirement. As a result, the circuit patterns applied to package PCBs (Printed Circuit Boards) are gradually becoming finer, and the number of input / output integrated circuits tends to increase. Such technological changes require important technological developments to reduce the line width and spacing of circuits.

[0003] The conventional tenting method has limitations in meeting such miniaturization requirements. Due to process constraints, the uniformity and quality of circuit patterns in the plating and etching processes deteriorate, making it difficult to ensure high-density design and stable power transmission characteristics. Against this background, new methods, namely MSAP (Modified Semi-Additive Process) and SAP (Semi-Additive Process) methods, have been attracting attention to overcome the limitations of existing methods and improve the miniaturization design rules.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present invention has been made in view of the above conventional problems, and an object of the present invention is to provide a circuit board and a method for manufacturing the same that overcome process constraints and meet the requirements of high-density circuit design.

Means for Solving the Problems

[0005] A circuit board according to one aspect of the present invention, made to achieve the above objective, comprises: an insulating layer having via holes penetrating in a first direction; a through via including a hollow portion extending in the first direction and configured to cover the inner wall of the via hole, and a land portion extending from the through portion in a second direction perpendicular to the first direction; a circuit layer spaced apart from the land portion of the through via and disposed on the insulating layer; and a plug including a plug body filling the hollow portion of the through via and protruding to the outside of the surface of the insulating layer, and a plug head extending from the plug body in a second direction and disposed on the land portion.

[0006] The plug head may protrude outward from the surface of the land portion. The diameter of the plug head along the second direction may be smaller than the diameter of the land portion along the second direction. The land portion may have a step on the surface facing the plug head. The step may have a side surface that aligns with the edge of the plug head. The number of metal layers in the through-hole may be less than the number of metal layers in the land portion. The through portion includes a seed layer pattern and an electroplating layer pattern sequentially laminated from the inner wall surface of the via hole, and the land portion may include a copper foil layer pattern, a seed layer pattern, and an electroplating layer pattern sequentially laminated on the insulating layer. The seed layer pattern may be an electroless plating layer pattern. Each of the circuit layer and the land portion may include a copper foil layer pattern, a seed layer pattern, and an electroplating layer pattern sequentially laminated on the insulating layer. The number of metal layers in the through-hole and the number of metal layers in the land portion may be the same. The through portion includes a seed layer pattern and an electroplating layer pattern sequentially laminated from the inner wall surface of the via hole, and the land portion may include a seed layer pattern and an electroplating layer pattern sequentially laminated on the insulating layer. The seed layer pattern may be an electroless plating layer pattern. The seed layer pattern may be a sputtering layer pattern. The circuit board may further include a primer resin layer between the insulating layer and the seed layer pattern.

[0007] A method for manufacturing a circuit board according to one aspect of the present invention, made to achieve the above objective, comprises the steps of: forming via holes penetrating a first insulating layer; forming a first seed layer on the surface of the first insulating layer on which the via holes are formed; forming a first mask pattern on the first seed layer that exposes the via holes and the first seed layer around them; forming an electroplating layer pattern of through vias having hollow portions penetrating in a first direction on the first seed layer exposed by the first mask pattern; forming a second mask pattern that exposes at least a portion of the hollow portion of the through vias and the land portions of the through vias extending onto the first insulating layer; forming a pre-plug to fill the hollow portion of the through vias; flattening the pre-plug and the second mask pattern; and removing the remaining second mask pattern after flattening to form a plug.

[0008] The method for manufacturing the circuit board may further include the step of forming a second insulating layer on the first insulating layer so as to embed the land portion of the through via and the plug. The step of forming the pre-plug may include filling the hollow portion of the through-via with a non-conductive material. The method for manufacturing the circuit board further includes the step of forming a copper foil layer on the first insulating layer, and the step of forming the first seed layer may include the step of forming the first seed layer on the copper foil layer. The step of forming the first seed layer may include the step of forming the first seed layer on the first insulating layer via sputtering or electroless plating. The method for manufacturing the circuit board may further include the step of forming a primer resin layer on the first insulating layer. [Effects of the Invention]

[0009] According to the present invention, the reduction in circuit pattern uniformity and quality problems that occur with existing manufacturing methods can be effectively solved. This makes it possible to further miniaturize the line width and spacing of circuits, enabling high-density design and significantly improving the performance of electronic devices, especially miniaturized IT equipment.

[0010] Furthermore, according to the present invention, power integrity characteristics can be improved by dramatically improving tolerances in the manufacturing process and increasing reliability. This means that it can be widely applied to various electronic equipment environments that require high performance and stability.

[0011] As a result, the present invention can improve the efficiency of the circuit board manufacturing process, meet the requirements for miniaturization design, and contribute to the realization of lighter, thinner, shorter, and more integrated electronic devices. [Brief explanation of the drawing]

[0012] [Figure 1] This is a schematic cross-sectional view showing the structure of a circuit board of a first example according to one embodiment. [Figure 2] This is a cross-sectional view showing an enlarged view of portion A of the circuit board shown in Figure 1. [Figure 3] This is a cross-sectional view illustrating a first example of a circuit board manufacturing method according to one embodiment. [Figure 4] This is a cross-sectional view illustrating a first example of a circuit board manufacturing method according to one embodiment. [Figure 5] This is a cross-sectional view illustrating a first example of a circuit board manufacturing method according to one embodiment. [Figure 6] This is a cross-sectional view illustrating a first example of a circuit board manufacturing method according to one embodiment. [Figure 7] This is a cross-sectional view illustrating a first example of a circuit board manufacturing method according to one embodiment. [Figure 8] This is a cross-sectional view illustrating a first example of a circuit board manufacturing method according to one embodiment. [Figure 9]It is a process cross-sectional view for explaining a manufacturing method of a first example of a circuit board according to an embodiment. [Figure 10] It is a process cross-sectional view for explaining a manufacturing method of a first example of a circuit board according to an embodiment. [Figure 11] It is a process cross-sectional view for explaining a manufacturing method of a first example of a circuit board according to an embodiment. [Figure 12] It is a process cross-sectional view for explaining a manufacturing method of a first example of a circuit board according to an embodiment. [Figure 13] It is a process cross-sectional view for explaining a manufacturing method of a second example of a circuit board according to an embodiment. [Figure 14] It is a process cross-sectional view for explaining a manufacturing method of a second example of a circuit board according to an embodiment. [Figure 15] It is a process cross-sectional view for explaining a manufacturing method of a second example of a circuit board according to an embodiment. [Figure 16] It is a cross-sectional view schematically showing the structure of a first example of a circuit board according to another embodiment. [Figure 17] It is a process cross-sectional view for explaining a manufacturing method of a first example of a circuit board according to another embodiment. [Figure 18] It is a process cross-sectional view for explaining a manufacturing method of a first example of a circuit board according to another embodiment. [Figure 19] It is a process cross-sectional view for explaining a manufacturing method of a first example of a circuit board according to another embodiment. [Figure 20] It is a process cross-sectional view for explaining a manufacturing method of a first example of a circuit board according to another embodiment. [Figure 21] It is a process cross-sectional view for explaining a manufacturing method of a first example of a circuit board according to another embodiment. [Figure 22] It is a process cross-sectional view for explaining a manufacturing method of a first example of a circuit board according to another embodiment. [Figure 23] It is a process cross-sectional view for explaining a manufacturing method of a first example of a circuit board according to another embodiment. [Figure 24]This is a cross-sectional view illustrating a first example of a circuit board manufacturing method according to another embodiment. [Figure 25] This is a schematic cross-sectional view showing the structure of a circuit board in a second example according to another embodiment. [Figure 26] This is a cross-sectional view illustrating a third example of a circuit board manufacturing method according to another embodiment. [Figure 27] This is a cross-sectional view illustrating a third example of a circuit board manufacturing method according to another embodiment. [Figure 28] This is a cross-sectional view illustrating a third example of a circuit board manufacturing method according to another embodiment. [Modes for carrying out the invention]

[0013] Hereinafter, specific examples of embodiments for carrying out the present invention will be described in detail with reference to the drawings.

[0014] In the drawings, parts unrelated to the description have been omitted in order to clearly illustrate the present invention, and the same or similar reference numerals have been used throughout the specification for identical or similar components.

[0015] Some components in the drawings may be exaggerated, omitted, or shown schematically, and the size of each component does not fully reflect its actual size. Furthermore, the drawings are intended to aid in understanding the embodiments disclosed herein and should be understood not to limit the technical ideas disclosed herein, and to include all modifications, equivalents, or substitutions that fall within the concept and technical scope of the invention.

[0016] Terms including ordinal numbers such as "first" and "second" used herein are used solely as identifiers to distinguish various components and do not limit the importance or order of the components.

[0017] When one part is said to be "on top" of another part, this includes not only direct contact but also cases where the other part is interposed between them. However, the expression "directly on top" means a direct contact relationship where there is no other part in between. Furthermore, such positional relationships are independent of the direction of gravity.

[0018] Terms such as “contains” or “has” as used herein indicate the presence of features, figures, stages, actions, components, parts, or combinations thereof described herein. This does not preclude the presence of additional features, figures, stages, actions, components, parts, or combinations thereof. Thus, unless otherwise stated, “contains” a particular component in a part means that other components may be added.

[0019] In this specification, "on a plane" means the object as viewed from above, and "on a cross-section" means the object as viewed from the side of a cross-section obtained by cutting it vertically.

[0020] In this specification, the term "connected" includes various forms of connection between two or more components. This includes not only direct connections but also indirect connections, physical connections, and electrical connections through other components, and includes cases where components are referred to by different names depending on their location or function but still function as a single unit.

[0021] Figure 1 is a schematic cross-sectional view showing the structure of a first example circuit board 10A according to one embodiment. Figure 2 is an enlarged cross-sectional view showing portion A of the circuit board shown in Figure 1.

[0022] Referring to Figure 1, the circuit board 10A according to this embodiment includes a first insulating layer 100 provided as a core layer. A first circuit layer 120 is arranged on both sides of the first insulating layer 100. A second insulating layer 200 is arranged on the first insulating layer 100 so as to cover the first circuit layer 120. A second circuit layer 220 including connection pads 220P and circuit wiring 220C is arranged on the second insulating layer 200. The second circuit layer 220 is connected to the first circuit layer 120 via laminated vias 210 that penetrate the second insulating layer 200.

[0023] A protective layer 300 is placed on the second insulating layer 200. The protective layer 300 protects the internal components from external physical and chemical damage. The protective layer 300 covers one surface of the second insulating layer 200, exposing at least a portion of the connection pad 220P. The protective layer 300 is made of a photosensitive resin, for example, a solder resist layer.

[0024] The first insulating layer 100 and the second insulating layer 200 include an insulating material. The insulating material includes a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material containing such a resin along with an inorganic filler, an organic filler, and / or glass fiber (glass fiber, glass cloth, and / or glass fabric), and is a photosensitive material and / or a non-photosensitive material. As an example, insulating materials such as SR (Solder Resist), ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), RCC (Resin Coated Copper), and CCL (Copper Clad Laminate) are used, but are not limited to these, and other polymer materials may be included. For example, prepregs are used, but are not limited to these. Also, although the first insulating layer 100 is shown as a single layer in Figure 1, it is not limited to this, and the first insulating layer 100 can also be composed of multiple thin layers laminated together.

[0025] The first circuit layer 120 and the second circuit layer 220 each transmit signals within the circuit board 10A. Metallic materials are used as the material for the first circuit layer 120 and the second circuit layer 220. These metallic materials include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The first circuit layer 120 and the second circuit layer 220 each perform various functions through their design, such as ground patterns, power patterns, and signal patterns. These patterns can take the form of lines, planes, or pads. In the case of a circuit layer located on the outermost layer of multiple circuit layers, it functions as a connecting pad for linking to other boards or components.

[0026] The first insulating layer 100 has via holes 104 that penetrate in a first direction, which is the lamination direction. Through vias 110 extend through the via holes 104, and the through vias 110 have hollow portions 111 that penetrate in the first direction. The through vias 110 include a through portion 110A that extends in the first direction so as to cover the inner wall of the via hole 104, and land portions 110B that extend in a second direction perpendicular to the first direction from both ends of the through portion 110A. The land portions 110B of the through vias 110 are located on the same layer as the first circuit layer 120 on the first insulating layer 100 and function to connect the through vias 110 to the first circuit layer 120.

[0027] Metallic materials are used for the through-vias 110 and stacked vias 210, respectively. These metallic materials include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Each of the through-vias 110 and stacked vias 210 may include signal vias, ground vias, power vias, etc., depending on the design.

[0028] The plug 112 fills the hollow portion 111 of the through via 110 and protrudes to the outside of the surface of the first insulating layer 100. The plug 112 contains insulating plugging ink. The plug 112 prevents oxidation of the through via 110 by filling the void inside the via hole 104. The plug 112 includes a plug body 112a that fills the hollow portion 111 of the through via 110 and extends to the outside of the surface of the first insulating layer 100, and a plug head 112b that extends from both ends of the plug body 112a in a second direction perpendicular to the first direction and is located on the land portion 110B of the through via 110. Here, the cross-sectional diameter of the plug head 112b along the second direction is larger than the cross-sectional diameter of the plug body 112a along the second direction. The hollow portion 111 is formed along the inner surface of the through portion 110A, and therefore the through portion 110A is positioned to surround the plug body 112a.

[0029] The detailed layer structure of the first circuit layer 120 and through-via 110 of the circuit board 10A according to one embodiment will be described in more detail below with additional reference to Figure 2.

[0030] Referring to Figures 1 and 2, the first circuit layer 120 includes a plurality of stacked metal layers, and includes a copper foil layer pattern 102C, a seed layer pattern 106C, and an electroplating layer pattern 108C that are sequentially stacked in a first direction on the insulating layer 100.

[0031] The through portion 110A of the through via 110 includes a seed layer pattern 106T and an electroplating layer pattern 108T that are laminated in the direction toward the center from the inner wall surface of the via hole 104. The land portion 110B of the through via 110 includes a copper foil layer pattern 102T, a seed layer pattern 106T, and an electroplating layer pattern 108T that are sequentially laminated in a first direction on the first insulating layer 100. That is, the seed layer pattern 106T is laminated on the copper foil layer pattern 102T, and the electroplating layer pattern 108T is laminated on the seed layer pattern 106T to form the land portion 110B of the through via 110.

[0032] Here, the seed layer patterns (106C, 106T) of the first circuit layer 120 and the through via 110 are metal layers formed by electroless plating, such as copper (Cu) layers, and the electroplated layer patterns (108C, 108T) are metal layers formed on the seed layer patterns 106C, 106T by electroplating, such as copper (Cu) layers.

[0033] The following describes a method for manufacturing a circuit board 10A according to one embodiment, with reference to Figures 3 to 12 along with Figure 1.

[0034] Figures 3 to 12 are cross-sectional process views illustrating a first example of a circuit board manufacturing method according to one embodiment.

[0035] Referring to Figure 3, a first insulating layer 100 is prepared, with copper foil layers 102 formed on both sides. The copper foil layers 102 are formed by laminating copper foil (Cu-foil) on both sides of the first insulating layer 100 and applying pressure. Via holes 104 are formed through the first insulating layer 100 and the copper foil layers 102. Multiple via holes 104 are formed by laser, mechanical drilling, or other methods.

[0036] Referring to Figure 4, a seed layer 106 is formed on the surface of the first insulating layer 100 on which the via holes 104 are formed. The seed layer 106 is formed on the copper foil layer 102 and on the inner wall of the via holes 104. The seed layer 106 is formed as a copper (Cu) layer via electroless plating. A first mask pattern 118P is formed on the seed layer 106, exposing the via holes 104 and the surrounding seed layer 106. The first mask pattern 118P exposes the region of the seed layer 106 located along the edge of the via holes 104. The first mask pattern 118P also exposes the seed layer 106 in the region where circuit wiring will be formed later. The first mask pattern 118P is patterned by exposing and developing a photosensitive dry film.

[0037] Referring to Figures 5 and 6, an electroplated layer pattern 108T is formed by electroplating onto the via hole 104 and the seed layer 106 exposed around it using the first mask pattern 118P. The electroplated layer pattern 108T is made of copper (Cu). An electroplated layer pattern 108C for forming the first circuit layer 120 is formed on the seed layer 106 exposed by using the first mask pattern 118P as a plating mask in a region of the first insulating layer 100 other than around the via hole 104. The electroplated layer pattern 108C is made of a copper (Cu) layer. Subsequently, the first mask pattern 118P is peeled off and removed.

[0038] Referring to Figure 7, after removing the first mask pattern 118P, the exposed seed layer 106 and the copper foil layer 102 beneath it are removed by flash etching to form the first circuit layer 120 and the through via 110. The first circuit layer 120 is formed on the first insulating layer 100 to include a copper foil layer pattern 102C, a seed layer pattern 106C, and an electroplating layer pattern 108C. The through via 110 includes a through portion 110A on the inner wall of the via hole 104, and a land portion 110B connected to the through portion 110A and extending onto the upper and lower surfaces of the first insulating layer 100. The through portion 110A of the through via 110 includes a seed layer pattern 106T and an electroplating layer pattern 108T laminated on the inner wall surface of the via hole 104. The land portion 110B of the through via 110 includes a copper foil layer pattern 102T, a seed layer pattern 106T, and an electroplating layer pattern 108T, which are laminated on the first insulating layer 100.

[0039] Referring to Figure 8, a second mask pattern 218P is formed on the first insulating layer 100 on which the first circuit layer 120 is formed. The second mask pattern 218P covers a portion of the land portion 110B of the through via 110, exposing a portion of the land portion 110B located along the hollow portion 111 of the through via 110 and its edge. The second mask pattern 218P is patterned by exposing and developing a photosensitive dry film.

[0040] Referring to Figure 9, a preliminary plug (112P) is formed that fills the hollow portion 111 of the through via 110, extending in stages onto the exposed land portion 110B and the second mask pattern 218P. That is, the preliminary plug 112P is partially located on the land portion 110B exposed by the second mask pattern 218P and again along the open edge of the second mask pattern 218P. The preliminary plug 112P is formed by printing insulating ink.

[0041] Referring to Figure 10, the portion of the preliminary plug 112P formed on the second mask pattern 218P and the second mask pattern 218P are both polished to planarize their surfaces. In this process, the portion of the preliminary plug 112P extending onto the second mask pattern 218P is removed, becoming the plug 112. Also, the thickness of the plug 112 portion and the second mask pattern 218P located on the land portion 110B becomes smaller than before the planarization, and the surfaces of the plug 112 and the second mask pattern 218P are substantially on the same plane. A portion of the plug 112 is surrounded by the through portion 110A of the through via 110 and is formed containing a non-conductive material.

[0042] Referring to Figure 11, when the remaining second mask pattern 218P is peeled off and removed, a plug 112 is formed that fills the hollow portion 111 of the through via 110 and protrudes onto the land portion 110B. Thus, the plug 112 includes a plug body 112a that fills the hollow portion 111 of the through via 110 that penetrates in a first direction and protrudes to the outside of the first insulating layer 100, and a plug head 112b that extends from the plug body 112a in a second direction perpendicular to the first direction and is positioned on the land portion 110B.

[0043] The land portion 110B of the through via 110 includes a copper foil layer pattern 102T, a seed layer pattern 106T, and an electroplating layer pattern 108T sequentially laminated on the first insulating layer 100, and at least a portion of the head 112b of the plug 112 is located on the electroplating layer pattern 108T of the land portion 110B.

[0044] Referring to Figure 12, a second insulating layer 200 is formed on the first insulating layer 100 so as to fill in the first circuit layer 120, the land portion 110B of the through via 110, and the plug head 112b. Then, the connection pad 220P and circuit wiring 220C of the second circuit layer 220 are formed on the second insulating layer 200. In addition, a build-up via 210 is formed through the second insulating layer 200 to connect the first circuit layer 120 and the circuit wiring 220C of the second circuit layer 220. The connection pad 220P of the second circuit layer 220, the circuit wiring 220C, and the build-up via 210 are formed using a normal wiring formation method, such as the subtractive method, AP (Additive Process), SAP (Semi Additive Process), or MSAP (Modified Semi Additive Process).

[0045] Referring to both Figure 12 and Figure 1, a protective layer 300 is formed on the second insulating layer 200 on which the connection pads 220P and circuit wiring 220C of the second circuit layer 220 are formed, exposing a portion of the connection pads 220P. The protective layer 300 is a solder resist layer formed by exposing and developing a photosensitive resin.

[0046] According to the circuit board manufacturing method of this embodiment, since a mask pattern is formed on the copper foil layer and seed layer laminated on the insulating layer, through-vias and plugs are formed afterward, through-vias can be formed more finely and precisely compared to the method in which the entire upper surface of the insulating layer is plated and then etched.

[0047] Figures 13 to 15 are cross-sectional process views illustrating a second example of a circuit board manufacturing method according to one embodiment.

[0048] In the circuit board manufacturing method described with reference to Figures 1 to 12, the first circuit layer 120 and the through-via 110 were formed so as to be separated from each other before forming the plug 112. That is, the seed layer 106 and the copper foil layer 102 were patterned by flash etching before filling the inside of the hollow portion 111 of the through-via 110 with a pre-plug 112P. On the other hand, in the circuit board manufacturing method according to this embodiment, the plug 122 is formed before flash etching for patterning the seed layer 106 and the copper foil layer 102, and the seed layer 106 and the copper foil layer 102 are flash-etched and patterned together with the plug 122 thus formed.

[0049] Referring to Figure 13, via holes 104 are formed through the first insulating layer 100, which has copper foil layers 102 formed on both sides, and a seed layer 106 is formed on the copper foil layers 102 and on the inner walls of the via holes 104 by electroless plating. After exposing the seed layer 106 of the via holes 104 and their surrounding areas, and the area in which the first circuit layer 120 is formed, using a first mask pattern, electroplating is performed to form an electroplated layer.

[0050] The electroplating layer formed on the seed layer 106 on the inner wall of the via hole 104 is connected to the electroplating layer around the via hole 104 to form a through via 115. Specifically, the electroplating layer on the inner wall of the via hole 104 forms the through portion 115A of the through via 115, and the electroplating layer around the via hole 104 forms the land portion 115B of the through via 115 as an electroplating layer pattern 108T. In addition, an electroplating layer pattern 108C is formed in the region where the first circuit layer 120 is formed.

[0051] Subsequently, a second mask pattern 218P is formed on the seed layer 106 and the electroplating layer patterns (108T, 108C). The second mask pattern 218P covers a portion of the electroplating layer pattern 108T that constitutes the land portion 115B of the through via 115, and exposes a portion of the hollow portion 116 of the through via 115 and the land portion 115B located along its edge. The second mask pattern 218P is patterned by exposing and developing a photosensitive dry film.

[0052] Subsequently, the hollow portion 116 of the through via 115 is filled, forming a preliminary plug 122P that extends in stages over the exposed land portion 115B and the second mask pattern 218P. That is, the preliminary plug 122P is partially located on the land portion 115B exposed by the second mask pattern 218P and again along the open edge of the second mask pattern 218P. The preliminary plug 122P is formed by printing insulating ink.

[0053] Referring to Figure 14, the portion of the preliminary plug 122P formed on the second mask pattern 218P and the second mask pattern 218P are both polished to planarize their surfaces. In this process, the portion of the preliminary plug 122P extending onto the second mask pattern 218P is removed to become plug 122. Also, the thickness of the portion of plug 122 located on the land portion 115B and the second mask pattern 218P becomes smaller than before the planarization work, and the surfaces of plug 122 and the second mask pattern 218P are substantially on the same plane. A portion of plug 122 is surrounded by the through portion 115A of the through via 115 and is formed containing a non-conductive material.

[0054] Subsequently, when the remaining second mask pattern 218P is peeled off and removed, a plug 122 is formed that fills the hollow portion 116 of the through via 115 and protrudes onto the land portion 115B. Thus, the plug 122 includes a plug body 122a that fills the hollow portion 116 of the through via 115 that penetrates in a first direction and protrudes to the outside of the first insulating layer 100, and a plug head 122b that extends from the plug body 122a in a second direction perpendicular to the first direction and is positioned on the land portion 115B.

[0055] Subsequently, the seed layer 106 and the copper foil layer 102 beneath it, which are exposed after the removal of the second mask pattern 218P, are removed by flash etching to form the first circuit layer 120 and the through via 115. The first circuit layer 120 is formed on the first insulating layer 100 to include a copper foil layer pattern 102C, a seed layer pattern 106C, and an electroplating layer pattern 108C. The through portion 115A of the through via 115 includes a seed layer pattern 106T and an electroplating layer pattern 108T laminated on the inner wall surface of the via hole 104. The land portion 115B of the through via 115 includes a copper foil layer pattern 102T, a seed layer pattern 106T, and an electroplating layer pattern 108T laminated on the first insulating layer 100.

[0056] At least a portion of the plug head 122b is located on the electroplating layer pattern 108T of the land portion 115B. During the flash etching process, a portion of the electroplating layer pattern 108T constituting the land portion 115B of the through via 115 is exposed to the etching solution, but the portion of the electroplating layer pattern 108T covered by the plug head 122b is not exposed to the etching solution. Therefore, the exposed portion of the electroplating layer pattern 108T is lower than the portion that is etched and not exposed. As a result, the electroplating layer pattern 108T of the land portion 115B has a step ST on the surface facing the plug head 122b, and the step ST has a side surface that aligns with the edge of the plug head 122b.

[0057] Referring to Figure 15, a second insulating layer 200 is formed on the first insulating layer 100 so as to fill in the first circuit layer 120, the land portion 115B of the through via 115, and the plug head 122b. Then, a second circuit layer 220 including a connection pad 220P and circuit wiring 220C is formed on the second insulating layer 200. In addition, a laminated via 210 is formed to connect the first circuit layer 120 and the second circuit layer 220 by penetrating the second insulating layer 200. The second circuit layer 220 and the laminated via 210 are formed using a normal wiring formation method, such as the subtractive method, AP (Additive Process), SAP (Semi Additive Process), or MSAP (Modified Semi Additive Process).

[0058] A protective layer 300 is formed on the second insulating layer 200, on which the connection pads 220P and circuit wiring 220C of the second circuit layer 220 are formed, exposing a portion of the connection pads 220P. The protective layer 300 is a solder resist layer formed by exposing and developing a photosensitive resin. This completes the circuit board 10B according to this embodiment.

[0059] Figure 16 is a schematic cross-sectional view showing the structure of a circuit board in a first example according to another embodiment.

[0060] Referring to Figure 16, the circuit board 20A according to this embodiment includes a first insulating layer 100 provided as a core layer. A first circuit layer 140 is placed on both sides of the first insulating layer 100. A second insulating layer 200 is placed on the first insulating layer 100 so as to cover the first circuit layer 140. A second circuit layer 240 including connection pads 240P and circuit wiring 240C is placed on the second insulating layer 200. The second circuit layer 240 is connected to the first circuit layer 140 via laminated vias 250 that penetrate the second insulating layer 200.

[0061] A protective layer 300 is placed on the second insulating layer 200. The protective layer 300 protects the internal components from external physical and chemical damage. The protective layer 300 covers one surface of the second insulating layer 200, exposing at least a portion of the connection pad 240P. The protective layer 300 is made of a photosensitive resin, such as a solder resist layer.

[0062] The first insulating layer 100 and the second insulating layer 200 include an insulating material. The insulating material includes a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material containing such a resin along with an inorganic filler, an organic filler, and / or glass fiber (glass fiber, glass cloth, and / or glass fabric), and is a photosensitive material and / or a non-photosensitive material. As an example, insulating materials such as SR (Solder Resist), ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), RCC (Resin Coated Copper), and CCL (Copper Clad Laminate) are used, but are not limited to these, and other polymer materials may be included. For example, prepregs are used, but are not limited to these. Also, although the first insulating layer 100 is shown as a single layer in Figure 16, it is not limited to this, and the first insulating layer 100 can also be composed of multiple thin layers laminated together.

[0063] The first circuit layer 140 and the second circuit layer 240 each transmit signals within the circuit board 20A. Metallic materials are used as the material for the first circuit layer 140 and the second circuit layer 240. These metallic materials include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The first circuit layer 140 and the second circuit layer 240 each perform various functions through their design, such as ground patterns, power patterns, and signal patterns. These patterns can take the form of lines, planes, or pads. In the case of a circuit layer located on the outermost layer of multiple circuit layers, it functions as a connecting pad for linking to other boards or components.

[0064] The first insulating layer 100 has via holes 104 that penetrate in a first direction, which is the lamination direction. Through vias 130 extend through the via holes 104, and the through vias 130 have hollow portions 131 that penetrate in the first direction. The through vias 130 include a through portion 130A that extends in the first direction so as to cover the inner wall of the via hole 104, and land portions 130B that extend in a second direction perpendicular to the first direction from both ends of the through portion 130A. The land portions 130B of the through vias 130 are located on the same layer as the first circuit layer 140 on the first insulating layer 100 and function to connect the through vias 130 to the first circuit layer 140.

[0065] Metallic materials are used for both the through-via 130 and the stacked via 250. These metallic materials include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Each of the through-via 130 and stacked via 250 may include signal vias, ground vias, power vias, etc., depending on the design.

[0066] The plug 132 fills the hollow portion 131 of the through via 130 and protrudes to the outside of the surface of the first insulating layer 100. The plug 132 contains insulating plugging ink. The plug 132 prevents oxidation of the through via 130 by filling the void inside the via hole 104. The plug 132 includes a plug body 132a that fills the hollow portion 131 of the through via 130 and extends to the outside of the surface of the first insulating layer 100, and a plug head 132b that extends from both ends of the plug body 132a in a second direction perpendicular to the first direction and is located on the land portion 130B of the through via 130. Here, the cross-sectional diameter of the plug head 132b along the second direction is greater than the cross-sectional diameter of the plug body 132a along the second direction. The hollow portion 131 is formed along the inner surface of the through portion 130A, and therefore the through portion 130A is positioned to surround the plug body 132a.

[0067] The first circuit layer 140 includes a plurality of stacked metal layers, and includes a seed layer pattern 126C and an electroplating layer pattern 128C that are sequentially stacked in a first direction on the insulating layer 100.

[0068] The through portion 130A of the through via 130 includes a seed layer pattern 126T and an electroplating layer pattern 128T that are stacked in the direction toward the center from the inner wall surface of the via hole 104. The land portion 130B of the through via 130 includes a seed layer pattern 126T and an electroplating layer pattern 128T that are sequentially stacked in the first direction on the first insulating layer 100. Here, the respective seed layer patterns (126C, 126T) of the first circuit layer 140 and the through via 130 are metal layers formed by electroless plating, such as copper (Cu) layers, and the electroplating layer patterns (128C, 128T) are metal layers formed on the seed layer pattern 126T by electroplating, such as copper (Cu) layers.

[0069] The manufacturing method of the circuit board 20A shown in Figure 16 will be described below with reference to Figures 17 to 24, along with Figure 16.

[0070] Figures 17 to 24 are cross-sectional process views illustrating a first example of a circuit board manufacturing method according to another embodiment.

[0071] Referring to Figure 17, via holes 104 are formed so as to penetrate the first insulating layer 100, and a seed layer 126 is formed on the surface of the first insulating layer 100 where the via holes 104 are formed. Multiple via holes 104 are formed by laser, mechanical drilling, etc. The seed layer 126 is formed on the first insulating layer 100 and on the inner walls of the via holes 104. The seed layer 126 is formed of a copper (Cu) layer via sputtering or electroless plating.

[0072] A first mask pattern 118P is formed on the seed layer 126, exposing the via hole 104 and the surrounding seed layer 126. The first mask pattern 118P exposes the region on the seed layer 126 located along the edge of the via hole 104. The first mask pattern 118P also exposes the seed layer 126 in the region where circuit wiring will be formed later. The first mask pattern 118P is patterned by exposing and developing a photosensitive dry film.

[0073] Referring to Figure 18, an electroplated layer pattern 128T is formed on the seed layer 106 exposed around the via hole 104 by electroplating using the first mask pattern 118P. The electroplated layer pattern 128T is made of copper (Cu). On the seed layer 126 exposed using the first mask pattern 118P as a plating mask in areas of the first insulating layer 100 other than around the via hole 104, an electroplated layer pattern 128C is formed to form the first circuit layer 140. The electroplated layer pattern 128C is made of a copper (Cu) layer. Subsequently, the first mask pattern 118P is peeled off and removed.

[0074] Referring to Figure 19, after the first mask pattern 118P is removed, the exposed seed layer 126 is removed via quick etching to form the first circuit layer 140 and the through via 130. The first circuit layer 140 is formed on the first insulating layer 100 to include a seed layer pattern 126C and an electroplating layer pattern 128C. The through via 130 includes a through portion 130A on the inner wall of the via hole 104, and a land portion 130B connected to the through portion 130A and extending onto the upper and lower surfaces of the first insulating layer 100. The through portion 130A of the through via 130 includes a seed layer pattern 126T and an electroplating layer pattern 128T laminated on the inner wall surface of the via hole 104. The land portion 130B of the through via 130 includes a seed layer pattern 126T and an electroplating layer pattern 128T laminated on the first insulating layer 100.

[0075] Referring to Figure 20, a second mask pattern 218P is formed on the first insulating layer 100 on which the first circuit layer 140 is formed. The second mask pattern 218P covers a portion of the land portion 130B of the through via 130, exposing a portion of the hollow portion 131 of the through via 130 and the land portion 130B located along its edge. The second mask pattern 218P is patterned by exposing and developing a photosensitive dry film.

[0076] Referring to Figure 21, a preliminary plug 132P is formed by filling the hollow portion 131 of the through via 130, and extending in stages over the exposed land portion 130B and the second mask pattern 218P. That is, the preliminary plug 132P is partially located on the land portion 130B exposed by the second mask pattern 218P and again along the periphery of the open edge of the second mask pattern 218P. The preliminary plug 132P is formed by printing insulating ink.

[0077] Referring to Figure 22, the pre-plug 132P and the second mask pattern 218P in the portion formed on the second mask pattern 218P are both polished to planarize their surfaces. In this process, the pre-plug 132P extending onto the second mask pattern 218P is removed, becoming plug 132. Also, the thickness of the plug 132 portion located on the land portion 130B and the second mask pattern 218P becomes smaller than before the planarization, and the surfaces of plug 132 and the second mask pattern 218P are substantially on the same plane. A portion of plug 132 is surrounded by the through portion 130A of the through via 130 and is formed containing a non-conductive material.

[0078] Referring to Figure 23, when the remaining second mask pattern 218P is peeled off and removed, a plug 132 is formed that fills the hollow portion 131 of the through via 130 and protrudes onto the land portion 130B. Thus, the plug 132 includes a plug body 132a that fills the hollow portion 131 of the through via 130 that penetrates in a first direction and protrudes to the outside of the first insulating layer 100, and a plug head 132b that extends from the plug body 132a in a second direction perpendicular to the first direction and is positioned on the land portion 130B.

[0079] The land portion 130B of the through via 130 includes a seed layer pattern 126T and an electroplating layer pattern 128T sequentially laminated on the first insulating layer 100, and at least a portion of the head 132b of the plug 132 is located on the electroplating layer pattern 128T of the land portion 130B.

[0080] Referring to Figure 24, a second insulating layer 200 is formed on the first insulating layer 100 so as to fill in the first circuit layer 140, the land portion 130B of the through via 130, and the plug head 132b. Then, a second circuit layer 240 including a connection pad 240P and circuit wiring 240C is formed on the second insulating layer 200. In addition, a laminated via 250 is formed to connect the first circuit layer 140 and the second circuit layer 240 by penetrating the second insulating layer 200. The second circuit layer 240 and the laminated via 250 are formed using a normal wiring formation method, such as the subtractive method, AP (Additive Process), SAP (Semi Additive Process), or MSAP (Modified Semi Additive Process).

[0081] Referring to both Figure 24 and Figure 16, a protective layer 300 is formed on the second insulating layer 200 on which the connection pad 240P and circuit wiring 240C of the second circuit layer 220 are formed, exposing a portion of the connection pad 240P. The protective layer 300 is a solder resist layer formed by exposing and developing a photosensitive resin.

[0082] Figure 25 is a schematic cross-sectional view showing the structure of a second example of a circuit board 20A' according to another embodiment.

[0083] In the circuit board manufacturing method described with reference to Figures 17 to 24, a primer resin layer 101 is coated onto the first insulating layer 100 before forming the seed layer 126, and a copper foil is laminated on the primer resin layer 101 to create and use a primer copper foil CCL (Copper Clad Laminate). The copper foil on the surface of the CCL is etched off before forming the seed layer 126, and the primer resin layer 101 is exposed in this process. A palladium catalyst is adsorbed onto the surface of the exposed primer resin layer 101, and the seed layer 126 is formed on the catalyst-adsorbed surface via sputtering or electroless plating. Therefore, the primer resin layer 101 is maintained throughout the circuit board manufacturing process.

[0084] Referring to Figure 25, in the second example of the circuit board 20A' according to this embodiment, the first circuit layer 140, through vias 130, and second circuit layer 240 are formed on the first insulating layer 100 while the primer resin layer 101 remains on the first insulating layer 100.

[0085] Figures 26 to 28 are cross-sectional process views illustrating a third example of a manufacturing method for the circuit board 20B according to another embodiment.

[0086] In the circuit board manufacturing method described with reference to Figures 17 to 24, the first circuit layer 140 and the through-vias 130 were formed to separate them from each other before forming the plugs 132. That is, the seed layer 126 was patterned via flash etching before filling the inside of the hollow portion 131 of the through-vias 130 with a pre-filled plug 132P. On the other hand, in the manufacturing method of the circuit board 20B according to this embodiment, the plugs 142 are formed before flash etching for patterning the seed layer 106, and the seed layer 106 is flash-etched and patterned together with the thus formed plugs 142.

[0087] Referring to Figure 26, via holes 104 are formed through the first insulating layer 100, and a seed layer 126 is formed on the inner wall of the via holes 104 and the surface of the first insulating layer 100 by electroless plating. After exposing the seed layer 126 of the via holes 104 and their surrounding areas, and the area in which the first circuit layer 140 is formed, using the first mask pattern, an electroplated layer is formed by electroplating.

[0088] The electroplating layer formed on the seed layer 126 on the inner wall of the via hole 104 is connected to the electroplating layer around the via hole 104 to form a through via 135. Specifically, the electroplating layer on the inner wall of the via hole 104 forms the through portion 135A of the through via 135, and the electroplating layer around the via hole 104 forms the land portion 135B of the through via 135 as an electroplating layer pattern 128T. In addition, an electroplating layer pattern 128C is formed in the region where the first circuit layer 140 is formed.

[0089] Subsequently, a second mask pattern 218P is formed on the seed layer 126 and the electroplating layer patterns (128T, 128C). The second mask pattern 218P covers a portion of the electroplating layer pattern 128T that constitutes the land portion 135B of the through via 135, and exposes a portion of the hollow portion 136 of the through via 135 and the land portion 135B located along its edge. The second mask pattern 218P is patterned by exposing and developing a photosensitive dry film.

[0090] Subsequently, the hollow portion 136 of the through via 135 is filled, forming a preliminary plug 142P that extends in stages over the exposed land portion 135B and the second mask pattern 218P. That is, the preliminary plug 142P is partially located on the land portion 135B exposed by the second mask pattern 218P and again along the periphery of the open edge of the second mask pattern 218P. The preliminary plug 142P is formed by printing insulating ink.

[0091] Referring to Figure 27, the portion of the preliminary plug 142P formed on the second mask pattern 218P and the second mask pattern 218P are both polished to flatten their surfaces. In this process, the portion of the preliminary plug 142P extending onto the second mask pattern 218P is removed to become plug 142. Also, the thickness of the portion of plug 142 located on the land portion 135B and the second mask pattern 218P becomes smaller than before the flattening process, and the surfaces of plug 142 and the second mask pattern 218P are substantially on the same plane. A portion of plug 142 is surrounded by the through portion 135A of the through via 135 and is formed containing a non-conductive material.

[0092] Subsequently, when the remaining second mask pattern 218P is peeled off and removed, a plug 142 is formed that fills the hollow portion 136 of the through via 135 and protrudes onto the land portion 135B. Thus, the plug 142 includes a plug body 142a that fills the hollow portion 136 of the through via 135 that penetrates in a first direction and protrudes to the outside of the first insulating layer 100, and a plug head 142b that extends from the plug body 142a in a second direction perpendicular to the first direction and is positioned on the land portion 135B.

[0093] Subsequently, the seed layer 126 exposed after the removal of the second mask pattern 218P is removed by flash etching to form the first circuit layer 140 and the through via 135. The first circuit layer 140 is formed on the first insulating layer 100 so as to include a seed layer pattern 126C and an electroplating layer pattern 128C. The through portion 135A of the through via 135 includes a seed layer pattern 126T and an electroplating layer pattern 128T laminated on the inner wall surface of the via hole 104. The land portion 135B of the through via 135 includes a seed layer pattern 126T and an electroplating layer pattern 128T laminated on the first insulating layer 100.

[0094] At least a portion of the plug head 142b is located on the electroplating layer pattern 128T of the land portion 135B. During the flash etching process, a portion of the electroplating layer pattern 128T constituting the land portion 135B of the through via 135 is exposed to the etching solution, but the portion of the electroplating layer pattern 128T covered by the plug head 142b is not exposed to the etching solution. Therefore, the exposed portion of the electroplating layer pattern 128T is lower than the portion that is etched and not exposed. As a result, the electroplating layer pattern 128T of the land portion 135B has a step ST on the surface facing the plug head 142b, and the step ST has a side surface that aligns with the edge of the plug head 142b.

[0095] Referring to Figure 28, a second insulating layer 200 is formed on the first insulating layer 100 so as to fill in the first circuit layer 140, the land portion 135B of the through via 135, and the plug head 142b. Then, a second circuit layer 240 including a connection pad 240P and circuit wiring 240C is formed on the second insulating layer 200. In addition, a laminated via 250 is formed to connect the first circuit layer 140 and the second circuit layer 240 by penetrating the second insulating layer 200. The second circuit layer 240 and the laminated via 250 are formed using a normal wiring formation method, such as subtractive, AP (Additive Process), SAP (Semi Additive Process), or MSAP (Modified Semi Additive Process).

[0096] A protective layer 300 is formed on the second insulating layer 200, on which the connection pads 240P and circuit wiring 240C of the second circuit layer 240 are formed, exposing a portion of the connection pads 240P. The protective layer 300 is a solder resist layer formed by exposing and developing a photosensitive resin. This completes the circuit board 20B according to this embodiment.

[0097] Although embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the embodiments described above, and can be modified and implemented in various ways without departing from the technical spirit of the present invention. [Explanation of Symbols]

[0098] 10A, 10B, 20A, 20A', 20B circuit board 100, 200 First and second insulating layers 101 Primer resin layer 102 Copper foil layer 102C, 102T copper foil layer pattern 104 Beer Hall 106 Seed Layer 106C, 106T, 126C, 126T seed layer patterns 108C, 108T, 128C, 128T electrolytic plating layer patterns 110, 115, 130, 135 through vias 110A, 115A, 130A, 135A penetrations 110B, 115B, 130B, 135B Land section 111, 116, 131, 136 Hollow part 112, 122, 132, 142 plugs 112a, 122a, 132a, 142a plug body 112b, 122b, 132b, 142b plug heads 112P, 122P, 132P, 142P spare plugs 118P, 218P First and Second Mask Patterns 120, 140 1st circuit layer 210, 250 stacked vias 220, 240 2nd circuit layer 220C Circuit Wiring 220P Connection Pad 300 protective layer ST step

Claims

1. An insulating layer having via holes penetrating in the first direction, A through via having a hollow portion extending in the first direction and configured to cover the inner wall of the via hole, and a land portion including a land portion extending from the through portion in a second direction perpendicular to the first direction, A circuit layer disposed on the insulating layer, separated from the land portion of the through via, A circuit board characterized by comprising a plug including a plug body that fills the hollow portion of the through via and protrudes to the outside of the surface of the insulating layer, and a plug head that extends from the plug body in the second direction and is disposed on the land portion.

2. The circuit board according to claim 1, characterized in that the plug head protrudes outward from the surface of the land portion.

3. The circuit board according to claim 1, characterized in that the diameter of the plug head along the second direction is smaller than the diameter of the land portion along the second direction.

4. The circuit board according to claim 1, characterized in that the land portion has a step on the surface facing the plug head.

5. The circuit board according to claim 4, characterized in that the step has a side surface that aligns with the edge of the plug head.

6. The circuit board according to claim 1, characterized in that the number of metal layers in the through-holes is less than the number of metal layers in the land portions.

7. The through portion includes a seed layer pattern and an electroplating layer pattern that are sequentially laminated from the inner wall surface of the via hole. The circuit board according to claim 6, characterized in that the land portion includes a copper foil layer pattern, a seed layer pattern, and an electrolytic plating layer pattern sequentially laminated on the insulating layer.

8. The circuit board according to claim 7, characterized in that the seed layer pattern is an electroless plating layer pattern.

9. The circuit board according to claim 1, characterized in that each of the circuit layer and the land portion includes a copper foil layer pattern, a seed layer pattern, and an electroplating layer pattern sequentially laminated on the insulating layer.

10. The circuit board according to claim 1, characterized in that the number of metal layers in the through-holes and the number of metal layers in the land areas are the same.

11. The through portion includes a seed layer pattern and an electroplating layer pattern that are sequentially laminated from the inner wall surface of the via hole. The circuit board according to claim 10, characterized in that the land portion includes a seed layer pattern and an electrolytic plating layer pattern sequentially laminated on the insulating layer.

12. The circuit board according to claim 11, characterized in that the seed layer pattern is an electroless plating layer pattern.

13. The circuit board according to claim 11, characterized in that the seed layer pattern is a sputtering layer pattern.

14. The circuit board according to claim 11, further comprising a primer resin layer between the insulating layer and the seed layer pattern.

15. The step of forming via holes that penetrate the first insulating layer, The steps include forming a first seed layer on the surface of the first insulating layer in which the via holes are formed, The steps include forming a first mask pattern on the first seed layer that exposes the via holes and the first seed layer around them, The steps include forming an electroplating layer pattern of through vias having hollow portions penetrating in a first direction on the first seed layer exposed by the first mask pattern, The steps include forming a second mask pattern that exposes at least a portion of the hollow portion of the through via and the land portion of the through via extending onto the first insulating layer, The steps include forming a preliminary plug to fill the hollow portion of the through via, The steps include flattening the aforementioned spare plug and the second mask pattern, A method for manufacturing a circuit board, comprising the step of removing the second mask pattern remaining after planarization to form a plug.

16. The method for manufacturing a circuit board according to claim 15, further comprising the step of forming a second insulating layer on the first insulating layer so as to embed the land portion of the through via and the plug.

17. The method for manufacturing a circuit board according to claim 15, characterized in that the step of forming the pre-plug includes a step of filling the hollow portion of the through-via with a non-conductive material.

18. The process further includes the step of forming a copper foil (Cu-foil) layer on the first insulating layer, The method for manufacturing a circuit board according to claim 15, characterized in that the step of forming the first seed layer includes the step of forming the first seed layer on a copper foil layer.

19. The method for manufacturing a circuit board according to claim 15, characterized in that the step of forming the first seed layer includes the step of forming the first seed layer on the first insulating layer via sputtering or electroless plating.

20. The method for manufacturing a circuit board according to claim 15, further comprising the step of forming a primer resin layer on the first insulating layer.

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