Design method for laminated structures and their bonding layers

Abstract

This invention provides a method for designing a laminated structure and its bonding layer. [Solution] The design method provides a first stacked structure, which is formed by stacking and bonding a plurality of wafers, and the first stacked structure comprises a plurality of die regions, a plurality of bonding test regions, and a dicing line. The dicing line separates the plurality of die regions, and the plurality of bonding test regions are located within the dicing line. Each of the plurality of bonding test regions includes a test circuit, and the test circuit includes a conductive bonding structure formed by bonding the bonding pads of the plurality of wafers to each other. The bonding pads in each of the plurality of bonding test regions have different design parameters. Electrical characteristic measurements are performed on the test circuits of each of the plurality of bonding test regions of the first stacked structure. Based on the results of the electrical characteristic measurements, the feasible design parameter range of the bonding pads in the plurality of die regions of the first stacked structure is determined.

Description

Technical Field

[0001] The present invention relates to a structure and its design method, and particularly to a laminated structure and a design method for its bonding layer.

Background Art

[0002] Generally, in order to achieve high-efficiency operations, a plurality of wafers are stacked on each other to form a stacked structure. In the previous process, it is possible to determine or verify the process window through an automation tool of the working equipment. However, in the subsequent bonding process, it cannot be determined through the above-mentioned automation tool, and it is difficult to predict related parameters of the bonding process, such as design parameters of bonding pads, process parameters of the bonding process, the number of stacked wafers, etc. Once the bonding fails during the design test process, the stacked structure of the batch will be lost, and it is necessary to perform design modifications corresponding to the layout of the die area, resulting in an increase in design cost and a decrease in execution efficiency. Therefore, how to improve the design of the bonding layer of the stacked structure is the current goal to be improved.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The present invention provides a design method for a stacked structure and its bonding layer that can effectively reduce the design cost and improve the efficiency.

Means for Solving the Problems

[0004] The present invention provides a method for designing a bonding layer in a laminated structure, comprising the following steps: providing a first laminated structure comprising a plurality of wafers stacked and bonded, wherein the first laminated structure comprises a plurality of die regions, a plurality of bonding test regions, and a dicing line. The dicing line separates the plurality of die regions, and the plurality of bonding test regions are located within the dicing line. Each of the plurality of bonding test regions of the first laminated structure includes a test circuit, and the test circuit of the first laminated structure includes a conductive bonding structure formed by bonding the bonding pads of the plurality of wafers to each other. Each of the plurality of wafers in the first laminated structure has different design parameters for the bonding pads in the plurality of bonding test regions. Electrical characteristic measurements are performed on each of the test circuits in the plurality of bonding test regions of the first laminated structure. Based on the results of the electrical characteristic measurements, the feasible design parameter range for the bonding pads in the plurality of die regions of the first laminated structure is determined.

[0005] The laminated structure of the present invention includes a first wafer and a second wafer. The first wafer includes a plurality of first die regions, a first dicing line, and a plurality of first bonding test regions. The first dicing line separates the plurality of first die regions. The plurality of first bonding test regions are located within the first dicing line, and each plurality of first bonding test regions includes a first region and a second region, the first region includes a plurality of first bonding pads, and the second region includes a plurality of second bonding pads. The second wafer includes a plurality of second die regions, a second dicing line, and a plurality of second bonding test regions. The second dicing line separates the plurality of second die regions. The plurality of second bonding test regions are located within the second dicing line, and each plurality of second bonding test regions includes a third region and a fourth region, the third region includes a plurality of third bonding pads, and the fourth region includes a plurality of fourth bonding pads. Multiple bonding pads in the second die regions of the second wafer are in direct contact with the corresponding bonding pads in the first die regions of the first wafer; multiple third bonding pads in the third region of the second wafer are in direct contact with multiple first bonding pads in the first region of the first wafer; and multiple fourth bonding pads in the fourth region of the second wafer are in direct contact with multiple second bonding pads in the second region of the first wafer. [Effects of the Invention]

[0006] Based on the above, the laminated structure of the present invention allows for the determination of the feasible range of bonding pad design parameters, bonding process parameters, and number of chip stacks in the laminated structure by performing electrical characteristic measurements on test circuits of multiple bonding test areas in the dicing line. Furthermore, adjustments can be made to the design of the bonding layer in the laminated structure based on these feasible ranges, without affecting the layout design of the die area in the laminated structure, effectively reducing design costs, and providing a design basis for further miniaturization or changes to the laminated structure in the future. [Brief explanation of the drawing]

[0007] [Figure 1] This is a flowchart illustrating a method for designing a bonding layer in a laminated structure according to one embodiment of the present invention. [Figure 2] This is a schematic cross-sectional view of a first laminated structure according to one embodiment of the present invention. [Figure 3] This is a schematic cross-sectional view of a bonding test area according to one embodiment of the present invention. [Figure 4] Figure 2 is a schematic top view of the bonding interface of the first wafer in the first stacked structure. [Figure 5] Figure 2 is a schematic top view of the bonding interface of the second wafer in the first stacked structure. [Figure 6A] This is a schematic top view of one embodiment of a bonding pad. [Figure 6B] This is a schematic top view of another embodiment of the bonding pad. [Figure 6C] This is a schematic top view of another embodiment of the bonding pad. [Figure 7] This diagram shows the relationship between the pitch and shape of bonding pads and their resistance values. [Figure 8] This is a schematic cross-sectional view of a bonding test area according to another embodiment of the present invention. [Figure 9]This diagram shows the relationship between the bonding offset and the bonding pad pitch. [Figure 10] This diagram shows the relationship between bonding temperature and bonding pad pitch. [Figure 11] This is a schematic cross-sectional view of a bonding test area according to another embodiment of the present invention. [Figure 12] This is a diagram showing the relationship between the number of wafer stacks and the resistance value. [Modes for carrying out the invention]

[0008] Referring to Figures 1 to 5, Figure 2 schematically illustrates the bonding of the bonding layer 110 of the first wafer W1 and the bonding layer 210 of the second wafer W2, but only shows the locations of the die area DR, dicing line SL, and bonding test area TR, and omits the illustration of other components. The design method S10 for the bonding layer of the laminated structure includes the following steps. First, a first laminated structure 10 is provided in block S100. The first laminated structure 10 is made by stacking and bonding a plurality of wafers (for example, a first wafer W1 and a second wafer W2). In some embodiments, as shown in Figures 2 to 4, the first wafer W1 includes a substrate 100, a bonding layer 110, and an internal wiring structure 120, the bonding layer 110 is provided on the substrate 100, and the internal wiring structure 120 is provided between the substrate 100 and the bonding layer 110. Similarly, the second wafer W2 includes a substrate 200, a bonding layer 210, and an internal wiring structure 220, wherein the bonding layer 210 is provided on the substrate 200, and the internal wiring structure 220 is provided between the substrate 200 and the bonding layer 210. The bonding layer 110 of the first wafer W1 and the bonding layer 210 of the second wafer are provided face-to-face, and the first stacked structure 10 is formed by hybrid bonding. In some embodiments, the first wafer W1 may be a base wafer, an interposer, or a memory wafer, and the second wafer W2 may be a memory wafer.

[0009] In some embodiments, the substrates 100, 200 may include semiconductor materials such as silicon, germanium, silicon carbide, gallium arsenide, gallium nitride, or other suitable materials. In some embodiments, devices (not shown) such as active elements, passive elements, or other suitable devices may be provided in or on the substrates 100, 200. The internal wiring structure 120 may include a plurality of alternately stacked conductive layers 122 and dielectric layers 124, providing the internal circuit layout of the first wafer W1. The internal wiring structure 220 may include a plurality of alternately stacked conductive layers 222 and dielectric layers 224, providing the internal circuit layout of the second wafer W2.

[0010] In some embodiments, the bonding layer 110 may include a plurality of bonding pads 112, a plurality of bonding vias 114, and a bonding dielectric layer 116. The plurality of bonding pads 112 and the plurality of bonding vias 114 are provided in the bonding dielectric layer 116. The bonding vias 114 are provided between the bonding pads 112 and the internal wiring structure 120, and electrically connect the bonding pads 112 and the conductive layer 122 of the internal wiring structure 120. On the other hand, the bonding layer 210 may include a plurality of bonding pads 212, a plurality of bonding vias 214, and a bonding dielectric layer 216. The plurality of bonding pads 212 and the plurality of bonding vias 214 are provided in the bonding dielectric layer 216. The bonding vias 214 are provided between the bonding pads 212 and the internal wiring structure 220, and electrically connect the bonding pads 212 and the conductive layer 222 of the internal wiring structure 220.

[0011] In some embodiments, a plurality of bonding pads 112 of the first wafer W1 may be metal-to-metal bonded with a plurality of corresponding bonding pads 212 of the second wafer W2, and a bonding dielectric layer 116 of the first wafer W1 may be dielectric layer-to-dielectric layer bonded with a bonding dielectric layer 216 of the second wafer W2, and a bonding structure may be formed between the interface of the first wafer W1 and the second wafer W2. The first wafer W1 and the second wafer W2 may be electrically connected to each other via the bonding pads 112 and 212 to form a first laminated structure 10. In this embodiment, the bonding process between the first wafer W1 and the second wafer W2 is carried out under preset process conditions.

[0012] In some embodiments, the materials of conductive layer 122 and conductive layer 222, bonding pad 112 and bonding pad 212, and bonding via 114 and bonding via 214 may include copper, aluminum, gold, tungsten, silver, platinum, titanium, tantalum, alloys thereof, or other suitable conductive materials. In some embodiments, the materials of dielectric layer 124 and dielectric layer 224, and bonding dielectric layer 116 and bonding dielectric layer 216 may include silicon oxide, polyimide, or other suitable dielectric materials.

[0013] In some embodiments, as shown in Figure 4, the first wafer W1 may include a plurality of first die regions DR1, a plurality of bonding test regions TR1, and a first dicing line SL1. The plurality of first die regions DR1 are arranged in an array, and the first dicing line SL1 separates the plurality of first die regions DR1. The first dicing line SL1 may include a plurality of dicing lines extending along the x-direction and arranged in the y-direction, and a plurality of dicing lines extending along the y-direction and arranged in the x-direction. The plurality of bonding test regions TR1 are located within the first dicing line SL1 to provide bonding pads 112 with different design parameters for subsequent bonding tests. For example, the plurality of bonding test regions TR1 may include bonding test regions TR1a, TR1b, TR1c, TR1d, TR1e, and TR1f. In some embodiments, the bonding test areas TR1a, TR1b, and TR1c are arranged in one first dicing line SL1 extending along the x-direction, and the bonding test areas TR1d, TR1e, and TR1f are arranged in another first dicing line SL1 extending along the x-direction. However, the present invention is not limited thereto, and the bonding test areas TR1a, TR1b, TR1c, TR1d, TR1e, and TR1f may be provided in any first dicing line SL1, and the number of bonding test areas may be adjusted according to actual requirements.

[0014] In some embodiments, multiple bonding pads 112 may be located within multiple first die regions DR1 and multiple bonding test regions TR1. For convenience of distinction, bonding pads 112 located within multiple first die regions DR1 will be referred to as bonding pads 112a, and bonding pads 112 located within multiple bonding test regions TR1 will be referred to as bonding pads 112b.

[0015] The bonding pads 112a located in the plurality of first die regions DR1 have preset design parameters at the initial design stage, and the bonding pads 112b located in the plurality of bonding test regions TR1 each include different design parameters. The design parameters of the bonding pads may include parameters such as the shape, size, pitch, etc. of the bonding pads. For example, the shapes of the bonding pads 112b in the bonding test regions TR1a, TR1b, and TR1c are all circular, but the size (e.g., diameter) and / or pitch of the bonding pads 112 in the bonding test region TR1a are smaller than the size (e.g., diameter) and / or pitch of the bonding pads 112 in the bonding test region TR1b, and the size (e.g., diameter) and / or pitch of the bonding pads 112 in the bonding test region TR1b are smaller than the size (e.g., diameter) and / or pitch of the bonding pads 112 in the bonding test region TR1c. On the other hand, the shapes of the bonding pads 112b in the bonding test regions TR1d, TR1e, and TR1f are all rounded squares, but the size (e.g., length and / or width) and / or pitch of the bonding pads 112b in the bonding test region TR1d are smaller than the size (e.g., length and / or width) and / or pitch of the bonding pads 112b in the bonding test region TR1e, and the size (e.g., length and / or width) and / or pitch of the bonding pads 112b in the bonding test region TR1e are smaller than the size (e.g., length and / or width) and / or pitch of the bonding pads 112b in the bonding test region TR1f. Thus, the bonding pads 112b having different design parameters may be provided in different bonding test regions TR1 respectively.

[0016] The bonding pads in Figures 6A to 6C may be bonding pads of the first wafer W1 or the second wafer W2. In some embodiments, the shape (in top view) of the bonding pad 112b of the bonding test area TR1 may be circular (shown in Figure 6A), elliptical, square (shown in Figure 6B), rectangular, rounded square (shown in Figure 6C), rounded rectangle, triangular, hexagonal, octagonal, or other shapes. In some embodiments, the size d1 (e.g., width measured in the x direction, length measured in the y direction, or diameter of the circle) of the bonding pad 112b of the bonding test area TR1 may be between 0.5 μm and 5 μm. In some embodiments, the pitch d2 of the bonding pad 112b of the bonding test area TR1 refers to the distance between the centers of two adjacent bonding pads 112, and the pitch d2 may be between 2 μm and 15 μm. In some embodiments, the ratio of the size d1 of the bonding pad 112b to the distance d3 of the bonding dielectric layer 116 between two adjacent bonding pads 112b (i.e., d1 / d3) < 0.4 can contribute to improving the bonding strength.

[0017] Similarly, as shown in FIG. 5, the second wafer W2 may include a plurality of second die regions DR2, a plurality of bonding test regions TR2, and a second dicing line SL2, which respectively correspond to the first die region DR1, the plurality of bonding test regions TR1, and the first dicing line SL1 of the first wafer W1. The plurality of second die regions DR2 are arranged in an array with respect to each other, and the second dicing line SL2 separates the plurality of second die regions DR2. The second dicing line SL2 may include a plurality of dicing lines extending along the x direction and arranged in the y direction, and a plurality of dicing lines extending along the y direction and arranged in the x direction. By positioning the plurality of bonding test regions TR2 in the second dicing line SL2, bonding pads 212 having different design parameters are provided to perform subsequent bonding tests. For example, the plurality of bonding test regions TR2 may include bonding test regions TR2a, TR2b, TR2c, TR2d, TR2e, and TR2f, which respectively correspond to the bonding test regions TR1a, TR1b, TR1c, TR1d, TR1e, and TR1f of the first wafer W1. In some embodiments, the bonding test regions TR2a, TR2b, and TR, are arranged in one second dicing line SL2 extending along the x direction, and the bonding test regions TR2d, TR2e, and TR2f are arranged in another second dicing line SL2 extending along the x direction. However, the present invention is not limited thereto, and the bonding test regions TR2a, TR2b, TR2c, TR2d, TR2e, and TR2f may be provided in any second dicing line SL2, and the number of the bonding test regions TR2 may be adjusted according to actual requirements. However, the positions and the number of the plurality of bonding test regions TR2 need to correspond to the positions and the number of the plurality of bonding test regions TR1.

[0018] In some embodiments, the plurality of bonding pads 212 may be located in the plurality of second die regions DR2 and the plurality of bonding test regions TR2. For the sake of convenience of distinction, here, the bonding pads 212 located in the plurality of second die regions DR2 are referred to as bonding pads 212a, and the bonding pads 212 located in the plurality of bonding test regions TR2 are referred to as bonding pads 212b.

[0019] Bonding pads 212a located in multiple second die regions DR2 have design parameters set in advance during the initial design phase, and bonding pads 212b located in multiple bonding test regions TR2 each include different design parameters and correspond to bonding pads 112b in multiple bonding test regions TR1, thereby facilitating bonding with bonding pads 112b in multiple bonding test regions TR1. For example, the shape, size, and pitch of the bonding pads 212b in bonding test areas TR2a, TR2b, and TR2c are basically the same as the shape, size, and pitch of the bonding pads 112b in the corresponding bonding test areas TR1a, TR1b, and TR1c. Therefore, the shape of the bonding pads 212b in bonding test areas TR2a, TR2b, and TR2c is all circular, the size (e.g., diameter) and / or pitch of the bonding pad 212 in bonding test area TR2a is smaller than the size (e.g., diameter) and / or pitch of the bonding pad 212 in bonding test area TR2b, and the size (e.g., diameter) and / or pitch of the bonding pad 212 in bonding test area TR2b is smaller than the size (e.g., diameter) and / or pitch of the bonding pad 212 in bonding test area TR2c. On the other hand, the shape, size, and pitch of the bonding pads 212b in bonding test areas TR2d, TR2e, and TR2f are basically the same as the shape, size, and pitch of the bonding pads 112b in the corresponding bonding test areas TR1d, TR1e, and TR1f. Therefore, the shape of the bonding pads 212b in bonding test areas TR2d, TR2e, and TR2f is all a rounded square. The size (e.g., length and / or width) and / or pitch of the bonding pad 212b in bonding test area TR2d is smaller than the size (e.g., diameter) and / or pitch of the bonding pad 212b in bonding test area TR2e, and the size (e.g., length and / or width) and / or pitch of the bonding pad 212b in bonding test area TR2e is smaller than the size (e.g., diameter) and / or pitch of the bonding pad 212b in bonding test area TR2f. Thus, bonding pads 212b with different design parameters may be provided in different bonding test areas TR2.

[0020] In some embodiments, a plurality of second die regions DR2 of the second wafer W2 correspond to a plurality of first die regions DR1 of the first wafer W1, and the bonding pads 212a of the plurality of second die regions DR2 are bonded to the bonding pads 112a of the plurality of first die regions DR1 to constitute a plurality of die regions DR of the first stacked structure 10. The second dicing line SL2 of the second wafer W2 corresponds to the first dicing line SL1 of the first wafer W1, and together they constitute a dicing line SL of the first stacked structure 10. A plurality of bonding test regions TR2 of the second wafer W2 correspond to a plurality of bonding test regions TR1 of the first wafer W1, and the bonding pads 212b of the plurality of bonding test regions TR2 are bonded to the bonding pads 112b of the plurality of bonding test regions TR1 to constitute a plurality of bonding test regions TR of the first stacked structure 10. That is, the first stacked structure 10 includes a plurality of die regions DR, a plurality of bonding test regions TR, and a dicing line SL. Multiple die regions DR are arranged in an array and separated by a dicing line SL, and multiple bonding test regions TR are located within the dicing line SL.

[0021] In some embodiments, multiple bonding test regions TR of the first laminated structure 10 each include a test circuit C1 (shown by dashed lines in Figure 3, with arrows indicating external connections used for electrical characteristic measurement), and the test circuit C1 extends between the first wafer W1 and the second wafer W2. In some embodiments, the test circuit C1 is a daisy-chain circuit, with half of the circuit in the first wafer W1 and the other half in the second wafer W2. Thus, the test circuit C1 includes multiple conductive bonding structures, each formed by bonding pads 112b located in the bonding test region TR1 of the first wafer W1 and bonding pads 212b located in the bonding test region TR2 of the second wafer W2 being bonded to each other. The multiple conductive bonding structures may be connected to each other via bonding vias 114 and conductive layer 122 and bonding vias 214 and conductive layer 222 to constitute the test circuit C1.

[0022] Referring to Figure 1, in block S110, electrical characteristic measurements are performed on each of the test circuits C1 of the multiple bonding test areas TR of the first laminated structure 10, such as measuring resistance or other electrical characteristics.

[0023] Referring to Figure 1, in block S120, the feasible design parameter range of the bonding pads 112 and 212 of the first laminated structure 10 is determined based on the results of the electrical characteristic measurement. In some embodiments, a relationship diagram may be created between the measured resistance value and the corresponding design parameters of the bonding pads 112b and 212b to determine the feasible design parameter range of the bonding pads 112b and 212b. For example, as shown in Figure 7, a relationship diagram may be created between the pitch and shape of the bonding pads and the resistance value. As can be seen from Figure 7, when the bonding pads 112b and 212b are square, the resistance value of the test circuit C1 is greater than the target range when the pitch of the bonding pads 112b and 212b is less than approximately 5 μm, and the resistance value of the test circuit C1 falls within the target range when the pitch of the bonding pads 112b and 212b is approximately 5 μm or more. When bonding pads 112b and 212b are square, it can be seen that the feasible pitch range for bonding pads 112b and 212b is approximately 5 μm or more. When bonding pads 112b and 212b are square with rounded corners, when the pitch of bonding pads 112 and 212 is less than approximately 6 μm, the resistance value of test circuit C1 is greater than the target range, and when the pitch of bonding pads 112b and 212b is approximately 6 μm or more, the resistance value of test circuit C1 falls within the target range. When bonding pads 112b and 212b are square with rounded corners, it can be seen that the feasible pitch range for bonding pads 112b and 212b is approximately 6 μm or more. When bonding pads 112b and 212b are circular, the resistance value of test circuit C1 is greater than the target range when the pitch of bonding pads 112b and 212b is less than approximately 10 μm, and the resistance value of test circuit C1 falls within the target range when the pitch of bonding pads 112b and 212b is approximately 10 μm or more. It can be seen that when bonding pads 112b and 212b are circular, the feasible pitch range for bonding pads 112b and 212b is approximately 10 μm or more. The above example is intended to clearly illustrate a method for determining the feasible pitch range of bonding pads 112b and 212b based on the results of electrical characteristic measurements, and is not intended to limit the present invention.It should be understood that the numerical range of pitch described above is for illustrative purposes only and does not limit the present invention. Here, the target range of resistance may be ±5% to ±10% of the target value Ro, and the target value Ro may be set to an appropriate value based on different applications, but the present invention is not limited thereto. The target range of resistance may be set as an upper and lower limit based on the set specification (spec). Similarly, by creating a relationship diagram between the size and shape of the bonding pad and the resistance value, a feasible size range for bonding pads 112b, 212b having different shapes may be obtained.

[0024] In some embodiments, the feasible design parameter range of the bonding pads 112a and 212a located in the die region DR of the current first laminated structure 10 may be used to determine whether the design parameters of the bonding pads 112a and 212a located in the die region DR of the current first laminated structure 10 conform to the feasible design parameter range. If the design parameters of the bonding pads 112a and 212a in the die region DR are within the feasible design parameter range, it indicates that the design parameters of the bonding pads 112a and 212a in the current die region DR are feasible. If the design parameters of the bonding pads 112a and 212a in the die region DR are outside the feasible design parameter range, the design parameters of the bonding pads 112a and 212a in the current die region DR can be modified based on the obtained feasible design parameter range of the bonding pads 112b and 212b. Since the bonding test area of ​​the first stacked structure 10 is located in the dicing line SL rather than in the die region DR, it is only necessary to modify the mask design of the bonding layer 110 of the first wafer W1 and the bonding layer 120 of the second wafer W2 based on the feasible design parameter range obtained above. This does not affect the internal design of the die region DR, and the overall design cost can be reduced.

[0025] In some embodiments, based on current process conditions and industry demands (e.g., input / output (I / O) count, cost considerations, space considerations, process capability, etc.), an optimized design parameter combination for the bonding pads 112a, 212a of the die region DR of the first laminated structure 10 can be obtained through a feasible design parameter range for the bonding pads 112b, 212b. Here, the optimized design parameter combination may refer to a combination of design parameters that can maximize the number of I / O bonds, is the easiest to manufacture, or can satisfy other process objectives.

[0026] Referring to Figure 1, block S130 provides a plurality of second stacked structures 20, which are formed by performing a bonding process under different process conditions. Each of the plurality of second stacked structures 20 is formed by stacking and bonding a plurality of wafers (for example, a third wafer W3 and a fourth wafer W4). The third wafer W3 has the same structure as the first wafer W1 described above, and the fourth wafer W4 has the same structure as the second wafer W2 described above, so they will not be described in detail here.

[0027] In some embodiments, the process conditions of the bonding process may include bonding temperature, bonding accuracy (or bonding offset amount), high-frequency power used for surface treatment processes of bonding pads before bonding, or other process parameters. As shown in Figure 8, the third wafer W3 and the fourth wafer W4 of a plurality of second stacked structures 20 may be offset during bonding, and the bonding pad 112 of the third wafer W3 (including a bonding pad 112a located in the first die region DR1 and a bonding pad 112b located in a plurality of bonding test regions TR1) and the corresponding bonding pad 212 of the fourth wafer W4 (including a bonding pad 212a located in the second die region DR2 and a bonding pad 212b located in a plurality of bonding test regions TR2) are offset by a distance s1 (i.e., bonding offset amount) in the horizontal direction (e.g., x or y direction). In some embodiments, the bonding offset amount may be in the range of 0 to 10% of the size of the bonding pads 112, 212. In some embodiments, the range of the bonding offset amount is limited to the specified range of resistance values. In some embodiments, each of the multiple second stacked structures 20 is formed by bonding a third wafer W3 and a fourth wafer W4 under different bonding temperatures. In some embodiments, each of the multiple second stacked structures 20 is formed by bonding a third wafer W3 and a fourth wafer W4 under different surface treatment conditions.

[0028] Referring to Figure 1, in block S140, electrical characteristic measurements are performed on each of the test circuits C1 of the multiple bonding test areas TR of the multiple second laminated structures 20, such as measuring resistance or other electrical characteristics.

[0029] Referring to Figure 1, in block S150, the process window of the bonding process that forms the first laminated structure 10 is determined by the results of measuring the electrical characteristics of multiple second laminated structures 20. In some embodiments, the process window of a process parameter may be determined by creating a relationship diagram between the measured resistance value and the corresponding process parameter. As an example, in Figure 9, a relationship diagram between the bonding offset amount and the bonding pad pitch may be created under conditions where some of the bonding pad design parameters and bonding process parameters are fixed. In Figure 9, the shaded area is the area where the measured resistance value is within the target range, meaning that bonding pads 112 and 212 having pitches within the shaded area may be allowed to have an offset within the corresponding bonding offset amount range. As an example, in Figure 10, a relationship diagram between the bonding temperature and the bonding pad pitch may be created under conditions where some of the bonding pad design parameters and bonding process parameters are fixed. In Figure 10, the shaded area represents the region where the measured resistance value is within the target range; that is, bonding pads 112 and 212 having pitches within this shaded area may be allowed to be bonded within the corresponding bonding temperature range. The above example is intended to clearly illustrate a method for determining the process window of the bonding process based on the results of electrical characteristic measurements and does not limit the present invention. It should be understood that the numerical ranges for pitch, bonding offset amount, and bonding temperature described above are illustrative and do not limit the present invention. Similarly, diagrams relating design parameters, bonding process parameters, and resistance values ​​for other bonding pads may also be created, thereby obtaining the process window for each bonding process parameter.

[0030] In some embodiments, the combination of bonding process parameters for the first laminated structure 10 can be optimized through a process window of bonding process parameters obtained by testing multiple second laminated structures 20 based on current process conditions and industry demands (e.g., input / output (I / O) count, cost considerations, space considerations, process capability, etc.).

[0031] Referring to Figure 1, block S160 provides a plurality of third stacked structures 30, each of which is made up of a different number of stacked wafers. As shown in Figure 11, each of the plurality of third stacked structures 30 includes a bottom wafer WB, a top wafer WT, and at least one intermediate wafer WM. The at least one intermediate wafer WM is provided between the bottom wafer WB and the top wafer WT. The bottom wafer WB may have the same structure as the first wafer W1 described above, for example, and the top wafer WT may have the same structure as the second wafer W2 described above, for example, and will not be described in detail here. The intermediate wafer WM may be a memory wafer, for example, similar to the second wafer W2 described above, but bonding pads 312 and 314 are provided on both of the two opposing surfaces of the intermediate wafer WM, so that they are bonded in correspondence with the bonding pads of the wafers provided above and below them. For clarity, Figure 11 only schematically illustrates the connections between bonding pads (including bonding pads 312, 314, 112, and 212) of adjacent wafers in the bonding test area TR and the test circuit C1, omitting the illustration of other components inside each wafer. Furthermore, in the bonding test area TR of the third stacked structure 30, the intermediate wafer WM further includes a conductive connecting member 316 located between bonding pads 312 and 314, thereby electrically connecting bonding pads 312 and 314 and forming part of the test circuit C1. In Figure 11, the conductive connecting member 316 is schematically represented by a conductive column, but this does not limit the present invention, and the conductive connecting member 316 may be any structure capable of electrically connecting adjacent and corresponding bonding pads 312 and 314. Although three intermediate wafers WM are schematically shown in Figure 11, this does not limit the present invention, and each of the multiple third stacked structures 30 may include 1 to 10 or more intermediate wafers WM.

[0032] Referring to Figure 1, in block S170, electrical characteristic measurements are performed on each of the test circuits C1 of the multiple bonding test areas TR of the multiple third laminated structures 30, such as measuring resistance or other electrical characteristics.

[0033] Referring to Figure 1, in block S180, the number of wafers that can be stacked in the first stacked structure 10 is determined by the results of electrical characteristic measurements of multiple third stacked structures 30. In some embodiments, the number of wafers that can be stacked in the first stacked structure 10 may be determined by creating a relationship diagram between the measured resistance value and the corresponding number of wafers. As an example, Figure 12 may be used to create a relationship diagram between the number of stacked wafers and the resistance value under the condition that the bonding pad design parameters and bonding process parameters are fixed. In Figure 12, when the number of stacked wafers is 1 to 5, the measured resistance value is within the target range. When the number of stacked wafers exceeds 5, the measured resistance value is outside the target range. As can be seen from this, under the condition that the bonding pad design parameters and bonding process parameters are fixed, the first stacked structure 10 can stack a maximum of 5 layers of wafers. The above example is intended to clearly explain how to determine the number of wafers that can be stacked in the first stacked structure 10 based on the results of electrical characteristic measurements of multiple third stacked structures 30, and is not intended to limit the present invention. Please understand that the numerical range for the number of wafer stacks mentioned above is for illustrative purposes only and is not intended to limit the present invention.

[0034] In this way, the feasibility of the first stacked structure 10 including different numbers of stacked wafers can be estimated through the electrical characteristic test results of the third stacked structure 30, and corresponding design modifications can be made early. For example, if it is desired that the first stacked structure 10 include stacked wafers exceeding the number of stackable wafers mentioned above, the resistance can be reduced and the number of stacked wafers increased by reducing the height of the bonding layer (including bonding pads and / or bonding vias) of each wafer, or by increasing the pitch of the bonding pads.

[0035] In summary, the laminated structure of the present invention, by providing multiple bonding test areas in the dicing line, allows for the determination of the feasible range of bonding pad design parameters, bonding process parameters, and chip stacking number by performing electrical characteristic measurements on the test circuits of the multiple bonding test areas. Furthermore, based on these feasible ranges obtained, adjustments can be made to the design of the bonding layer in the laminated structure, effectively reducing design costs without affecting the layout design of the die area in the laminated structure, and providing a design basis for further miniaturization or changes to the laminated structure in the future.

[0036] Although the present invention has been disclosed above by embodiments, these embodiments are not intended to limit the invention, and those skilled in the art can make some changes and modifications without departing from the spirit and scope of the invention, and therefore the scope of protection of the present invention shall be based on the appended claims. [Industrial applicability]

[0037] The laminated structure and the method for designing its bonding layer according to the present invention are applicable to the chip design domain for high-efficiency computing. [Explanation of Symbols]

[0038] 10:First laminated structure 20:Second laminated structure 30:Third layered structure 100, 200: Circuit board 110, 210: Bonding layer 112, 112a, 112b, 212, 212a, 212b, 312, 314: Bonding pads 114, 214: Joint vias 116, 216: Junction dielectric layer 120, 220: Internal wiring structure 122, 222: Conductive layer 124, 224: Dielectric layer 316: Conductive connecting member C1: Test circuit DR: Die Area DR1: First die region DR2: Second die area Ro: Target value S10:Design method S100, S110, S120, S130, S140, S150, S160, S170, S180: Block SL: Dicing Line SL1: First dicing line SL2: Second dicing line TR, TR1, TR1a, TR1b, TR1c, TR1d, TR1e, TR1f, TR2, TR2a, TR2b, TR2c, TR2d, TR2e, TR2f: Bonding test area W1: First wafer W2: Second wafer W3: Third wafer W4: 4th wafer WB: Bottom wafer WT: Top wafer WM: Intermediate wafer d1: Size d2: pitch d3, s1: distance x, y, z: direction

Claims

1. The present invention provides a first stacked structure, wherein the first stacked structure is formed by stacking and bonding a plurality of wafers, the first stacked structure comprises a plurality of die regions, a plurality of bonding test regions, and a dicing line, the dicing line separating the plurality of die regions, and the plurality of bonding test regions located within the dicing line, each of the plurality of bonding test regions of the first stacked structure includes a test circuit, the test circuit of the first stacked structure includes a conductive bonding structure formed by bonding the bonding pads of the plurality of wafers to each other, and the plurality of wafers of the first stacked structure have different design parameters for the bonding pads in each of the plurality of bonding test regions. To perform electrical characteristic measurements on each of the test circuits in the plurality of bonding test regions of the first laminated structure, Based on the results of the electrical characteristic measurement, the feasible design parameter range of the bonding pads in the plurality of die regions of the first laminated structure is determined. including, Design method for bonding layers in laminated structures.

2. The design parameters of the bonding pad include shape, size, and / or pitch. A method for designing the bonding layer of a laminated structure according to claim 1.

3. The first layered structure is, Multiple first die regions, A first dicing line that separates the plurality of first die regions, A plurality of first bonding test regions, each located within the first dicing line and including a first region containing a plurality of first bonding pads and a second region containing a plurality of second bonding pads. including, The first wafer and Multiple second die regions, A second dicing line separates the plurality of second chip regions, A plurality of second bonding test regions, each located within the second dicing line and including a third region containing a plurality of third bonding pads and a fourth region containing a plurality of fourth bonding pads. including, Second wafer and Includes, The bonding pads in the plurality of second die regions of the second wafer are bonded to the corresponding bonding pads in the plurality of first die regions of the first wafer, the plurality of third bonding pads in the third region of the second wafer are bonded to the plurality of first bonding pads in the first region of the first wafer to form a first test circuit, and the plurality of fourth bonding pads in the fourth region of the second wafer are bonded to the plurality of second bonding pads in the second region of the first wafer to form a second test circuit. A method for designing the bonding layer of a laminated structure according to claim 1.

4. The plurality of first bonding pads and the plurality of third bonding pads have basically the same shape, size, and pitch, and the plurality of second bonding pads and the plurality of fourth bonding pads have basically the same shape, size, and pitch. A method for designing the bonding layer of a laminated structure according to claim 3.

5. The first test circuit extends between the first region of the first wafer and the third region of the second wafer, and the second test circuit extends between the second region of the first wafer and the fourth region of the second wafer. A method for designing the bonding layer of a laminated structure according to claim 3.

6. If the electrical characteristics of the first test circuit are within the target range, the design parameters of the plurality of first bonding pads or the plurality of third bonding pads are applied to the bonding pads in the plurality of first die regions or the plurality of second die regions. A method for designing the bonding layer of a laminated structure according to claim 3.

7. The aforementioned second bonding test area is, A second conductive layer is provided on the plurality of third bonding pads, A second conductive via is provided between the second conductive layer and the plurality of third bonding pads, and electrically connects the second conductive layer and the plurality of third bonding pads. It further includes, The first bonding test area is, A first conductive layer is provided on the plurality of first bonding pads, A first conductive via is provided between the first conductive layer and the plurality of first bonding pads, and electrically connects the first conductive layer and the plurality of first bonding pads. It further includes, The first test circuit is composed of the first conductive layer, the first conductive via, the plurality of first bonding pads, the plurality of second bonding pads, the second conductive via, and the second conductive layer. A method for designing the bonding layer of a laminated structure according to claim 3.

8. The present invention provides a plurality of second stacked structures, each of which is formed by stacking and bonding a third wafer and a fourth wafer, and the plurality of second stacked structures are formed by performing bonding processes under different process conditions. To perform electrical characteristic measurements on each of the test circuits of the multiple bonding test regions of the multiple second laminated structures, The process window of the bonding process for the first laminated structure is determined based on the results of the electrical characteristic measurement of the plurality of second laminated structures. This also includes, A method for designing the bonding layer of a laminated structure according to claim 1.

9. The process conditions include bonding temperature, bonding offset amount, and pre-treatment high-frequency power applied to the bonding pad surface. A method for designing a bonding layer in a laminated structure according to claim 8.

10. The present invention provides a plurality of third stacked structures, wherein each of the plurality of third stacked structures is formed by stacking and bonding a different number of wafers. To perform electrical characteristic measurements on each of the test circuits of the multiple bonding test regions of the multiple third laminated structures, The number of wafers that the first stacked structure can stack is determined based on the results of the electrical characteristic measurements of the plurality of third stacked structures. This also includes, A method for designing the bonding layer of a laminated structure according to claim 1.

11. Multiple first die regions, A first dicing line that separates the plurality of first die regions, A plurality of first bonding test regions, each located within the first dicing line and including a first region containing a plurality of first bonding pads and a second region containing a plurality of second bonding pads. including, The first wafer and Multiple second die regions, A second dicing line separates the plurality of second chip regions, A plurality of second bonding test regions, each located within the second dicing line and including a third region containing a plurality of third bonding pads and a fourth region containing a plurality of fourth bonding pads. including, Second wafer and Includes, The bonding pads in the plurality of second die regions of the second wafer are in direct contact with the corresponding bonding pads in the plurality of first die regions of the first wafer, the plurality of third bonding pads in the third region of the second wafer are in direct contact with the plurality of first bonding pads in the first region of the first wafer, and the plurality of fourth bonding pads in the fourth region of the second wafer are in direct contact with the plurality of second bonding pads in the second region of the first wafer. Laminated structure.

12. The shapes of the plurality of first bonding pads and the plurality of second bonding pads are different. The laminated structure according to claim 11.

13. The sizes of the plurality of first bonding pads and the sizes of the plurality of second bonding pads are different. The laminated structure according to claim 11.

14. The pitch of the plurality of first bonding pads and the pitch of the plurality of second bonding pads are different. The laminated structure according to claim 11.

15. A first test circuit extending between the first region of the first wafer and the third region of the second wafer, A second test circuit extending between the second region of the first wafer and the fourth region of the second wafer, This also includes, The laminated structure according to claim 11.

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