Integrated circuit device including a buffer circuit and method of operating the integrated circuit device

Abstract

This invention provides a technology for stably changing the settings of a buffer circuit during the process of changing the operating frequency of an integrated circuit device. [Solution] The integrated circuit device according to the present invention includes one or more input terminals, a buffer setting storage circuit that acquires and stores buffer setting information in response to a clock synchronization status signal, and one or more buffer circuits that are set based on the buffer setting information stored in the buffer setting storage circuit and receive signals from one or more input terminals.

Description

Technical Field

[0001] The present invention relates to an integrated circuit device including a buffer circuit.

Background Art

[0002] Various integrated circuit devices operate in synchronization with a clock and can support operations at various frequencies. Memory devices also operate in synchronization with a clock, but not only is the frequency of the clock fixed, but also the frequency of the clock may be changed during operation for performance improvement or power consumption reduction.

Summary of the Invention

Problems to be Solved by the Invention

[0003] An object of the present invention is to provide a technique for stably changing the setting of a buffer circuit in the process of changing the operating frequency of an integrated circuit device.

Means for Solving the Problems

[0004] An integrated circuit device according to an embodiment of the present invention can include one or more input terminals, a buffer setting storage circuit that takes in and stores buffer setting information in response to a clock synchronization status signal, and one or more buffer circuits that are set based on the buffer setting information stored in the buffer setting storage circuit and receive signals from the one or more input terminals.

[0005] The buffer setting storage circuit can take in and store the buffer setting information in response to the transition of the clock synchronization status signal from the sink-on state to the sink-off state.

[0006] An operating method for an integrated circuit device according to one embodiment of the present invention may include the steps of: changing clock frequency setting information; decoding the clock frequency setting information to generate buffer setting information; transitioning from a clock sync-on state to a clock sync-off state; and applying the buffer setting information to one or more buffer circuits in response to the transition.

[0007] The integrated circuit device is a memory device, the one or more buffer circuits are buffer circuits for receiving one or more command address signals, and the method may further include the steps of transitioning from the clock sync-off state to the clock sync-on state, generating a sync-on internal clock by dividing the input clock frequency, receiving one or more command address signals synchronized with the sync-on internal clock by the one or more buffer circuits, and decoding the one or more command address signals. [Effects of the Invention]

[0008] According to the present invention, the settings of the buffer circuit during the process of changing the operating frequency of an integrated circuit device can be stably changed. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a diagram showing the configuration of a memory device (100) according to one embodiment of the present invention. [Figure 2] Figure 2 is a configuration diagram showing an example of the internal clock generation circuit (180) shown in Figure 1. [Figure 3] Figure 3 is a timing diagram showing the operation of the internal clock generation circuit (180). [Figure 4] Figure 4 is a timing diagram showing the operation of the internal clock generation circuit (180). [Modes for carrying out the invention]

[0010] The embodiments of the present invention will be described below with reference to the attached drawings.

[0011] Figure 1 is a configuration diagram of a memory device 100 according to one embodiment of the present invention. Figure 1 shows the configuration for receiving control signals in the memory device 100.

[0012] Referring to Figure 1, the memory device 100 includes command address input terminals 101_0 to 101_N, chip selection signal input terminal 103, clock input terminal 105, command address buffer circuits 110_0 to 110_N, chip selection signal buffer circuit 113, clock buffer circuit 115, latch circuits 120_0 to 120_N, command decoder 130, mode register set circuit 140, setting decoder circuit 150, buffer setting storage circuit 160, synchronization state signal generation circuit 170, and internal clock generation circuit 180.

[0013] The command address buffer circuits 110_0 to 110_N receive the command address signal CA<0:N> transmitted to the command address input terminals 101_0 to 101_N. The command address buffer circuits 110_0 to 110_N are configured by the buffer setting information BUF_SET<0:k>, and the current usage and operating speed can be changed by the buffer setting information BUF_SET<0:k>.

[0014] The chip selection signal buffer circuit 113 receives the chip selection signal CS transmitted to the chip selection signal input terminal 103.

[0015] The clock buffer circuit 115 can receive the clock signals CLK_t and CLK_c transmitted to the clock input terminal 105. Since clock signals CLK_t and CLK_c are differential signals, the clock input terminal 105 can also have two terminals.

[0016] The internal clock generation circuit 180 generates a sync-on internal clock ICLK by dividing the clocks CLK_t and CLK_c received by the clock buffer circuit 115. A sync-on internal clock ICLK means an internal clock whose rising edge is synchronized with the input section of the chip selection signal CS. The internal clock generation circuit 180 can perform a sync-on operation using the chip selection signal CS, which is activated in the sync-off state, and generate a sync-on signal SYNC_ON to indicate that it has been sync-on. Details of the internal clock generation circuit 180 will be explained with reference to Figure 2.

[0017] The latch circuits 120_0 to 120_N store the command address signals received by the command address buffer circuits 110_0 to 110_N in synchronization with the internal clock ICLK. Each of the latch circuits 120_0 to 120_N may also be a D flip-flop.

[0018] The command decoder 130 decodes the command address signals and chip selection signals CS stored in the latch circuits 120_0 to 120_N, understands the operation instructed by the memory controller to the memory device 100, and generates signals corresponding to that operation. The active signal ACT can be a signal that instructs an active operation, the precharge signal PCG can be a signal that instructs a precharge operation, and the refresh signal REF can be a signal that instructs a refresh operation. The read signal RD can be a signal that instructs a read operation, and the write signal WR can be a signal that instructs a write operation. The clock sync off command SYNC_OFF_CMD is a signal that is activated when there is an instruction to turn off the clock sync, and the frequency change signal FSP_OP_CHANGE is a signal that is activated when there is an instruction to apply a setting value due to a frequency change. On the other hand, the command decoder 130 can control the setting of the mode register set circuit 140 based on the decoding result.

[0019] The mode register set circuit 140 can store various settings of the memory device 100 under the control of the command decoder 130. These various settings include various voltage levels required for operation, operating timing information, latency values, and operating frequency information.

[0020] The setting decoder circuit 150 generates buffer setting information BUF_SET_P<0:k> to operate the command address buffer circuits 110_0 to 110_N in the optimal state based on the frequency setting information FSP stored in the mode register set circuit 140. The frequency setting information is also called frequency set point information and contains the frequency information of the clocks CLK_t and CLK_c input to the memory device 100. The setting decoder circuit 150 can grasp the frequency information of the clock set based on the frequency setting information FSP and generate the optimal buffer setting information BUF_SET_P<0:k> according to that information. For example, each of the command address buffer circuits 110_0 to 110_N can be a differential amplifier that receives the input signal by comparing the level of the input signal with the level of a reference voltage, and the amount of current of the differential amplifier can be adjusted based on the buffer setting information BUF_SET_P<0:k>. Table 1 below summarizes the operation of the buffer setting information BUF_SET_P<0:k> based on the frequency setting information FSP and the command address buffer circuits 110_0~110_N. The buffer setting information BUF_SET_P<0:k> generated by the setting decoder circuit 150 is not immediately reflected in the command address buffer circuits 110_0~110_N, but is reflected in the command address buffer circuits 110_0~110_N via the buffer setting storage circuit 160. The symbol P is added to distinguish between the buffer setting information BUF_SET_P<0:k> generated by the setting decoder circuit 150 and the buffer setting information BUF_SET<0:k> output from the buffer setting storage circuit 160.

[0021]

Table 1

[0022] The buffer setting storage circuit 160 captures and stores the buffer setting information BUF_SET_P<0:k> generated by the setting decoder circuit 150 in response to the clock synchronization state signal SYNC_STATE. The clock synchronization state signal SYNC_STATE is a signal indicating whether it is in the clock sink-on state or the sink-off state. The buffer setting storage circuit 160 can capture and store the buffer setting information BUF_SET_P<0:k> in response to the transition of the clock synchronization state signal SYNC_STATE from the sink-on state to the sink-off state. The buffer setting storage circuit 160 can include D flip-flops. In the case of the clock sink-on state, the command address signal CA<0:N> is transmitted from the memory controller to the memory device 100. However, if the value of the buffer setting information BUF_SET<0:k> input to the command address buffer circuits 110_0 to 110_N changes in the clock sink-on state, it may cause malfunction due to sudden setting changes in the command address buffer circuits 110_0 to 110_N. Since the buffer setting storage circuit 160 captures and stores the buffer setting information BUF_SET_P<0:k> in response to the state change to the clock sink-off state, that is, the value of the buffer setting information BUF_SET<0:k> output from the buffer setting storage circuit 160 changes at this time, the stable operation of the command address buffer circuits 110_0 to 110_N can be ensured.

[0023] The synchronization state signal generation circuit 170 generates a clock synchronization state signal SYNC_STATE. The synchronization state signal generation circuit 170 can include an OR gate 171 and an SR latch 173. The OA gate activates the sink-off signal SYNC_OFF when one or more of the clock sink-off command SYNC_OFF_CMD and the frequency change signal FSP_OP_CHANGE are activated. When the clock sink-off command SYNC_OFF_CMD is activated, the clock synchronization is turned off, and when the frequency change signal FSP_OP_CHANGE is activated, the clock synchronization can also be turned off. The SR latch 173 can generate the clock synchronization state signal SYNC_STATE at a high level in response to the activation of the sink-off signal SYNC_OFF, and generate the clock synchronization state signal SYNC_STATE at a low level in response to the activation of the sink-on signal SYNC_ON. The high level of the clock synchronization state signal SYNC_STATE means the clock sink-off state, and the low level of the clock synchronization state signal SYNC_STATE can mean the clock sink-on state.

[0024] Figure 2 is a configuration diagram showing an example of the internal clock generation circuit 180 of FIG. 1.

[0025] Referring to FIG. 2, the internal clock generation circuit 180 includes a frequency divider 210, a selection circuit 220, and a phase detection circuit 230.

[0026] The frequency divider 210 generates a divided clock DIV_CLK and an inverted divided clock DIV_CLKB by dividing the clocks CLK_t and CLK_c received by the clock buffer circuit 115. The divided clock DIV_CLK can have a frequency that is 1 / 2 of the clocks CLK_t and CLK_c, and the inverted divided clock DIV_CLKB can be a clock obtained by inverting the divided clock DIV_CLK.

[0027] The selection circuit 220 responds to the detection signal DET by selecting and outputting either the divided clock DIV_CLK or the inverted divided clock DIV_CLKB as the sync-on internal clock ICLK.

[0028] The phase detection circuit 230 operates in the sync-off state, but it can determine whether or not it is in the sync-off state using the clock synchronization state signal SYNC_STATE. The phase detection circuit 230 can perform sync-on operation using the chip selection signal CS, which is activated in the sync-off state. The phase detection circuit 230 can determine which of the divided clock DIV_CLK and the inverted divided clock DIV_CLKB is synchronized with the chip selection signal CS, and can generate a detection signal DET indicating the result. Furthermore, it can activate the sync-on signal SYNC_ON, which indicates that sync-on has been performed.

[0029] Figures 3 and 4 are timing diagrams showing the operation of the internal clock generation circuit 180.

[0030] The operation shown in Figures 3 and 4 indicates that it starts in a sync-off state.

[0031] First, referring to Figure 3, we can see that the detection signal DET has been at a high level since before time 301, and that the frequency divider clock DIV_CLK is selected as the internal clock ICLK based on the level of the detection signal DET.

[0032] At time point 305, the chip selection signal CS is activated, but within the activation period of the chip selection signal CS, the rising edge of the frequency divider clock DIV_CLK precedes the rising edge of the inverted frequency divider clock DIV_CLKB. This means that the chip selection signal CS is synchronized with the rising edge of the frequency divider clock DIV_CLK, but not with the rising edge of the inverted frequency divider clock DIV_CLKB.

[0033] Since the divided clock DIV_CLK is the internal clock that has been set to sync-on, the detection signal DET remains at a high level, and the divided clock DIV_CLKB can be continuously selected as the internal clock ICLK. The internal clock generation circuit 180 can also activate the sync-on signal SYNC_ON, which indicates that the sync-on operation has been completed.

[0034] After sync-on, the chip selection signal CS and command address signal CA<0:N> can be input in synchronization with the internal clock ICLK.

[0035] Referring to Figure 4, it can be seen that the detection signal DET has been at a high level since before time 401, and that the frequency divider clock DIV_CLK is selected as the internal clock ICLK based on the level of the detection signal DET.

[0036] At time point 405, the chip selection signal CS is activated, but within the activation interval of the chip selection signal CS, the rising edge of the inverted divider clock DIV_CLKB precedes the rising edge of the divider clock DIV_CLK. This means that the chip selection signal CS is synchronized with the rising edge of the inverted divider clock DIV_CLKB, but not with the rising edge of the divider clock.

[0037] Since the inverted divided clock DIV_CLKB is the sync-on internal clock, the detection signal DET is changed from a high level to a low level, and from then on the inverted divided clock DIV_CLKB can be selected and output as the internal clock ICLK. The internal clock generation circuit 180 can also activate the sync-on signal SYNC_ON, which indicates that the sync-on operation is complete.

[0038] To reduce current consumption, the memory device 100 does not use the externally input clocks CLK_t and CLK_c directly, but instead uses a divided clock. Considering this, the memory controller does not apply the chip selection signal CS and command address signal CA<0:N> to the memory device 100 every clock cycle with respect to clocks CLK_t and CLK_c. Instead, it applies the chip selection signal CS and command address signal CA<0:N> once every two clock cycles with respect to clocks CLK_t and CLK_c. That is, the chip selection signal CS and command address signal CA<0:N> are applied in synchronization with the rising edge of the divided clock DIV_CLK, or with the rising edge of the inverted divided clock DIV_CLKB. The clock sync-on process is the operation of deciding which of the divided clocks DIV_CLK and the inverted divided clock DIV_CLKB to be selected as the sync-on internal clock and used as the clock for receiving the command address signal CA<0:N>.

[0039] Next, we will refer again to Figures 1 to 4 to explain the operation of the memory device 100.

[0040] (1) The first memory device 100 can operate while receiving the chip selection signal CS and the command address signal CA<0:N> using the internal clock DIV_CLK which is sync-on in the sync-on state.

[0041] (2) The clock frequency setting may be changed while the second memory device 100 is in operation. That is, the operating frequency setting of the mode register set circuit 140 may be changed by the control of the command decoder 130. Furthermore, the setting decoder circuit 150 can generate buffer setting information BUF_SET_P<0:k> based on the changed frequency setting information FSP of the mode register set circuit 1401.

[0042] (3) The third memory device 100 is changed from a sync-on state to a sync-off state, which allows the buffer setting information BUF_SET_P<0:k> to be input to and stored in the buffer setting storage circuit 160. This means that the buffer setting information BUF_SET_P<0:k> is applied to the command address buffer circuits 110_0 to 110_N.

[0043] (4) The fourth memory controller can change the frequencies of the clocks CLK_t and CLK_c applied to the memory device 100 and activate the chip selection signal CS for sync-on operation.

[0044] (5) The phase detection circuit 230 of the internal clock generation circuit 180 detects whether the chip selection signal CS is synchronized with either the divided clock DIV_CLK or the inverted divided clock DIV_CLKB, and based on the detection result, it can select either the divided clock DIV_CLK or the inverted divided clock DIV_CLKB as the synchronized internal clock ICLK.

[0045] (6) In the future, the memory device 100 can operate while receiving the command address signal CA<0:N> in synchronization with the internal clock ICLK.

[0046] In the embodiments described above, the process of changing the settings of the command address buffer circuits 110_0 to 110_N in the memory device 100 was explained. However, it goes without saying that the embodiments described above can be applied to other types of buffer circuits in the memory device 100 and to buffer circuits in other types of integrated circuit devices other than the memory device 100.

[0047] Although the technical concept of the present invention has been specifically described above with reference to the preferred embodiments, it should be noted that the embodiments described above are merely for illustrative purposes and do not limit the present invention. Furthermore, those skilled in the art should understand that a variety of embodiments are possible within the scope of the technical concept of the present invention. [Explanation of symbols]

[0048] 100: Memory device 101_0~101_N: Command address input terminals 103: Chip selection signal input terminal 105: Clock input terminal 110_0~110_N: Command address buffer circuit 113: Chip Selection Signal Buffer Circuit 115: Clock buffer circuit 120_0~120_N: Latch circuit 130: Command Decoder 140: Mode Register Set Circuit 150: Configuration Decoder Circuit 160: Buffer setting storage circuit 170: Synchronization status signal generation circuit 180: Internal clock generation circuit

Claims

1. One or more input terminals, A buffer setting storage circuit that acquires and stores buffer setting information in response to a clock synchronization status signal, One or more buffer circuits that are configured based on buffer setting information stored in the buffer setting storage circuit and that receive signals from one or more input terminals, An integrated circuit device including an integrated circuit.

2. The integrated circuit apparatus according to claim 1, wherein the buffer setting storage circuit acquires and stores the buffer setting information in response to the clock synchronization state signal transitioning from a sync-on state to a sync-off state.

3. A setting decoder circuit that generates the buffer setting information based on frequency setting information, A synchronization state signal generation circuit that changes the clock synchronization state signal to a first level indicating the sync-off state in response to the activation of the sync-off signal, and changes the clock synchronization state signal to a second level indicating the sync-on state in response to the activation of the sync-on signal, The integrated circuit apparatus according to claim 2, further comprising:

4. The integrated circuit apparatus according to claim 3, wherein the sync-off signal is activated when one or more of the following are instructed: clock sync-off and frequency change.

5. The aforementioned integrated circuit device is a memory device, The aforementioned one or more input terminals are one or more command address input terminals. The integrated circuit apparatus according to claim 2.

6. An internal clock generation circuit that generates an internal clock that is sync-on by dividing the input clock frequency, One or more latch circuits that latch command address signals received by one or more buffer circuits in synchronization with the internal clock that has been sync-on, A command decoder that decodes command address signals stored in one or more latch circuits, The integrated circuit apparatus according to claim 5, further comprising:

7. Steps to change the clock frequency setting information, The steps include: decoding the aforementioned clock frequency setting information to generate buffer setting information; A step to transition from the clock sync on state to the clock sync off state, In response to the transition, the steps include applying the buffer setting information to one or more buffer circuits, A method for operating an integrated circuit device, including the device itself.

8. The aforementioned integrated circuit device is a memory device, The aforementioned one or more buffer circuits are buffer circuits for receiving one or more command address signals. The method for operating the integrated circuit device according to claim 7.

9. The steps include transitioning from the clock sync off state to the clock sync on state, The steps include generating an internal clock that is sync-on by dividing the input clock frequency, The steps include receiving one or more command address signals synchronized with the internal clock that has been synced on by one or more buffer circuits, The steps include decoding one or more command address signals, A method for operating an integrated circuit device, further including the above.

10. The step of generating the internal clock that is set to sync-on is: The steps include: generating a divided clock and an inverted divided clock by dividing the input clock; A step of selecting either the divided clock or the inverted divided clock as the internal clock set to sync-on based on the sync-on information, A method for operating an integrated circuit device, including the device itself.

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