Multistream Read Cache Management for Data Storage Devices

Abstract

The present invention provides a data storage device (DSD) and method including a disk medium with improved read performance. [Solution] The method receives read commands from one or more hosts, each requesting data corresponding to a different range of logical addresses, and uses internal prefetch commands to cache the prefetched data in a cache segment. The data corresponds to a subsequent range of logical addresses. The internal prefetch commands are executed in an order based on the total time required to move the head to execute the commands. The method also designates new data as available to cache once it has completed the read commands associated with the largest logical address of the data cached in the cache segment.

Description

Technical Field

[0001] A data storage device (DSD) is often used to record data on a storage medium or to reproduce data from a storage medium. One type of storage medium includes rotating disks such as those in a hard disk drive (HDD). The read performance of a DSD is often measured in terms of how quickly it can return the data requested by a host from the DSD (i.e., latency performance), and how much data it can return within a certain period of time (i.e., throughput performance).

[0002] [[ID=*]]

[0003] [[ID=1)) One way to improve the read performance of a DSD that includes a disk medium is to continue reading data from the data track on the disk using a "read-ahead" prefetch after executing a read command, and to cache this additional data in a read cache stored in a faster-access memory such as the dynamic random access memory (DRAM) of the DSD. Since data for a particular file or object is likely to be stored on the same track or an adjacent track, a host that requests data related to previously requested data may send an additional read command for this related data, and this related data may be cached or prefetched from the read-ahead prefetch into the read cache. The prefetched data can then be provided to the host more quickly from the read cache to improve the read performance of the DSD.The read cache has limited storage capacity and is typically managed by a Longest Unused (LRU) cache management policy that discards or overwrites data associated with the oldest accessed data in the read cache. However, traditional prefetch and LRU policies can result in performance disadvantages for multi-stream read workloads, which are becoming more common for disk-based DSDs. Multi-stream read workloads involve receiving read commands for data or streams of data corresponding to different non-sequential logical address ranges (e.g., logical block addresses (LBAs)) used by one or more hosts. In such multi-stream read workloads, the DSD will often discard older cached data for the first stream to make space in the read cache for data related to the second stream, but the host can still send new commands for the prefetched data of the discarded first stream. In such cases, the DSD rereads the requested data that was discarded from the read cache, resulting in a loss of read performance and inefficient use of the read cache. [Brief explanation of the drawing]

[0004] The features and advantages of the embodiments of this disclosure will become more apparent from the detailed description below when interpreted in conjunction with the drawings. The drawings and related description are provided to illustrate the embodiments of this disclosure and not to limit the scope of the claims. [Figure 1] This is a plan view of an exemplary data storage device (DSD) according to one or more embodiments. [Figure 2] This document shows an example of using an internal prefetch command in one or more embodiments. [Figure 3A] The first part of an example of a multi-stream cache segment release policy according to one or more embodiments is shown. [Figure 3B] The second part of an example of the multi-stream cache segment release policy in Figure 3A, according to one or more embodiments, is shown. [Figure 3C] A third portion of the example multi-stream cache segment release policy shown in Figures 3A and 3B, according to one or more embodiments, is shown. [Figure 4] This is a flowchart for an internal prefetch command process, according to one or more embodiments. [Figure 5] This is a flowchart for an internal prefetch command ordering process according to one or more embodiments. [Figure 6] This is a flowchart for the internal prefetch command activation process according to one or more embodiments. [Figure 7] This is a flowchart for a multi-stream cache segment release process according to one or more embodiments. [Figure 8] This is a flowchart for a cache segment management process according to one or more embodiments. [Figure 9] This is a flowchart for a cache segment specification process according to one or more embodiments. [Modes for carrying out the invention]

[0005] The following detailed description includes numerous specific details to provide a complete understanding of the disclosure. However, it will be apparent to those skilled in the art that various embodiments disclosed may be carried out without some of these specific details. In other examples, well-known structures and techniques are not described in detail to avoid unnecessarily obscuring the various embodiments.

[0006] Exemplary data storage device Figure 1 is a plan view of an exemplary data storage device (DSD) 100 according to one or more embodiments illustrating an exemplary operating environment. In some implementations, the DSD 100 may include a hard disk drive (HDD) or other types of DSDs, the other types of DSDs comprising a rotating magnetic disk as a data recording medium, such as a solid-state hybrid drive (SSHD) which may include solid-state non-volatile memory in addition to one or more disks.

[0007] In the example in Figure 1, the DSD100 communicates with one or more hosts 101 that send commands to the DSD100 to read data on disk 120 and / or write data to disk 120. In some implementations, the hosts 101 and the DSD100 can form a computer system such as a desktop, laptop, media player, or client and server. In this regard, the hosts 101 and the DSD100 may be housed separately; for example, the host 101 may be one or more clients accessing the DSD100 as a server. In other implementations, the hosts 101 and the DSD100 may be housed together as part of a single electronic device. In other implementations, the hosts 101 and the DSD100 may not be located in the same place, but may be in different geographical locations.

[0008] As shown in the example in Figure 1, the DSD100 includes a slider 114 with a magnetic read / record head 112. Collectively, the slider 114 and head 112 may be referred to as the head slider. The DSD100 further includes at least one head gimbal assembly (HGA) 110, the HGA 110 comprising the head slider, a lead suspension 116 typically attached to the head slider via a flexure, and a load beam 118 attached to the lead suspension 116. Typically, the HGA includes multiple heads arranged to read and write data on multiple disk surfaces.

[0009] The DSD100 also includes at least one disk 120 rotatably mounted on a spindle 124, and a drive motor (not shown) attached to the spindle 124 for rotating the disk 120. The head 112 includes a write unit or write element and a read unit or read element, for writing and reading data stored on the disk 120 of the DSD100, respectively. The disk 120, or a plurality of disks stacked below the disk 120, can be attached to the spindle 124 by disk clamps 128.

[0010] As shown in Figure 1, the DSD100 further includes an arm 132 mounted on the HGA110, a carriage 134, a voice-coil motor (VCM) including an armature 136 and a voice coil 140 mounted on the carriage 134, and a stator 144 including a voice coil magnet (not shown). The armature 136 of the VCM is mounted on the carriage 134 and is configured to move the arm 132 and the HGA110 to access a portion of the disk 120, and is attached to the pivot shaft 148 by an interposed pivot bearing assembly 152. In the case of multiple disks, the carriage 134 is arranged to carry a series of arms that are interlocked to resemble a comb, and may therefore be referred to as an "E-block" or comb.

[0011] An assembly comprising a head gimbal assembly (e.g., HGA110) including a flexure to which a head slider is coupled, an actuator arm (e.g., arm 132) and / or a load beam to which the flexure is coupled, and an actuator (e.g., VCM) to which the actuator arm is coupled, can be collectively referred to as a head stack assembly (HSA). However, an HSA may include more or fewer components than those described. For example, an HSA may refer to an assembly that further includes electrical interconnection components. Generally, an HSA is an assembly configured to move the head slider to access portions of disk 120 for read and write operations.

[0012] Referring further to Figure 1, electrical signals (e.g., current to the voice coil 140 of the VCM), including write signals to the head 112 and read signals from the head 112, are provided by a flexible interconnect cable 156 ("flex cable"). An Arm-Electronics (AE) module 160 may have an onboard preamplifier for the read signals, as well as other read and write channel electronics, and provides the connection between the flex cable 156 and the head 112. The AE module 160 may be mounted on the carriage 134 as shown, or may be included as part of the circuitry 166 of the controller 170. The flex cable 156 is coupled to an electrical connector block 164, which provides electrical communication to the controller 170 located beneath the electrical connector block 164 via an electrical feedthrough provided by a base or housing 168. Together with the cover, the housing 168 provides a sealed protective enclosure for the data storage components of the DSD 100.

[0013] Other electronic components, including a disk controller and servo electronics which may further include a digital signal processor (DSP), provide electrical signals to the drive motor, the voice coil 140 of the VCM, and the head 112 of the HGA 110. The electrical signals provided to the drive motor enable the drive motor to spin while providing torque to the spindle 124, which is then transmitted to the disk 120 attached to the spindle 124. As a result, the disk 120 spins in direction 172. The disk 120 forms a gas cushion that acts as a gas bearing, on which the gas bearing surface (GBS) of the slider 114 rests, thereby causing the slider 114 to float above the surface of the disk 120 without contacting the thin magnetic recording layer of the disk 120 on which data is recorded.

[0014] The electrical signals supplied to the voice coil 140 of the VCM enable the head 112 of the HGA 110 to access tracks such as track 176 on which data is recorded. Thus, the armature 136 of the VCM swings along the arc 180, which enables the head 112 of the HGA 110 to access various tracks on the disk 120. The data is stored on the disk 120 in multiple radially nested tracks located within sectors on the disk 120, such as sector 188 of track 176 in the wedge 184. Each track on the disk surface consists of multiple sectors, such as sector 188, which can store the recorded data and a header containing a servo burst signal pattern. The servo burst signal pattern may include, for example, an ABCD servo burst signal pattern, which is information identifying track 176, and error correction code information. When accessing track 176, the reading element of the head 112 of the HGA110 reads a servo burst signal pattern, which provides a position-error-signal (PES) to the servo electronics, which controls the electrical signal provided to the voice coil 140 of the VCM to enable the head 112 to follow track 176. Once track 176 is found and sector 188 is identified, the head 112 reads data from or writes data to track 176 in response to instructions, such as instructions received by the controller 170 from an external host 101, such as a microprocessor of a computer system.

[0015] In the example in Figure 1, the controller 170 is shown by a dashed line connected to the electrical connector block 164 to indicate that the controller 170 is communicating with the electrical connector block 164. As will be understood by those skilled in the art, in some implementation forms, the controller 170 may include a printed circuit board (PCB) coupled to the bottom surface of the DSD 100, such as a housing 168. As shown in the example in Figure 1, the controller 170 comprises a circuit 166 and at least one memory 174, the memory 174 may include dynamic random access memory (DRAM) or other solid-state memory such as storage class memory (SCM) used for rapid access to data.

[0016] While the description herein generally refers to solid-state memory, it should be understood that solid-state memory may include one or more of various types of memory devices, such as flash integrated circuits, NAND memory (e.g., single-level cell (SLC) memory, multi-level cell (MLC) memory (i.e., two or more levels), or any combination thereof), NOR memory, electrically erasable programmable read-only memory (EEPROM), chalcogenide RAM (C-RAM), phase-change memory (PCM), programmable metallization cell RAM (PMC-RAM or PMCm), ovonic unified memory (OUM), resistive RAM (RRAM), ferroelectric memory (FeRAM), magnetoresistive RAM (MRAM), and / or other discrete non-volatile memory (NVM) chips, or any combination thereof.

[0017] Circuit 166 may include electronic components for performing different functions for the operation of the DSD, such as an interface controller, a Read / Write Integrated Circuit (R / W IC), an AE module, a motor driver, a servo processor, and other digital processors and associated memory. In this regard, circuit 166 may include one or more processors for executing instructions, such as a microcontroller, DSP, Application-Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA), Graphics Processing Unit (GPU), hardwired logic, analog circuitry, and / or a combination thereof. In some implementations, circuit 166 may include a System on a Chip (SoC), and the SoC may also include one or more memories of at least one memory 174.

[0018] As shown in Figure 1, at least one memory 174 stores a cache manager 10 and a read cache 12, the read cache 12 including a cache segment 14. As will be described in more detail below, the cache segment 14 (i.e., a read buffer) can be used to cache data read from disk 120 to execute read commands received from one or more hosts, such as host 101. In some implementations, each cache segment 14 may have a predetermined data storage capacity, such as corresponding to a specific number of sectors on disk 120.

[0019] In addition, the cache segment 14 can cache additional data (i.e., additional prefetched data) corresponding to a range of logical addresses that sequentially follows the initial range of logical addresses containing the data requested by the read command. Prefetching this data can improve the read performance of the DSD 100 so that future read commands from host 101 for data that may be part of a read stream or related to a larger range of logical addresses can be performed by returning the prefetched data from the cache segment to the requesting host. This can improve the read performance of the DSD because data can typically be prefetched relatively quickly by continuing to read data on the same or adjacent tracks, and the prefetched data can be returned from the solid-state memory 174 with faster access for new read commands compared to waiting for the disk to rotate to a specific starting position and / or moving the head 112 to a specific track for a new read command.

[0020] As will be described in more detail below, the cache manager 10 can use an internal prefetch command to read additional data following the data read for a host read command and prefetch it into the cache segment 14 of the data read cache 12. Execution of the internal prefetch command can be ordered based at least in part on the total time to move one or more heads of the HGA to their respective disk positions to execute the internal prefetch command. This typically improves the read performance of a multi-stream read workload over conventional read-ahead prefetching because the order of prefetching is not primarily determined by the order in which host read commands are received, which can cause read-ahead prefetching at disparate positions across one or more disk surfaces. Instead, the internal prefetch commands of the present disclosure take great advantage of the sequential or contiguous nature of each stream to prefetch data corresponding to a range of subsequent logical addresses (e.g., logical block addresses) in an order that reduces the total time to move at least one head to different positions on at least one disk. The time reduction can be achieved by reducing the idle time when the head has to wait for the disk to rotate to reach the starting position to begin reading the data and / or by reducing the seek time when moving the head or HGA from one radial disk position to another.

[0021] In addition, in response to completing a read command associated with the maximum logical address of data stored in a cache segment, the cache manager 10 can use a multi-stream cache segment release policy that is more suitable for multi-stream read workloads by designating that cache segment as available for caching newly read data. This typically improves the read performance of multi-stream workloads over the conventional least recently used (LRU) cache policy. This is because in a read stream, after data corresponding to the maximum logical address is requested, it is unlikely that data within the cache segment corresponding to a lower logical address will be requested by the host. The released cache segment then becomes available to cache data for another stream that may still have new read commands, instead of freeing an LRU cache segment that caches prefetched data for another stream.

[0022] Referring to FIG. 1, the cache manager 10 can include computer-executable instructions executed by a circuit 166, such as part of the firmware of the DSD, to manage the caching of data within the cache segment 14. In some implementations, the cache manager 10 can also manage a write cache that is used to cache received data for write commands for storing data on the disk 120, or another disk that is circumferentially aligned with the disk 120.

[0023] As those skilled in the art will understand by referring to this disclosure, other implementations of the DSD100 may differ from the example shown in Figure 1. For example, the circuit 166 or a portion thereof may be located outside the controller 170, for example, by forming part of the AE module 160 in other implementations. As another example, one or more memories 174 in Figure 1 may also include a write cache for caching data to be written to the disk 120.

[0024] Figure 2 shows an example of using internal prefetch commands in one or more embodiments. As shown in Figure 2, there are four read streams S1, S2, S3, and S4 associated with different non-sequential or non-contiguous ranges of logical addresses (i.e., LBAs in Figure 2). Each read stream contains read commands received by the DSD (e.g., DSD100 in Figure 1) from one or more hosts (e.g., host 101 in Figure 1) for each range of logical addresses. Logical addresses in different ranges increase from left to right. In Figure 2, read streams S1-S4 are shown overlapping, but this is for illustrative purposes only, and the non-sequential ranges of logical addresses in different read streams do not overlap.

[0025] In the lower part of Figure 2, below the dashed line, the temporal order of read commands received from the host and the execution of commands by DSD are shown, with time increasing from left to right. Host commands are executed by a host task or host process run by the DSD circuitry to identify the requested data, retrieve it from the cache segment, and send the requested data back to the requesting host. Internal prefetch commands are executed by a DSD task or DSD process run by the DSD circuitry to read data from one or more disks of the DSD and cache the read data in the cache segment.

[0026] The upward arrow above "Int Prefetch Cmd 3" indicates the point in time for the cache segment shown above the dashed line of the read stream. At the point indicated by the upward arrow, the DSD has received read commands C4-1, C4-2, C3-1, C1-1, C2-1, and C1-2 from the host and is receiving read command C1-3 from the host. In addition, at the point indicated by the upward arrow, the DSD has executed internal prefetch command 4 (i.e., Int Prefetch Cmd 4) and is executing internal prefetch command 3 (i.e., Int Prefetch Cmd 3).

[0027] As shown above the dashed line in Figure 2, the cross-hatched portion of the read stream indicates data cached in the cache segment of the read cache (e.g., cache segment 14 of read cache 12 in Figure 1) at the point indicated by the upward arrow. In the example in Figure 2, the data C4-1 and C4-2 for the first two read commands received from the host are already cached in cache segment 4-1, along with other prefetched data corresponding to the logical addresses that follow sequentially after the requested data. The requested data for the first two read commands can be quickly provided to the requesting host using the prefetched data for these commands.

[0028] The DSD task or process of the cache manager (e.g., cache manager 10 in Figure 1) dispatches a first internal prefetch command, "Int Prefetch Cmd 4," when cache segment 4-1 is nearly filled with data (e.g., 75% to 95%). In the example in Figure 2, internal prefetch command 4 is dispatched before any commands are received from the host for data to be cached in cache segment 4-2. Internal prefetch command 4 caches additional prefetched data corresponding to subsequent logical address ranges that sequentially follow the initial logical address range corresponding to the prefetched data cached in cache segment 4-1. In particular, internal prefetch command 4 is executed even if another read command for a different read stream is received by DSD along with the reception of read command C3-1. Cache segment 4-2 is filled with prefetched data for read stream S4 in anticipation of receiving additional read commands for read stream S4.

[0029] Conventional systems would not continue to fill another cache segment of read stream S4 without receiving additional read commands for the read stream, but instead would focus on executing read commands C3-1 and C1-1. However, executing read commands for a multi-stream workload in this way may reduce the read performance of the DSD compared to using internal prefetch commands in this disclosure, because it does not take full advantage of prefetching sequentially addressed data despite scattering read commands across different read streams.

[0030] After filling cache segment 4-2 with prefetched data for internal prefetch command 4, DSD executes internal prefetch command 3 to cache additional prefetched data corresponding to subsequent logical address ranges following the initial logical address range corresponding to the data cached in cache segment 3-1. Data for read command C3-1 can then be provided to the requesting host using the prefetched data in cache segment 3-1.

[0031] The DSD is executing an internal prefetch command 3 for a subsequent logical address range, and the internal prefetch command 3 is indicated by a dashed line for read stream S3, along with dashed brackets for the cache segment. According to one aspect of this disclosure, when multiple read streams are detected, a multi-stream cache segment release policy is used to replace or reduce the use of a conventional LRU cache management policy. In some implementations, the DSD may monitor the logical addresses for received read commands and determine that there are at least two active read streams if there are different groups of read commands with different logical addresses by a threshold number of logical addresses. In some implementations, this determination or detection of multiple read streams may not occur until after a threshold number of read commands have been received for each read stream, or after a predetermined period has elapsed since the first read command was received for the first detected read stream.

[0032] In a multistream cache release policy, a cache segment is designated as available for caching newly read data in response to the completion of a read command associated with the maximum logical address of the data stored in the cache segment. A read command may be associated with the maximum logical address of a cache segment, such that the maximum logical address corresponds to at least a portion of the data requested by the read command. Completion of a read command can refer to, for example, sending the data requested by the command to the requesting host, queuing the requested data in the DSD data transmission queue, packaging the requested data into packets, or other types of preparation or stages in response to the read command.

[0033] In the example in Figure 2, the multi-stream cache segment release policy can result in cache segment 1-1 being reused for S3's internal prefetch command 3 without the need to overwrite or clear the longest unused or inaccessible cache segment (i.e., the cache segment that has not been used longest to complete a read command), which could still cache prefetched data for another stream that may be immediately requested by the host. Such cache management is more suitable for multi-stream workloads that may be associated with disparate ranges of logical addresses for different streams compared to using an LRU cache management policy.

[0034] After filling the cache segment for internal prefetch command 3, the DSD executes internal prefetch command 2 to read the prefetched data for read stream S2. The requested data for read command C2-1 can be provided to the requesting host using the prefetched data in cache segment 2-1. In particular, internal prefetch command 2 is executed before internal prefetch command 1, even if read command C1-1 is received before read command C2-1.

[0035] As described above, the ordering of the execution of internal prefetch commands reduces the total time it takes to move one or more heads of the DSD (e.g., head 112 in Figure 1) to different positions for executing internal prefetch commands, rather than following an order primarily determined by the order in which read commands are received from one or more hosts. This typically improves read performance in terms of both throughput (i.e., the amount of requested data that can be returned within a given time frame) and latency (i.e., the time it takes to return the requested data) because more data can be prefetched for each stream in a shorter period of time by taking advantage of the sequential or continuous nature of the read streams. In some implementations, the ordering of internal prefetch commands to reduce the total time it takes to move one or more heads can be achieved at least partially using rotational position optimization (RPO) algorithms.

[0036] In the example in Figure 2, the last internal prefetch command, internal prefetch command 1, is executed after internal prefetch command 2 to cache additional prefetched data corresponding to subsequent logical address ranges following the initial logical address range corresponding to the prefetched data in cache segments 1-2, which includes the requested data for read commands C1-3. The order in which internal prefetch command 1 is executed after internal prefetch command 2 is based on reducing the amount of seek or movement of one or more heads across one or more disks. This can improve DSD read performance by ordering the execution of internal prefetch commands to spend more time reading data from disks and less time moving from one track location to another across disks.

[0037] Those skilled in the art will understand, by referring to this disclosure, that other examples of using internal prefetch commands are possible, and that the example in Figure 2 is for illustrative purposes only. For example, other examples of using internal prefetch commands may include a different number of read commands and read streams.

[0038] Figure 3A shows the first part of an example of a multi-stream cache segment release policy according to one or more embodiments. As shown in the example in Figure 3A, there are four read streams S1, S2, S3, and S4, and the cross-hatched sections of the read streams indicate the data cached in each cache segment. Specifically, S1 has data cached in cache segment 1-1, S3 has data cached in cache segment 3-1, and S4 has data cached in cache segment 4-1. The DSD task is currently caching data in cache segment 2-1 of S2, as indicated by the dashed line in S2.

[0039] The circled numbers in Figure 3A indicate the command execution order. Read command C4-1 is the first command to be executed, and is performed by the DSD host task identifying and retrieving the requested data for command C4-1 before sending it to the requesting host. Next, read command C3-1 is executed for S3, followed by read command C2-1 for S2. Read command C3-2 is executed last in Figure 3.

[0040] Cache segment 1-1 of S1 is the LRU cache segment in the example in Figure 3A, and is released or designated in the conventional manner as available to cache newly read data when more cache segments or read buffers are needed. In contrast, the multi-stream cache segment release policy of this disclosure retains the cached data in cache segment 1-1 and, instead, releases cache segment 3-1 upon completion of read command C3-2 at the end of cache segment 3-1 with respect to logical addressing or LBA. The DSD in this disclosure can monitor the progress of each read stream (e.g., via a cache manager), and when a completed command for a stream reaches the end of a cache segment, that cache segment is designated as available to cache newly read data.

[0041] As shown in Figure 3B, commands C1-1 and C1-2 are received by S1 and can be executed by the DSD host task identifying and retrieving prefetched data for the commands from cache segment 1-1. Cache segment 1-1 is no longer an LRU cache segment because data has been used from this cache segment for commands C1-1 and C1-2. Now, cache segment 4-1 has become the new LRU cache segment because it has not been used for the longest time to complete the read commands. As described above, the multi-stream cache segment release policy of this disclosure improves the read performance of the DSD for multi-stream read workloads by replacing or reducing the use of the LRU cache management policy, such as by using the LRU cache policy for multi-stream read workloads only when the multi-stream cache segment release policy is active but there are no cache segments available to cache data.

[0042] As shown in Figure 3B, cache segment 3-1 is released upon completion of read command C3-2 in Figure 3A and can be reused for cache segment 3-2 when caching data containing the requested data for read command C3-3 in Figure 3B. This is in contrast to the conventional LRU cache management policy in which LRU cache segment 4-1 is released for reuse as cache segment 3-2. Prefetched data cached in cache segment 1-1 can be used to complete commands C1-1 and C1-2 for S1, and prefetched data cached in cache segment 2-1 can be used to complete command C2-2 for S2.

[0043] In Figure 3C, cache segment 1-1 is released according to the multi-stream cache segment release policy, upon completion of read command C1-2 associated with the maximum LBA of data cached in the cache segment. In this regard, cache segment 1-1 is released instead of S4's LRU cache segment 4-1. As shown in Figure 3C, read command C4-2 is last received and executed using data prefetched in LRU cache segment 4-1. The requested data for read command C4-2 is available for the host task to complete the read command much faster than if cache segment 4-1 had been released using the LRU cache management policy. In the released scenario, the DSD would have to reread the requested data for read command C4-2 from disk, which would take longer than providing prefetched data for this command from cache segment 4-1 as shown in Figure 3C.

[0044] Those skilled in the art will understand, by referring to this disclosure, that other examples of multistream cache segment release policies may differ from the examples in Figures 3A-3C. For example, the multistream cache segment release policy may be used in several implementations without using the internal prefetch command described above, as in the example in Figure 2. Such implementations may offer improved read cache management compared to using a conventional LRU cache management policy, although the use of the internal prefetch command typically provides further read performance improvements for multistream read workloads.

[0045] Exemplary process Figure 4 is a flowchart for an internal prefetch command process according to one or more embodiments. The process in Figure 4 can be executed, for example, by the circuit 166 of the DSD100 which runs the cache manager 10 in Figure 1. In this regard, the circuit 166 may, in some implementations, include means for performing the functions of the internal prefetch command process in Figure 4.

[0046] In block 402, the DSD receives read commands from one or more hosts. Each read command requests data stored on one or more disks of the DSD, corresponding to a different range of logical addresses. The different range of logical addresses may be for different read streams that request data within a different range of logical addresses, or data within a subsequent range of logical addresses that follows sequentially after or are contiguous with the different range. Referring to the example described above for Figure 2, the different range may include the LBAs of the data requested for read streams S1-S4.

[0047] In block 404, the DSD executes an internal prefetch command to cache the prefetched data in each cache segment of the read cache (for example, cache segment 14 of read cache 12 in Figure 1). The cached prefetched data corresponds to a subsequent range of logical addresses that follows a different range of logical addresses sequentially.

[0048] In particular, internal prefetch commands are executed in an order based at least partially on the total time it takes to move one or more DSD heads (e.g., head 112 in Figure 1) to their respective positions on one or more disks in order to read data for the internal prefetch commands. The total time it takes to move one or more heads can attempt to reduce idle time during which the heads may have to wait for the disks to rotate and reach the starting position before beginning to read data, and / or seek time when moving the heads from one radial position to another before beginning to read data. In some implementations, DSD may use an RPO algorithm to order internal prefetch commands.

[0049] As mentioned above, ordering internal prefetch commands to reduce latency when reading data from disk can improve DSD's read performance for multi-stream read workloads. In this regard, DSD can order internal prefetch commands more independently of the order in which read commands are received from one or more hosts, which allows DSD to better utilize the sequential nature of read streams, even though individual read commands for different streams are scattered across one or more disks in different locations.

[0050] Those skilled in the art will understand, by referring to this disclosure, that other methods are possible for performing the internal prefetch command process. For example, in some implementations, the DSD may wait for a certain period of time before enabling the internal prefetch command in block 404 to ensure that the read command is actually associated with an ongoing read stream.

[0051] Figure 5 is a flowchart for an internal prefetch command ordering process according to one or more embodiments. The process in Figure 5 can be executed, for example, by the circuit 166 of the DSD100 which runs the cache manager 10 of Figure 1. In this regard, in some implementations, the circuit 166 may include means for performing the functions of the internal prefetch command ordering process of Figure 5. In some implementations, the process in Figure 5 may form part of the internal prefetch command process of Figure 4 described above.

[0052] In block 502, a first read command is received from the host requesting first data stored on at least one disk of the DSD. The first data corresponds to a first logical address within the range of initial logical addresses.

[0053] In block 504, the first read command is executed by caching the first prefetched data at least partially in the first cache segment. The first prefetched data corresponds to the initial range of logical addresses and includes the first data requested by the first read command. In this regard, the initial caching of data for the read stream can be based on the position of the initial read command for the read stream, and additional data that logically follows the data requested with respect to logical addressing can be prefetched in anticipation of further read commands for the read stream.

[0054] In block 506, after receiving a first read command, but before executing an internal prefetch command to cache additional prefetched data corresponding to a range of first logical addresses that sequentially follows the initial range of logical addresses, a second read command is received from one or another host. The second read command requests second data stored on at least one disk of the DSD that is not included in the first prefetched data or the additional prefetched data. The second read command may be for a different read stream than the read stream containing the first read command. In other words, the data requested for the second read command corresponds to one or more logical addresses that are not included in the initial range of logical addresses or the subsequent range of logical addresses, and may therefore be located on one or more disks relatively far away (e.g., radially far) from the locations of the data requested for the first read command and the data prefetched for the internal prefetch command.

[0055] In block 508, an internal prefetch command is executed to cache additional prefetched data in a second cache segment. The additional prefetched data corresponds to a range of first logical addresses that sequentially follows the initial range of logical addresses used in the first cache segment.

[0056] In block 510, additional prefetched data from an internal prefetch command is cached in the second cache segment before the requested second data for the second read command is cached in the second cache segment. Despite receiving the second read command from the host before executing the internal prefetch command, the DSD continues to prefetch data after the first prefetched data because the additional prefetched data may be requested later for the first read stream, and it is more efficient to continue reading data sequentially from disk than to return to this position after executing the second read command.

[0057] Those skilled in the art will understand, by referring to this disclosure, that other implementations of the internal prefetch command reordering process in Figure 5 may differ. For example, the process in Figure 5 may include only a portion of the multistream read workload, as in the examples in Figures 2 or 3A-3C described above. As described above for Figure 2, the internal prefetch commands can be executed more independently of the order in which read commands for different read streams are received by the DSD.

[0058] Figure 6 is a flowchart for an internal prefetch command activation process according to one or more embodiments. The process in Figure 6 can be performed, for example, by a circuit 166 of the DSD100 that runs the cache manager 10 of Figure 1. In this regard, the circuit 166 may, in some implementations, include means for performing the functions of the internal prefetch command activation process in Figure 6.

[0059] In block 602, read commands are received from one or more hosts, requesting data corresponding to logical addresses within a range of logical addresses. In this regard, a read command may indicate a single logical address or a range of logical addresses by providing the starting logical address and length of the data to be read.

[0060] In block 604, the DSD determines that a read command is associated with at least two different read streams corresponding to different non-sequential ranges of logical addresses. This determination may include, for example, monitoring the logical addresses of data requested by one or more hosts to determine whether the logical addresses are grouped into different ranges of logical addresses corresponding to different read streams. In some implementations, requests for data associated with logical addresses that differ by more than a certain number of addresses can be identified as separate read streams.

[0061] In block 606, DSD executes an internal prefetch command if it determines that a read command is associated with at least two different read streams. As described above, the internal prefetch command may be executed by a DSD task or process that can continue to cache or prefetch data into a cache segment before receiving any commands from the host to read additional prefetched data.

[0062] Those skilled in the art will understand, by referring to this disclosure, that other implementations of the internal prefetch command activation process in Figure 6 may differ. For example, the activation of internal prefetch commands may require a number of read streams different from 2, as in the exemplary process described above. In other implementations, the circuit may not activate the use of internal prefetch commands until it determines, for example, that there are at least 3 read streams. In another exemplary variation, other implementations may require a threshold number of read commands for different read streams, and / or a threshold period during which different read streams are active, before switching to the use of internal prefetch commands.

[0063] Figure 7 is a flowchart for a multi-stream cache segment release process according to one or more embodiments. The process in Figure 7 can be performed, for example, by the circuit 166 of the DSD100 which runs the cache manager 10 of Figure 1. In this regard, the circuit 166 may, in some implementation forms, include means for performing the functions of the multi-stream cache segment release process of Figure 7.

[0064] In block 702, the DSD receives read commands from one or more hosts to read data from at least one disk of the DSD. In some implementations, read commands may be associated with different read streams requesting data within different logical address ranges. In other implementations, read commands may be associated with only a single read stream, or they may represent separate read commands that are not related to each other.

[0065] In block 704, the DSD caches data read from at least one disk in a cache segment of the read cache (for example, cache segment 14 of the read cache 12 in Figure 1). The data cached in the cache segment may include data requested by a read command, and may also include additional data physically located on the disk surface in a sequential or consecutive location relative to the data requested by the read command, such as data located on the same track or adjacent tracks. In this regard, the cache segment may have a predetermined storage capacity for caching the requested data and additional data, such as the amount of data stored in a particular number of sectors on the disk surface.

[0066] In block 706, a cache segment is designated as available for caching other data in response to the completion of a read command associated with the largest logical address of data cached in the cache segment. As described above with respect to the example in Figure 3, such a read cache management policy is generally more suitable for multi-stream read workloads than an LRU cache management policy that otherwise designates the cache segment that most recently provided data for a read command. Completion of a read command in block 706 can refer to, for example, sending the data requested by the command to the requesting host, queuing the requested data in the DSD data transmission queue, packaging the requested data into a packet, or any other type of preparation or stage in response to the read command.

[0067] Those skilled in the art will understand, by referring to this disclosure, that other implementations of the multi-stream cache segment release process in Figure 7 may differ. For example, in some implementations, the cache segment release process may not be activated or triggered until after multiple read streams have been detected for an received read command, or after it has been determined in some other way that there are multiple read streams. In such implementations, the DSD may switch between the LRU cache management policy and the multi-stream cache segment release policy depending on the workload, as described below with reference to the process in Figure 8. In addition, as will be described in more detail below with reference to the process in Figure 9, the LRU cache management policy may be used temporarily when there are no available cache segments to cache the read data while the multi-stream cache segment release policy is in use.

[0068] Figure 8 is a flowchart for a cache segment management process according to one or more embodiments. The process in Figure 8 can be performed, for example, by the circuit 166 of the DSD100 which runs the cache manager 10 of Figure 1. In this regard, the circuit 166 may, in some implementation forms, include means for performing the functions of the cache segment management process of Figure 8.

[0069] In block 802, the DSD determines that the received read command is associated with at least two different read streams corresponding to a range of non-sequential logical addresses. In some implementations, the DSD may monitor the logical addresses for the read commands and determine that there are at least two active read streams if there are different groups of read commands with different logical addresses by a threshold number of logical addresses. In some implementations, the determination in block 802 may not be performed until after a threshold number of read commands have been received for each read stream, or until a predetermined period has elapsed since the first read command for the first detected read stream was received.

[0070] In block 804, DSD activates a multi-stream cache segment release policy that specifies a cache segment to cache newly read data as a read command corresponding to the maximum logical address of data cached in each cache segment is completed. By using the multi-stream cache segment release policy when there is a multi-stream read workload, DSD can better utilize the sequential nature of read streams to prefetch data that is likely to follow for each read stream, without having to release an LRU cache segment that could still cache data immediately requested by another read stream. Instead of releasing an LRU cache segment, a cache segment that caches data for completed read commands associated with the maximum logical address of the cache segment can be released instead of the LRU cache segment.

[0071] In block 806, it is determined that only one read stream is currently active. The dashed line between blocks 804 and 806 in Figure 8 indicates the passage of time over which the read workload may have changed. In block 806, the determination that only one read stream is active may be made by monitoring the active read stream and determining that no new read commands have been received for other read streams after a predetermined period of time. In some implementations, the DSD cache manager may maintain a list or other data structure to identify the active read stream.

[0072] In block 808, DSD deactivates the multi-stream cache segment release policy in response to its determination that only one read stream is currently active. DSD reactivates the LRU policy, which specifies the cache segment that has not been used for the longest time to complete the read command, in order to cache newly read data. The LRU policy may perform better than the multi-stream cache segment release policy for a single read stream or for individual read commands that are not part of a read stream. For such single-read-stream and individual read workloads, the additional prefetched data in the LRU cache segment is less likely to be requested by the host compared to the prefetched data cached in a cache segment that was used more recently to complete the read command. In some cases, the additional prefetched data may include data that was part of a prefetch lookup, or it may be prefetched data that may remain from the use of internal prefetch commands from when DSD was previously handling a multi-stream read workload.

[0073] Those skilled in the art will understand, by referring to this disclosure, that other implementations of the cache segment management process in Figure 8 may differ. For example, the activation of the multi-stream cache segment release policy may be triggered by determining or detecting a different minimum number of read streams, such as three or more read streams, as opposed to at least two read streams as in block 802 of Figure 8.

[0074] Figure 9 is a flowchart for a cache segment designation process according to one or more embodiments. The process in Figure 9 can be performed, for example, by the circuit 166 of the DSD100 which runs the cache manager 10 of Figure 1. In this regard, the circuit 166 may, in some implementations, include means for performing the functions of the cache segment designation process of Figure 9.

[0075] In block 902, DSD determines that while the multi-stream cache segment release policy is active, there are no cache segments available to cache data to be read from at least one disk. In some implementations, the data being read may be for internal prefetch commands used by DSD to prefetch data for different read streams. In other implementations, DSD may not use internal prefetch commands, but may still use the multi-stream cache segment release policy for multi-stream read workloads.

[0076] In block 904, the DSD designates the longest unused cache segment for caching the data to be read. The longest unused cache segment may be the cache segment most recently accessed by the DSD's host task to prepare a response to a read command received from the host. In this regard, completion of a read command can refer, for example, to sending the data requested by the command to the requesting host, queuing the requested data in the DSD's data transmission queue, packaging the requested data into a packet, or any other type of preparation or stage in response to the read command.

[0077] Switching from using a multi-stream cache segment release policy to using an LRU cache management policy to release cache segments may be temporary in that the DSD continues to use the multi-stream cache segment release policy after the LRU cache segments have been made reusable. This allows for continued caching of data while still leveraging the read stream tendency to read data corresponding to increasing logical addresses by continuing to use the multi-stream cache segment release policy.

[0078] Those skilled in the art will understand, by referring to this disclosure, that other implementations of the cache segment designation process in Figure 9 may differ. For example, in other implementations, the LRU cache policy may be temporarily activated when the number of available cache segments falls below a threshold number, such as when there are two or fewer cache segments available to cache newly read data.

[0079] The aforementioned systems and methods for managing read caches for multi-stream read workloads can provide more efficient use of the read cache by freeing up cache segments when data from those segments is used for read commands corresponding to the largest logical address of the cache segment. In addition, the disclosed, DSD-ordered, internal prefetch commands provide more efficient use of the read cache and improved read performance by being more independent of the disjointed order in which read commands may be received for multiple read streams. Internal prefetch commands improve DSD read performance for multi-stream workloads compared to conventional prefetching typically by reducing the amount of idle time spent waiting for the disk to rotate to a particular starting position for non-sequential or non-contiguous read operations, and by reducing seek time when moving the head over longer distances across disk surfaces in a less efficient manner to perform reads in a less sequential manner.

[0080] Other Embodiments Those skilled in the art will understand that various illustrative logic blocks, modules, and processes described in connection with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. Furthermore, the aforementioned processes can be embodied on a computer-readable medium that enables or performs specific functions on a processor or controller circuit.

[0081] To clearly illustrate this hardware and software compatibility, various illustrative components, blocks, and modules are described in general terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and design constraints imposed on the overall system. A person skilled in the art may implement the described functionality in various ways for specific uses, but such implementation decisions should not be construed as causing a departure from the scope of this disclosure.

[0082] The various illustrative logic blocks, units, modules, processing circuits, and control circuits described in relation to the examples disclosed herein may be implemented or run in general-purpose processors, GPUs, DSPs, ASICs, FPGAs or other programmable logic devices, individual gate or transistor logic, individual hardware components, or any combination thereof, designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor or controller circuit may also be implemented as a computing device, for example, a combination of a DSP and a microprocessor, multiple microprocessors, a SoC, one or more microprocessors combined with a DSP core, or any other combination of such configurations.

[0083] The activities of a method or process described in relation to the examples disclosed herein may be embodied directly by hardware, in a software module executed by a processor or controller circuit, or in a combination of the two. The steps of a method or algorithm may also be performed in an alternative order to those provided in the examples. The software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disks, removable media, optical media, or any other form of storage medium known in the art. The exemplary storage medium is coupled to the processor or controller circuit so that the processor or controller circuit can read information from and write information to the storage medium. Alternatively, the storage medium may be integrated with the processor or controller circuit. The processor or controller circuit and the storage medium may reside in an ASIC or SoC.

[0084] The foregoing description of the exemplary embodiments disclosed is provided to enable those skilled in the art to construct or use embodiments of the present disclosure. Various modifications to these examples will be readily apparent to those skilled in the art, and the principles disclosed herein may be applied to other examples without departing from the spirit and scope of the present disclosure. The embodiments described should be considered in all respects to be illustrative and non-restrictive. In addition, the use of the language in the form of “at least one of A and B” in the following claims should be understood to mean “A only, B only, or both A and B.”

Claims

1. A data storage device (DSD), At least one disk configured to store data, At least one head configured to read data from the at least one disk, At least one memory configured to store multiple cache segments for caching data read from the at least one disk, It is a circuit, The read commands, each of which is a read command, request data corresponding to a different range of logical addresses stored on at least one disk, are received from one or more hosts. The system is configured to execute multiple internal prefetch commands to cache prefetched data corresponding to subsequent logical address ranges that sequentially follow the aforementioned different logical address ranges in each of the multiple cache segments. A DSD comprising a circuit in which the plurality of internal prefetch commands are executed in an order based at least partially on the total time required to move the at least one head to each of the at least one disk locations in order to execute the plurality of internal prefetch commands.

2. The DSD according to claim 1, wherein each of the plurality of cache segments has a predetermined data storage capacity.

3. The aforementioned circuit, The host receives a first read command requesting first data stored on at least one disk, corresponding to a first logical address within a range of initial logical addresses of the different ranges of logical addresses. In response to receiving the first read command, the first read command is executed by at least partially caching the first prefetched data corresponding to the initial logical address range, which includes the requested first data, in the first cache segment of the plurality of cache segments, One of the multiple internal prefetch commands is executed to cache additional prefetched data corresponding to a first logical address range that follows the initial logical address range in a second cache segment of the multiple cache segments. After receiving the first read command and before executing the internal prefetch command, a second read command is received from the host or another host requesting second data stored on at least one disk that is not included in the first prefetched data or the additional prefetched data. The DSD according to claim 1, further configured to cache the additional prefetched data in the second cache segment before caching the requested second data in the cache segment of the plurality of cache segments.

4. The DSD according to claim 1, wherein the plurality of read commands are associated with at least two different read streams that request data stored on the at least one disk corresponding to a range of non-sequential logical addresses.

5. The aforementioned circuit, The plurality of read commands are determined to be associated with at least two different read streams that request data stored on the at least one disk corresponding to a range of non-sequential logical addresses, The DSD according to claim 1, further configured to execute the plurality of internal prefetch commands in response to determining that the plurality of read commands are associated with at least two different read streams, thereby caching the prefetched data in the respective cache segments.

6. The aforementioned circuit, The DSD according to claim 1, further configured to designate a cache segment as available for caching other data in response to the completion of a read command associated with the largest logical address of data cached in one of the plurality of cache segments.

7. The aforementioned circuit, The plurality of read commands are determined to be associated with at least two different read streams corresponding to a range of non-sequential logical addresses, The DSD according to claim 1, further configured to activate a multi-stream cache segment release policy that designates a cache segment among the plurality of cache segments for caching newly read data, based on the determination that the plurality of read commands are associated with at least two different read streams, in accordance with the completion of the read command associated with the maximum logical address of the data cached in each cache segment.

8. A method for managing a read cache in at least one memory of a data storage device (DSD), Receiving multiple read commands from one or more hosts to read data from at least one disk of the DSD, The data read from the at least one disk is cached in a plurality of cache segments of the read cache, wherein at least a portion of the cached data includes data requested for the plurality of received read commands. A method comprising: designating a cache segment as available for caching other data in response to the completion of a read command associated with the largest logical address of data cached in one of the plurality of cache segments.

9. The determination that the aforementioned multiple read commands are associated with at least two different read streams corresponding to a range of non-sequential logical addresses, The method of claim 8, further comprising: determining that the plurality of read commands are associated with at least two different read streams, and activating a multi-stream cache segment release policy that designates a cache segment among the plurality of cache segments for caching newly read data in response to the completion of a read command associated with the maximum logical address of data cached in each cache segment.

10. While the multi-stream cache segment release policy is active, Determining that there are no cache segments of the plurality of cache segments available for caching data to be read from at least one disk, The method according to claim 9, further comprising designating the longest unused cache segment among the plurality of cache segments as available for caching the data to be read, wherein the longest unused cache segment is the cache segment among the plurality of cache segments that has not been used for the longest time to complete a read command.

11. Determining that only one read stream is currently active, The method according to claim 9, further comprising: determining that only one read stream is currently active, deactivating the multi-stream cache segment release policy; and reactivating the longest unused policy, which designates a cache segment among the plurality of cache segments for caching newly read data that has not been used for the longest time to complete a read command.

12. The method according to claim 8, wherein each of the plurality of cache segments has a predetermined data storage capacity.

13. The process involves executing a plurality of internal prefetch commands to cache the prefetched data in each of the plurality of cache segments, wherein the prefetched data corresponds to a range of subsequent logical addresses that sequentially follows a range of different logical addresses containing the data requested for the plurality of read commands. The method according to claim 8, wherein the plurality of internal prefetch commands are executed in an order at least partially based on the total time required to move the head of the DSD to each of the positions on the at least one disk in order to execute the plurality of internal prefetch commands.

14. Receiving a first read command from a host requesting first data stored on at least one disk, wherein the first data corresponds to a first logical address within a range of initial logical addresses of the different ranges of logical addresses. In response to receiving the first read command, the first read command is executed by at least partially caching first prefetched data containing the requested first data in a first cache segment among the plurality of cache segments, wherein the first prefetched data corresponds to the range of the initial logical addresses. Executing one of the multiple internal prefetch commands to cache additional prefetched data in a second cache segment of the multiple cache segments, wherein the additional prefetched data corresponds to a first logical address range that follows sequentially after the initial logical address range. After receiving the first read command and before executing the internal prefetch command, a second read command is received from the host or another host, the second read command requests second data stored on the at least one disk that is not included in the first prefetched data or the additional prefetched data. The method according to claim 13, further comprising caching the additional prefetched data in the second cache segment before caching the requested second data in the cache segment of the plurality of cache segments.

15. Determining that the plurality of read commands are associated with at least two different read streams that request data stored on the at least one disk corresponding to a range of non-sequential logical addresses, The method of claim 13, further comprising: determining that the plurality of read commands are associated with at least two different read streams, executing the plurality of internal prefetch commands to cache the prefetched data in the respective cache segments.

16. A data storage device (DSD), At least one disk configured to store data, At least one head configured to read data from the at least one disk, At least one memory configured to store multiple cache segments for caching data read from the at least one disk, A means for receiving multiple read commands from one or more hosts, wherein each of the multiple read commands requests data corresponding to a different range of logical addresses stored on the at least one disk. Means for executing multiple internal prefetch commands and caching the prefetched data in each of the multiple cache segments, wherein the prefetched data corresponds to a subsequent range of logical addresses that sequentially follows the range of different logical addresses, The plurality of internal prefetch commands are executed in a DSD in an order at least partially based on the total time required to move the at least one head to each of the at least one disk locations in order to execute the plurality of internal prefetch commands.

17. The DSD according to claim 16, wherein each of the plurality of cache segments has a predetermined data storage capacity.

18. Means for receiving a first read command from a host requesting first data stored on at least one disk, wherein the first data corresponds to a first logical address within a range of initial logical addresses of different ranges of logical addresses. A means for executing the first read command by, in response to receiving the first read command, at least partially caching first prefetched data containing the requested first data in a first cache segment of the plurality of cache segments, wherein the first prefetched data corresponds to the range of the initial logical addresses, Means for executing an internal prefetch command among the plurality of internal prefetch commands to cache additional prefetched data in a second cache segment among the plurality of cache segments, wherein the additional prefetched data corresponds to a first logical address range that follows sequentially after the initial logical address range. Means for receiving a second read command from the host or another host after receiving the first read command and before executing the internal prefetch command, wherein the second read command requests second data stored on the at least one disk that is not included in the first prefetched data or the additional prefetched data. The DSD according to claim 16, further comprising means for caching the additional prefetched data in the second cache segment before caching the requested second data in the cache segment of the plurality of cache segments.

19. Means for determining that the plurality of read commands are associated with at least two different read streams that request data stored on the at least one disk corresponding to a range of non-sequential logical addresses, The DSD according to claim 16, further comprising means for executing the plurality of internal prefetch commands in response to determining that the plurality of read commands are associated with at least two different read streams, thereby caching the prefetched data in the respective cache segments.

20. The DSD according to claim 16, further comprising means for designating the cache segment as available for caching other data in response to the completion of a read command associated with the largest logical address of data cached in the cache segment among the plurality of cache segments.

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