Semiconductor circuits and semiconductor devices

Abstract

To provide semiconductor circuits that enable high-speed signal transmission. [Solution] The semiconductor circuit of the embodiment includes first and second first conductivity type transistors, first and second second conductivity type transistors, first to third resistors and capacitors, and first and second constant current sources. The first and second resistors are connected between the first power node and the first and second nodes, respectively, and the first and second nodes are connected to the first and second output nodes. One end and the other end of the first and second second conductivity type transistors are connected to the first and second nodes and the third and fourth nodes, respectively, and the gate ends are connected to the first and second input nodes. The first and second constant current sources are connected between the third and fourth nodes and the second power node, respectively, and the third resistor and capacitor are connected in parallel between the third and fourth nodes. The first and second first conductivity type transistors are connected between the first power node and the second and first input nodes, respectively, and the gate ends are connected to the first and second nodes.

Description

Technical Field

[0001] Embodiments relate to semiconductor circuits and semiconductor devices.

Background Art

[0002] Semiconductor circuits used for transmitting high-speed signals within an integrated circuit are known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a semiconductor circuit capable of realizing high-speed signal transmission.

Means for Solving the Problems

[0005] Note: The specific number in "U.S. Patent Application Publication No. **************" should be filled in according to the actual patent number. Here it is replaced with "**************" for the sake of generality.The semiconductor circuit of the embodiment includes first and second first-conductivity transistors, first and second second-conductivity transistors, first to third resistors, capacitors, and first and second constant current sources. The first resistor is connected between a first power supply node and a first node, and the first node is connected to a first output node. The second resistor is connected between a first power supply node and a second node, and the second node is connected to a second output node. One end and the other end of the first second-conductivity transistor are connected to a first node and a third node, respectively, and the gate terminal of the first second-conductivity transistor is connected to a first input node. One end and the other end of the second second-conductivity transistor are connected to a second node and a fourth node, respectively, and the gate terminal of the second second-conductivity transistor is connected to a second input node. One end and the other end of the first constant current source are connected to a third node and a second power supply node, respectively. One end and the other end of the second constant current source are connected to the fourth node and the second power supply node, respectively. The third resistor and the capacitor are connected in parallel between the third node and the fourth node. One end and the other end of the first first conductivity type transistor are connected to the first power supply node and the second input node, respectively, and the gate terminal of the first first conductivity type transistor is connected to the first node. One end and the other end of the second first conductivity type transistor are connected to the first power supply node and the first input node, respectively, and the gate terminal of the second first conductivity type transistor is connected to the second node. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a circuit diagram showing an example of the circuit configuration of a semiconductor circuit according to the first embodiment. [Figure 2] Figure 2 is a circuit diagram showing an example of the circuit configuration of a semiconductor circuit according to a modified example of the first embodiment. [Figure 3] Figure 3 is a schematic diagram showing an overview of the operation of the semiconductor circuit according to the first embodiment. [Figure 4] Figure 4 is a waveform diagram showing the simulation results of the operation of the semiconductor circuit according to the first embodiment. [Figure 5]Figure 5 is a waveform diagram showing a specific example of the operation of a semiconductor circuit according to the comparative example. [Figure 6] Figure 6 is a waveform diagram showing a specific example of the operation of a semiconductor circuit according to the first embodiment. [Figure 7] Figure 7 is a circuit diagram showing an example of the circuit configuration of a semiconductor circuit according to the second embodiment. [Figure 8] Figure 8 is a circuit diagram showing an example of the circuit configuration of a semiconductor circuit according to a modified example of the second embodiment. [Figure 9] Figure 9 is a circuit diagram showing an example of the circuit configuration of a semiconductor circuit according to the third embodiment. [Figure 10] Figure 10 is a circuit diagram showing an example of the circuit configuration of a semiconductor circuit according to a modified example of the third embodiment. [Figure 11] Figure 11 is a circuit diagram showing an example of the circuit configuration of a semiconductor circuit according to the first configuration example of the fourth embodiment. [Figure 12] Figure 12 is a circuit diagram showing an example of the circuit configuration of a semiconductor circuit according to the second configuration example of the fourth embodiment. [Figure 13] Figure 13 is a circuit diagram showing an example of the circuit configuration of a semiconductor circuit according to the third configuration example of the fourth embodiment. [Figure 14] Figure 14 is a circuit diagram showing an example of the circuit configuration of a semiconductor circuit according to the fourth configuration example of the fourth embodiment. [Figure 15] Figure 15 is a circuit diagram showing an example of the circuit configuration of a semiconductor circuit according to the fifth configuration example of the fourth embodiment. [Figure 16] Figure 16 is a circuit diagram showing an example of the circuit configuration of a semiconductor circuit according to the sixth configuration example of the fourth embodiment. [Figure 17] Figure 17 is a block diagram showing an example of the configuration of a semiconductor device according to the first configuration example of the fifth embodiment. [Figure 18] Figure 18 is a block diagram showing an example of the configuration of an input / output circuit in a semiconductor device according to the first configuration example of the fifth embodiment. [Figure 19] Figure 19 is a block diagram showing an example of the configuration of a data input circuit in a semiconductor device according to the first configuration example of the fifth embodiment. [Figure 20] FIG. 20 is a circuit diagram showing an example of the configuration of a C2C circuit included in a data input circuit in a semiconductor device according to the first configuration example of the fifth embodiment. [Figure 21] FIG. 21 is a circuit diagram showing an example of the configuration of a C2C circuit included in a data input circuit in a semiconductor device according to the first configuration example of the fifth embodiment. [Figure 22] FIG. 22 is a block diagram showing an example of the configuration of a semiconductor device according to the second configuration example of the fifth embodiment. [Figure 23] FIG. 23 is a block diagram showing an example of the configuration of a semiconductor device according to the third configuration example of the fifth embodiment. [Figure 24] FIG. 24 is a block diagram showing an example of the configuration of a semiconductor device according to the fourth configuration example of the fifth embodiment. [Figure 25] FIG. 25 is a block diagram showing an example of the configuration of a semiconductor device according to the fifth configuration example of the fifth embodiment. [Figure 26] FIG. 26 is a block diagram showing an example of the configuration of a semiconductor device according to the sixth configuration example of the fifth embodiment. [Figure 27] FIG. 27 is a block diagram showing an example of the configuration of a semiconductor device according to the seventh configuration example of the fifth embodiment. [Figure 28] FIG. 28 is a block diagram showing an example of the configuration of a semiconductor device according to the eighth configuration example of the fifth embodiment. [Figure 29] FIG. 29 is a circuit diagram showing an example of the circuit configuration of a constant current source composed of N-type transistors. [Figure 30] FIG. 30 is a circuit diagram showing an example of the circuit configuration of a constant current source composed of P-type transistors.

Embodiments for Carrying Out the Invention

[0007] Each embodiment will be described below with reference to the drawings. Each embodiment illustrates an apparatus or method for realizing the technical idea of ​​the invention. The drawings are schematic or conceptual. Diagrams of the components are omitted where appropriate. In this specification, components having substantially the same function and configuration are denoted by the same reference numeral. Numbers and letters added to reference numerals are used to distinguish similar elements that are referred to by the same reference numeral.

[0008] In this specification, N-type transistors NM and NT are, for example, N-type MOS transistors. P-type transistors PM and PT are, for example, P-type MOS transistors. Resistors R may be provided as elements or as wiring. Constant current source CS is a power supply circuit that controls the output current to a constant value. The power supply voltage is applied to the power supply node VDD. The ground voltage is applied to the ground node VSS. The power supply voltage is a voltage higher than the ground voltage. An input signal is input to the input node. An output signal is output from the output node. The voltages of the input node and output node are also called "input voltage" and "output voltage," respectively. The " / " appended to the reference code indicates that the inverted signal of the signal input to the node of the combined reference code is input or output.

[0009] <1> First Embodiment The semiconductor circuit 1 according to the first embodiment is a 2-input, 1-output (2 in 1 out) CML (Current Mode Logic) to CMOS circuit (hereinafter referred to as the "C2C circuit") having a configuration that feeds back the signal of an active inductor. The details of the semiconductor circuit 1 according to the first embodiment will be described below.

[0010] <1-1> Composition Figure 1 is a circuit diagram showing an example of the circuit configuration of semiconductor circuit 1 according to the first embodiment. As shown in Figure 1, semiconductor circuit 1 is a C2C circuit that receives small analog signals at input nodes IN and / IN and outputs a large digital signal from output node OUT. Semiconductor circuit 1 includes, for example, P-type transistors PM10 to PM12, N-type transistors NM10 and NM11, resistor R10, constant current source CS10, and nodes ND10 to ND12.

[0011] The source and drain terminals of the P-type transistor PM10 are connected to power node VDD and node ND10, respectively. The gate terminal of the P-type transistor PM10 is connected to node ND10 via resistor R10. The drain and source terminals of the N-type transistor NM10 are connected to nodes ND10 and ND12, respectively. The gate terminal of the N-type transistor NM10 is connected to input node IN.

[0012] The source and drain terminals of the P-type transistor PM11 are connected to the power node VDD and node ND11, respectively. The gate terminal of the P-type transistor PM11 is connected to node ND10. Node ND11 is connected to the output node OUT. The drain and source terminals of the N-type transistor NM11 are connected to nodes ND11 and ND12, respectively. The gate terminal of the N-type transistor NM11 is connected to the input node IN.

[0013] The input and output terminals of the constant current source CS10 are connected to node ND12 and the ground node VSS, respectively.

[0014] The source and drain terminals of the P-type transistor PM12 are connected to the power node VDD and the input node / IN, respectively. The gate terminal of the P-type transistor PM12 is connected to the gate terminal of the P-type transistor PM10. The P-type transistor PM12 may be smaller than the P-type transistor PM10. The size ratio of the P-type transistor PM12 to the P-type transistor PM10 is, for example, 1:1.2 to 7.

[0015] In the C2C circuit of the first embodiment, the transistor receiving the input signal may be a P-type transistor. Below, a semiconductor device 1A having a PMOS transistor receiving the input signal will be described as a modified C2C circuit of the first embodiment.

[0016] Figure 2 is a circuit diagram showing an example of the circuit configuration of a semiconductor circuit 1A according to a modified example of the first embodiment. As shown in Figure 2, the semiconductor circuit 1A includes, for example, P-type transistors PM13 and PM14, N-type transistors NM12 to NM14, resistor R11, constant current source CS11, and nodes ND13 to ND15.

[0017] The input and output terminals of the constant current source CS11 are connected to power node VDD and node ND13, respectively.

[0018] The source and drain terminals of the P-type transistor PM13 are connected to nodes ND13 and ND14, respectively. The gate terminal of the P-type transistor PM13 is connected to the input node IN. The drain and source terminals of the N-type transistor NM12 are connected to node ND14 and the ground node VSS, respectively. The gate terminal of the N-type transistor NM12 is connected to node ND14 via resistor R11.

[0019] The source and drain terminals of the P-type transistor PM14 are connected to nodes ND13 and ND15, respectively. The gate terminal of the P-type transistor PM14 is connected to the input node / IN. Node ND15 is connected to the output node OUT. The drain and source terminals of the N-type transistor NM13 are connected to node ND15 and the ground node VSS, respectively. The gate terminal of the N-type transistor NM13 is connected to node ND14.

[0020] The drain and source terminals of the N-type transistor NM14 are connected to the input node / IN and the ground node VSS, respectively. The gate terminal of the N-type transistor NM14 is connected to the gate terminal of the N-type transistor NM12. The N-type transistor NM14 may be smaller than the N-type transistor NM12. The size ratio of the N-type transistor NM14 to the N-type transistor NM12 is, for example, 1:1.2 to 7.

[0021] <1-2> Operation Figure 3 is a schematic diagram showing an overview of the operation of semiconductor circuit 1 according to the first embodiment. As shown in Figure 3, in semiconductor circuit 1, a parasitic capacitance PC is formed at the gate terminal of the P-type transistor PM10. In semiconductor circuit 1, the combination of the parasitic capacitance PC and resistor R10 functions as an RC filter. As a result, the combination of the P-type transistor PM10, the parasitic capacitance PC, and resistor R10 functions as an active inductor. Then, in semiconductor circuit 1, the P-type transistor PM12 feeds back the signal from the active inductor to the input node / IN.

[0022] Specifically, the on / off states of N-type transistors NM10 and NM11 change in response to the input signals IN and / IN. As a result, the voltage at node ND10 changes according to the state of N-type transistors NM10 and NM11. When a high-frequency signal is input to input nodes IN and / IN, the parasitic capacitance PC is charged when N-type transistor NM10 is in the ON state. Consequently, the high-frequency signal at the gate terminal of P-type transistor PM10 can be suppressed and become a DC signal. In semiconductor circuit 1, the gate terminal of P-type transistor PM12 is connected to the gate terminal of P-type transistor PM10, and P-type transistor PM12 is connected between the power supply node VDD and the input node / IN. This allows P-type transistor PM12 to feed back a signal based on the voltage at the gate terminal of P-type transistor PM10 to node / IN, thereby reducing the gain near DC of semiconductor circuit 1.

[0023] Furthermore, in semiconductor circuit 1A, similar to semiconductor circuit 1, the N-type transistor NM14 can feed back a signal based on the gate terminal voltage of the N-type transistor NM12 to node / IN, thereby reducing the DC gain of semiconductor circuit 1A.

[0024] <1-3> Effects of the First Embodiment The semiconductor circuits 1 and 1A according to the first embodiment described above enable high-speed signal transmission. The effects of the first embodiment will be described in detail below.

[0025] The frequency of signals used to transmit and receive data between two devices tends to increase as data communication speeds rise. Therefore, it is desirable that the circuits used for signal transmission be able to handle high-frequency signals. However, as signal frequencies increase, the receiving circuit may not be able to achieve full swing, potentially causing skew.

[0026] One way to suppress skew is to include multiple CMLs in the input node's path to reduce the gain near DC. Reducing the gain near DC allows for full swing in the receiving circuit, enabling high-speed operation. However, including multiple CMLs in the input node's path requires a large circuit area and high current consumption, which can increase the cost of the semiconductor circuit.

[0027] Therefore, the semiconductor circuits 1 and 1A according to the first embodiment include a transistor that operates based on the voltage of an active inductor. This allows the semiconductor circuits 1 and 1A to feed back a voltage based on a signal input to input node IN to the corresponding input node / IN.

[0028] Figure 4 is a waveform diagram showing the simulation results of the operation of the semiconductor circuit 1 according to the first embodiment. Figure 4 shows the change in voltage at the output node of the semiconductor circuit 1 when the signal input to the input node changes from a DC signal to a high-frequency signal. The change in voltage at the output node of the semiconductor circuit 1 corresponding to the first embodiment is shown by a dashed line. In addition, as a comparative example, the simulation results when the P-type transistor PM12 is omitted from the semiconductor circuit 1 are shown by a solid line in Figure 4.

[0029] As shown in Figure 4, in the comparative example, DX is the difference between the output voltage based on the DC signal and the peak output voltage during the first swing when the signal changes from DC to high frequency. On the other hand, in the first embodiment, DY is smaller than DX, the difference between the output voltage based on the DC signal and the peak output voltage during the first swing when the signal changes from DC to high frequency. In other words, in the semiconductor circuit 1 according to the first embodiment, the gain near DC of the semiconductor circuit 1 (transmission circuit) is reduced by the P-type transistor PM12. The semiconductor circuit 1A can also reduce the gain near DC by the N-type transistor NM14, similar to the semiconductor circuit 1.

[0030] Figures 5 and 6 are waveform diagrams showing specific examples of the operation of semiconductor circuit 1. Figures 5 and 6 correspond to a comparative example and the first embodiment, respectively. The waveforms shown in (A) of Figures 5 and 6 show the timing of the transition between the "L" level and the "H" level of the signal input to semiconductor circuit 1. The waveforms shown in (B) of Figures 5 and 6 show the output signal of semiconductor circuit 1 based on the signal shown in (A). Regions AR1 to AR3 shown in (B) of Figures 5 and 6 extract a period of one pulse. Specifically, region AR1 extracts the output voltage waveform when a "H" level signal is input from a "L" level DC signal for one pulse. Region AR2 extracts the output voltage waveform when a high-frequency signal is input. Region AR3 extracts the output voltage waveform when a "L" level signal is input from an "H" level DC signal for one pulse.

[0031] As shown in Figure 5(B), in each of the comparative example's regions AR1 to AR3, the output voltage is not able to swing fully. Specifically, in the comparative example, the difference (amplitude) between the output voltage based on the "L" level DC signal and the output voltage based on the "H" level DC signal is shown as "A1". In the comparative example, the amount of fluctuation in the output voltage is smaller than A1 in all of the regions AR1 to AR3. Figure 5(C) shows the waveforms of regions AR1 and AR3 in the comparative example superimposed so that the timing of the transition from "L" level to "H" level is aligned. As shown in Figure 5(C), in each of the comparative example's regions AR1 and AR3, since full swing is not achieved, the timing of crossing the threshold used to determine the "H" level and "L" level is different when transitioning from the "L" level to the "H" level. In other words, skew can occur in the comparative example.

[0032] On the other hand, as shown in Figure 6(B), the output voltage can swing fully in each of the regions AR1 to AR3 of the first embodiment. Specifically, in the first embodiment, the difference (amplitude) between the output voltage based on the "L" level DC signal and the output voltage based on the "H" level DC signal is shown as "A2". In the first embodiment, the amount of fluctuation in the output voltage is equivalent to A2 in all of the regions AR1 to AR3. Figure 6(C) shows the waveforms of regions AR1 and AR3 in the first embodiment superimposed. As shown in Figure 6(C), since the output voltage can swing fully in each of the regions AR1 and AR3 of the first embodiment, the timing of crossing the threshold used to determine the "H" level and the "L" level when transitioning from the "L" level to the "H" level is approximately simultaneous. In other words, skew can be suppressed in the first embodiment.

[0033] As described above, the semiconductor circuits 1 and 1A according to the first embodiment can improve the output voltage to a state closer to full swing than when the voltage of the active inductor is not fed back. As a result, the semiconductor circuits 1 and 1A can improve skew and achieve high-speed operation corresponding to high frequencies. In other words, the semiconductor circuits 1 and 1A can achieve high-speed signal transmission.

[0034] Furthermore, in semiconductor circuits 1 and 1A according to the first embodiment, there is only one transistor added to feed back the voltage of the active inductor. Such a single transistor achieves the same effect as when multiple CMLs are provided in the input node path. Therefore, semiconductor circuits 1 and 1A according to the first embodiment can realize circuits with a smaller area than when multiple CMLs are provided in the input node path.

[0035] In the first embodiment, the example given was a case where there is one transistor added to feed back the voltage of the active inductor, but the invention is not limited to this. Depending on the layout of the circuit area around semiconductor circuits 1 and 1A according to the first embodiment, the P-type transistor PM12 and N-type transistor NM14 may be composed of multiple transistors. Specifically, for example in semiconductor circuit 1, the gate terminals of multiple P-type transistors PM12 are connected to the gate terminals of P-type transistors PM10, and the multiple P-type transistors PM12 are connected between the power node VDD and the input node / IN. The total size of the multiple P-type transistors PM12 may be smaller than that of the P-type transistor PM10. The ratio of the total size of the multiple P-type transistors PM12 to the size of the P-type transistor PM10 is, for example, 1:1.2 to 7. Specifically, for example in semiconductor circuit 1A, the drain terminals and source terminals of multiple N-type transistors NM14 are connected to the input node / IN and the ground node VSS, respectively. The gate terminals of the multiple N-type transistors NM14 are connected to the gate terminals of N-type transistors NM12. The combined size of multiple N-type transistors NM14 may be smaller than that of an N-type transistor NM12. The ratio of the combined size of multiple N-type transistors NM14 to the size of an N-type transistor NM12 is, for example, 1:1.2 to 7.

[0036] Furthermore, it is preferable that the semiconductor circuits 1 and 1A according to the first embodiment be used interchangeably depending on the input signal (input circuit). By using the NMOS-based semiconductor circuit 1 and the PMOS-based semiconductor circuit 1A interchangeably depending on the characteristics of the input signal, high-speed signal transmission with more desirable efficiency can be achieved.

[0037] <2> Second Embodiment The semiconductor circuit 2 according to the second embodiment is a 2-input, 2-output (2 in 2 out) differential amplifier circuit having a configuration that feeds back the signal from an active inductor. The details of the semiconductor circuit 2 according to the second embodiment will be described below.

[0038] <2-1> Composition Figure 7 is a circuit diagram showing an example of the circuit configuration of the semiconductor circuit 2 according to the second embodiment. As shown in Figure 7, the semiconductor circuit 2 is a differential amplifier circuit that amplifies the difference between two input voltages input to input nodes IN and / IN, respectively, and outputs it from output nodes OUT and / OUT. The semiconductor circuit 2 includes, for example, P-type transistors PM20 to PM23, N-type transistors NM20 and NM21, resistors R20 and R21, a constant current source CS20, and nodes ND20 to ND22.

[0039] The source and drain terminals of the P-type transistor PM20 are connected to power supply nodes VDD and ND20, respectively. The gate terminal of the P-type transistor PM20 is connected to node ND20 via resistor R20. Node ND20 is connected to output node OUT. The drain and source terminals of the N-type transistor NM20 are connected to nodes ND20 and ND22, respectively.

[0040] The source and drain terminals of the P-type transistor PM21 are connected to power supply nodes VDD and ND21, respectively. The gate terminal of the P-type transistor PM21 is connected to node ND21 via resistor R21. Node ND21 is connected to the output node / OUT. The drain and source terminals of the N-type transistor NM21 are connected to nodes ND21 and ND22, respectively.

[0041] The input and output terminals of the constant current source CS20 are connected to node ND22 and the ground node VSS, respectively.

[0042] The source and drain terminals of the P-type transistor PM22 are connected to the power node VDD and the input node / IN, respectively. The gate terminal of the P-type transistor PM22 is connected to the gate terminal of the P-type transistor PM20. The P-type transistor PM22 may be smaller than the P-type transistor PM20. The size ratio of the P-type transistor PM22 to the P-type transistor PM20 is, for example, 1:1.2 to 7.

[0043] The source and drain terminals of the P-type transistor PM23 are connected to the power node VDD and the input node IN, respectively. The gate terminal of the P-type transistor PM23 is connected to the gate terminal of the P-type transistor PM21. The P-type transistor PM23 may be smaller than the P-type transistor PM21. The size ratio of the P-type transistor PM23 to the P-type transistor PM21 is, for example, 1:1.2 to 7.

[0044] In the differential amplifier circuit of the second embodiment, the transistor that receives the input signal may be a P-type transistor. Below, a semiconductor device 2A having a PMOS transistor that receives the input signal will be described as a differential amplifier circuit of the second embodiment.

[0045] Figure 8 is a circuit diagram showing an example of the circuit configuration of a semiconductor circuit 2A according to a modified example of the second embodiment. As shown in Figure 8, the semiconductor circuit 2A includes, for example, P-type transistors PM24 and PM25, N-type transistors NM22 to NM25, resistors R22 and R23, a constant current source CS21, and nodes ND23 to ND25.

[0046] The input and output terminals of the constant current source CS21 are connected to power node VDD and node ND23, respectively.

[0047] The source and drain terminals of the P-type transistor PM24 are connected to nodes ND23 and ND24, respectively. The gate terminal of the P-type transistor PM24 is connected to the input node IN. Node ND24 is connected to the output node OUT. The drain and source terminals of the N-type transistor NM22 are connected to node ND24 and the ground node VSS, respectively. The gate terminal of the N-type transistor NM22 is connected to node ND24 via resistor R22.

[0048] The source and drain terminals of the P-type transistor PM25 are connected to nodes ND23 and ND25, respectively. The gate terminal of the P-type transistor PM25 is connected to the input node / IN. Node ND25 is connected to the output node / OUT. The drain and source terminals of the N-type transistor NM23 are connected to node ND25 and the ground node VSS, respectively. The gate terminal of the N-type transistor NM23 is connected to node ND25 via resistor R23.

[0049] The drain and source terminals of the N-type transistor NM24 are connected to the input node / IN and the ground node VSS, respectively. The gate terminal of the N-type transistor NM24 is connected to the gate terminal of the N-type transistor NM22. The N-type transistor NM24 may be smaller than the N-type transistor NM22. The size ratio of the N-type transistor NM24 to the N-type transistor NM22 is, for example, 1:1.2 to 7.

[0050] The drain and source terminals of the N-type transistor NM25 are connected to the input node IN and the ground node VSS, respectively. The gate terminal of the N-type transistor NM25 is connected to the gate terminal of the N-type transistor NM23. The N-type transistor NM25 may be smaller than the N-type transistor NM23. The size ratio of the N-type transistor NM25 to the N-type transistor NM23 is, for example, 1:1.2 to 7.

[0051] <2-2> Effects of the second embodiment In semiconductor circuit 2, P-type transistor PM22 feeds back a signal based on the gate terminal voltage of P-type transistor PM20, which corresponds to the active inductor, to node / IN. Furthermore, in semiconductor circuit 2, P-type transistor PM23 feeds back a signal based on the gate terminal voltage of P-type transistor PM21, which corresponds to the active inductor, to node IN. As a result, semiconductor circuit 2 can reduce the gain near DC.

[0052] Similarly, in semiconductor circuit 2A, the N-type transistor NM24 feeds back a signal to node / IN based on the voltage at the gate terminal of the N-type transistor NM22, which corresponds to the active inductor. Furthermore, in semiconductor circuit 2A, the N-type transistor NM25 feeds back a signal to node IN based on the voltage at the gate terminal of the N-type transistor NM23, which corresponds to the active inductor. As a result, semiconductor circuit 2A can reduce the gain near DC.

[0053] Therefore, the semiconductor circuits 2 and 2A according to the second embodiment can improve the output voltage to a state close to full swing, similar to the first embodiment. As a result, the semiconductor circuits 2 and 2A can improve skew and achieve high-speed operation corresponding to high frequencies. Furthermore, the semiconductor circuits 2 and 2A according to the second embodiment can be implemented with small area circuits, similar to the first embodiment. Moreover, by using the semiconductor circuits 2 and 2A according to the second embodiment differently depending on the input signal, it is possible to achieve high-speed signal transmission with more desirable efficiency.

[0054] <3> Third Embodiment The semiconductor circuit 3 according to the third embodiment is a 2-input, 2-output (2 in 2 out) continuous time linear equalizer (CTLE) that, like an active inductor, has a configuration that feeds back the signals of the operating node. The details of the semiconductor circuit 3 according to the third embodiment will be described below.

[0055] <3-1> Composition Figure 9 is a circuit diagram showing an example of the circuit configuration of the semiconductor circuit 3 according to the third embodiment. As shown in Figure 9, the semiconductor circuit 3 is a CTLE that amplifies two input voltages input to input nodes IN and / IN, respectively, and outputs them from output nodes OUT and / OUT. The semiconductor circuit 3 can amplify a specific frequency band of the signal. The semiconductor circuit 3 includes, for example, P-type transistors PM30 and PM31, N-type transistors NM30 and NM31, resistors R30 to R32, capacitive elements (capacitors) CP30, constant current sources CS30 and CS31, and nodes ND30 to ND33.

[0056] Node ND30 is connected to the output node OUT. Node ND30 is connected to the power node VDD via resistor R30. The drain and source terminals of the N-type transistor NM30 are connected to nodes ND30 and ND32, respectively. The input and output terminals of the constant current source CS30 are connected to node ND32 and the ground node VSS, respectively.

[0057] Node ND31 is connected to the output node / OUT. Node ND31 is connected to the power node VDD via resistor R31. The drain and source terminals of the N-type transistor NM31 are connected to nodes ND31 and ND33, respectively. The input and output terminals of the constant current source CS31 are connected to node ND33 and the ground node VSS, respectively.

[0058] A resistor R32 and a capacitive element CP30 are connected in parallel between nodes ND32 and ND33. Resistor R32 and capacitive element CP30 function as an RC filter.

[0059] The source and drain terminals of the P-type transistor PM30 are connected to the power node VDD and the input node / IN, respectively. The gate terminal of the P-type transistor PM30 is connected to node ND30.

[0060] The source and drain terminals of the P-type transistor PM31 are connected to the power node VDD and the input node IN, respectively. The gate terminal of the P-type transistor PM31 is connected to node ND31.

[0061] In the CTLE of the third embodiment, the transistor receiving the input signal may be a P-type transistor. Below, a semiconductor device 3A having a PMOS transistor receiving the input signal will be described as a modified CTLE of the third embodiment.

[0062] Figure 10 is a circuit diagram showing an example of the circuit configuration of a semiconductor circuit 3A according to a modified example of the third embodiment. As shown in Figure 10, the semiconductor circuit 3A includes, for example, P-type transistors PM32 and PM33, N-type transistors NM32 and NM33, resistors R33 to R35, capacitive element CP31, constant current sources CS32 and CS33, and nodes ND34 to ND37.

[0063] The input and output terminals of the constant current source CS32 are connected to power node VDD and node ND34, respectively. The source and drain terminals of the P-type transistor PM32 are connected to nodes ND34 and ND36, respectively. Node ND36 is connected to the output node OUT. Node ND36 is connected to the ground node VSS via resistor R34.

[0064] The input and output terminals of the constant current source CS33 are connected to power supply nodes VDD and ND35, respectively. The source and drain terminals of the P-type transistor PM33 are connected to nodes ND35 and ND37, respectively. Node ND37 is connected to the output node / OUT. Node ND37 is connected to the ground node VSS via resistor R35.

[0065] A resistor R33 and a capacitive element CP31 are connected in parallel between nodes ND34 and ND35. The resistor R33 and the capacitive element CP31 function as an RC filter.

[0066] The drain and source terminals of the N-type transistor NM32 are connected to the input node / IN and the ground node VSS, respectively. The gate terminal of the N-type transistor NM32 is connected to node ND36.

[0067] The drain and source terminals of the N-type transistor NM33 are connected to the input node IN and the ground node VSS, respectively. The gate terminal of the N-type transistor NM33 is connected to node ND37.

[0068] Furthermore, the resistance values ​​of resistors R32 and R33, and the capacitance values ​​of capacitive elements CP30 and CP31, included in semiconductor circuits 3 and 3A, may be configured to be adjustable based on control signals input from an external source.

[0069] <3-2> Effects of the Third Embodiment In semiconductor circuit 3, the P-type transistor PM30 feeds back a signal based on the voltage of node ND30, which operates similarly to an active inductor, to node / IN. Furthermore, in semiconductor circuit 3, the P-type transistor PM31 feeds back a signal based on the voltage of node ND31, which operates similarly to an active inductor, to node IN. As a result, semiconductor circuit 3 can reduce the gain near DC.

[0070] Similarly, in semiconductor circuit 3A, the N-type transistor NM32 feeds back a signal based on the voltage of node ND36, which operates similarly to an active inductor, to node / IN. Furthermore, in semiconductor circuit 3A, the N-type transistor NM33 feeds back a signal based on the voltage of node ND37, which operates similarly to an active inductor, to node IN. As a result, semiconductor circuit 3A can reduce the gain near DC.

[0071] Therefore, the semiconductor circuits 3 and 3A according to the third embodiment can improve the output voltage to a state close to full swing, similar to the first embodiment. As a result, the semiconductor circuits 3 and 3A can improve skew and achieve high-speed operation corresponding to high frequencies. Furthermore, the semiconductor circuits 3 and 3A according to the third embodiment can be implemented with small area circuits, similar to the first embodiment. Moreover, by using the semiconductor circuits 3 and 3A according to the third embodiment selectively depending on the input signal, high-speed signal transmission with more desirable efficiency can be achieved.

[0072] <4> Fourth Embodiment The semiconductor circuit according to the fourth embodiment has a configuration in which a circuit is added to each of the semiconductor circuits 1, 1A, 2, 2A, 3, and 3A of the first to third embodiments that allows switching whether or not to use a transistor that feeds back the signal of the active inductor. The details of the semiconductor circuit according to the fourth embodiment will be described below.

[0073] <4-1> Composition Hereinafter, semiconductor device 1 to which the fourth embodiment is applied will be referred to as semiconductor circuit 1B according to the first configuration example of the fourth embodiment. Semiconductor device 1A to which the fourth embodiment is applied will be referred to as semiconductor circuit 1C according to the second configuration example of the fourth embodiment. Semiconductor device 2 to which the fourth embodiment is applied will be referred to as semiconductor circuit 2B according to the third configuration example of the fourth embodiment. Semiconductor device 2A to which the fourth embodiment is applied will be referred to as semiconductor circuit 2C according to the fourth configuration example of the fourth embodiment. Semiconductor device 3 to which the fourth embodiment is applied will be referred to as semiconductor circuit 3B according to the fifth configuration example of the fourth embodiment. Semiconductor device 3A to which the fourth embodiment is applied will be referred to as semiconductor circuit 3C according to the sixth configuration example of the fourth embodiment.

[0074] <Example Configuration 1: C2C Circuit (NMOS-based)> Figure 11 is a circuit diagram showing an example of the circuit configuration of semiconductor circuit 1B according to the first configuration example of the fourth embodiment. As shown in Figure 11, semiconductor circuit 1B has a configuration in which, for example, P-type transistors PM15 and PM16 and P-type transistors PT10 to PT12 are added to semiconductor circuit 1.

[0075] In semiconductor circuit 1B, a circuit similar to that of semiconductor circuit 1 is formed by P-type transistors PM10 to PM12, N-type transistors NM10 and NM11, resistor R10, constant current source CS10, and nodes ND10 to ND12, which correspond to semiconductor circuit 1.

[0076] The drain terminals of P-type transistors PM15 and PM16 are connected to the input node / IN. The gate terminals of P-type transistors PM15 and PM16 are connected to the gate terminal of P-type transistor PM10.

[0077] P-type transistor PT10 is connected between the power node VDD and the source terminal of P-type transistor PM12. P-type transistor PT11 is connected between the power node VDD and the source terminal of P-type transistor PM15. P-type transistor PT12 is connected between the power node VDD and the source terminal of P-type transistor PM16.

[0078] In other words, the source terminals of the P-type transistors PT10 to PT12 are connected to the power node VDD. The drain terminal of P-type transistor PT10 is connected to the source terminal of P-type transistor PM12. The drain terminal of P-type transistor PT11 is connected to the source terminal of P-type transistor PM15. The drain terminal of P-type transistor PT12 is connected to the source terminal of P-type transistor PM16.

[0079] The gate terminal of the P-type transistor PT10 is input with control signal EN10. The gate terminal of the P-type transistor PT11 is input with control signal EN11. The gate terminal of the P-type transistor PT12 is input with control signal EN12. Control signals EN10 to EN12 are signals that can be individually controlled by an external control circuit. The on / off state of each of the P-type transistors PT10 to PT12 can be controlled based on control signals EN10 to EN12.

[0080] In the first configuration example of the fourth embodiment, the number of pairs of P-type transistors PM and PT (for example, P-type transistors PM12 and PT10) connected in series between the power supply node VDD and the input node / IN may be one or more. In the first configuration example of the fourth embodiment, it is sufficient that multiple P-type transistors PT included in multiple pairs of P-type transistors PM and PT connected in series between the power supply node VDD and the input node / IN are configured to be individually controllable on / off.

[0081] <Second Configuration Example: C2C Circuit (PMOS-based)> Figure 12 is a circuit diagram showing an example of the circuit configuration of semiconductor circuit 1C according to the second configuration example of the fourth embodiment. As shown in Figure 12, semiconductor circuit 1C has a configuration in which, for example, N-type transistors NM15 and NM16 and N-type transistors NT10 to NT12 are added to semiconductor circuit 1A.

[0082] In semiconductor circuit 1C, a circuit similar to that in semiconductor circuit 1A is formed by P-type transistors PM13 and PM14, N-type transistors NM12 to NM14, resistor R11, constant current source CS11, and nodes ND13 to ND15.

[0083] The drain terminals of N-type transistors NM15 and NM16 are connected to the input node / IN. The gate terminals of N-type transistors NM15 and NM16 are connected to the gate terminal of N-type transistor NM12.

[0084] N-type transistor NT10 is connected between N-type transistor NM14 and the ground node VSS. N-type transistor NT11 is connected between N-type transistor NM15 and the ground node VSS. N-type transistor NT12 is connected between N-type transistor NM16 and the ground node VSS. Specifically, the source terminals of N-type transistors NT10 to NT12 are connected to the ground node VSS. The drain terminal of N-type transistor NT10 is connected to the source terminal of N-type transistor NM14. The drain terminal of N-type transistor NT11 is connected to the source terminal of N-type transistor NM15. The drain terminal of N-type transistor NT12 is connected to the source terminal of N-type transistor NM16.

[0085] The gate terminal of N-type transistor NT10 is input with control signal EN10. The gate terminal of N-type transistor NT11 is input with control signal EN11. The gate terminal of N-type transistor NT12 is input with control signal EN12. The on / off state of each of the N-type transistors NT10 to NT12 can be controlled based on the control signals EN10 to EN12.

[0086] In the second configuration example of the fourth embodiment, the number of pairs of N-type transistors NM and NT (for example, N-type transistors NM14 and NT10) connected in series between the input node / IN and the ground node VSS is one or more. In the second configuration example of the fourth embodiment, it is sufficient that multiple N-type transistors NT included in multiple pairs of N-type transistors NM and NT connected in series between the input node / IN and the ground node VSS are configured to be individually controllable on / off.

[0087] <Third Configuration Example: Differential Amplifier Circuit (NMOS-based)> Figure 13 is a circuit diagram showing an example of the circuit configuration of semiconductor circuit 2B according to the third configuration example of the fourth embodiment. As shown in Figure 13, semiconductor circuit 2B has a configuration in which, for example, P-type transistors PM26 and PM27 and P-type transistors PT20 to PT23 are added to semiconductor circuit 2.

[0088] In semiconductor circuit 2B, a circuit similar to that in semiconductor circuit 2 is formed by P-type transistors PM20 to PM23, N-type transistors NM20 and NM21, resistors R20 and R21, constant current source CS20, and nodes ND20 to ND22.

[0089] The drain terminal of P-type transistor PM26 is connected to the input node / IN. The gate terminal of P-type transistor PM26 is connected to the gate terminal of P-type transistor PM20. The drain terminal of P-type transistor PM27 is connected to the input node IN. The gate terminal of P-type transistor PM27 is connected to the gate terminal of P-type transistor PM21.

[0090] P-type transistor PT20 is connected between power node VDD and P-type transistor PM22. P-type transistor PT21 is connected between power node VDD and P-type transistor PM26. P-type transistor PT22 is connected between power node VDD and P-type transistor PM23. P-type transistor PT23 is connected between power node VDD and P-type transistor PM27. Specifically, the source terminals of each of the P-type transistors PT20 to PT23 are connected to power node VDD. The drain terminal of P-type transistor PT20 is connected to the source terminal of P-type transistor PM22. The drain terminal of P-type transistor PT21 is connected to the source terminal of P-type transistor PM26. The drain terminal of P-type transistor PT22 is connected to the source terminal of P-type transistor PM23. The drain terminal of P-type transistor PT23 is connected to the source terminal of P-type transistor PM27.

[0091] The gate terminal of the P-type transistor PT20 is input with control signal EN20. The gate terminal of the P-type transistor PT21 is input with control signal EN21. The gate terminal of the P-type transistor PT22 is input with control signal EN22. The gate terminal of the P-type transistor PT23 is input with control signal EN23. Control signals EN20 to EN23 are signals that can be individually controlled by an external control circuit. The on / off state of each of the P-type transistors PT20 to PT23 can be controlled based on control signals EN20 to EN23.

[0092] In the third configuration example of the fourth embodiment, the number of pairs of P-type transistors PM and PT (for example, P-type transistors PM22 and PT20) connected in series between the power supply node VDD and the input node IN or / IN may be one or more. In the third configuration example of the fourth embodiment, it is sufficient that multiple P-type transistors PT included in multiple pairs of P-type transistors PM and PT connected in series between the power supply node VDD and the input node IN or / IN are configured to be individually controllable on / off. As for the pairs of P-type transistors PM and PT, at least one of those connected to the input node IN and one connected to the input node / IN may be provided.

[0093] <Fourth Configuration Example: Differential Amplifier Circuit (PMOS-based)> Figure 14 is a circuit diagram showing an example of the circuit configuration of semiconductor circuit 2C according to the fourth configuration example of the fourth embodiment. As shown in Figure 14, semiconductor circuit 2C has a configuration in which, for example, N-type transistors NM26 and NM27 and N-type transistors NT20 to NT23 are added to semiconductor circuit 2A.

[0094] In semiconductor circuit 2C, a circuit similar to that in semiconductor circuit 2A is formed by P-type transistors PM24 and PM25, N-type transistors NM22 to NM25, resistors R22 and R23, constant current source CS21, and nodes ND23 to ND25.

[0095] The drain terminal of N-type transistor NM26 is connected to the input node / IN. The gate terminal of N-type transistor NM26 is connected to the gate terminal of N-type transistor NM22. The drain terminal of N-type transistor NM27 is connected to the input node IN. The gate terminal of N-type transistor NM27 is connected to the gate terminal of N-type transistor NM23.

[0096] N-type transistor NT20 is connected between N-type transistor NM24 and the ground node VSS. N-type transistor NT21 is connected between N-type transistor NM26 and the ground node VSS. N-type transistor NT22 is connected between N-type transistor NM25 and the ground node VSS. N-type transistor NT23 is connected between N-type transistor NM27 and the ground node VSS. Specifically, the source terminals of N-type transistors NT20 to NT23 are connected to the ground node VSS. The drain terminal of N-type transistor NT20 is connected to the source terminal of N-type transistor NM24. The drain terminal of N-type transistor NT21 is connected to the source terminal of N-type transistor NM26. The drain terminal of N-type transistor NT22 is connected to the source terminal of N-type transistor NM25. The drain terminal of N-type transistor NT23 is connected to the source terminal of N-type transistor NM27.

[0097] The gate terminal of N-type transistor NT20 is input with control signal EN20. The gate terminal of N-type transistor NT21 is input with control signal EN21. The gate terminal of N-type transistor NT22 is input with control signal EN22. The gate terminal of N-type transistor NT23 is input with control signal EN23. The on / off state of each of the N-type transistors NT20 to NT23 can be controlled based on the control signals EN20 to EN23.

[0098] In the fourth configuration example of the fourth embodiment, the number of pairs of N-type transistors NM and NT (for example, N-type transistors NM24 and NT20) connected in series between the input node IN or / IN and the ground node VSS may be one or more. In the fourth configuration example of the fourth embodiment, it is sufficient that multiple N-type transistors NT included in multiple pairs of N-type transistors NM and NT connected in series between the input node IN or / IN and the ground node VSS are configured to be individually controllable on / off. As for the pairs of N-type transistors NM and NT, it is sufficient that at least one of those connected to the input node IN and the input node / IN is provided.

[0099] <Example Configuration 5: CTLE (NMOS-based)> Figure 15 is a circuit diagram showing an example of the circuit configuration of semiconductor circuit 3B according to the fifth configuration example of the fourth embodiment. As shown in Figure 15, semiconductor circuit 3B has a configuration in which, for example, P-type transistors PM34 and PM35 and P-type transistors PT30 to PT33 are added to semiconductor circuit 3.

[0100] In semiconductor circuit 3B, a circuit similar to that in semiconductor circuit 3 is formed by P-type transistors PM30 and PM31, N-type transistors NM30 and NM31, resistors R30 to R32, capacitive element CP30, constant current sources CS30 and CS31, and nodes ND30 to ND33.

[0101] The drain terminal of P-type transistor PM34 is connected to the input node / IN. The gate terminal of P-type transistor PM34 is connected to the gate terminal of P-type transistor PM30. The drain terminal of P-type transistor PM35 is connected to the input node IN. The gate terminal of P-type transistor PM35 is connected to the gate terminal of P-type transistor PM31.

[0102] P-type transistor PT30 is connected between power node VDD and P-type transistor PM30. P-type transistor PT31 is connected between power node VDD and P-type transistor PM34. P-type transistor PT32 is connected between power node VDD and P-type transistor PM31. P-type transistor PT33 is connected between power node VDD and P-type transistor PM35. Specifically, the source terminals of P-type transistors PT30 to PT33 are connected to power node VDD. The drain terminal of P-type transistor PT30 is connected to the source terminal of P-type transistor PM30. The drain terminal of P-type transistor PT31 is connected to the source terminal of P-type transistor PM34. The drain terminal of P-type transistor PT32 is connected to the source terminal of P-type transistor PM31. The drain terminal of P-type transistor PT33 is connected to the source terminal of P-type transistor PM35.

[0103] The gate terminal of the P-type transistor PT30 is input with control signal EN30. The gate terminal of the P-type transistor PT31 is input with control signal EN31. The gate terminal of the P-type transistor PT32 is input with control signal EN32. The gate terminal of the P-type transistor PT33 is input with control signal EN33. Control signals EN30 to EN33 are signals that can be individually controlled by an external control circuit. The on / off state of each of the P-type transistors PT30 to NT33 can be controlled based on control signals EN30 to EN33.

[0104] In the fifth configuration example of the fourth embodiment, the number of pairs of P-type transistors PM and PT (for example, P-type transistors PM30 and PT30) connected in series between the power supply node VDD and the input node IN or / IN may be one or more. In the fifth configuration example of the fourth embodiment, it is sufficient that multiple P-type transistors PT included in multiple pairs of P-type transistors PM and PT connected in series between the power supply node VDD and the input node IN or / IN are configured to be individually controllable on / off. As for the pairs of P-type transistors PM and PT, it is sufficient that at least one of those connected to the input node IN and the input node / IN is provided.

[0105] <Example Configuration #6: CTLE (PMOS-based)> Figure 16 is a circuit diagram showing an example of the circuit configuration of semiconductor circuit 3C according to the sixth configuration example of the fourth embodiment. As shown in Figure 16, semiconductor circuit 3C has a configuration in which, for example, N-type transistors NM34 and NM35 and N-type transistors NT30 to NT33 are added to semiconductor circuit 3A.

[0106] In semiconductor circuit 3C, a circuit similar to that in semiconductor circuit 3A is formed by P-type transistors PM32 and PM33, N-type transistors NM32 and NM33, resistors R33 to R35, capacitive element CP31, constant current sources CS32 and CS33, and nodes ND34 to ND37.

[0107] The drain terminal of the N-type transistor NM34 is connected to the input node / IN. The gate terminal of the N-type transistor NM34 is connected to the gate terminal of the N-type transistor NM32. The drain terminal of the N-type transistor NM35 is connected to the input node IN. The gate terminal of the N-type transistor NM35 is connected to the gate terminal of the N-type transistor NM33.

[0108] N-type transistor NT30 is connected between N-type transistor NM32 and the ground node VSS. N-type transistor NT31 is connected between N-type transistor NM34 and the ground node VSS. N-type transistor NT32 is connected between N-type transistor NM33 and the ground node VSS. N-type transistor NT33 is connected between N-type transistor NM35 and the ground node VSS. Specifically, the source terminals of N-type transistors NT30 to NT33 are connected to the ground node VSS. The drain terminal of N-type transistor NT30 is connected to the source terminal of N-type transistor NM32. The drain terminal of N-type transistor NT31 is connected to the source terminal of N-type transistor NM34. The drain terminal of N-type transistor NT32 is connected to the source terminal of N-type transistor NM33. The drain terminal of N-type transistor NT33 is connected to the source terminal of N-type transistor NM35.

[0109] The gate terminal of N-type transistor NT30 is input with control signal EN30. The gate terminal of N-type transistor NT31 is input with control signal EN31. The gate terminal of N-type transistor NT32 is input with control signal EN32. The gate terminal of N-type transistor NT33 is input with control signal EN33. The on / off state of each of the N-type transistors NT30 to NT33 can be controlled based on the control signals EN30 to EN33.

[0110] In the sixth configuration example of the fourth embodiment, the number of pairs of N-type transistors NM and NT (for example, N-type transistors NM32 and NT30) connected in series between the input node IN or / IN and the ground node VSS may be one or more. In the sixth configuration example of the fourth embodiment, it is sufficient that multiple N-type transistors NT included in multiple pairs of N-type transistors NM and NT connected in series between the input node IN or / IN and the ground node VSS are configured to be individually controllable on / off. As for the pairs of N-type transistors NM and NT, it is sufficient that at least one of those connected to the input node IN and the input node / IN is provided.

[0111] <4-2> Effects of the fourth embodiment In each configuration example of the fourth embodiment described above, the number of transistors that feed back the voltage of the active inductor to the input node can be changed by the control signal EN. In other words, in each configuration example of the fourth embodiment, the amount of adjustment of the gain near DC can be changed according to the input signal. The more transistors that feed back the voltage of the active inductor to the input node, the more the gain near DC can be reduced. Therefore, the semiconductor circuits 1B, 1C, 2B, 2C, 3B, and 3C according to the fourth embodiment can improve skew in a more preferable setting, such as achieving full swing while maintaining the amplitude of the signal, by adjusting the gain near DC according to the input signal, thereby enabling high-speed operation.

[0112] <5> Fifth Embodiment The fifth embodiment relates to a specific example of a semiconductor device utilizing at least one of the semiconductor circuits 1, 1A-1C, 2, 2A-2C, 3, and 3A-3C described in the first to fourth embodiments. Details of the semiconductor device according to the fifth embodiment are described below.

[0113] <5-1> Composition The first to eighth configuration examples of the fifth embodiment will be described below in order.

[0114] <Example Configuration 1: NAND Flash Memory> At least one of the semiconductor circuits 1, 1A-1C, 2, 2A-2C, 3, and 3A-3C described in the first to fourth embodiments may be used in a NAND flash memory. Below, as an example of such a NAND flash memory, a semiconductor device 100 according to the first configuration example of the fifth embodiment will be described.

[0115] (Configuration of semiconductor device 100) Figure 17 is a block diagram showing an example of the configuration of a semiconductor device 100 (NAND flash memory) according to the first configuration example of the fifth embodiment. As shown in Figure 17, the semiconductor device 100 is configured to be controllable by a memory controller 110. The semiconductor device 100 includes, for example, a memory cell array 101, an input / output circuit 102, a logic controller 103, a register circuit 104, a sequencer 105, a driver circuit 106, a low decoder module 107, and a sense amplifier module 108.

[0116] The memory cell array 101 is a collection of multiple memory cells (memory cell transistors) MC capable of storing data non-volatilely. The memory cell array 101 is divided into multiple blocks BLK. A block BLK is used, for example, as a data erasure unit. A block BLK contains multiple pages. A page consists of multiple memory cells MC and is used as a unit for writing and reading data. The memory cell array 101 is provided with multiple bit lines BL and multiple word lines WL. Each memory cell MC is associated with one bit line BL and one word line WL. When multiple memory cell MCs are associated with the same pair of bit line BL and word line WL, these memory cell MCs can be independently selected using multiple selection transistors connected between the bit line BL and each memory cell MC. Each memory cell MC is a field-effect transistor with a stacked gate structure having a charge storage layer. The charge storage layer may be a floating gate electrode or a charge trap film. Multiple memory cell MCs are arranged in a two-dimensional or three-dimensional array.

[0117] The input / output circuit 102 is a semiconductor integrated circuit configured to transmit and receive, for example, an 8-bit wide signal DQ<7:0> and signals DQS and / DQS to and from the memory controller 110. Signal DQ may include data, status information, address information, commands, etc. Signals DQS and / DQS are signals that define the transmission and reception timing of signal DQ. Signals DQS and / DQS are a signal pair with opposite phases to each other. The input / output circuit 102 can transfer received address information and commands to the register circuit 104. The input / output circuit 102 can transmit and receive data DAT to and from the sense amplifier module 58.

[0118] The input / output circuit 102 may also be called the memory interface circuit of the semiconductor device 100. Multiple pads PD included in the semiconductor device 100 are connected to the interface circuit of the memory controller 110. Multiple pads PD are used for input and output of signals DQ<7:0>, DQS, and / DQS. Signal DQ<7:0> may also be called the "data signal". Signals DQS and BDQS may also be called the "data strobe signal and its inverted signal". Signals DQS and / or BDQS may also be called the "clock signal", "operation clock signal", "strobe signal", or "timing control signal".

[0119] The signal DQ is, for example, a pulse signal. Each pulse in the signal DQ corresponds to modulated data. As a data modulation method, for example, pulse-amplitude modulation (PAM) is used. Pulse-amplitude modulation is a modulation method that transmits data using the voltage (amplitude) of pulses at regular intervals. When pulse-amplitude modulation is used as the data modulation method, the voltage level of each pulse in the signal DQ corresponds to 1-bit data or multi-bit data. The memory controller 110 may operate as a receiving device and the semiconductor device 100 may operate as a transmitting device.

[0120] The logic controller 103 controls the input / output circuit 102 and the sequencer 105 based on the control signals received from the memory controller 110.

[0121] The register circuit 104 holds status information, address information, and commands. The status information is updated according to the state of the semiconductor device 100. The status information is output to the memory controller 110 based on instructions from the memory controller 110. The address information may include block addresses, page addresses, column addresses, etc. Commands include instructions related to various operations of the semiconductor device 100.

[0122] The sequencer 105 controls the overall operation of the semiconductor device 100. For example, the sequencer 105 can perform read operations, write operations, erase operations, etc., based on the commands and address information held in the register circuit 104.

[0123] The driver circuit 106 generates voltages used in read operations, write operations, erase operations, etc. The driver circuit 106 then supplies the generated voltages to the memory cell array 101, the row decoder module 107, and the sense amplifier module 108, etc.

[0124] The row decoder module 107 is a circuit connected to row-direction wiring (such as word lines WL) provided on the memory cell array 101. The row decoder module 107 includes multiple row decoders, each associated with a multiple block BLK. Each row decoder includes a block decoder capable of decoding block addresses. The row decoder module 107 selects a block BLK based on the decoding result of the block decoder of each row decoder. The row decoder module 107 transfers the voltage supplied from the driver circuit 106 to, for example, a word line WL in the selected block BLK via the associated row decoder RD.

[0125] The sense amplifier module 108 is a circuit connected to the column-direction wiring (bit lines BL) provided in the memory cell array 101. The sense amplifier module 108 includes multiple sense amplifier units, each associated with a plurality of bit lines BL. Each sense amplifier unit has the function of applying a voltage to the associated bit line BL, determining data based on the voltage of the bit line BL, and temporarily storing the data. In a read operation, the sense amplifier module 108 reads data from the memory cell array 101 and transfers the read data to the input / output circuit 102. In a write operation, the sense amplifier module 108 applies a desired voltage to the bit lines BL based on the data received from the input / output circuit 102.

[0126] (Configuration of input / output circuit 102) Figure 18 is a block diagram showing an example of the configuration of an input / output circuit 102 provided in a semiconductor device 100 (NAND flash memory) according to the first configuration example of the fifth embodiment. Figure 18 shows the case where the memory controller 110 operates as a transmitter and the semiconductor device 100 operates as a receiver. As shown in Figure 18, the semiconductor device 100 includes, for example, an input receiver (IREC) 111, a driver circuit 112, a write duty cycle adjuster (WDCA) 113, a plurality of data input circuits 114-0 to 114-7, and a processing circuit 115.

[0127] IREC111 is a circuit that transmits signals within the chip. IREC111 is connected to pad PD, which receives the signal DQS, and to pad PD, which receives the signal BDQS. The output signal of IREC111 is input to driver circuit 112. Because IREC111 directly receives small external signals (DQS and BDQS), it requires a large circuit area.

[0128] The driver circuit 112 is a circuit that transmits signals within the input / output circuit 102, following the IREC 111. The driver circuit 112 amplifies the signal input from the IREC 111 and inputs it to the WDCA 113. The circuit area of ​​the driver circuit 112 is smaller than, for example, the IREC 111 and the WDCA individually.

[0129] WDCA113 is a circuit that adjusts the duty cycle of signals DQS and BDQS received from the memory controller 110 during a write operation, for example. In other words, WDCA113 compensates for the duty cycle deviation of signals DQS and BDQS. Then, WDCA113 distributes the DQS and BDQS signals, with the duty cycle deviation compensated, as a clock signal CLK to each data input circuit 114. Note that WDCA113 requires a large circuit area because it transmits signals via long-distance wiring within the input / output circuit 102. The length of the wiring connecting WDCA113 and the data input circuit 114 varies depending on the location of the data input circuit 114.

[0130] Multiple data input circuits 114-0 to 114-7 are connected to multiple pads PD, respectively. Each data input circuit 114 is a circuit that converts an electrical signal input via pad PD into a digital signal. Specifically, each data input circuit 114 samples data contained in the signal DQ input to pad PD based on the clock signal CLK input from WDCA113 and the inverted signal / CLK of the clock signal CLK (not shown). Then, each data input circuit 114 inputs the sampled data to the processing circuit 115. Data input circuits 114-0 to 114-7 are connected to the signal DQ <0> ~DQ <7> They are associated with each other.

[0131] The processing circuit 115 is a circuit that handles data input from data input circuits 114-0 to 114-7. Examples of processing circuits 115 include the register circuit 104 and the sense amplifier module 108.

[0132] When the semiconductor device 100 exchanges signals DQ, the transmitting device (e.g., the memory controller 110) sends signals DQS and / DQS to the receiving device. The receiving device then samples the signal DQ at a timing based on a clock signal generated from the received signals DQS and / DQS. For example, if the receiving device is the semiconductor device 100, the data sampled by the data input circuit 114 is stored in the memory cell array 101.

[0133] Furthermore, each of the IREC111, driver circuit 112, and WDCA113 is composed of, for example, a differential amplifier circuit. That is, at least one of the semiconductor circuits 2, 2A to 2C can be applied to each of the IREC111, driver circuit 112, and WDCA113.

[0134] (Configuration of data input circuit 114) Figure 19 is a block diagram showing an example of the configuration of a data input circuit 114 in a semiconductor device 100 (NAND flash memory) according to the first configuration example of the fifth embodiment. The data input circuit 114 includes, for example, a C2C circuit 120, a full-scale amplifier (FS) 121, a CTLE 122, and a sampler 123.

[0135] The C2C circuit 120 amplifies the clock signal CLK input from the WDCA113 and the inverted signal / CLK of the clock signal CLK (not shown). The C2C circuit 120 corresponds to either semiconductor circuits 1 and 1A described in the first embodiment. Because the C2C circuit 120 is a circuit located after a long-distance wiring from the WDCA113, it tends to be small in area.

[0136] FS121 is a circuit that converts the signal amplified via the C2C circuit 120 to a CMOS level. FS121 then inputs the converted CMOS-level clock signal CLK to the sampler 123. In this specification, the CMOS level is a logic level corresponding to either "0" data or "1" data. Hereafter, the voltage of the logic level corresponding to "0" data will also be referred to as the "L" level, and the voltage of the logic level corresponding to "1" data will also be referred to as the "H" level.

[0137] CTLE122 is an equalizer circuit that receives an electrical signal input to the data input circuit 114. CTLE122 compensates for the input signal DQ and inputs it to the sampler 123. Multiple CTLE122s may be provided in series between the pad PD that receives the signal DQ and the sampler 123. In this case, the wiring length connecting the multiple CTLE122s may be long. Semiconductor circuits 3, 3A, 3B, or 3C may be used as CTLE122.

[0138] The sampler 123 samples data from signal DQ based on the timing indicated by the clock signal CLK. Then, the sampler 123 transfers the sampling result of signal DQ (data DAT, etc.) to the processing circuit 115.

[0139] (Configuration of C2C circuit 120) Figure 20 is a circuit diagram showing an example of the configuration of a C2C circuit 120 included in the data input circuit 114 of a semiconductor device (NAND flash memory) 100 according to the first configuration example of the fifth embodiment. As shown in Figure 20, the C2C circuit 120 includes, for example, semiconductor circuits 1H and 1L. Semiconductor circuits 1H and 1L have the same circuit configuration as semiconductor circuit 1 described in the first embodiment, except for the connection relationship between input nodes IN and / IN. For example, a clock signal CLK is input to input node IN, and an inverted signal / CLK of the clock signal is input to input node / IN.

[0140] Specifically, the gate terminal of the N-type transistor NM10 in semiconductor circuit 1H is connected to the input node IN. The gate terminal of the N-type transistor NM11 in semiconductor circuit 1H is connected to the input node IN. The gate terminal of the N-type transistor NM10 in semiconductor circuit 1L is connected to the input node IN. The gate terminal of the N-type transistor NM11 in semiconductor circuit 1L is connected to the input node IN. In other words, the N-type transistor NM10 in semiconductor circuit 1H and the N-type transistor NM11 in semiconductor circuit 1L are connected to the input node IN. The N-type transistor NM11 in semiconductor circuit 1H and the N-type transistor NM10 in semiconductor circuit 1L are connected to the input node IN.

[0141] As a result, semiconductor circuits 1H and 1L output complementary signals. For example, if a HIGH level signal is output from node ND11 of semiconductor circuit 1H, a LOW level signal is output from node ND11 of semiconductor circuit 1L. The other configurations of semiconductor circuits 1H and 1L are the same as those of semiconductor circuit 1. When semiconductor circuits 1H and 1L are used in combination, a constant current source CS may be added to suppress the effects of process variations.

[0142] Figure 21 is a circuit diagram showing an example of the configuration of a C2C circuit 120A included in the data input circuit 114 of a semiconductor device 100 according to the first configuration example of the fifth embodiment. As shown in Figure 21, the C2C circuit 120A includes semiconductor circuits 1H and 1L and a constant current source CS12.

[0143] The constant current source CS12 is connected between the power node VDD and the P-type transistor PM12 of semiconductor circuit 1H, and between the power node VDD and the P-type transistor PM12 of semiconductor circuit 1L. That is, the input terminal of the constant current source CS12 is connected to the power node VDD. The output terminal of the constant current source CS12 is connected to the source of the P-type transistor PM12 of semiconductor circuit 1H and the source of the P-type transistor PM12 of semiconductor circuit 1L, respectively. As a result, the C2C circuit 120A can reduce its sensitivity to process variations and realize a highly accurate compensation circuit.

[0144] <Second Configuration Example: NOR-type Flash Memory> At least one of the semiconductor circuits 1, 1A-1C, 2, 2A-2C, 3, and 3A-3C described in the first to fourth embodiments may be used in a random-access non-volatile semiconductor memory device (e.g., a NOR-type flash memory). Below, a semiconductor device 200 according to the second configuration example of the fifth embodiment will be described as an example of such a NOR-type flash memory.

[0145] Figure 22 is a block diagram showing an example of the configuration of a semiconductor device 200 (NOR type flash memory) according to a second configuration example of the fifth embodiment. As shown in Figure 22, the semiconductor device 200 includes, for example, a memory cell array 201, a row control circuit 202, a column control circuit 203, an address register 204, a data buffer 205, an input / output shift register 206, a voltage generation circuit 207, and a sequencer 208.

[0146] The memory cell array 201 includes a plurality of memory cells (memory cell transistors) MTx. In the semiconductor device 200, the gate terminal of each memory cell MTx is connected to a corresponding word line WL from a plurality of word lines WL. One end of the current path of each memory cell MTx is connected to a corresponding bit line BL from a plurality of bit lines BL. The other end of the current path of each memory cell MTx is connected to a source line, for example, to ground. The plurality of memory cells MTx are arranged in a two-dimensional array or a three-dimensional array. The memory cell MTx is a field-effect transistor with a stacked gate structure having a charge storage layer. The charge storage layer may be a floating gate electrode or a charge trap film.

[0147] The row control circuit 202 selects a word line from among several word lines WL according to the address information. The row control circuit 202 applies a predetermined voltage to the selected word line (and the unselected word lines) according to write, read, and erase operations.

[0148] The column control circuit 203 selects a bit line from among multiple bit lines BL according to the address information. The column control circuit 203 applies a predetermined voltage to the selected bit line (and the unselected bit lines) according to write, read, and erase operations.

[0149] The address register 204 temporarily stores address information from the input / output shift register 206. The address register 204 sends the address information to the row control circuit 202 and the column control circuit 203.

[0150] The data buffer 205 temporarily stores data read from the memory cell array 201 and data written from the input / output shift register 206.

[0151] The input / output shift register 206 temporarily stores the signal DQ transferred between the memory cell array 201 and the outside of the semiconductor device 200. The input / output shift register 206 sends address information to the address register 204. The input / output shift register 206 sends write data to the data buffer 205. The input / output shift register 206 sends read data supplied from the memory cell array 201 to the outside of the semiconductor device 200. The input / output shift register 206 can perform parallel-to-serial conversion of data DQ.

[0152] The voltage generation circuit 207 generates multiple types of voltages used for writing, reading, and erasing operations. The voltage generation circuit 207 supplies the generated voltages to the row control circuit 202, the column control circuit 203, and the like.

[0153] The sequencer 208 controls the operation of the entire semiconductor device 200 based on various control signals, such as the reset signal RESETn, the hold signal HOLDn, and the write protect signal Wn.

[0154] The configuration of the semiconductor device 200 (NOR flash memory) is not limited to this. The semiconductor device 200 may include other components such as a status register. The status register temporarily stores status signals that indicate the internal operating status of the semiconductor device 200 and the execution results of the operation sequence.

[0155] In the semiconductor device 200 according to the second configuration example of the fifth embodiment, for example, the C2C circuit (semiconductor circuits 1, 1A, 1B, and 1C) described in the above embodiment can be applied to the sequencer 208 and the input / output shift register 206.

[0156] <Third Configuration Example: DRAM (Dynamic Random Access Memory)> At least one of the semiconductor circuits 1, 1A-1C, 2, 2A-2C, 3, and 3A-3C described in the first to fourth embodiments may be used in a volatile semiconductor memory device (e.g., DRAM). Below, a semiconductor device 300 according to the third configuration example of the fifth embodiment will be described as an example of such a DRAM.

[0157] Figure 23 is a block diagram showing an example of the configuration of a semiconductor device 300 (DRAM) according to the third configuration example of the fifth embodiment. As shown in Figure 23, the semiconductor device 300 includes, for example, a memory cell array 301, a row decoder 302, a column decoder 303, a command decoder 304, an address decoder 305, a command / address input circuit 306, a sense amplifier circuit 307, a transfer gate 308, a read / write amplifier (RWAMP) circuit 309, an input / output circuit 310, a clock input circuit 311, an internal clock generation circuit 312, and a voltage generation circuit 313.

[0158] The memory cell array 301 includes multiple memory cells MC. Each memory cell MC of the semiconductor device 300 includes a cell capacitor CC and a cell transistor CT. The gate of the cell transistor CT is connected to one of several word lines WL. One end of the current path of the cell transistor CT is connected to a bit line BL. The other end of the current path of the cell transistor CT is connected to one end of the cell capacitor CC. The other end of the cell capacitor CC is connected to a ground node. The cell capacitor CC can store an amount of charge corresponding to the data to be stored. The cell transistor CT switches between conduction / non-conductivity (selection / deselection of the memory cell) between the memory cell MC and the bit line BL. Multiple memory cells MC are arranged in a two-dimensional or three-dimensional array within the memory cell array 301. For example, the memory cell array 301 includes multiple banks. Each bank is a control unit containing multiple memory cells MC. Multiple banks can operate independently of each other.

[0159] The row decoder 302 controls the selection / deselection of row-direction wiring (e.g., word lines WL) of the memory cell array 301 based on the decoding results of the address information and the decoding results of the command.

[0160] The column decoder 303 controls the selection / deselection of column-direction wiring (e.g., bit lines BL) of the memory cell array 301 based on the decoding results of the address information and the decoding results of the command.

[0161] The command decoder 304 decodes the command received from the command / address input circuit 306. The command decoder 304 then sends the decoded command result to the row decoder 302 and the column decoder 303, respectively.

[0162] The address decoder 305 decodes the address information received from the command / address input circuit 306. The address decoder 305 then sends the decoded address information to the row decoder 302 and the column decoder 303, respectively.

[0163] The command / address input circuit 306 receives a command / address signal CA supplied from an external source. The command / address signal CA includes command and address information. The command / address input circuit 306 sends the command and address information to the command decoder 304 and the address decoder 305, respectively.

[0164] The sense amplifier circuit 307 senses and amplifies the signal from the memory cell MC during read operation. The sense amplifier circuit 307 sends the signal from the memory cell MC as read data to the input / output circuit 310 via the transfer gate 308 and RWAMP 309. The sense amplifier circuit 307 receives write data from the input / output circuit 310 via the transfer gate 308 and RWAMP 309. The sense amplifier circuit 307 outputs a signal corresponding to the write data to the bit line BL.

[0165] The transfer gate 308 controls the data transfer between the sense amplifier circuit 307 and the RWAMP 309.

[0166] The RWAMP309 amplifies the signal level (signal value) according to the read data, and the signal level according to the written data.

[0167] The input / output circuit 310 functions as an interface circuit for the signal DQ transferred between the memory cell array 301 and the outside of the semiconductor device 300. The input / output circuit 310 sends write data to the memory cell array 301 at a timing synchronized with the internal clock CLK2. The input / output circuit 310 also sends read data to an external device of the semiconductor device 300 at a timing synchronized with the internal clock CLK2. For example, the input / output circuit 310 receives a data mask signal DM. Based on the data mask signal DM, the input / output circuit 310 performs masking on the signal DQ (data).

[0168] The clock input circuit 311 receives an external clock (hereinafter referred to as the external clock) CLK1. The clock input circuit 311 sends the external clock CLK1 to the internal clock generation circuit 312.

[0169] The internal clock generation circuit 312 generates an internal clock CLK2 based on the external clock CLK1. The internal clock generation circuit 312 sends the generated internal clock CLK2 to the input / output circuit 310, etc.

[0170] The voltage generation circuit 313 uses an external power supply voltage (the voltage applied to the power supply node VDD and the voltage applied to the ground node VSS) to generate multiple voltages used for each of the various operating sequences of the semiconductor device 300. The voltage generation circuit 313 sends the generated voltages to other circuits (for example, RWAMP 309).

[0171] In the third configuration example of the fifth embodiment, the semiconductor device 300 is exemplified as being a DRAM, but it is not limited to this. The semiconductor device 300 may be a random access memory other than a DRAM. For example, the semiconductor device 300 may be an SRAM (Static RAM).

[0172] In the semiconductor device 300 according to the third configuration example of the fifth embodiment, for example, the CTLE (semiconductor circuits 3, 3A, 3B, and 3C) described in the above embodiment can be applied to the input / output circuit 310, the clock input circuit 311, and the internal clock generation circuit 312.

[0173] <Fourth Configuration Example: Crosspoint Memory> At least one of the semiconductor circuits 1, 1A-1C, 2, 2A-2C, 3, and 3A-3C described in the first to fourth embodiments may be used in a crosspoint memory. Below, as an example of such a crosspoint memory, a semiconductor device 400 according to the fourth configuration example of the fifth embodiment will be described.

[0174] Figure 24 is a block diagram showing an example of the configuration of a semiconductor device 400 (crosspoint type memory) according to the fourth configuration example of the fifth embodiment. As shown in Figure 24, the semiconductor device 400 operates based on the control of a memory controller 410. The memory controller 410 can instruct the semiconductor device 400 to perform read operations, write operations, etc., in response to commands from an external host device. The semiconductor device 400 is a memory device that uses an MTJ (Magnetic Tunnel Junction) element as a memory cell, and is a type of resistive random-access memory. The MTJ element utilizes the magnetoresistance effect due to the magnetic tunnel junction. The MTJ element is also called a magnetoresistance effect element. The semiconductor device 400 includes, for example, a memory cell array 401, an input / output circuit 402, a control circuit 403, a row selection circuit 404, a column selection circuit 405, a write circuit 406, and a read circuit 407.

[0175] The memory cell array 401 includes multiple memory cells MC, multiple word lines WL, and multiple bit lines BL. Figure 24 shows one set of memory cells MC, word lines WL, and bit lines BL. Memory cells MC can store data non-volatilely. Each memory cell MC is connected between one word line WL and one bit line BL and is associated with a row-column pair. A row address is assigned to the word line WL. A column address is assigned to the bit line BL. One or more memory cells MC may be identified by the selection of one row and one or more columns.

[0176] The input / output circuit 402 is connected to the memory controller 410 and manages communication between the semiconductor device 400 and the memory controller 410. The input / output circuit 402 forwards the control signal CNT and command CMD received from the memory controller 410 to the control circuit 403. The input / output circuit 402 sends the row address and column address contained in the address signal ADD received from the memory controller 410 to the row selection circuit 404 and column selection circuit 405, respectively. The input / output circuit 402 forwards the data DAT received from the memory controller 410 to the write circuit 406. The input / output circuit 402 sends the data DAT received from the read circuit 407 to the memory controller 2.

[0177] The control circuit 403 controls the operation of the entire semiconductor device 400. For example, the control circuit 403 performs read operations and write operations based on the control signal CNT and the command CMD. For example, in a write operation, the control circuit 403 generates the voltage used for writing data and supplies it to the write circuit 406. Also, in a read operation, the control circuit 403 generates the voltage used for reading data and supplies it to the read circuit 407.

[0178] The row selection circuit 404 is connected to multiple word lines WL. The row selection circuit 404 then selects one word line WL identified by the row address. The selected word line WL is electrically connected to a driver circuit, which is not shown in the diagram.

[0179] The column selection circuit 405 is connected to multiple bit lines BL. The column selection circuit 405 then selects one or more bit lines BL identified by the column address. The selected bit lines BL are electrically connected to a driver circuit (not shown).

[0180] The writing circuit 406 supplies the voltage used for writing data to the column selection circuit 405 based on the control of the control circuit 403 and the data DAT (data requested to be written) received from the input / output circuit 402. When the current based on the data DAT flows through the memory cell MC, the desired data is written to the memory cell MC.

[0181] The read circuit 407 includes a sense amplifier. Based on the control of the control circuit 403, the read circuit 407 supplies a voltage to the column selection circuit 405 that is used to read the data. The sense amplifier then determines the data stored in the memory cell MC based on the voltage or current of the selected bit line BL. The read circuit 407 then sends the data DAT (data read from the memory cell array 401) corresponding to the determination result to the input / output circuit 402.

[0182] In the fourth configuration example of the fifth embodiment, the semiconductor device 400 is shown as an example where it is an MRAM, but the invention is not limited to this. The semiconductor device 400 may be any other resistive random access memory. For example, the semiconductor device 400 may be a memory device using a transition metal oxide element having variable resistance characteristics as a memory element (for example, a resistive random access memory such as ReRAM (Resistive Random Access Memory)), a memory device using a phase change element as a memory element (for example, a phase change memory such as PCRAM (Phase Change Random Access Memory)), or a memory device using a ferroelectric element as a memory element (for example, a ferroelectric memory such as FeRAM (Ferroelectric Random Access Memory)).

[0183] In the semiconductor device 400 according to the fourth configuration example of the fifth embodiment, for example, the CTLE (semiconductor circuits 3, 3A, 3B, and 3C) described in the above embodiment can be applied to the input / output circuit 402 and the control circuit 403.

[0184] <Example Configuration 5: Image Sensor> At least one of the semiconductor circuits 1, 1A-1C, 2, 2A-2C, 3, and 3A-3C described in the first to fourth embodiments may be used as an image sensor. Below, as an example of such an image sensor, a semiconductor device 500 according to the fifth configuration example of the fifth embodiment will be described.

[0185] Figure 25 is a block diagram showing an example of the configuration of a semiconductor device 500 (image sensor) according to the fifth configuration example of the fifth embodiment. As shown in Figure 25, the semiconductor device 500 includes, for example, a pixel array 501, a row scanning circuit 502, a column processing circuit 503, a column scanning circuit 504, a system control circuit 505, and a signal processing circuit 506.

[0186] The pixel array 501 has multiple pixels PX. The multiple pixels PX are arranged in a two-dimensional grid along the row direction and the column direction. Each pixel PX has a photoelectric conversion element. The photoelectric conversion element generates an electric charge corresponding to the amount of light received and stores the generated charge. Filters may be provided within the pixel array 501 for the light incident surface of each pixel PX. For example, the arrangement pattern of the multiple filters may be, for example, a Bayer pattern. In the pixel array 501, the multiple pixels PX arranged in the row direction are commonly connected to a pixel drive line PDL. In the pixel array 501, the multiple pixels PX arranged in the column direction are commonly connected to one of the multiple vertical signal lines VSL.

[0187] The row scanning circuit 502 is connected to one end of a plurality of pixel drive lines PDL. The row scanning circuit 502 generates drive signals for reading signals from pixels PX. The row scanning circuit 502 drives all pixels PX of the pixel array 501 simultaneously or in row units via the plurality of pixel drive lines PDL. The signals output from the plurality of pixels PX driven by the row scanning circuit 502 are supplied to the column processing circuit 903 via the corresponding vertical signal line VSL for each pixel PX arranged in the row direction.

[0188] The column processing circuit 503 performs predetermined signal processing on the signal supplied via the vertical signal line VSL. This allows the column processing circuit 503 to generate a pixel signal. The column processing circuit 503 can also temporarily store the generated pixel signal. The column processing circuit 503 can perform, for example, noise reduction processing or analog-to-digital conversion (AD conversion) processing. The digital signal obtained by AD conversion is output to the signal processing circuit 506.

[0189] The column scanning circuit 504 sequentially selects the readout circuits corresponding to the arrangement of pixel signals from the column processing circuit 503. Through selective scanning by the column scanning circuit 504, the pixel signals processed pixel by pixel in the column processing circuit 503 are output in a predetermined order.

[0190] The system control circuit 505 receives a system clock signal and the like via an external controller (not shown) of the semiconductor device 500. The system control circuit 505 includes a timing generator and the like. The timing generator generates various timing signals based on the system clock signal. Based on these generated timing signals, the system control circuit 505 drives the row scanning circuit 502, the column processing circuit 503, and the column scanning circuit 504, etc.

[0191] The signal processing circuit 506 has at least an arithmetic processing function. The signal processing circuit 506 performs various signal processing, such as arithmetic processing, on the pixel signals output from the column processing circuit 503.

[0192] The digital signal output from the signal processing circuit 506 is then output to an external image processing circuit 507 of the semiconductor device 500. The image processing circuit 507 performs predetermined processing on the digital signal. The image processing circuit 507 then generates an image signal for displaying an image on a predetermined display device.

[0193] In the semiconductor device 500 according to the fifth configuration example of the fifth embodiment, for example, the CTLE (semiconductor circuits 3, 3A, 3B, and 3C) described in the above embodiment can be applied to a system control circuit 505 that receives a system clock signal.

[0194] <Configuration Example 6: Communication Interface> At least one of the semiconductor circuits 1, 1A-1C, 2, 2A-2C, 3, and 3A-3C described in the first to fourth embodiments may be used as a communication interface. Below, as an example of such a communication interface, a semiconductor device 600 according to the sixth configuration example of the fifth embodiment will be described. The communication interface may be a wired circuit such as optical or Ethernet (registered trademark), or a wireless circuit such as RF.

[0195] Figure 26 is a block diagram showing an example of the configuration of a semiconductor device 600 (communication interface) according to the sixth configuration example of the fifth embodiment. As shown in Figure 26, the semiconductor device 600 is a differential transmission type input / output interface circuit (for example, a transceiver). Specifically, the semiconductor device 600 includes input / output terminals 601A and 601B, resistor-capacitor (RC) circuits 602A and 602B, analog-to-digital (AD) conversion circuit 603, capacitor circuits 604A and 604B, digital-to-analog (DA) conversion circuit 605, current sink circuit 606, clock phase adjustment circuit 607, control clock generation circuit 608, input monitor 609, input / output monitor 610, PVT monitor 611, global bias generation circuit 612, bias generation circuits 613 and 614, and input / output control circuit 615.

[0196] Input / output terminals 601A and 601B are a pair of differential input / output terminals. The semiconductor device 600 can transmit and receive differential signals IO+ and IO-, respectively, via input / output terminals 601A and 601B. The two differential signals IO+ and IO- are complementary to each other. The two input / output terminals 601A and 601B that form a pair for differential transmission may also be called a differential input / output terminal pair. Within the semiconductor device 600, the pair of signal lines for differential transmission may also be called a differential transmission path.

[0197] RC circuits 602A and 602B are provided corresponding to input / output terminals 601A and 601B, respectively. RC circuit 602A is connected to the signal path of input / output terminal 601A. RC circuit 602B is connected to the signal path of input / output terminal 601B. RC circuits 602A and 602B control the time constant of the supplied signal. RC circuits 602A and 602B consist of resistors and capacitors and are circuits that can be designed (programmed) after implementation. RC circuits may also be called RC networks.

[0198] The AD conversion circuit 603 receives the differential signals IO+ and IO- input to the semiconductor device 600 via the RC circuits 602A and 602B. The AD conversion circuit 603 also receives the reference signals IOMVR+ and IOMVR- from the bias generation circuit 613. Based on the reference signals IOMVR+ and IOMVR-, the AD conversion circuit 603 converts the signals IO+ and IO- from analog signals to digital signals.

[0199] Capacitor circuit 604A is provided between RC circuit 602A and DA conversion circuit 605. Capacitor circuit 604B is provided between RC circuit 602B and DA conversion circuit 605. Capacitor circuit 604A is connected to RC circuit 602A. Capacitor circuit 604B is connected to RC circuit 602B. Capacitor circuits 604A and 604B include multiple capacitors. Capacitor circuits 604A and 604B perform signal smoothing.

[0200] The DA conversion circuit 605 receives a digital signal. The DA conversion circuit 605 receives reference signals IOMVR+ and IOMVR- from the bias generation circuit 613. Based on the received digital signal and the reference signals IOMVR+ and IOMVR-, the DA conversion circuit 605 generates analog signals DACOUT+ and DACOUT-. The analog signals DACOUT+ and DACOUT- are complementary signals. The DA conversion circuit 605 sends the generated analog signal DACOUT+ to the input / output terminal 601A via the capacitor circuit 604A and RC circuit 602A. The DA conversion circuit 605 sends the generated analog signal DACOUT- to the input / output terminal 601B via the capacitor circuit 604B and RC circuit 602B. As a result, the signals DACOUT+ and DACOUT- are output to the outside of the semiconductor device 600 as differential signals IO+ and IO-, respectively. The DA conversion circuit 605 also sends the analog signals DACOUT+ and DACOUT- to the current sink circuit 606.

[0201] The current sink circuit 606 controls the magnitude of the current flowing through the input / output terminal 601 and the signal line to within the range permitted by the specifications of the communication interface.

[0202] The clock phase adjustment circuit 607 adjusts the phase of the reference clock signal and generates various clock signals used by the semiconductor device 600.

[0203] The control clock generation circuit 608 adjusts the phase of the reference clock signal and generates various clock signals used by the semiconductor device 600.

[0204] The input monitor 609 monitors the signal IO+ at input / output terminal 601A and the signal IO- at input / output terminal 601B.

[0205] The input / output monitor 610 monitors multiple clock signals received from the control clock generation circuit 608.

[0206] The PVT monitor 611 monitors various bandgap voltages and bias voltages within the semiconductor device 600. The bandgap voltage is the reference voltage for the signal's voltage amplitude. The bias voltage is the voltage for the operation of each circuit block within the semiconductor device 600.

[0207] The global bias generation circuit 612 generates the main bias voltage used for each circuit block within the semiconductor device 600.

[0208] The bias generation circuit 613 generates a reference voltage for the bias voltage (bias signal) of the AD conversion circuit 603 and the DA conversion circuit 605.

[0209] The bias generation circuit 614 generates bias voltages for the AD conversion circuit 603 and the input / output control circuit 615.

[0210] The input / output control circuit 615 generates control signals for each circuit block in the semiconductor device 600. The input / output control circuit 615 supplies the generated control signals to each circuit block.

[0211] In the semiconductor device 600 according to the sixth configuration example of the fifth embodiment, for example, the CTLE (semiconductor circuits 3, 3A, 3B, and 3C) described in the above embodiment may be applied to the control clock generation circuit 608. Furthermore, in the semiconductor device 600 according to the sixth configuration example of the fifth embodiment, the differential amplifier circuits (semiconductor circuits 2, 2A, 2B, and 2C) described in the above embodiment may be applied to circuits that handle differential signals (for example, the AD conversion circuit 603, the DA conversion circuit 605, the current sink circuit 606, the input monitor 609, and the bias generation circuit 613).

[0212] <Example 7: Wireless Device> At least one of the semiconductor circuits 1, 1A-1C, 2, 2A-2C, 3, and 3A-3C described in the first to fourth embodiments may be used in a wireless device. Below, as an example of such a wireless device, a semiconductor device 700 according to the seventh configuration example of the fifth embodiment will be described.

[0213] Figure 27 is a block diagram showing an example of the configuration of a semiconductor device 700 (wireless device) according to the seventh configuration example of the fifth embodiment. As shown in Figure 27, the semiconductor device 700 includes, for example, a top layer 710, a transmitting unit 720, a switching unit 730, a receiving unit 740, a reference clock generation circuit 750, and a clock generation circuit 760.

[0214] The upper layer 710 is a functional block that handles frames transmitted and received by the semiconductor device 700. The upper layer 710 can, for example, perform MAC layer processing. For example, the upper layer 710 generates a frame using traffic generated from the wireless device application and inputs the generated frame to the transmitter 720. The upper layer 710 also extracts data from the frame received from the receiver 740 and inputs the extracted data to the application.

[0215] The transmitter 720 converts the frame input from the upper layer 710 into a radio signal and transmits it via the antenna. The transmitter 720 includes, for example, a modulator 721, a frequency converter 722, and an amplifier 723. The modulator 721 inputs the modulated signal of the input frame to the frequency converter 722. The frequency converter 722 converts the frequency of the input signal to a desired frequency and inputs it to the amplifier 723. The amplifier 723 is a Solid State Power Amplifier (SSPA) that amplifies the input signal. The amplifier 723 includes, for example, an amplification circuit, an isolator, and a low-pass filter. The signal output from the amplifier 723 is radiated from the antenna via the switching unit 730.

[0216] The switching unit 730 is a circuit that can switch the connection to the antenna between the transmitting unit 720 and the receiving unit 740.

[0217] The receiver 740 extracts frames from the radio signal received via the antenna and inputs them to the upper layer 710. The receiver 740 includes, for example, an amplifier 741, a frequency converter 742, and a demodulator 743. The amplifier 741 amplifies the signal received via the antenna and inputs it to the frequency converter 742. The amplifier 741 includes, for example, a bandpass filter and an amplification circuit. The frequency converter 742 converts the frequency of the input signal to a desired frequency and inputs it to the demodulator 743. The demodulator 743 demodulates the input signal to extract the frames contained in the radio signal. The demodulator 743 then inputs the extracted frames to the upper layer 710.

[0218] The reference clock generation circuit 750 generates a reference clock signal used by the semiconductor device 700.

[0219] The clock generation circuit 760 generates multiple clock signals used by the semiconductor device 700 based on a reference clock signal. The clock generation circuit 760 then inputs the generated clock signals to, for example, the modulator 721, frequency converters 722 and 742, and demodulator 743.

[0220] In the semiconductor device 700 according to the seventh configuration example of the fifth embodiment, for example, the C2C circuit (semiconductor circuits 1, 1A, 1B, and 1C) described in the above embodiment can be applied to the demodulator 743.

[0221] <Configuration Example 8: Microcontroller> At least one of the semiconductor circuits 1, 1A-1C, 2, 2A-2C, 3, and 3A-3C described in the first to fourth embodiments may be used in a microcontroller. Below, as an example of such a microcontroller, a semiconductor device 800 according to the eighth configuration example of the fifth embodiment will be described.

[0222] Figure 28 is a block diagram showing an example of the configuration of a semiconductor device 800 (microcontroller) according to the eighth configuration example of the fifth embodiment. As shown in Figure 28, the semiconductor device 800 includes, for example, a processor 801, a bus control circuit 802, a flash memory 803, a RAM 804, a DA conversion circuit 805, an AD conversion circuit 806, a timer 807, an input / output (I / O) port 808, an oscillator 809, and an interrupt controller 810. The bus of the semiconductor device 800 is connected to the processor 801, the bus control circuit 802, the flash memory 803, the RAM 804, the DA conversion circuit 805, the AD conversion circuit 806, the timer 807, and the input / output port 808. The bus of the semiconductor device 800 is the signal and data transmission path within the semiconductor device 800.

[0223] The processor 801 performs various processes within the semiconductor device 800. The processor 801 performs various processes on the supplied data. The processor 801 is, for example, a CPU.

[0224] The bus control circuit 802 controls the bus of the semiconductor device 800. The bus control circuit 802 may be located within the processor 801.

[0225] The flash memory 803 is a storage device capable of storing data non-volatilely. The flash memory 803 is, for example, a NOR-type flash memory. However, the flash memory 803 may also be a NAND-type flash memory.

[0226] RAM804 is a memory device that temporarily stores data. RAM804 is a random access memory, such as SRAM or DRAM.

[0227] The DA conversion circuit 805 converts a digital signal (digital value) into an analog signal (analog value).

[0228] The AD conversion circuit 806 converts analog signals into digital signals.

[0229] Timer 807 manages the time (operation timing) within the semiconductor device 800.

[0230] The input / output port 808 functions as an interface circuit in the semiconductor device 800. The input / output port 808 includes, for example, four ports P1, P2, P3, and P4. The number of ports provided by the input / output port 808 may be three or fewer, or five or more. The input / output port 808 receives signals, including data and addresses, from outside the semiconductor device 800 via each of ports P1, P2, P3, and P4. The input / output port 808 sends signals, such as data, to the outside of the semiconductor device 800 via each of ports P1, P2, P3, and P4. The input / output port 808 conforms to standards such as GPIO (General purpose input / output), USART (Universal synchronous / asynchronous receiver / transmitter), or I2C (Inter-integrated circuit).

[0231] Oscillator 809 outputs a clock signal as a synchronization signal to processor 801. The clock signal has a certain period (number of clock cycles). As a result, processor 801 performs various processes at timings synchronized with the clock signal. The period of the clock signal can be, for example, 4MHz, 8MHz, 12MHz, or 24MHz.

[0232] The interrupt controller 810 receives external interrupt instructions. For example, the interrupt controller 810 has registers for managing the status of interrupt requests. Based on the received external interrupt instructions, the interrupt controller 810 sends various interrupt requests to the processor 801. In response to the interrupt request, the processor 801 temporarily suspends the process it is currently running and executes the processing of the interrupt request. After the processing of the interrupt request is completed, the processor 801 resumes the suspended process.

[0233] In addition, the semiconductor device 800 according to the eighth configuration example of the fifth embodiment may be a system-on-a-chip (SoC), a system-in-package (SIP), or a system-on-a-package (SoP). The semiconductor device 800 is used, for example, in embedded systems. The semiconductor device 800 may be used, for example, in automotive devices, home appliances, computers, industrial machinery, railway vehicles, aircraft, and ships.

[0234] Furthermore, the semiconductor device 800 may be classified based on its bus width, memory structure, and instruction set. Bus width refers to the size of the data bus. For example, based on bus width, the semiconductor device 800 can be classified as an 8-bit microcontroller, a 16-bit microcontroller, or a 32-bit microcontroller. A higher bus width allows the semiconductor device 800 to achieve better performance.

[0235] In the semiconductor device 800 according to the eighth configuration example of the fifth embodiment, for example, the CTLE (semiconductor circuits 3, 3A, 3B, and 3C) described in the above embodiment may be applied to the input / output port 808. Also, in the semiconductor device 800 according to the eighth configuration example of the fifth embodiment, for example, the C2C circuit (semiconductor circuits 1, 1A, 1B, and 1C) described in the above embodiment may be applied to the processor 801.

[0236] <5-2> Effects of the Fifth Embodiment As the storage capacity of NAND flash memory increases, the frequency of signals transmitted and received between the semiconductor memory device and the memory controller increases, making data transfer in the signal transmission circuit within the input / output circuit 102 difficult. For example, because the wiring lengths between the WDCA 113 and each data input circuit 114 are different, variations in skew may occur for each of the multiple data input circuits 114 that receive different signals DQ from each other.

[0237] Therefore, in the first configuration example of the fifth embodiment, the input / output circuit 102 of the semiconductor device 100 (NAND flash memory) is equipped with the C2C circuit described in the above embodiment. As a result, the input / output circuit 102 can reduce the gain near DC and suppress variations in skew for each data input circuit 114. Consequently, the semiconductor device 100 according to the first configuration example of the fifth embodiment can utilize high-frequency signals and realize high-speed transmission of data, etc., between it and the memory controller 110.

[0238] Furthermore, the second to eighth configuration examples of the fifth embodiment, similar to the first configuration example of the fifth embodiment, can achieve high-speed signal transmission by utilizing at least one of the C2C circuit, differential amplifier circuit, and CTLE described in the first to fourth embodiments, i.e., at least one of the semiconductor circuits 1, 1A to 1C, 2, 2A to 2C, 3, and 3A to 3C.

[0239] <6> others In this specification, an "H" level voltage corresponds to a voltage above a threshold when determining data in a binary manner. An "L" level voltage corresponds to a voltage below a threshold when determining data in a binary manner. In this specification, "logical level" corresponds to either an "H" level or an "L" level. In this specification, "connected" means electrically connected, and does not exclude, for example, another element in between. "Electrically connected" may be through an insulator, as long as it is possible to operate as if electrically connected.

[0240] In this specification, one end and the other end of a transistor correspond to the source end or drain end of the transistor, respectively. In this specification, “conductivity type” corresponds to “N-type” or “P-type”. For example, a transistor of first conductivity type corresponds to one of an N-type transistor and a P-type transistor, and a transistor of second conductivity type corresponds to the other of an N-type transistor and a P-type transistor. One end and the other end may be called the “first end” and the “second end”. The ground node VSS may be called the power node. The input and output ends of the constant current source CS correspond to one end and the other end of the current path of the constant current source CS, respectively. One end of the constant current source CS corresponds to one of the input end and the output end, and the other end of the constant current source CS corresponds to the other of the input end and the output end.

[0241] In the above embodiment, each of the constant current sources CS10, CS20, CS30, and CS31 is composed of, for example, one N-type MOS transistor. Each of the constant current sources CS11, CS12, CS21, CS32, and CS33 is composed of, for example, one P-type MOS transistor. Note that the constant current source CS may be composed of multiple transistors. For example, the constant current source CS may include a current mirror circuit containing two transistors. In this case, each of the constant current sources CS10, CS20, CS30, and CS31 includes a current mirror circuit composed of N-type MOS transistors, and each of the constant current sources CS11, CS12, CS21, CS32, and CS33 includes a current mirror circuit composed of P-type MOS transistors.

[0242] Figure 29 is a circuit diagram showing an example of the circuit configuration of a constant current source CS (hereinafter referred to as constant current source CSN) composed of N-type transistors. As shown in Figure 29, the constant current source CSN has, for example, N-type transistors NM90 and NM91, and nodes ND90 to ND92. The drain and gate terminals of N-type transistor NM90 are connected to node ND90. The drain terminal of N-type transistor NM91 is connected to node ND91. The gate terminal of N-type transistor NM91 is connected to node ND90. The source terminals of N-type transistors NM90 and NM91 are connected to node ND92. Node ND92 is connected to, for example, the ground node VSS. In the constant current source CSN, the voltage of node ND90 is controlled so that the current flowing through N-type transistor NM91 remains constant. That is, the input terminal of the constant current source CSN corresponds to node ND91. The output terminal of the constant current source CSN corresponds to node ND92.

[0243] Figure 30 is a circuit diagram showing an example of the circuit configuration of a constant current source CS (hereinafter referred to as constant current source CSP) composed of P-type transistors. As shown in Figure 30, the constant current source CSP has, for example, P-type transistors PM90 and PM91, and nodes ND93 to ND95. Node ND93 is connected to the power supply node VDD. The source terminals of P-type transistors PM90 and PM91 are connected to node ND93. The gate terminal and drain terminal of P-type transistor PM90 are connected to node ND94. The gate terminal of P-type transistor PM91 is connected to node ND94. The drain terminal of P-type transistor PM91 is connected to node ND95. In the constant current source CSP, the voltage at node ND94 is controlled so that the current flowing through P-type transistor PM91 remains constant. That is, the input terminal of the constant current source CSP corresponds to node ND93. The output terminal of the constant current source CSP corresponds to node ND95.

[0244] In this specification, transistor sizes are compared using the gate width, for example, in the case of a planar MOSFET. In this specification, transistor sizes are compared using the number of fins, for example, in the case of a FinFET. In this specification, transistor sizes are compared using the number of stacked nanosheet semiconductor layers, for example, in the case of a Nanosheet transistor.

[0245] In a FinFET, the gate electrode faces two or more sides of the channel region. The channel region is formed within a convex shape formed on the surface of a semiconductor substrate, and this convex semiconductor region is called a fin. A single transistor may have multiple fins. If the number of fins in one transistor is less than the number of fins in other transistors, then one transistor is smaller than the other transistors. If the ratio of the size of one transistor (e.g., P-type transistor PM12) to the size of other transistors (e.g., P-type transistor PM10) is 1:1.2 to 7, then for example, if one transistor has one fin, the number of fins in the other transistors is 2 to 7, and if one transistor has two fins, the number of fins in the other transistors is 3 to 14.

[0246] In a nanosheet, the gate electrode faces the channel region, enclosing it. The channel region is formed within a planar semiconductor layer (nanosheet). Multiple planar semiconductor layers may be stacked spaced apart. If the number of semiconductor layers in one transistor is less than the number of semiconductor layers in other transistors, then one transistor is smaller than the other. If the ratio of the size of one transistor (e.g., P-type transistor PM12) to the size of another transistor (e.g., P-type transistor PM10) is 1:1.2 to 7, then for example, if one transistor has one semiconductor layer, the other transistors have 2 to 7 semiconductor layers, and if one transistor has two semiconductor layers, the other transistors have 3 to 14 stacked semiconductor layers.

[0247] In this specification, “NMOS-based” indicates that the transistor receiving the input signal is an N-type transistor. “PMOS-based” indicates that the transistor receiving the input signal is a P-type transistor. CML (Current Mode Logic) is a circuit that transmits small analog signals. CMOS, strictly speaking, refers to a CMOS inverter, which is a circuit that transmits large digital signals. A C2C circuit corresponds to a circuit that converts small analog signals to large digital signals. A fixed pattern consisting of a series of “L” level signals or a pattern consisting of a series of “H” level signals may be considered a DC signal.

[0248] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents.

Claims

1. First and second first conductivity type transistors, First and second second-conductivity transistors, The first to third resistances, Capacitor and, It comprises first and second constant current sources, The first resistor is connected between the first power supply node and the first node, and the first node is connected to the first output node. The second resistor is connected between the first power node and the second node, and the second node is connected to the second output node. One end and the other end of the first second conductivity type transistor are connected to the first node and the third node, respectively, and the gate end of the first second conductivity type transistor is connected to the first input node. One end and the other end of the second second conductivity type transistor are connected to the second node and the fourth node, respectively, and the gate end of the second second conductivity type transistor is connected to the second input node. One end and the other end of the first constant current source are connected to the third node and the second power supply node, respectively. One end and the other end of the second constant current source are connected to the fourth node and the second power supply node, respectively. The third resistor and the capacitor are connected in parallel between the third node and the fourth node. One end and the other end of the first first conductivity type transistor are connected to the first power supply node and the second input node, respectively, and the gate end of the first first conductivity type transistor is connected to the first node. One end and the other end of the second first conductivity transistor are connected to the first power node and the first input node, respectively, and the gate end of the second first conductivity transistor is connected to the second node. Semiconductor circuit.

2. The first conductivity type is P-type, The second conductivity type is N-type, A higher voltage is applied to the first power supply node than to the second power supply node. The semiconductor circuit according to claim 1.

3. The first conductivity type is N-type, The second conductivity type is P-type, A lower voltage is applied to the first power supply node than to the second power supply node. The semiconductor circuit according to claim 1.

4. Further comprising third to fifth first-conductivity transistors, One end and the other end of the third first conductivity type transistor are connected to the first power supply node and the second input node, respectively, and the gate end of the third first conductivity type transistor is connected to the gate end of the first first conductivity type transistor. The fourth first conductivity type transistor is connected between the first power node and the first first conductivity type transistor. The fifth first conductivity type transistor is connected between the first power node and the third first conductivity type transistor. Different control signals are input to the gate terminal of the fourth first conductivity transistor and the gate terminal of the fifth first conductivity transistor. The semiconductor circuit according to claim 1.

5. Further comprising sixth to eighth first conductivity type transistors, One end and the other end of the sixth first conductivity type transistor are connected to the first power supply node and the first input node, respectively, and the gate terminal of the sixth first conductivity type transistor is connected to the gate terminal of the second first conductivity type transistor. The seventh first conductivity type transistor is connected between the first power node and the second first conductivity type transistor. The eighth first conductivity type transistor is connected between the first power node and the sixth first conductivity type transistor. Different control signals are input to the gate terminal of the seventh first conductivity transistor and the gate terminal of the eighth first conductivity transistor. The semiconductor circuit according to claim 4.

6. A data input circuit comprising the semiconductor circuit described in claim 1, A first pad connected to the first input node and receiving a first signal from an external source, A second pad that receives a second signal from an external source, A third pad that receives a third signal from an external source, An amplification circuit that generates a clock signal based on the second signal and the third signal, The system includes a processing circuit that handles the data output from the data input circuit, The data input circuit includes a sampler that samples the output signal of the semiconductor circuit generated based on the first signal based on the clock signal and outputs the sampled data to the processing circuit. Semiconductor equipment.

7. The data input circuit comprises a plurality of the semiconductor circuits, The plurality of semiconductor circuits are connected in series between the first pad and the sampler. The semiconductor device according to claim 6.

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