High electron-mobility transistors made of Group III nitrides with an embedded p-type layer and their fabrication process

Abstract

The present invention provides a gallium nitride high electron mobility transistor having an embedded p-type layer. [Solution] The apparatus includes a substrate. The apparatus further includes a group III nitride buffer layer on the substrate and a group III nitride barrier layer on the group III nitride buffer layer, wherein the group III nitride barrier layer includes a band gap larger than the band gap of the group III nitride buffer layer. The apparatus further includes a source electrically coupled to the group III nitride barrier layer, a gate electrically coupled to the group III nitride barrier layer, a drain electrically coupled to the group III nitride barrier layer, and a p region located in or on the substrate below the group III nitride barrier layer.

Description

[Technical Field]

[0001] Cross-reference of prior applications This application is a continuation-in-part application of U.S. Patent Application No. 16 / 260,095 filed on 28 January 2019, which is incorporated herein by reference in whole, and is a continuation-in-part application of U.S. Patent Application No. 15 / 424,209 filed on 3 February 2017, which is incorporated herein by reference in whole, and is now a continuation-in-part application of U.S. Patent No. 10,192,980 issued on 29 January 2019, which is incorporated herein by reference in whole, and is a continuation-in-part application of U.S. Patent Application No. 15 / 192,545 filed on 24 June 2016, which is incorporated herein by reference in whole.

[0002] This disclosure relates to microelectronic devices, and more particularly to gallium nitride high electron-mobility transistors having an embedded p-type layer. This disclosure also relates to processes for fabricating microelectronic devices, and more particularly to processes for fabricating gallium nitride high electron-mobility transistors having an embedded p-type layer. [Background technology]

[0003] Group III nitride-based high electron-mobility transistors (HEMTs) are very promising candidates for both high-power radio frequency (RF) applications and low-frequency high-power switching applications. This is because the material properties of Group III nitrides, such as GaN and its alloys, enable high voltage and high current along with high RF gain and linearity in RF applications. Typical Group III nitride HEMTs rely on the configuration of a two-dimensional electron gas (2DEG) formed at the interface between a Group III nitride (e.g., AlGaN) barrier layer with a larger bandgap and a Group III nitride material (e.g., GaN) buffer layer with a smaller bandgap, where the smaller the bandgap of the material, the higher the electron affinity. The 2DEG is an accumulation layer within the smaller bandgap material and can contain high electron concentration and high electron mobility.

[0004] A key challenge in these transistor devices is the design of the buffer layer. Currently, many designs use deep-level impurities such as iron (Fe) or carbon (C) to minimize leakage current through the buffer layer under high drain voltage conditions. However, both Fe and C introduce a drain delay effect, where the recovery of the drain current is slow when the drain voltage changes from a high to a low value. This is undesirable for both power and RF applications, as it leads to lower switching current, lower efficiency, and other problems. In telecommunications applications, such a drain delay effect can lead to distortion and complicate pre-distortion correction schemes. The drain delay effect can be eliminated by using a high-purity buffer layer that does not contain Fe or C. However, these devices have high leakage current through the buffer layer, which is also unacceptable.

[0005] The high electric fields present within these devices due to high voltages and currents can lead to charge trapping, resulting in reduced performance. Overlapping gate structures or field plates are used to correct the electric field and improve the performance of Group III nitride HEMTs.

[0006] Therefore, alternative solutions are needed to address the delay effect in Group III nitride HEMTs and improve the performance of such devices. [Overview of the project]

[0007] According to one aspect of the present invention, a transistor device uses an embedded p-layer to enable the use of a higher purity buffer layer, thereby reducing leakage current while reducing drain delay effects. In certain embodiments, the transistor device is a Group III nitride HEMT comprising a Group III nitride buffer layer on a substrate and a Group III nitride barrier layer on the Group III nitride buffer layer. The Group III nitride (e.g., AlGaN) barrier layer has a larger bandgap than the Group III nitride (e.g., GaN) buffer layer. Source, gate, and drain contacts are electrically coupled to the Group III nitride barrier layer. The p-region is provided under the Group III nitride barrier layer.

[0008] In certain embodiments, the transistor device is a Group III nitride HEMT comprising a Group III nitride buffer layer on a substrate and a Group III nitride barrier layer on the Group III nitride buffer layer. The Group III nitride (e.g., AlGaN) barrier layer has a larger bandgap than the Group III nitride (e.g., GaN) buffer layer. Source, gate, and drain contacts are electrically coupled to the Group III nitride barrier layer. The transistor further includes a contact pad electrically coupled to the p-region.

[0009] In certain embodiments, the transistor device is a Group III nitride HEMT comprising a Group III nitride buffer layer on a substrate and a Group III nitride barrier layer on the Group III nitride buffer layer. The Group III nitride (e.g., AlGaN) barrier layer has a larger bandgap than the Group III nitride (e.g., GaN) buffer layer. Source, gate, and drain contacts are electrically coupled to the Group III nitride barrier layer. The gate is electrically coupled to the p-region.

[0010] In certain embodiments, the p-region is within and / or on the substrate beneath the barrier layer.

[0011] In certain embodiments, the p-region is implanted.

[0012] In certain embodiments, the p-region is located within the epitaxial layer.

[0013] In a particular embodiment, the p region includes multiple p regions.

[0014] In certain embodiments, the p region has separate contacts.

[0015] In certain embodiments, the p region is electrically connected to the source.

[0016] In certain embodiments, the p region is electrically connected to the gate.

[0017] In certain embodiments, the HEMT includes a field plate.

[0018] In certain embodiments, the field plate is electrically connected to the source.

[0019] In certain embodiments, the field plate and the p region are connected to the source.

[0020] In certain embodiments, the transistor may include a connection that electrically connects the contact pad to the p region.

[0021] In certain embodiments, the contact pad is configured to receive at least one of a bias and a signal.

[0022] In certain embodiments, the transistor may include a connection that electrically connects the gate to the p region.

[0023] A schematic aspect of the present invention includes a method for fabricating the transistor device described above.

[0024] Additional features, advantages, and aspects of this disclosure may be described or made apparent from the following detailed description, drawings, and consideration of the claims. Furthermore, it should be understood that both the above summary of this disclosure and the following detailed description are illustrative and intended to provide further explanation without limiting the claims of this disclosure.

[0025] The accompanying drawings included to provide a further understanding of this disclosure are incorporated herein and constitute part of this specification, serving to illustrate aspects of this disclosure and, together with detailed descriptions, to explain the principles of this disclosure. No attempt is made to provide more detail about the structural details of this disclosure than is necessary for a fundamental understanding of this disclosure and the various ways in which it can be implemented. [Brief explanation of the drawing]

[0026] [Figure 1] This is a cross-sectional view of one embodiment of a transistor according to this disclosure. [Figure 2] This is a cross-sectional view of another embodiment of the transistor according to this disclosure. [Figure 3] This is a cross-sectional view of another embodiment of the transistor according to this disclosure. [Figure 4] This is a cross-sectional view of another embodiment of the transistor according to this disclosure. [Figure 5] This is a cross-sectional view of another embodiment of the transistor according to this disclosure. [Figure 6] This is a cross-sectional view of another embodiment of the transistor according to this disclosure. [Figure 7] This is a cross-sectional view of another embodiment of the transistor according to this disclosure. [Figure 8] This is a cross-sectional view of another embodiment of the transistor according to this disclosure. [Figure 9] This is a cross-sectional view of another embodiment of the transistor according to this disclosure. [Figure 10] This is a cross-sectional view of another embodiment of the transistor according to this disclosure. [Figure 11] This is a plan view of another embodiment of the transistor according to this disclosure. [Figure 12] This is a cross-sectional view of another embodiment of the transistor according to this disclosure. [Figure 13] This is a cross-sectional view of another embodiment of the transistor according to this disclosure. [Figure 14] This figure shows the process for fabricating transistors according to this disclosure. [Figure 15] This figure shows the distribution of Al injected under the channeling conditions according to the embodiment of this disclosure, compared with a simulation of conventional injection conditions. [Figure 16] This is a cross-sectional view of another embodiment of the transistor according to this disclosure. [Figure 17] This is a cross-sectional view of another embodiment of the transistor according to this disclosure. [Figure 18] This is a cross-sectional view of another embodiment of the transistor according to this disclosure. [Figure 19] This is a cross-sectional view of another embodiment of the transistor according to this disclosure. [Figure 20] This is a cross-sectional view of another embodiment of the transistor according to this disclosure. [Figure 21] This is a cross-sectional view of another embodiment of the transistor according to this disclosure. [Figure 22] This is a cross-sectional view of another embodiment of the transistor according to this disclosure. [Figure 23] This is a cross-sectional view of another embodiment of the transistor according to this disclosure. [Figure 24] This is a cross-sectional view of another embodiment of the transistor according to this disclosure. [Figure 25] This is a cross-sectional view of another embodiment of the transistor according to this disclosure. [Figure 26] This is a cross-sectional view of another embodiment of the transistor according to this disclosure. [Figure 27] This is a cross-sectional view of another embodiment of the transistor according to this disclosure. [Figure 28] This is a cross-sectional view of another embodiment of the transistor according to this disclosure. [Figure 29] This is a cross-sectional view of another embodiment of the transistor according to this disclosure. [Figure 30]This is a cross-sectional view of another embodiment of the transistor according to this disclosure. [Figure 31] This is a cross-sectional view of another embodiment of the transistor according to this disclosure. [Figure 32] This is a cross-sectional view of another embodiment of the transistor according to this disclosure. [Figure 33] This is a cross-sectional view of another embodiment of the transistor according to this disclosure. [Figure 34] This is a cross-sectional view of another embodiment of the transistor according to this disclosure. [Figure 35] This is a cross-sectional view of another embodiment of the transistor according to this disclosure. [Modes for carrying out the invention]

[0027] Aspects of this disclosure, as well as their various features and advantageous details, will be described in more detail with reference to the non-limiting aspects and examples described and / or illustrated in the accompanying drawings and detailed in the following description. It should be noted that, even if not expressly expressed herein, features shown in the drawings are not necessarily depicted to scale, and features of one aspect may be used in other aspects, as will be understood by those skilled in the art. Descriptions of well-known components and processing techniques may be omitted to avoid unnecessarily obscuring aspects of this disclosure. The examples used herein are intended solely to facilitate understanding of how this disclosure can be carried out and to enable those skilled in the art to carry out aspects of this disclosure. Therefore, the examples and aspects herein should not be construed as limiting the scope of this disclosure, which is defined solely by the accompanying claims and applicable law. Furthermore, it should be noted that throughout some of the drawings, the same reference numerals represent similar parts in different embodiments disclosed.

[0028] While terms such as "First," "Second," etc., may be used herein to describe various elements, it will be understood that these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, without departing from the scope of this disclosure, the First element may be referred to as the Second element, and similarly, the Second element may be referred to as the First element. In this specification, the term "and / or" includes any combination of one or more of the related items listed.

[0029] When an element such as a layer, region, or substrate is described as being located "on" another element, or extending "onto" another element, it can be understood that this element is directly located on the other element, can extend directly onto the other element, or may have an intervening element. In contrast, when an element is described as being located "directly on" another element, or extending "directly onto" another element, there is no intervening element. Similarly, when an element such as a layer, region, or substrate is described as being located "over" another element, or extending "over" another element, it can be understood that this element is directly located on the other element, can extend directly onto the other element, or may have an intervening element. In contrast, when an element is described as being located "directly over" another element, or extending "directly over" another element, there is no intervening element. When an element is described as being "connected" or "coupled" to another element, it should be understood that this element can be directly connected or coupled to the other element, or that there may be an intermediary element. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there is no intermediary element.

[0030] Relative terms such as "below" or "above," "upper" or "lower," or "horizontal" or "vertical" may be used herein to describe the relationship between one element, layer, or region and another element, layer, or region shown in the diagram. It should be understood that these terms and the discussions above are intended to encompass different orientations of the device, in addition to the orientation shown in the diagram.

[0031] The terminology used herein is intended solely to describe specific aspects and is not intended to limit the disclosure. In this specification, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless otherwise explicitly indicated in the context. It will be further understood that, as used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of the described features, integers, steps, actions, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, actions, elements, components, and / or groups thereof.

[0032] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as those generally understood by those skilled in the art to which this disclosure belongs. Terms used herein should be construed to have a meaning consistent with their meaning in the context of this specification and in the relevant art, and it will be further understood that they should not be construed in an idealized or overly formal sense unless explicitly defined herein.

[0033] In addition to the type of structure, the properties of the semiconductor material on which the transistor is formed can also affect its operating parameters. Among the properties that influence the operating parameters of a transistor, electron mobility, saturation electron drift rate, breakdown field, and thermal conductivity can affect the high-frequency and high-power characteristics of the transistor.

[0034] Electron mobility is a measure of how quickly electrons are accelerated to their saturation velocity in the presence of an electric field. In the past, semiconductor materials with high electron mobility were preferred because they could generate more current with a smaller electric field, resulting in a faster response time when an electric field was applied. Saturation electron drift velocity is the maximum velocity that electrons can reach within a semiconductor material. In high-frequency applications, a faster velocity leads to a shorter source-to-drain time, so materials with a faster saturation electron drift velocity are preferred.

[0035] The breakdown field is the electric field strength at which a Schottky junction breaks and the current through the gate of a device suddenly increases. Generally, materials with high breakdown fields are preferred for high-power, high-frequency transistors because a larger field can be supported by a material of a given size. A larger field allows for faster transients because it can accelerate electrons more quickly than a smaller field.

[0036] Thermal conductivity is the ability of a semiconductor material to dissipate heat. In typical operation, all transistors generate heat. High-power and high-frequency transistors typically generate more heat than small-signal transistors. As the temperature of a semiconductor material increases, the junction leakage current generally increases, and the current through the field-effect transistor generally decreases, due to a decrease in carrier mobility with increasing temperature. Therefore, if heat is dissipated from the semiconductor, the material remains at a lower temperature and can carry a larger current with a lower leakage current.

[0037] This disclosure includes both extrinsic and intrinsic semiconductors. Intrinsic semiconductors are undoped (pure). Extrinsic semiconductors are doped, meaning that agents have been introduced to alter the electron and hole carrier concentrations of the semiconductor in thermal equilibrium. Both p-type and n-type semiconductors are disclosed, where p-type semiconductors have a hole concentration greater than the electron concentration, and n-type semiconductors have an electron concentration greater than the hole concentration.

[0038] Silicon carbide (SiC) possesses excellent physical and electronic properties, which should theoretically enable the fabrication of electronic devices that can operate at higher temperatures, higher powers, and higher frequencies than devices fabricated from silicon (Si) or gallium arsenide (GaAs) substrates. A high breakdown field of approximately 4 × E6 V / cm, a high saturation electron drift rate of approximately 2.0 × E7 cm / sec, and a high thermal conductivity of approximately 4.9 W / cm-°K indicate that SiC should be suitable for high-frequency and high-power applications. In some embodiments, the transistors of the present invention are provided on Si, GaAs, or other suitable substrates.

[0039] The drain delay of the disclosed HEMT is addressed in some embodiments by adding structures. These structures utilize embedded p-type layers to reduce the drain delay while simultaneously achieving high breakdown without unnecessarily increasing the leakage current. The p-type layer helps optimize the breakdown voltage and can be easily charged and discharged, thereby ensuring a reduction in drain delay. In one embodiment, the p-type layer is formed within a SiC substrate.

[0040] In embodiments where the p-region is formed within the substrate, two problems can be mitigated: 1. Forming a p-type layer within Group III N using ion implantation is difficult. Selective ion implantation allows for optimization of the device structure by enabling different dopant concentrations in different regions, which can be more difficult with epitaxial growth. However, it should be understood that the embedded p-regions according to different embodiments of the present invention can be located solely within the substrate, extend from the substrate to the epitaxial layer, or be located solely within the epitaxial layer. Dopants can be incorporated into the epitaxial layer by ion implantation alone, by epitaxial growth, or a combination of both. 2. P-type doping of GaN with magnesium (Mg) also exhibits a memory effect, which hinders the formation of sharp interfaces.

[0041] The disclosed process and structure can enable the development of Group III N HEMTs with high voltage capability suitable for power switching while reducing drain delay. The disclosed process and structure can also result in smaller device structures (through optimization of field shaping), thereby reducing costs. In addition, with appropriate design, the disclosed structure can also be applied to high-power RF devices for telecommunications and other application areas. A significant advantage is the minimization of the device's memory effect, which is a serious problem for telecommunications applications.

[0042] Figure 1 shows a cross-sectional view of one embodiment of the transistor according to this disclosure.

[0043] In particular, Figure 1 shows a cross-sectional view of transistor 100. Transistor 100 may include a substrate layer 102. The substrate layer 102 can be made from silicon carbide (SiC). In some embodiments, the substrate layer 102 can be a semi-insulating SiC substrate, a p-type substrate, an n-type substrate, etc. In some embodiments, the substrate layer 102 can be doped at a very low concentration. In one embodiment, the background impurity level can be reduced. In one embodiment, the background impurity level is 1E15 / cm 3 The following is possible: In one embodiment, the substrate layer 102 can be formed from SiC selected from the group consisting of 6H, 4H, 15R, 3C SiC, etc., the SiC having semi-insulating properties and being doped with vanadium or any other suitable dopant, or being high-purity undoped and having defects that provide semi-insulating properties.

[0044] In another embodiment, the substrate layer 102 may be GaAs, GaN, or other material suitable for the application fields described herein. In yet another embodiment, the substrate layer 102 may include sapphire, spinel, ZnO, silicon, or any other material capable of supporting the growth of a Group III nitride material.

[0045] Depending on the material of the substrate layer 102, a nucleation layer 136 can be formed on the substrate layer 102 to reduce lattice mismatch between the substrate layer 102 and the next layer in the transistor 100. In one embodiment, the nucleation layer 136 is formed directly on the substrate layer 102. In another embodiment, the nucleation layer 136 is formed on the substrate layer 102 with an intervening layer, such as a SiC epitaxial layer, formed on the SiC substrate layer 102. The nucleation layer 136 is made of a group III nitride material, such as Al x In y1-x-yThis can include different suitable materials such as GaN (where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, x + y ≤ 1). The nucleation layer 136 can be formed on the substrate layer 102 using known semiconductor growth techniques such as metal oxide chemical vapor deposition (MOCVD), hydride vapor deposition (HVPE), and molecular beam epitaxy (MBE). In some embodiments, the nucleation layer is AlN or AlGaN, such as undoped AlN or AlGaN.

[0046] In some embodiments, the buffer layer 104 is formed directly on the nucleation layer 136, or formed on the nucleation layer 136 together with an intervening layer. Depending on the embodiment, the buffer layer 104 is made of Al x Ga y In (1-x-y) N (where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, x + y ≤ 1) can be formed from different suitable materials such as Group III nitrides, for example GaN, aluminum gallium nitride (AlGaN), aluminum nitride (AlN), or other suitable materials. In one embodiment, the buffer layer 104 is formed from GaN. The buffer layer 104 or a portion thereof can be doped with dopants such as Fe and / or C, or alternatively, it can be completely or partially undoped. In one embodiment, the buffer layer 104 is located directly on the substrate layer 102.

[0047] In one embodiment, the buffer layer 104 can be high-purity GaN. In one embodiment, the buffer layer 104 can be high-purity GaN, which can be low-doped n-type. In one embodiment, the buffer layer 104 can also use a higher bandgap group III nitride layer on the side of the buffer layer 104 opposite to the barrier layer 108 as a back barrier, such as an AlGaN back barrier, to achieve better electron confinement.

[0048] In one aspect, the buffer layer 104 can have a buffer layer thickness defined as the distance between the upper surface of the substrate layer 102 and the lower surface of the barrier layer 108. In one aspect, the buffer layer thickness can be less than 0.8 μm, less than 0.7 μm, less than 0.6 μm, less than 0.5 μm, or less than 0.4 μm. In one aspect, the buffer layer thickness can have a range of 0.8 μm to 0.6 μm, 0.7 μm to 0.5 μm, 0.6 μm to 0.4 μm, 0.5 μm to 0.3 μm, 0.4 μm to 0.2 μm, or 0.7 μm to 0.3 μm.

[0049] In one aspect, the transistor 100 can have an intervening layer thickness defined as the length between the upper surface of the substrate layer 102 and the lower surface of the barrier layer 108. In one aspect, the intervening layer thickness can be less than 0.8 μm, less than 0.7 μm, less than 0.6 μm, less than 0.5 μm, or less than 0.4 μm. In one aspect, the intervening layer thickness can have a range of 0.8 μm to 0.6 μm, 0.7 μm to 0.5 μm, 0.6 μm to 0.4 μm, 0.5 μm to 0.3 μm, or 0.4 μm to 0.2 μm.

[0050] The barrier layer 108 can be formed on the buffer layer 104. In one aspect, the barrier layer 108 can be formed directly on the buffer layer 104, and in other aspects, the barrier layer 108 can be formed on the buffer layer 104 together with an intervening layer. Depending on the embodiment, the buffer layer 104 can be Al x Ga y In (1-x-y)N (where 0≦x≦1, 0≦y≦1, x+y≦1) can be formed from different suitable materials such as AlGaN, AlN, or InAlGaN, or other suitable materials such as Group III nitrides. In one embodiment, the barrier layer 108 can be AlGaN, and in another embodiment, the barrier layer 108 is AlN. In one embodiment, the barrier layer 108 can be undoped. In one embodiment, the barrier layer 108 can be doped. In one embodiment, the barrier layer 108 can be an n-type material. In some embodiments, the barrier layer 108 can have multiple n-type material layers with different carrier concentrations. In one embodiment, the barrier layer 108 can be a Group III nitride or a combination thereof. In one embodiment, the band gap of the buffer layer 104 can be made smaller than the band gap of the barrier layer 108 in order to form a two-dimensional electron gas (2DEG) at the heterointerface 152 between the buffer layer 104 and the barrier layer 108 when an appropriate level of bias is applied. In one embodiment, when an appropriate level of bias is applied, the band gap of the buffer layer 104, which can be made of GaN, can be made smaller than the band gap of the barrier layer 108, which can be made of AlGaN, in order to form a two-dimensional electron gas (2DEG) at the heterointerface 152 between the buffer layer 104 and the barrier layer 108.

[0051] In one embodiment, a source 110, a drain 112, and a gate 114 are formed on a barrier layer 108. The source 110, drain 112, and / or gate 114 can be placed directly on the barrier layer 108, or they can be located on an intervening layer on the barrier layer 108, such as an AlGaN layer on an AlN barrier layer. Other or additional intervening layers are also possible. For example, a spacer layer 116 of SiN, AlO, SiO, SiO2, AlN, or a combination thereof can be provided on the barrier layer 108 or other intervening layers. In one embodiment, the barrier layer 108 may include a region 164 of N+ material beneath the source 110 and / or drain 112. In one embodiment, the barrier layer 108 may include a Si-doped region 164 beneath the source 110 and / or drain 112. In one embodiment, an n-type dopant is injected into the region 164.

[0052] To protect and isolate the gate 114 and drain 112, a spacer layer 116 can be placed on the barrier layer 108, opposite the buffer layer 104 and adjacent to the gate 114, drain 112, and source 110. The spacer layer 116 can be a passivation layer made from SiN, AlO, SiO, SiO2, AlN, or a combination of multiple layers thereof. In one embodiment, the spacer layer 116 is a passivation layer made from SiN. In one embodiment, the spacer layer 116 can be deposited using MOCVD, plasma chemical deposition (CVD), thermal filament CVD, or sputtering. In one embodiment, the spacer layer 116 can include the deposition of Si3N4. In one embodiment, the spacer layer 116 forms an insulating layer. In one embodiment, the spacer layer 116 forms an insulator. In one embodiment, the spacer layer 116 can be a dielectric.

[0053] In some embodiments, the gate 114 is deposited in a channel formed within the spacer layer 116, and the T-gate is formed using semiconductor processing techniques understood by those skilled in the art. Other gate configurations are also possible. In some embodiments, a second spacer layer 117 is formed on the first spacer layer 116 and the gate 114, and a field plate 132 can be provided on the second spacer layer 117. In other embodiments, for example, the first spacer layer 116 is formed on the barrier layer 108 and the gate 114. In such embodiments, the field plate 132 can be formed directly on the first spacer layer 116. Other multiple field plate configurations are also possible, including configurations in which the field plate 132 overlaps or does not overlap the gate 114, and / or configurations in which multiple field plates 132 are used.

[0054] According to embodiments of the present invention, an embedded p-region or p-type material layer 120 is formed below the barrier layer 108, between the barrier layer 108 and the substrate layer 102, and / or within the substrate layer 102. The p-type material region can be provided independently within the substrate layer 102, can extend from the substrate layer 102 to the epitaxial layer, or can be located independently within the epitaxial layer. The dopant can be incorporated into the epitaxial layer by ion implantation alone, by epitaxial growth, or a combination of both. The p-type material layer 120 can span multiple layers and may include multiple different or stepwise p-doped regions. Depending on the embodiment, the p-type material layer 120 or a portion thereof can extend from a p-type material contact 118 in a recess 119 formed within the transistor 100, and can extend to or beyond the source 110, to or beyond the gate 114, to or in front of the gate 114, to the gate 114, and / or across the transistor 100.

[0055] In certain embodiments, the p-type material contact 118 is electrically connected to receive an external signal or bias. In certain embodiments, the source 110 is electrically connected to the p-type material layer 120 via a connector 138. In certain embodiments, the field plate 132 is electrically connected to the source 110 via a connector 140. In certain embodiments, the field plate 132 is connected to the source 110, and the source 110 is connected to the p-type material layer 120 via connector 140, connector 138, or a single connector to both. In certain embodiments, the transistor 100 may further include connectors 138 and 140 configured to connect the field plate 132 directly to the p-type material contact 118. In certain embodiments, the transistor 100 may further include connectors 138 and 140 configured to connect the field plate 132 directly to the p-type material contact 118 without connecting to the source 110. In certain embodiments, the transistor 100 may further include connectors 138 and 140 configured to connect the field plate 132 directly to the p-type material contact 118 without any intervening connectors. In certain embodiments, the gate 114 is electrically connected to the p-type material layer 120 via a connector 154.

[0056] According to aspects of the present invention, at least some portions of the substrate layer 102 may include a p-type material layer 120. According to aspects of the present invention, the p-type material layer 120 can be formed by ion implantation and annealing of aluminum (Al). In other aspects, the p-type material layer 120 can be formed by ion implantation of boron, gallium, or any other material capable of forming a p-type layer, or a combination thereof. In one aspect, the p-type material layer 120 can be formed by implantation and annealing of Al before the growth of any GaN layer. In one aspect, ion packaging may utilize channeling implantation. In one aspect, channeling implantation may include aligning an ion beam with the substrate layer 102. Ion beam alignment can increase implantation efficiency.

[0057] Aspects of this disclosure are based on the understanding that by using implantation channeling, it is possible to controlly form implanted regions of silicon carbide with very uniform depth, and as a result, reduce lattice damage. Channeling occurs when ions are implanted along the crystal axes of a semiconductor. When the implantation direction is close to the principal axis of the crystal lattice, the atoms in the crystal lattice appear to be "aligned" with respect to the implantation direction, and the implanted ions appear to travel through channels created by the crystal structure. This reduces the likelihood of collisions between the implanted ions and atoms in the crystal lattice. As a result, the depth of the implantation is greatly increased.

[0058] Generally, channeling occurs in silicon carbide when the implantation direction is within approximately ±0.2° of the crystal axis of the silicon carbide crystal. In some embodiments, implantation can be greater than ±0.2° of the crystal axis of the silicon carbide crystal, but this implantation may be less effective. For example, when the implantation direction is greater than approximately ±0.2° of the crystal axis of the silicon carbide crystal, atoms in the lattice may appear to be randomly dispersed with respect to the implantation direction, which may reduce the channeling effect. In this specification, the term “implantation angle” refers to the implantation direction and the c-axis of the semiconductor layer into which the ions are implanted or <0001> This refers to the angle between the crystal axis and the axis of the silicon carbide layer. Therefore, an injection angle of less than approximately 2° relative to the c-axis of the silicon carbide layer can be expected to result in channeling. However, other injection angles can be used similarly.

[0059] In one embodiment, the p-type material layer 120 is injected at 25°C with an injection energy E1 = 100 keV and a dosage of 1 E13 cm³. 2 In 4H-SiC injected under the channeling conditions described above... 27 It can be formed by ion implantation of Al. In one embodiment, the p-type material layer 120 is implanted at 25°C with an implantation energy E2 = 300 keV and a dosage of 1 E13 cm³. 2 In 4H-SiC injected under the channeling conditions described above... 27Al can be formed by ion implantation. However, other implantation energies and doses are also intended. For example, in some embodiments, the implantation energies can be 20 keV to 80 keV, 80 keV to 120 keV, 120 keV to 160 keV, 160 keV to 200 keV, 200 keV to 240 keV, 240 keV to 280 keV, 280 keV to 340 keV, 340 keV to 400 keV, 20 keV to 400 keV, and / or 80 keV to 340 keV, and in some embodiments, the implantation dose is 0.6E13 cm 2 ~0.8E13cm 2 , 0.8E13cm 2 ~1.2E13cm 2 , 1.2E13cm 2 ~1.6E13cm 2 , 1.6E13cm 2 ~2E13cm 2 , 0.6E13cm 2 ~2E13cm 2 , and / or 0.8E13cm 2 ~1.2E13cm 2 This can be done. In addition, it should be noted that the p-type material layer 120 can be formed by injecting other materials such as boron (B) and gallium (Ga), followed by high-temperature annealing.

[0060] In one embodiment, as a result of ion implantation, the p-type material layer 120 can be a deep layer. In one embodiment, as a result of ion implantation, the p-type material layer 120 can have a thickness of 1 μm or less. In one embodiment, as a result of ion implantation, the p-type material layer 120 can have a thickness of 0.7 μm or less. In one embodiment, as a result of ion implantation, the p-type material layer 120 can have a thickness of 0.5 μm or less. In one embodiment, as a result of ion implantation, the p-type material layer 120 can have a thickness of 0.3 μm to 0.5 μm. In one embodiment, as a result of ion implantation, the p-type material layer 120 can have a thickness of 0.2 μm to 0.6 μm. In one embodiment, as a result of ion implantation, the p-type material layer 120 can have a thickness of 0.4 μm to 0.6 μm. In one embodiment, as a result of ion implantation, the p-type material layer 120 can have a thickness of 0.6 μm to 0.8 μm. In one embodiment, as a result of ion implantation, the p-type material layer 120 can have a thickness of 0.6 μm to 1.6 μm. In one embodiment, as a result of ion implantation, the p-type material layer 120 can have a thickness of 0.6 μm to 2.1 μm. In one embodiment, as a result of ion implantation, the p-type material layer 120 can have a thickness of 1 μm to 5 μm. In one embodiment, the implantation and / or administration of the p-type material layer 120 is 1 cm 3 The range can be 5E15 to 5E17, and it can extend to a maximum depth of 5 μm.

[0061] In one embodiment, as a result of ion implantation, the p-type material layer 120 can have a thickness of 0.05% to 0.3% of the thickness of the substrate layer 102. In one embodiment, as a result of ion implantation, the p-type material layer 120 can have a thickness of 0.05% to 0.1% of the thickness of the substrate layer 102. In one embodiment, as a result of ion implantation, the p-type material layer 120 can have a thickness of 0.1% to 0.15% of the thickness of the substrate layer 102. In one embodiment, as a result of ion implantation, the p-type material layer 120 can have a thickness of 0.15% to 0.2% of the thickness of the substrate layer 102. In one embodiment, as a result of ion implantation, the p-type material layer 120 can have a thickness of 0.2% to 0.25% of the thickness of the substrate layer 102. In one embodiment, as a result of ion implantation, the p-type material layer 120 can have a thickness of 0.25% to 0.3% of the thickness of the substrate layer 102.

[0062] The p-type material layer 120 can be injected into the substrate layer 102 and subsequently annealed. Annealing can enable the injection. In one embodiment, a masking layer material can be used during injection. In some embodiments, a capping layer material can be used to cover the wafer surface during the annealing of the p-type material layer 120 to prevent substrate desorption at high temperatures. After the p-type material layer 120 is formed, the masking layer material can be removed. Annealing can be performed for 5 to 30 minutes in a temperature range of 1500 to 1850°C. Other annealing times and temperature profiles are also intended.

[0063] In some embodiments, the substrate layer 102 can be fabricated from a p-type SiC substrate. Furthermore, in these embodiments, the substrate layer 102, which is a p-type SiC substrate, can subsequently be subjected to a process described herein, which includes the injection of an additional p-type layer.

[0064] Figures 2 to 34 illustrate different embodiments and aspects of the present invention, and in various embodiments and figures, the same reference numerals represent similar parts. It should be understood that features described in one embodiment may be added to or superseded by features in another embodiment.

[0065] As shown in Figures 2 and 3, the substrate layer 102 may include a p+ layer 106. The p+ layer 106 can be used to reduce the charging time constant and to achieve contact formation. In some embodiments, the p+ layer 106 can also be formed by ion implantation and annealing. The p+ layer 106 can be doped to the highest possible concentration with the lowest possible sheet resistance. In some embodiments, the p+ layer 106 may be located within the gate-source region. In some embodiments, the p+ layer 106 may be located within the gate-source region and partially below the gate 114. In some embodiments, the p+ layer 106 may be located within a restricted area, which will be described in more detail below. In some embodiments, the p+ layer 106 may have a thickness of less than 0.6 μm. In some embodiments, the p+ layer 106 may have a thickness of less than 0.5 μm. In some embodiments, the p+ layer 106 may have a thickness of less than 0.4 μm. In some embodiments, the p+ layer 106 can have a thickness of less than 0.3 μm. In some embodiments, the p+ layer 106 can have a thickness of less than 0.2 μm. In some embodiments, the p+ layer 106 can have a thickness of 0.1 to 0.6 μm. In some embodiments, the p+ layer 106 can have a thickness of 0.5 to 0.6 μm. In some embodiments, the p+ layer 106 can have a thickness of 0.4 to 0.5 μm. In some embodiments, the p+ layer 106 can have a thickness of 0.3 to 0.4 μm. In some embodiments, the p+ layer 106 can have a thickness of 0.2 to 0.3 μm. In some embodiments, the p+ layer 106 can have a thickness of 0.1 to 0.3 μm. In some embodiments, the p+ layer 106 can have a thickness of 0.05 to 0.25 μm. In some embodiments, the p+ layer 106 can have a thickness of 0.15 to 0.25 μm.

[0066] In one embodiment, the source 110 may have a p-type material contact 118 on the p+ layer 106. The p-type material contact 118 may be formed on the p+ layer 106 within a recess 119 provided in the buffer layer 104 and the barrier layer 108. The p-type material contact 118 may be electrically coupled to the p+ layer 106. The recess may extend to the p+ layer 106 to allow the p-type material contact 118 to be generated in the p+ layer 106. The recess 119 may be formed by etching, or it may be defined using a material that can be removed after the recess 119 has been generated.

[0067] In one embodiment, the source 110 may have a p-type material contact 118 on a p-type material layer 120. The p-type material contact 118 may be formed on the p-type material layer 120 within a recess 119 provided in the buffer layer 104 and the barrier layer 108. The p-type material contact 118 may be electrically coupled to the p-type material layer 120. The recess 119 may extend into the p-type material layer 120 to allow the p-type material contact 118 to be generated in the p-type material layer 120. The recess 119 may be formed by etching, or it may be defined using a material that can be removed after the recess 119 has been generated.

[0068] In one embodiment, the p-type material contact 118 can be formed in or on a layer of the transistor 100 within a recess 119 provided as shown by the dashed frame in Figure 1. In this embodiment, the recess 119 can be configured as a partial recess, a partial groove, etc., on the surface of the transistor 100. In one embodiment, a p-dopant can be injected and / or doped into a region or area located beneath or adjacent to the p-type material contact 118 to form an electrical connection with the p-type material layer 120 and / or the p+ layer 106. In one embodiment, this layer can be an epitaxial material on which the p-type material contact 118 is provided. In one embodiment, during the epitaxial growth of this layer or other layers, a p-dopant can be injected and / or doped into a region or area located beneath or adjacent to the p-type material contact 118 to form an electrical connection with the p-type material layer 120 and / or the p+ layer 106. Although not shown in the remaining figures, this embodiment may be included in any embodiment of transistor 100 as illustrated or described herein.

[0069] In one embodiment, the p-type material contact 118 can be formed in or on the buffer layer 104 within a recess 119 that extends to the buffer layer 104, as shown by the dashed box below in Figure 1. In this embodiment, the recess 119 can be configured as a partial recess, a partial groove, etc., on the surface of the transistor 100. In one embodiment, a p-dopant can be injected and / or doped into a region or area located below or adjacent to the p-type material contact 118 to form an electrical connection with the p-type material layer 120 and / or the p+ layer 106. In one embodiment, the buffer layer 104 can be made of an epitaxial material, on which the p-type material contact 118 is provided. In one embodiment, during the epitaxial growth of the buffer layer 104 or other layer, a p-dopant can be injected and / or doped into a region or area located below or adjacent to the p-type material contact 118 to form an electrical connection with the p-type material layer 120 and / or the p+ layer 106. Although not shown in the remaining figures, this embodiment may be included in any embodiment of transistor 100 as illustrated or described herein.

[0070] In one embodiment, the p-type material contact 118 can be formed in or on the barrier layer 108, as shown by the dashed box above in Figure 1. In this embodiment, the recess 119 may or may not be formed. If the recess 119 is formed, it can be configured as a partial recess, a partial groove, etc., within the surface of the transistor 100. In one embodiment, a p-dopant can be injected and / or doped into a region or area located beneath or adjacent to the p-type material contact 118 to form an electrical connection with the p-type material layer 120 and / or the p+ layer 106. In one embodiment, the barrier layer 108 can be an epitaxial material on which the p-type material contact 118 is provided. In one embodiment, during the epitaxial growth of the barrier layer 108 or other layer, a p-dopant can be injected and / or doped into a region or area located beneath or adjacent to the p-type material contact 118 to form an electrical connection with the p-type material layer 120 and / or the p+ layer 106. Although not shown in the remaining figures, this embodiment may be included in any embodiment of transistor 100 as illustrated or described herein.

[0071] In one embodiment, a spacer layer 116 can be provided on the barrier layer 108. In one embodiment, a second spacer layer 117 can be provided on the gate 114 and the first spacer layer 116. In one embodiment, the spacer layer 116 may include a nonconductive material such as a dielectric. In one embodiment, the spacer layer 116 may include multiple different dielectric layers or combinations of dielectric layers. In one embodiment, the spacer layer 116 may have many different thicknesses, with a preferred thickness range of approximately 0.05 to 2 μm.

[0072] In one embodiment, the spacer layer 116 may contain a material such as a Group III nitride material having different Group III elements, such as an alloy of Al, Ga, or In, and a preferred spacer layer material is Al x In y Ga 1-x-y (Here, 0 ≤ x ≤ 1, and 0 ≤ y ≤ 1, x + y ≤ 1).

[0073] Figure 4 shows a cross-sectional view of another embodiment of the transistor according to this disclosure, and Figure 5 shows a cross-sectional view of another embodiment of the transistor according to this disclosure.

[0074] As shown in Figures 4 and 5, an epitaxial layer 202 can be formed on the substrate layer 102. In one embodiment, the epitaxial layer 202 can be formed on the substrate layer 102. In another embodiment, the epitaxial layer 202 can be directly formed on the substrate layer 102. In the embodiments of Figures 4 and 5, the p-type material layer 120 can be located within the epitaxial layer 202. In some embodiments, in a specific embodiment where the substrate layer 102 includes a substrate material such as GaAs or GaN, the p-type material layer 120 can be located within the epitaxial layer 202. In some embodiments, the epitaxial layer 202 can be a group III nitride material. In some embodiments, the epitaxial layer 202 can be two or more group III nitride materials.

[0075] In one embodiment, the epitaxial layer 202 is formed from SiC. In some embodiments, the p-type material layer 120 can be located within the epitaxial layer 202 and can be SiC. In some embodiments, the p-type material layer 120 can be located within the epitaxial layer 202 and can be SiC, and the p-type material layer 120 can contain Al and / or Br. In some embodiments, the p-type material layer 120 can be located within the epitaxial layer 202 and can be SiC, and the p-type material layer 120 can contain Al and / or Br implantation.

[0076] In some embodiments, the p-type material layer 120 can be located within the epitaxial layer 202. In some embodiments, the p-type material layer 120 can be located within the epitaxial layer 202 and can be GaN. In some embodiments, the p-type material layer 120 can be located within the epitaxial layer 202 and can be GaN, and the p-type material layer 120 can contain magnesium (Mg), carbon (C), and / or zinc. In some embodiments, the p-type material layer 120 can be located within the epitaxial layer 202 and can be GaN, and the p-type material layer 120 can contain implantation of magnesium (Mg), carbon (C), and / or zinc.

[0077] In one embodiment, the epitaxial layer 202 can be placed on the substrate layer 102. In one embodiment, the epitaxial layer 202 can be placed directly on the substrate layer 102. In one embodiment, the buffer layer 104 can be placed on the epitaxial layer 202. In one embodiment, the buffer layer 104 can be placed directly on the epitaxial layer 202. In one embodiment, the p-type material layer 120 can be injected into the epitaxial layer 202 as described herein and subsequently annealed. Furthermore in this embodiment, the epitaxial layer 202 can subsequently be subjected to the process described herein, which may include the formation and / or injection of a p+ layer 106.

[0078] In one embodiment, an epitaxial layer 202 can be placed on a substrate layer 102, and a buffer layer 104 can be formed on the epitaxial layer 202. In another embodiment, an epitaxial layer 202 can be placed on a substrate layer 102, and a buffer layer 104 can be directly formed on the epitaxial layer 202.

[0079] In one embodiment, as a result of ion implantation, the p-type material layer 120 can have a thickness of 10% to 20% of the thickness of the epitaxial layer 202. In one embodiment, as a result of ion implantation, the p-type material layer 120 can have a thickness of 20% to 30% of the thickness of the epitaxial layer 202. In one embodiment, as a result of ion implantation, the p-type material layer 120 can have a thickness of 30% to 40% of the thickness of the epitaxial layer 202. In one embodiment, as a result of ion implantation, the p-type material layer 120 can have a thickness of 40% to 50% of the thickness of the epitaxial layer 202. In one embodiment, as a result of ion implantation, the p-type material layer 120 can have a thickness of 50% to 60% of the thickness of the epitaxial layer 202. In one embodiment, as a result of ion implantation, the p-type material layer 120 can have a thickness of 60% to 70% of the thickness of the epitaxial layer 202. In one embodiment, as a result of ion implantation, the p-type material layer 120 can have a thickness of 70% to 80% of the thickness of the epitaxial layer 202. In another embodiment, as a result of ion implantation, the p-type material layer 120 can have a thickness of 80% to 90% of the thickness of the epitaxial layer 202.

[0080] In another embodiment, the epitaxial layer 202 can utilize a p-type material, and the epitaxial layer 202 can be placed on a substrate layer 102. In yet another embodiment, the epitaxial layer 202 can utilize a p-type material, and the epitaxial layer 202 can be placed directly on a substrate layer 102. In this regard, in certain embodiments, the epitaxial layer 202 can be grown from a p-type material, and as a result, the epitaxial layer 202 may have a p-type material layer 120, eliminating the need for the injection described herein to form the p-type material layer 120. Subsequently, the epitaxial layer 202 can be subjected to a process including the injection of a p+ layer 106 as described herein. In some embodiments, the epitaxial layer 202 can be formed by epitaxial growth using an off-axis oriented wafer.

[0081] Figure 5 shows a cross-sectional view of another embodiment of the transistor according to the present disclosure. In the embodiment of Figure 5, the epitaxial layer 202 can be formed from a p-type material and the epitaxial layer 202 can be placed on a substrate layer 102. In one embodiment, the epitaxial layer 202 can be formed from a p-type material and the epitaxial layer 202 can be placed directly on the substrate layer 102. In this embodiment, the entire epitaxial layer 202 can form a p-type material layer 120. Subsequently, the epitaxial layer 202 can be subjected to a process including the injection of a p+ layer 106 as described herein.

[0082] In some embodiments, the p-type material layer 120 may also be configured to have a dosing and / or injection profile that varies orthogonally to the surface. In some embodiments, the p-type material layer 120 may also be configured to have a profile that varies orthogonally to the surface extending into the cross-section of these figures. This profile can be optimized to achieve a desired breakdown voltage, device size, switching time, etc.

[0083] In one embodiment, the p-type material layer 120 can be uniformly present beneath the transistor 100 in the case of a specific application field shown in Figures 2, 4, and 6.

[0084] In another embodiment for a specific application field, such as RF applications, the p-type material layer 120 may be located within a restricted area, such as a portion of the gate-source region of the transistor 100, as shown in Figures 3 and 5 and described in more detail below.

[0085] In some embodiments, a portion of the voltage from drain 112 to source 110 can be reduced within the region of the p-type material layer 120. This can also cause lateral channel attenuation. Lateral attenuation can reduce the lateral electric field and increase the breakdown voltage. Alternatively, a smaller structure can be obtained for the required breakdown voltage. The p-type material layer 120 can eliminate the need to administer buffer C or Fe required to maintain the applied drain voltage. Eliminating C and Fe reduces current reduction under operating conditions (no trapping). Furthermore, in some embodiments, the p-type material layer 120 can support the electric field.

[0086] In some embodiments, the epitaxial layer 202 may include a p+ layer 106, as shown in Figures 4, 5, and 6. The p+ layer 106 can be used to reduce the charging time constant and to achieve contact formation. In some embodiments, the p+ layer 106 may also be formed by ion implantation and annealing. The p+ layer 106 may be doped to the highest possible concentration with the lowest possible sheet resistance. In some embodiments, the p+ layer 106 may be located within the gate-source region. In some embodiments, the p+ layer 106 may be located within the gate-source region and partially below the gate 114. In some embodiments, the p+ layer 106 may be located within a restricted area, which will be described in more detail below. In some embodiments, the p+ layer 106 may have a thickness of less than 0.3 μm. In some embodiments, the p+ layer 106 may have a thickness of less than 0.2 μm. In some embodiments, the p+ layer 106 may have a thickness of 0.1 to 0.3 μm. In some embodiments, the p+ layer 106 can have a thickness of 0.05 to 0.25 μm. In some embodiments, the p+ layer 106 can have a thickness of 0.15 to 0.25 μm.

[0087] Figure 7 shows a cross-sectional view of another embodiment of the transistor according to this disclosure.

[0088] In particular, Figure 7 shows a transistor 100 that may include one or more embodiments of the present disclosure as described herein. Specifically, the embodiment of Figure 7 shows that the buffer layer 104 may include an upper 602 of high-purity GaN, and the buffer layer 104 may also include a lower 604 that can form an AlGaN back barrier to achieve better electron confinement. In one embodiment, the lower 604 forming the back barrier may be n-type AlGaN. The back barrier structure may be implemented in any embodiment of the present disclosure.

[0089] In embodiments of the transistor 100 of this disclosure, the buffer layer 104 can be designed to be of a high-purity type where the Fermi level is in the upper half of the band gap, thereby minimizing the slow trapping effect typically observed in GaN HEMTs. In this regard, traps below the Fermi level are always filled, and therefore slow transients can be prevented. In some embodiments, the buffer layer 104 can be made as thin as possible, consistently achieving good crystal quality. The applicant has already demonstrated that a 0.4 μm layer has good quality.

[0090] In embodiments of the transistor 100 of this disclosure, Al is grown via an epitaxial crystal growth method such as MOCVD (metal-organic chemical vapor deposition), HVPE (hydride vapor deposition), or MBE (molecular beam epitaxy). x In y Ga 1-x-y A nucleation layer 136 or buffer layer 104 (where 0≦x≦1 and 0≦y≦1, x+y≦1) can be grown on the substrate layer 102. The formation of the nucleation layer 136 may depend on the material of the substrate layer 102.

[0091] In embodiments of the transistor 100 of this disclosure, the buffer layer 104 can be formed by lateral epitaxial overgrowth (LEO). LEO can improve the crystal quality of the GaN layer, for example. When the semiconductor layers of a HEMT are epitaxial, each epitaxial layer growing can affect the characteristics of the device. For example, LEO can reduce the dislocation density within the epitaxial GaN layer.

[0092] In embodiments of the transistor 100 of this disclosure, the injection of the p-type material layer 120 can extend the overall length of the transistor 100, as shown in Figures 2, 4, and 6. In some embodiments, the injection of the p-type material layer 120 can partially extend the length of the transistor 100, as shown in Figures 3 and 5.

[0093] In embodiments of the transistor 100 of this disclosure, the p-type material layer 120 can be neutralized to limit the length of the p-type material layer 120. In one embodiment, neutralization may include the implantation of impurities. In one embodiment, neutralizing the p-type material layer 120 may include absorbing the charge of the p-type material layer 120 with a material of opposite polarity. Another method for limiting the length of the p-type material layer 120 may be etching the p-type material layer 120. Another method for limiting the length of the p-type material layer 120 may be limiting the implantation area using a masking material.

[0094] In embodiments of the transistor 100 of this disclosure, the p-type material layer 120 can be formed by growing the p-type material layer 120. The growth can be, for example, epitaxial. To limit the length of the p-type material layer 120, the p-type material layer 120 can be neutralized by etching or other methods.

[0095] In an embodiment of the transistor 100 of this disclosure, the substrate layer 102 can be etched, and the p-type material layer 120 can be formed by growing the p-type material layer 120. In one embodiment, the growth can be epitaxial.

[0096] In embodiments of the transistor 100 of this disclosure, the p-type material layer 120 may be an epitaxial layer formed from SiC. In some embodiments, the p-type material layer 120 may be an epitaxial layer, may be SiC, and may contain Al and / or Br. In some embodiments, the p-type material layer 120 may be an epitaxial layer, may be SiC, and may contain implantation of Al and / or Br.

[0097] In embodiments of the transistor 100 of this disclosure, the p-type material layer 120 may be an epitaxial layer and may be GaN. In some embodiments, the p-type material layer 120 may be an epitaxial layer and may be GaN, and may contain magnesium (Mg), carbon (C), and / or zinc. In some embodiments, the p-type material layer 120 may be an epitaxial layer and may be GaN, and may contain implantation of magnesium (Mg), carbon (C), and / or zinc.

[0098] In an embodiment of the transistor 100 of this disclosure, the substrate layer 102 can be etched, and the p+ layer 106 can be formed by growing the p+ layer 106. In one embodiment, the growth can be epitaxial.

[0099] In embodiments of the transistor 100 of this disclosure, the p+ layer 106 may be an epitaxial layer formed from SiC. In some embodiments, the p+ layer 106 may be an epitaxial layer, may be SiC, and may contain Al and / or Br. In some embodiments, the p+ layer 106 may be an epitaxial layer, may be SiC, and may contain implantation of Al and / or Br.

[0100] In embodiments of the transistor 100 of this disclosure, the p+ layer 106 may be an epitaxial layer and may be made of GaN. In some embodiments, the p+ layer 106 may be an epitaxial layer and may be made of GaN and may contain magnesium (Mg), carbon (C), and / or zinc. In some embodiments, the p+ layer 106 may be an epitaxial layer and may be made of GaN and may contain implantation of magnesium (Mg), carbon (C), and / or zinc.

[0101] In embodiments of the transistor 100 of this disclosure, the substrate layer 102 may be silicon carbide and may include a carbon plane. In one embodiment, the substrate layer 102 may be silicon carbide and may include a carbon plane adjacent to the buffer layer 104. In one embodiment, the substrate layer 102 may be silicon carbide and may include a carbon plane, and the substrate layer 102 may be flipped over so as to be adjacent to the buffer layer 104. In this embodiment, the buffer layer 104 may be GaN and may have a nitrogen plane adjacent to the carbon plane of the substrate layer 102. In one embodiment, the buffer layer 104 may be GaN and may have alternating GaN layers and N layers, with the N layers and / or nitrogen plane adjacent to the carbon plane of the substrate layer 102.

[0102] In embodiments of the transistor 100 of this disclosure, the buffer layer 104 may include nonpolar GaN. In one embodiment, the buffer layer 104 may include semipolar GaN. In one embodiment, the buffer layer 104 may include hot-walled epitaxy. In one embodiment, the buffer layer 104 may include hot-walled epitaxy having a thickness in the range of 0.15 μm to 0.25 μm, 0.2 μm to 0.3 μm, 0.25 μm to 0.35 μm, 0.3 μm to 0.35 μm, 0.35 μm to 0.4 μm, 0.4 μm to 0.45 μm, 0.45 μm to 0.5 μm, 0.5 μm to 0.55 μm, or 0.15 μm to 0.55 μm. The p-type material layer 120 can help avoid problems associated with fracture and material impurities. For example, in the absence of the p-type material layer 120, the transistor 100 may require impurities that are not adequately evaporated. The p-type material layer 120 can be formed beneath the source 110 and can extend toward the gate 114 of the device.

[0103] In embodiments of the transistor 100 of this disclosure, the p-type material layer 120 can extend and remain along its entire length, as shown in Figures 2, 4, and 6. In one embodiment, the p-type material layer 120 can generally extend and remain along its entire length, as shown in Figures 3 and 5.

[0104] In another aspect of this disclosure, the p-type material layer 120 does not have to extend across the entire area of ​​the transistor 100 indicated by the length p120 arrow shown in Figures 3 and 5. In this regard, the p-type material layer 120 can be selectively positioned as described herein, can be positioned along its entire length and selectively removed as described herein, can be positioned along its entire length and selectively electrically neutralized as described herein, and so on. Thus, the specific structures of the p-type material layer 120 described later encompass any of these processes that result in the p-type material layer 120 having the operating structure and position described later. In other words, the length and / or size of the p-type material layer 120 does not include partially electrically neutralized portions, partially etched portions, etc. The length and / or size of the p-type material layer 120 may depend on the application field of the transistor 100, the requirements of the transistor 100, etc. By limiting the p-type material layer 120 so that it does not extend beyond the gate 114, adverse effects on RF performance in specific transistor application areas are avoided.

[0105] Furthermore, referring to the embodiments described later, the p-type material layer 120 can extend horizontally parallel to the arrow of length p120. Moreover, the p-type material layer 120 can extend horizontally parallel to the arrow of length p120 to a point defined by a line extending perpendicularly to the arrow of length p120 and through the components of the illustrated transistor 100.

[0106] In one aspect of the present disclosure, the p-type material layer 120 can extend laterally from at least below the source 110 toward the first edge 124 of the gate 114, as shown in Figure 3.

[0107] In certain aspects of this disclosure, the p-type material layer 120 can extend horizontally to a point within a range of about 0 to about 0.7 μm of the first edge 124 of the gate 114. In certain aspects of this disclosure, the p-type material layer 120 can extend horizontally to a point within a range of about 0 to about 0.5 μm of the first edge 124 of the gate 114. In certain aspects of this disclosure, the p-type material layer 120 can extend horizontally to a point within a range of about 0 to about 0.3 μm of the first edge 124 of the gate 114. In one aspect of this disclosure, the p-type material layer 120 can extend horizontally at least from below the source 110 to a position below the second edge 122 of the gate 114. In certain aspects of this disclosure, the p-type material layer 120 can extend horizontally to a point within a range of about 0 to about 0.7 μm of the second edge 122 of the gate 114. In certain aspects of this disclosure, the p-type material layer 120 can extend horizontally to a point within a range of about 0 to about 0.5 μm of the second edge 122 of the gate 114. In certain aspects of this disclosure, the p-type material layer 120 can extend horizontally to a point within a range of about 0 to about 0.3 μm of the second edge 122 of the gate 114.

[0108] In other embodiments, the length p120 of the p-type material layer 120 can be seen in relation to the position and / or length of other components shown in Figure 3. Length SD can be the length between the edge 142 of the source 110 and the edge 144 of the drain 112, as shown by line 150 in Figure 3.

[0109] In one embodiment, the length of the p-type material layer 120 can be extended by 10% to 20% of the length of the SD, meaning that the p-type material layer 120 can extend 10% to 20% beyond the edge 142 of the source 110 toward the drain 112. In one embodiment, the length of the p-type material layer 120 can be extended by 20% to 30% of the length of the SD, meaning that the p-type material layer 120 can extend 20% to 30% beyond the edge 142 of the source 110 toward the drain 112. In one embodiment, the length of the p-type material layer 120 can be extended by 30% to 40% of the length of the SD, meaning that the p-type material layer 120 can extend 30% to 40% beyond the edge 142 of the source 110 toward the drain 112. In one embodiment, the length of the p-type material layer 120 can extend by 40% to 50% of the length of the SD, meaning that the p-type material layer 120 can extend 40% to 50% beyond the edge 142 of the source 110 toward the drain 112. In another embodiment, the length of the p-type material layer 120 can extend by 50% to 60% of the length of the SD, meaning that the p-type material layer 120 can extend 50% to 60% beyond the edge 142 of the source 110 toward the drain 112.

[0110] In one aspect of this disclosure, the p+ layer 106 does not have to extend across the entire area of ​​the substrate layer 102 indicated by the length p+106 arrow shown in these figures. In this regard, the p+ layer 106 can be selectively positioned, as will be described in detail below, the p+ layer 106 can be positioned along its entire length and selectively removed, the p+ layer 106 can be positioned along its entire length and selectively electrically neutralized, and so on. Thus, the specific structures of the p+ layer 106 described below encompass any of these configurations, resulting in the p+ layer 106 having the operating structure and position described below. In other words, the length and / or size of the p+ layer 106 does not include any partially electrically neutralized or partially etched portions. The length and / or size of the p+ layer 106 may depend on the application area of ​​the transistor 100, the requirements of the transistor 100, and so on.

[0111] Furthermore, referring to the embodiments described later, the p+ layer 106 can extend horizontally parallel to an arrow of length p+106. Moreover, the p+ layer 106 can extend horizontally parallel to an arrow of length p+106 to a point defined by a line extending perpendicularly to the arrow of length p+106 through the components of the illustrated transistor 100.

[0112] In certain aspects of this disclosure, the p+ layer 106 may extend to a point within a range of about 0 to about 0.7 μm of the first edge 124 of the gate 114. In certain aspects of this disclosure, the p+ layer 106 may extend to a point within a range of about 0 to about 0.5 μm of the first edge 124 of the gate 114. In certain aspects of this disclosure, the p+ layer 106 may extend to a point within a range of about 0 to about 0.3 μm of the first edge 124 of the gate 114. In one aspect of this disclosure, the p+ layer 106 may extend laterally at least from below the source 110 to below the second edge 122 of the gate 114. In certain aspects of this disclosure, the p+ layer 106 may extend to a point within a range of about 0 to about 0.7 μm of the second edge 122 of the gate 114. In certain aspects of this disclosure, the p+ layer 106 may extend to a point within a range of about 0 to about 0.5 μm of the second edge 122 of the gate 114. In certain aspects of this disclosure, the p+ layer 106 may extend to a point within a range of about 0 to about 0.3 μm of the second edge 122 of the gate 114.

[0113] In other embodiments, the length of the p+ layer 106 can also be viewed in relation to the position and / or length of other components, based on the length SD shown in Figure 3. In this case, the length SD can be the length between the edge 142 of the source 110 and the edge 144 of the drain 112, as shown in Figure 3.

[0114] In one embodiment, the length of the p+ layer 106 can be extended by 10% to 20% of the SD length, meaning that the p+ layer 106 can extend 10% to 20% beyond the edge 142 of the source 110 toward the drain 112. In one embodiment, the length of the p+ layer 106 can be extended by 20% to 30% of the SD length, meaning that the p+ layer 106 can extend 20% to 30% beyond the edge 142 of the source 110 toward the drain 112. In one embodiment, the length of the p+ layer 106 can be extended by 30% to 40% of the SD length, meaning that the p+ layer 106 can extend 30% to 40% beyond the edge 142 of the source 110 toward the drain 112. In one embodiment, the length of the p+ layer 106 can extend by 40% to 50% of the length of the SD, meaning that the p+ layer 106 can extend 40% to 50% beyond the edge 142 of the source 110 toward the drain 112. In one embodiment, the length of the p+ layer 106 can extend by 50% to 60% of the length of the SD, meaning that the p+ layer 106 can extend 50% to 60% beyond the edge 142 of the source 110 toward the drain 112. In one embodiment, the length of the p+ layer 106 can extend by 60% to 70% of the length of the SD, meaning that the p+ layer 106 can extend 60% to 70% beyond the edge 142 of the source 110 toward the drain 112. In one embodiment, the length of the p+ layer 106 can extend by 70% to 80% of the length of the SD, which means that the p+ layer 106 can extend 70% to 80% beyond the edge 142 of the source 110 toward the drain 112.

[0115] A gate contact can be provided for the gate 114 between the source 110 and the drain 112. Furthermore, in certain embodiments of this disclosure, the gate contact can be located on the barrier layer 108. In one embodiment, the gate contact can be located directly on the barrier layer 108.

[0116] The gate 114 can be formed from platinum (Pt), nickel (Ni), and / or gold (Au), but other metals known to those skilled in the art to achieve the Schottky effect can also be used. In one embodiment, the gate 114 may include a Schottky gate contact having a three-layer structure. Such a structure may have advantages due to the high adhesion of some materials. In one embodiment, the gate 114 may further include a coating layer of a highly conductive metal. In one embodiment, the gate 114 may be configured as a T-shaped gate.

[0117] In another embodiment, one or more metal coating layers may be provided on one or more of the source 110, p-type material contact 118, drain 112, and gate 114. These coating layers may be Au, silver (Ag), Al, Pt, Ti, Si, Ni, Al, and / or copper (Cu). Other suitable highly conductive metals may also be used for the coating layers. In one or more embodiments, the metal coating layers may be electrically coupled to the p-type material contact 118. In another embodiment, the source 110, p-type material contact 118, drain 112, and gate 114 may include Au, silver (Ag), Al, Pt, Ti, Si, Ni, Al, and / or copper (Cu). Other suitable highly conductive metals may also be used.

[0118] Figure 8 shows a cross-sectional view of another embodiment of a transistor according to the present disclosure. In particular, Figure 8 shows a transistor 100 that may include one or more embodiments of the present disclosure described herein. In the embodiment of Figure 8, the p-type material layer 120 may be formed in or on the substrate layer 102, and the transistor 100 may include a second buffer layer 126. Figure 8 shows a transistor 100 having a first buffer layer 104 and a second buffer layer 126, although the transistor 100 may also use only one buffer layer 104. In one embodiment, Al may be injected into the substrate layer 102 and annealed to form the p-type material layer 120 within the substrate layer 102. In one embodiment, the substrate layer 102 may be doped with the p-type material layer 120. In one embodiment, the substrate layer 102 may be doped with boron to form the p-type material layer 120. Other materials including Ga are also intended. The length of the p-type material layer 120 near the surface of the p-type material layer 120 can be limited using techniques described in other embodiments.

[0119] In one embodiment, the second buffer layer 126 can be deposited or grown on the first buffer layer 104 on the side of the first buffer layer 104 opposite to the substrate layer 102. In one embodiment, the second buffer layer 126 can be formed directly on the first buffer layer 104. In one embodiment, the second buffer layer 126 can be a high-purity material such as gallium nitride (GaN) or AlN. In one embodiment, the second buffer layer 126 can be high-purity GaN. In one embodiment, the second buffer layer 126 can be high-purity AlN. The second buffer layer 126 can be a p-type material or an n-type material. In another embodiment, the second buffer layer 126 can be undoped.

[0120] In embodiments of the transistor 100 of this disclosure, the contacts of the source 110, gate 114, and / or drain 112 may include Al, Ti, Si, Ni, and / or Pt. In some embodiments, the p-type material contact 118 may include Al, Ti, Si, Ni, and / or Pt. In certain embodiments, the material of the contacts of the source 110, gate 114, and / or drain 112 may be the same material as the p-type material contact 118. In this embodiment, using the same material may be beneficial in that it may make manufacturing easier, simpler, and / or less expensive. In other embodiments, the materials of the contacts of the source 110, gate 114, drain 112, and p-type material contact 118 may be different.

[0121] In an embodiment of the transistor 100 of this disclosure, the p+ layer 106 may be a graded layer. In one embodiment, the p+ layer 106 may be a step graded layer. In one embodiment, the p+ layer 106 may consist of multiple layers. In one embodiment, the p-type material layer 120 may be a graded layer. In one embodiment, the p-type material layer 120 may be a step graded layer. In one embodiment, the p-type material layer 120 may consist of multiple layers.

[0122] Figure 9 shows a cross-sectional view of another embodiment of the transistor according to the present disclosure. In particular, Figure 9 shows a transistor 100 that may include one or more embodiments of the present disclosure described herein.

[0123] In particular, the transistor 100 in Figure 9 may include the aforementioned p+ layer 106 (not shown in Figure 9). In other embodiments, the transistor 100 in Figure 9 does not need to utilize the p+ layer 106 shown in Figure 9. In one embodiment of Figure 9, the transistor 100 can be implemented using only the p+ layer 106. In one embodiment of Figure 9, the transistor 100 can be implemented using both the p+ layer 106 and the p-type material layer 120. In one embodiment of Figure 9, the transistor 100 can be implemented using only the p-type material layer 120.

[0124] Figure 9 further illustrates the implementation of the field plate 132. In one embodiment, the field plate 132 can be placed on a spacer layer 117 between the gate 114 and the drain 112. In one embodiment, the field plate 132 can be deposited on a spacer layer 117 between the gate 114 and the drain 112. In one embodiment, the field plate 132 can be electrically connected to one or more other components in the transistor 100. In one embodiment, the field plate 132 does not need to be electrically connected to any other components of the transistor 100. In some embodiments, the field plate 132 can be adjacent to the gate 114 and may include an additional spacer layer 117 of dielectric material at least partially on the gate 114 to isolate the gate 114 from the field plate 132. In some embodiments, the field plate 132 can overlap the gate 114 and may include an additional spacer layer 117 of dielectric material at least partially on the gate 114 to isolate the gate 114 from the field plate 132.

[0125] The field plate 132 can extend from the edge of the gate 114 by different distances, with a preferred distance range being approximately 0.1 to 2 μm. In some embodiments, the field plate 132 can contain many different conductive materials, preferred of which are metals or combinations of metals, and are deposited using standard metallization methods. In one embodiment, the field plate 132 can include titanium, gold, nickel, titanium / gold, nickel / gold, and so on.

[0126] In one embodiment, the field plate 132 can be formed on a spacer layer 117 between the gate 114 and the drain 112, and the field plate 132 is adjacent to the gate 114 rather than overlapping it. In one embodiment, the space between the gate 114 and the field plate 132 can be wide enough to isolate the gate 114 from the field plate 132, while being small enough to maximize the field field effect provided by the field plate 132.

[0127] In certain embodiments, the field plate 132 can reduce the peak operating electric field within the transistor 100. In certain embodiments, the field plate 132 can reduce the peak operating electric field within the transistor 100 and increase the breakdown voltage of the transistor 100. In certain embodiments, the field plate 132 can reduce the peak operating electric field within the transistor 100 and reduce trapping within the transistor 100. In certain embodiments, the field plate 132 can reduce the peak operating electric field within the transistor 100 and reduce leakage current within the transistor 100.

[0128] In embodiments of the present disclosure, the heterointerface 152 can be located between the barrier layer 108 and the buffer layer 104. In one embodiment, electrodes for the source 110 and drain 112 can be formed to create an ohmic contact, and so, when an appropriate level of bias is applied to the electrodes of the gate 114, current flows between the electrodes of the source 110 and drain 112 via a two-dimensional electron gas (2DEG) induced at the heterointerface 152 between the buffer layer 104 and the barrier layer 108. In one embodiment, the heterointerface 152 can be in the range of 0.005 μm to 0.007 μm, 0.007 μm to 0.009 μm, and 0.009 μm to 0.011 μm.

[0129] Figure 10 shows a cross-sectional view of another embodiment of the transistor according to the present disclosure. In particular, Figure 10 shows a transistor 100 that can include any one or more embodiments of the present disclosure described herein. In particular, in some embodiments, the transistor 100 of Figure 10 can include the p+ layer 106 (not shown in Figure 10) described above. In other embodiments, the p+ layer 106 may not be used. In one embodiment of Figure 10, the transistor 100 can be implemented by the p+ layer 106 alone. In one embodiment of Figure 10, the transistor 100 can be implemented by the p+ layer 106 and the p-type material layer 120. In one embodiment of Figure 10, the transistor 100 can be implemented by the p-type material layer 120 alone.

[0130] In various embodiments, the use of embedded p-layers, such as the p+ layer 106 and / or the p-type material layer 120, can be beneficial for transistor 100, implemented as a HEMT for RF applications, in obtaining high breakdown voltage and good isolation between input and output.

[0131] However, in some application areas, such as RF switch applications, the embedded p-layer does not need to be connected to the source 110 as described herein. In this regard, forward bias conduction between the p-layer (p+ layer 106 and / or p-type material layer 120) and the drain 112 can cause input / output isolation losses when the transistor 100 is in the off state. To avoid, minimize, and / or limit this problem, the embodiment shown in Figure 10 of this disclosure may include connecting the embedded p-layer (p+ layer 106 and / or p-type material layer 120) to the gate 114.

[0132] In particular, Figure 10 further illustrates that the p-type material contact 118 can be electrically connected to the gate 114 by a connector 154 (gate interconnect). In one embodiment, the connector 154 can be formed on spacer layers 116 and / or 117 so as to extend between the p-type material contact 118 and the gate 114. In some embodiments, the connector 154 can include a conductive material, many different conductive materials, preferably a metal or a combination of metals, which is deposited using a standard metallization method. In one embodiment, these materials may include one or more of titanium, gold, nickel, etc.

[0133] In some embodiments, the source 110 and drain 112 can be symmetrical with respect to the gate 114. In some embodiments of the application field of switch devices, the source 110 and drain 112 can be symmetrical with respect to the gate 114.

[0134] An additional advantage of the configuration in Figure 10 is that the p-layer can be used as a second gate, thereby enabling the use of multiple barrier layers 108 and / or multiple channel layers. In this regard, multiple barrier layers 108 and / or multiple channel layers can reduce the on-resistance of transistor 100, which is an important performance characteristic. In a further embodiment of Figure 10, the reduction in on-resistance can be achieved without significantly increasing the input / output capacitance, which is another important characteristic. In certain embodiments, the configuration in Figure 10 can enable a reduction in the Ron-Coff product, which is an important performance indicator for RF switches.

[0135] Figure 11 shows a partial plan view of another embodiment of the transistor according to the present disclosure. In particular, Figure 11 shows a transistor 100 which may include one or more embodiments of the present disclosure described herein. In particular, in some embodiments, the transistor 100 of Figure 11 may be configured such that the p-layer may have separate contacts 162 and be configured to receive its own bias and signal. In this way, the p-layer may be used to tune the characteristics of the transistor 100.

[0136] Figure 11 further illustrates transistor 100, including source 110, gate 114, and drain 112. In this regard, some of the various layers and components of transistor 100 may not be shown for the sake of clarity.

[0137] In one embodiment of Figure 11, the transistor 100 can be implemented using only the p+ layer 106. In another embodiment of Figure 11, the transistor 100 can be implemented using the p+ layer 106 and the p-type material layer 120. In yet another embodiment of Figure 11, the transistor 100 can be implemented using only the p-type material layer 120. In all cases, the p+ layer 106 and the p-type material layer 120 are indicated by dashed lines showing that one or more layers are embedded within them.

[0138] In one embodiment, the p-type material layer 120 may include a contact pad 162. In this embodiment, the p-type material layer 120 can receive its own bias and signal through the contact pad 162. In this regard, the p-type material layer 120 can be used to adjust the characteristics of the transistor 100.

[0139] In one embodiment, the p-type material layer 120 may include a p-type material contact 118. The p-type material contact 118 can be electrically connected to a connector 166, which can be electrically connected to a contact pad 162. In some embodiments, the connector 166 may include a conductive material, many different conductive materials, preferably a metal or a combination of metals, which is deposited using a standard metallization method. In one embodiment, these materials may include one or more of titanium, gold, nickel, etc.

[0140] In one embodiment, the p+ layer 106 may be provided with a contact pad 162. In this embodiment, the p+ layer 106 can receive its own bias and signal via the contact pad 162. In this regard, the characteristics of the transistor 100 can be adjusted using the contact pad 162.

[0141] In one embodiment, the p+ layer 106 may include a p-type material contact 118. The p-type material contact 118 can be electrically connected to a connector 166, and the connector 166 can be electrically connected to a contact pad 162.

[0142] In one embodiment, the connection portion 166 can be a metal connection extending from a p-type material contact 118 to a contact pad 162. In one embodiment, the contact pad 162 can be an embedded contact pad. In this regard, the contact pad 162 can be embedded in any one of the above-described structures of the transistor 100. In one embodiment, the contact pad 162 can be placed on a barrier layer 108. In one embodiment, the contact pad 162 can be placed directly on the barrier layer 108. In one embodiment, the contact pad 162 can be placed on a spacer layer 116 on the barrier layer 108. In one embodiment, the contact pad 162 can be separate and isolated from the gate 114, source 110, and / or drain 112. Figure 11 further shows a gate pad 168 electrically connected to the gate 114. Please note that the sizes, arrangements, and configurations of the p-type material contact 118, connector 166, contact pad 162, p+ layer 106, and p-type material layer 120 shown in Figure 11 are for illustrative purposes only. Other sizes, arrangements, and configurations are also intended.

[0143] Figure 12 shows a cross-sectional view of another embodiment of the transistor according to this disclosure.

[0144] In particular, Figure 12 shows a transistor 100 that may include one or more embodiments of the present disclosure described herein. In particular, in some embodiments, the transistor 100 of Figure 12 may include the p+ layer 106 described above. In other embodiments, the p+ layer 106 may not be used. In one embodiment of Figure 12, the transistor 100 can be implemented by the p+ layer 106 alone. In one embodiment of Figure 12, the transistor 100 can be implemented by the p+ layer 106 and a p-type material layer 120 (not shown in Figure 12). In one embodiment of Figure 12, the transistor 100 can be implemented by the p-type material layer 120 alone. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 may be injected as described herein. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 may be formed as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 may be injected as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be formed as described herein.

[0145] In particular, the transistor 100 in Figure 12 shows a field plate 132 connected to a source 110 via a connector 140 (source-field plate interconnect). In this embodiment, the field plate 132 does not have to include a connector to the p-type material layer 120. In one embodiment, the connector 140 can be formed on a spacer layer 116 and / or spacer layer 117 so as to extend between the field plate 132 and the source 110. In one embodiment, the connector 140 can be formed together with the field plate 132 during the same manufacturing step. In one embodiment, multiple connectors 140 can be used. In one embodiment, multiple field plates 132 can be used. In one embodiment, multiple field plates 132 can be used, and each of the multiple field plates 132 can be stacked with a dielectric material in between. In some embodiments, the connector 140 can include a conductive material, many different conductive materials, preferred materials are metals or combinations of metals, and are deposited using standard metallization methods. In one embodiment, these materials may include one or more of titanium, gold, nickel, and the like.

[0146] Figure 13 shows a cross-sectional view of another embodiment of the transistor according to this disclosure.

[0147] In particular, Figure 13 shows a transistor 100 that can include one or more embodiments of the present disclosure described herein. In particular, in some embodiments, the transistor 100 of Figure 13 can include the p+ layer 106 (not shown in Figure 13) described above. In other embodiments, the p+ layer 106 may not be used. In one embodiment of Figure 13, the transistor 100 can be implemented by the p+ layer 106 alone. In one embodiment of Figure 13, the transistor 100 can be implemented by the p+ layer 106 and the p-type material layer 120. In one embodiment of Figure 13, the transistor 100 can be implemented by the p-type material layer 120 alone. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be injected as described herein. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be formed as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be injected as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be formed as described herein.

[0148] In particular, the transistor 100 in Figure 13 shows a field plate 132 connected to a source 110 via a connector 140. Figure 13 further shows that a connector 138 can electrically connect the p-type material contact 118 to the source 110. In one embodiment, the connector 138 can be formed on a spacer layer 116 and / or spacer layer 117 so as to extend between the p-type material contact 118 and the source 110. In one embodiment, the transistor 100 may further include connectors 138 and 140 configured to directly connect the field plate 132 to the p-type material contact 118. In one embodiment, the transistor 100 may further include connectors 138 and 140 configured to directly connect the field plate 132 to the p-type material contact 118 without connecting to the source 110. In one embodiment, the transistor 100 may further include connectors 138 and 140 configured to connect the field plate 132 directly to the p-type material contact 118 without any intervening connectors. In some embodiments, the connector 138 may include a conductive material, many different conductive materials, preferably a metal or a combination of metals, which is deposited using a standard metallization method. In one embodiment, these materials may include one or more of titanium, gold, nickel, etc.

[0149] Figure 14 illustrates a process for fabricating a transistor according to this disclosure. In particular, Figure 14 shows an exemplary process 500 for fabricating the transistor 100 of this disclosure. Note that process 500 is merely illustrative and can be consistently modified in various embodiments disclosed herein.

[0150] Process 500 can be initiated in step 502 by forming a substrate layer 102. The substrate layer 102 can be made from silicon carbide (SiC). In some embodiments, the substrate layer 102 can be a semi-insulating SiC substrate, a p-type substrate, an n-type substrate, etc. In some embodiments, the substrate layer 102 can be doped at a very low concentration. In one embodiment, the background impurity level can be reduced. In one embodiment, the background impurity level is 1E15 / cm 3 The following is possible: The substrate layer 102 may be formed from SiC selected from the group consisting of 6H, 4H, 15R, 3C SiC, etc. In another embodiment, the substrate layer 102 may be GaAs, GaN, or other material suitable for the application field described herein. In another embodiment, the substrate layer 102 may include sapphire, spinel, ZnO, silicon, or any other material capable of supporting the growth of a Group III nitride material.

[0151] In a first embodiment relating to the transistor 100 of Figures 2 and 3, the process 500 may include a step 504 in which Al is implanted into the substrate layer 102 to form a p-type material layer 120 within the substrate layer 102, for example, as shown in Figures 2 and 3. The p-type material layer 120 can be formed by ion implantation and annealing of Al. In one embodiment, the p-type material layer 120 can be formed by implantation and annealing of Al before any GaN layer is grown. In one embodiment, ion packaging may utilize channeling implantation. In one embodiment, channeling implantation may include aligning an ion beam with the substrate layer 102. Ion beam alignment can increase implantation efficiency. In some embodiments, the process 500 may further include implanting Al into the substrate layer 102 to form a p+ layer 106 within the substrate layer 102, for example, as shown in Figures 2 and 3. The substrate layer 102 can then be annealed as defined herein. In one embodiment, the p-type material layer 120 is injected at 25°C with an injection energy E1 = 100 keV and a dosage of 1 E13 cm³. 2In 4H-SiC injected under the channeling conditions described above... 27 It can be formed by ion implantation of Al. In one embodiment, the p-type material layer 120 is implanted at 25°C with an implantation energy E2 = 300 keV and a dosage of 1 E13 cm³. 2 In 4H-SiC injected under the channeling conditions described above... 27 It can be formed by ion implantation of Al. However, other implantation energies and dosages are also considered.

[0152] In a first embodiment relating to the transistor 100 of Figures 3 and 4, a buffer layer 104 can be formed on the substrate layer 102 in step 506. The buffer layer 104 can be grown or deposited on the substrate layer 102. In one embodiment, the buffer layer 104 can be made of GaN. In another embodiment, the buffer layer 104 can be formed by LEO. In one embodiment, a nucleation layer 136 can be formed on the substrate layer 102, and in step 506, a buffer layer 104 can be formed on the nucleation layer 136. The buffer layer 104 can be grown or deposited on the nucleation layer 136. In one embodiment, the buffer layer 104 can be made of GaN. In another embodiment, the buffer layer 104 can be formed by LEO.

[0153] In a second embodiment relating to the transistor 100 of Figures 4 and 5, the process 500 may include, as a further part of step 504, forming an epitaxial layer 202 on the substrate layer 102. Thereafter, as shown in Figures 3 and 4, a p-type material layer 120 can be formed within the epitaxial layer 202 by removal, etching, damage, etc. In addition, a p+ layer 106 can be formed as described herein.

[0154] In a second embodiment relating to the transistor 100 of Figures 4 and 5, a buffer layer 104 can be formed on the epitaxial layer 202 in step 506. The buffer layer 104 can be grown or deposited on the epitaxial layer 202. In one embodiment, the buffer layer 104 can be made of GaN. In another embodiment, the buffer layer 104 can be formed of LEO.

[0155] In step 508, a barrier layer 108 can be formed on the buffer layer 104. The barrier layer 108 can be an n-type conductive layer or it can be undoped. In one embodiment, the barrier layer 108 can be AlGaN.

[0156] In step 510, a spacer layer 116 can be formed. The spacer layer 116 can be a passivation layer such as SiN, AlO, SiO, SiO2, AlN, or a combination of several of these layers, and can be deposited on the exposed surface of the barrier layer 108. In another aspect of the disclosure, a recess can be created by removing at least a portion of the barrier layer 108 and at least a portion of the buffer layer 104 to create a place for contact with the p-type material layer 120. The recess 119 can be created by removing any material on the p-type material layer 120 within the region portion related to the source 110, exposing the p-type material layer 120 on the side opposite to the substrate layer 102. In another aspect of the disclosure, the recess 119 can be created by removing at least a portion of the barrier layer 108 and at least a portion of the buffer layer 104 to create a place for contact with the p+ layer 106. The recess formation process can remove any material on the p+ layer 106 within the region associated with the source 110, and expose the p+ layer 106 on the side opposite to the substrate layer 102.

[0157] Furthermore, during process 500, as part of step 512, a source 110 can be placed on the barrier layer 108. The source 110 can be an ohmic contact of a suitable material that can be annealed. For example, the source 110 can be annealed at a temperature of about 500°C to about 800°C for about 2 minutes. However, other times and temperatures can also be utilized. For example, a time of about 30 seconds to about 10 minutes can be acceptable. In some embodiments, the source 110 can include Al, Ti, Si, Ni, and / or Pt. In one embodiment, a region 164 of N+ material can be formed beneath the source 110 within the barrier layer 108. In one embodiment, the region 164 beneath the drain 112 can be doped with Si.

[0158] Furthermore, during process 500, as part of step 512, a drain 112 can be placed on the barrier layer 108. Similar to the source 110, the drain 112 can also be an ohmic contact of Ni or another suitable material and can be annealed in the same manner. In one embodiment, an n+ injector can be used together with the barrier layer 108, and a contact is made in this injector. In one embodiment, a region 164 of N+ material can be formed beneath the drain 112 within the barrier layer 108. In one embodiment, the region 164 beneath the drain 112 can be doped with Si.

[0159] Furthermore, during process 500, as part of step 512, the gate 114 can be placed on the barrier layer 108 between the source 110 and the drain 112. For the gate 114, layers of Ni, Pt, Au, etc., can be formed by vapor deposition or another technique. The gate structure can then be completed by depositing Pt and Au or other suitable materials. In some embodiments, the contacts of the gate 114 may include Al, Ti, Si, Ni, and / or Pt.

[0160] Furthermore, during process 500, as part of step 512, a p-type material contact 118 can be formed. After the p+ layer 106 is exposed, nickel or another suitable material can be evaporated to deposit the p-type material contact 118. For example, nickel or another suitable material can be annealed to form an ohmic contact. In some embodiments, the contacts of the p-type material contact 118 can include Al, Ti, Si, Ni, and / or Pt. Such deposition and annealing processes can be carried out using conventional techniques known to those skilled in the art. For example, an ohmic contact for the p-type material contact 118 can be annealed at a temperature of about 600°C to about 1050°C. After the p-type material contact 118 is formed on the p+ layer 106, a metal coating layer can electrically couple the p-type material contact 118 of the p+ layer 106 to the source 110. By doing so, the conductivity of the p+ layer 106 and the source 110 can be maintained at the same potential.

[0161] By forming electrodes for source 110 and drain 112, an ohmic contact can be created, and therefore, when an appropriate level of bias is applied to the electrode of gate 114, current flows between the electrodes of source 110 and drain 112 via a two-dimensional electron gas (2DEG) induced at the heterointerface 152 between the buffer layer 104 and the barrier layer 108. In one embodiment, the heterointerface 152 can be in the range of 0.005 μm to 0.007 μm, 0.007 μm to 0.009 μm, and 0.009 μm to 0.011 μm.

[0162] The gate 114 can extend over a spacer or spacer layer 116. The spacer layer 116 can be etched, and the gate 114 can be deposited such that the bottom of the gate 114 is in contact with the surface of the barrier layer 108. The metal forming the gate 114 can be patterned to extend across the spacer layer 116, so that the top of the gate 114 forms a field plate 132.

[0163] Furthermore, in some embodiments of process 500, as part of step 512, the field plate 132 can be placed on another spacer layer 117 and separated from the gate 114. In one embodiment, the field plate 132 can be deposited on the spacer layer 117 between the gate 114 and the drain 112. In some embodiments, the field plate 132 can contain many different conductive materials, preferred materials being metals or combinations of metals, which are deposited using standard metallization methods. In one embodiment, the field plate 132 can include titanium, gold, nickel, titanium / gold, nickel / gold, etc. In one embodiment, the connector 140 can be formed together with the field plate 132 during the same manufacturing step (see Figure 12). In one embodiment, multiple field plates 132 can be used. In one embodiment, multiple field plates 132 can be used, and each of the multiple field plates 132 can be stacked with a dielectric material in between. In one embodiment, the field plate 132 extends toward the edge of the gate 114 and toward the drain 112. In one embodiment, the field plate 132 extends toward the source 110. In another embodiment, the field plate 132 extends toward the drain 112 and the source 110. In yet another embodiment, the field plate 132 does not extend toward the edge of the gate 114. Finally, this structure can be covered with a dielectric spacer layer such as silicon nitride. The dielectric spacer layer can also be implemented similarly to the spacer layer 116. Furthermore, it should be noted that the cross-sectional shape of the gate 114 shown in these figures is illustrative. For example, in some embodiments, the cross-sectional shape of the gate 114 does not have to include a T-shaped extension. Other structures of the gate 114, such as the structures of the gate 114 shown in Figure 8 or Figure 1, can also be utilized.

[0164] Furthermore, in some embodiments of process 500, a connection portion 154 can be formed as part of step 512. In one embodiment, the connection portion 154 can be formed to extend between the p-type material contact 118 and the gate 114 (see Figure 16). In one embodiment, the connection portion 154 can be formed on the spacer layer 116 to extend between the p-type material contact 118 and the gate 114.

[0165] Furthermore, in some embodiments of process 500, a connector 140 can be formed as part of step 512 (see Figure 13). In some embodiments, the connector 140 allows the field plate 132 to be electrically connected to the source 110. In one embodiment, the connector 140 can be formed on the spacer layer 117 so as to extend between the field plate 132 and the source 110.

[0166] Furthermore, in some embodiments of process 500, a connector 166 and a contact pad 162 can be formed as part of step 512 (see Figure 11). In one embodiment, a p-type material contact 118 can be electrically connected to the connector 166, and the connector 166 can be electrically connected to the contact pad 162. Furthermore, in some embodiments of process 500, a gate pad 168 can be formed.

[0167] It should be noted that the steps of process 500 can be performed in different orders, consistent with the embodiments described above. Furthermore, process 500 can be modified to have more or fewer process steps, consistent with the various embodiments disclosed herein. In one embodiment of process 500, the transistor 100 can be constructed by the p+ layer 106 alone. In one embodiment of process 500, the transistor 100 can be constructed by the p+ layer 106 and the p-type material layer 120. In one embodiment of process 500, the transistor 100 can be constructed by the p-type material layer 120 alone.

[0168] Figure 15 shows the distribution of Al implanted under the channeling conditions according to the embodiment of this disclosure, compared with simulations of conventional implantation conditions. In particular, Figure 15 shows the distribution of Al implanted under channeling conditions along the C axis (secondary ion mass spectrometry (SIMS) data) in 4H-SiC, compared with simulations of conventional off-axis implantation conditions (TRIM). 27 The distribution of Al is shown. The infusion energies used were E1=100keV and E2=300keV at 25°C, and the dose was 1E13cm -2 In this regard, the p-type material layer 120 can be consistently injected with this injection energy and dosage. However, other injection energies and dosages are also intended as described herein.

[0169] In one embodiment, the p-type material layer 120 can have a doping concentration less than that of the p+ layer 106. In one embodiment, the p+ layer 106 can be doped to the highest possible concentration with the lowest feasible sheet resistance. In one embodiment, the p-type material layer 120 can have an injection concentration smaller than that of the p+ layer 106. In one embodiment, the p+ layer 106 can have the highest possible injection concentration with the lowest feasible sheet resistance. In one embodiment, the p-type material layer 120 is 10 19 It can have an injection concentration of less than 10 20 It can have an injection concentration of less than 10 17 ~10 20 , 10 19 ~10 20 , 10 18 ~10 19 , or 10 17 ~10 18 It can have an injection concentration of 10. In one embodiment, the p+ layer 106 is 10 19 The above injection concentration can be achieved. In one embodiment, the p+ layer 106 is 10 18 ~10 20 , 10 18 ~10 19 , or 10 19 ~10 20 It can have an injection concentration of [value].

[0170] In one embodiment, the dosage of the p-type material layer 120 is 1E17cm 3 It can be less than . In one embodiment, the dosage of the p-type material layer 120 is 2E17cm 3 It can be less than . In one embodiment, the dosage of the p-type material layer 120 is 6E17cm 3 It can be less than . In one embodiment, the dosage of the p-type material layer 120 is 2E18cm 3 It can be less than 1 cm. In one embodiment, the amount of p-type material layer 120 is 1 cm 3 The concentration can be within the range of 5E15 to 5E17. In these embodiments, the dosage concentration of the p+ layer 106 can be greater than the dosage concentration of the p-type material layer 120.

[0171] Figure 16 shows a cross-sectional view of another embodiment of the transistor according to this disclosure.

[0172] In particular, Figure 16 shows a transistor 100 that may include one or more embodiments of the present disclosure described herein. In particular, in some embodiments, the transistor 100 of Figure 16 may include the p+ layer 106 (not shown in Figure 16) described above. In other embodiments, the p+ layer 106 may not be used. In one embodiment of Figure 16, the transistor 100 can be implemented by the p+ layer 106 alone. In one embodiment of Figure 16, the transistor 100 can be implemented by the p+ layer 106 and the p-type material layer 120. In one embodiment of Figure 16, the transistor 100 can be implemented by the p-type material layer 120 alone. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be injected as described herein. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be formed as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be injected as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be formed as described herein.

[0173] In particular, Figure 16 shows a transistor 100 that includes a gate 114 and a connector 154. In one embodiment, the connector 154 can connect the gate 114 to a p-type material contact 118. In one embodiment, the gate 114 can be a T-shaped gate. In one embodiment, the gate 114 can be a non-T-shaped gate.

[0174] Figure 17 shows a cross-sectional view of another embodiment of the transistor according to this disclosure.

[0175] In particular, Figure 17 shows a transistor 100 that may include one or more embodiments of the present disclosure described herein. In particular, in some embodiments, the transistor 100 of Figure 17 may include the p+ layer 106 described above. In other embodiments, the p+ layer 106 may not be used. In one embodiment of Figure 17, the transistor 100 can be implemented by the p+ layer 106 alone. In one embodiment of Figure 17, the transistor 100 can be implemented by the p+ layer 106 and the p-type material layer 120. In one embodiment of Figure 17, the transistor 100 can be implemented by the p-type material layer 120 alone. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be injected as described herein. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be formed as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be injected as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be formed as described herein.

[0176] In particular, Figure 17 shows a transistor 100 that can include a p+ layer 106 within a substrate layer 102. In one embodiment, the transistor 100 can include a p-type material layer 120 within a substrate layer 102. In one embodiment, the transistor 100 can include a p+ layer 106 within an epitaxial layer 202. In one embodiment, the transistor 100 can include a p-type material layer 120 within an epitaxial layer 202. In one embodiment, the transistor 100 can include a p+ layer 106 within a substrate layer 102, a p-type material layer 120 within a substrate layer 102, a p+ layer 106 within an epitaxial layer 202, and a p-type material layer 120 within an epitaxial layer 202. Figure 17 further shows that the transistor 100 can include a field plate 132.

[0177] Figure 18 shows a cross-sectional view of another embodiment of the transistor according to this disclosure.

[0178] In particular, Figure 18 shows a transistor 100 that can include one or more embodiments of the present disclosure described herein. In particular, in some embodiments, the transistor 100 of Figure 18 can include the p+ layer 106 (not shown) described above. In other embodiments, the p+ layer 106 may not be used. In one embodiment of Figure 18, the transistor 100 can be implemented by the p+ layer 106 alone. In one embodiment of Figure 18, the transistor 100 can be implemented by the p+ layer 106 and the p-type material layer 120. In one embodiment of Figure 18, the transistor 100 can be implemented by the p-type material layer 120 alone. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be injected as described herein. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be formed as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be injected as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be formed as described herein.

[0179] In particular, Figure 18 shows that the transistor 100 may include a field plate 132. In one embodiment, the transistor 100 may further include a connector 140 for connecting the field plate 132 to the source 110. In one embodiment, the transistor 100 may further include a connector 138 for connecting the field plate 132 and / or the source 110 to the p-type material contact 118. In one embodiment, the transistor 100 may further include connectors 138 and 140 configured to connect the field plate 132 directly to the p-type material contact 118. In one embodiment, the transistor 100 may further include connectors 138 and 140 configured to connect the field plate 132 directly to the p-type material contact 118 without connecting to the source 110. In one embodiment, the transistor 100 may further include connectors 138 and 140 configured to connect the field plate 132 directly to the p-type material contact 118 without any intervening connectors.

[0180] Figure 19 shows a cross-sectional view of another embodiment of the transistor according to this disclosure.

[0181] In particular, Figure 19 shows a transistor 100 that can include one or more embodiments of the present disclosure described herein. In particular, in some embodiments, the transistor 100 of Figure 19 can include the p+ layer 106 (not shown) described above. In other embodiments, the p+ layer 106 may not be used. In one embodiment of Figure 19, the transistor 100 can be implemented by the p+ layer 106 alone. In one embodiment of Figure 19, the transistor 100 can be implemented by the p+ layer 106 and the p-type material layer 120. In one embodiment of Figure 19, the transistor 100 can be implemented by the p-type material layer 120 alone. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be injected as described herein. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be formed as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be injected as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be formed as described herein.

[0182] In particular, Figure 19 shows a transistor 100 that can include a p-type material layer 120 within a substrate layer 102. In one embodiment, the transistor 100 can include a p-type material layer 120 within an epitaxial layer 202. In one embodiment, the transistor 100 can include a p-type material layer 120 within a substrate layer 102 and can also include a p-type material layer 120 within an epitaxial layer 202.

[0183] In one embodiment of Figure 19, the transistor 100 may include a field plate 132. In one embodiment, the transistor 100 may further include a connector 140 for connecting the field plate 132 to a source 110. In one embodiment, the transistor 100 may further include a connector 138 (source interconnect) for connecting the field plate 132 and / or the source 110 to a p-type material contact 118. In one embodiment, the transistor 100 may further include connectors 138 and 140 configured to connect the field plate 132 directly to the p-type material contact 118. In one embodiment, the transistor 100 may further include connectors 138 and 140 configured to connect the field plate 132 directly to the p-type material contact 118 without connecting to the source 110. In one embodiment, the transistor 100 may further include connectors 138 and 140 configured to connect the field plate 132 directly to the p-type material contact 118 without any intervening connectors.

[0184] Figure 20 shows a cross-sectional view of another embodiment of the transistor according to this disclosure.

[0185] In particular, Figure 20 shows a transistor 100 that can include one or more embodiments of the present disclosure described herein. In particular, in some embodiments, the transistor 100 of Figure 20 can include the p+ layer 106 described above. In other embodiments, the p+ layer 106 may not be used. In one embodiment of Figure 20, the transistor 100 can be implemented by the p+ layer 106 alone. In one embodiment of Figure 20, the transistor 100 can be implemented by the p+ layer 106 and the p-type material layer 120. In one embodiment of Figure 20, the transistor 100 can be implemented by the p-type material layer 120 alone. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be injected as described herein. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be formed as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be injected as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be formed as described herein.

[0186] In particular, Figure 20 shows a transistor 100 that can contain a p+ layer 106 within the epitaxial layer 202. Figure 20 further shows that the transistor 100 can contain a p-type material layer 120 within the epitaxial layer 202.

[0187] In one embodiment of Figure 20, the transistor 100 may include a field plate 132. In one embodiment, the transistor 100 may further include a connector 140 for connecting the field plate 132 to a source 110. In one embodiment, the transistor 100 may further include a connector 138 (source interconnect) for connecting the field plate 132 and / or the source 110 to a p-type material contact 118. In one embodiment, the transistor 100 may further include connectors 138 and 140 configured to connect the field plate 132 directly to the p-type material contact 118. In one embodiment, the transistor 100 may further include connectors 138 and 140 configured to connect the field plate 132 directly to the p-type material contact 118 without connecting to the source 110. In one embodiment, the transistor 100 may further include connectors 138 and 140 configured to connect the field plate 132 directly to the p-type material contact 118 without any intervening connectors.

[0188] Figure 21 shows a cross-sectional view of another embodiment of the transistor according to this disclosure.

[0189] In particular, Figure 21 shows a transistor 100 that can include one or more embodiments of the present disclosure described herein. In particular, in some embodiments, the transistor 100 of Figure 21 can include the p+ layer 106 (not shown) described above. In other embodiments, the p+ layer 106 may not be used. In one embodiment of Figure 21, the transistor 100 can be implemented by the p+ layer 106 alone. In one embodiment of Figure 21, the transistor 100 can be implemented by the p+ layer 106 and the p-type material layer 120. In one embodiment of Figure 21, the transistor 100 can be implemented by the p-type material layer 120 alone. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be injected as described herein. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be formed as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be injected as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be formed as described herein.

[0190] In particular, Figure 21 shows a transistor 100 that can include a p-type material layer 120 within a substrate layer 102. In one embodiment shown in Figure 21, the transistor 100 can include a gate 114 having a T-shaped cross-section. In one embodiment, the gate 114 can be a gate that is not T-shaped.

[0191] In one embodiment of Figure 21, the transistor 100 may include a field plate 132. In one embodiment, the transistor 100 may further include a connector 140 for connecting the field plate 132 to a source 110. In one embodiment, the transistor 100 may further include a connector 138 for connecting the field plate 132 and / or the source 110 to a p-type material contact 118. In one embodiment, the transistor 100 may further include connectors 138 and 140 configured to connect the field plate 132 directly to the p-type material contact 118. In one embodiment, the transistor 100 may further include connectors 138 and 140 configured to connect the field plate 132 directly to the p-type material contact 118 without connecting to the source 110. In one embodiment, the transistor 100 may further include connectors 138 and 140 configured to connect the field plate 132 directly to the p-type material contact 118 without any intervening connectors.

[0192] Figure 22 shows a cross-sectional view of another embodiment of the transistor according to this disclosure.

[0193] In particular, Figure 22 shows a transistor 100 that can include one or more embodiments of the present disclosure described herein. In particular, in some embodiments, the transistor 100 of Figure 22 can include the p+ layer 106 (not shown) described above. In other embodiments, the p+ layer 106 may not be used. In one embodiment of Figure 22, the transistor 100 can be implemented by the p+ layer 106 alone. In one embodiment of Figure 22, the transistor 100 can be implemented by the p+ layer 106 and the p-type material layer 120. In one embodiment of Figure 22, the transistor 100 can be implemented by the p-type material layer 120 alone. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be injected as described herein. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be formed as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be injected as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be formed as described herein.

[0194] In particular, Figure 22 shows a transistor 100 that can include a p-type material layer 120 within a substrate layer 102. In one embodiment shown in Figure 22, the transistor 100 can include a gate 114 having a T-shaped cross-section. In one embodiment, the gate 114 can be a gate that is not T-shaped. In one embodiment, the transistor 100 can include a connector 154. In one embodiment, the connector 154 can connect the gate 114 to a p-type material contact 118.

[0195] Figure 23 shows a cross-sectional view of another embodiment of the transistor according to this disclosure.

[0196] In particular, Figure 23 shows a transistor 100 that can include one or more embodiments of the present disclosure described herein. In particular, in some embodiments, the transistor 100 of Figure 23 can include the p+ layer 106 (not shown) described above. In other embodiments, the p+ layer 106 may not be used. In one embodiment of Figure 23, the transistor 100 can be implemented by the p+ layer 106 alone. In one embodiment of Figure 23, the transistor 100 can be implemented by the p+ layer 106 and the p-type material layer 120. In one embodiment of Figure 23, the transistor 100 can be implemented by the p-type material layer 120 alone. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be injected as described herein. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be formed as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be injected as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be formed as described herein.

[0197] In particular, Figure 23 shows a transistor 100 that can include a p-type material layer 120 within the epitaxial layer 202. In one embodiment shown in Figure 23, the transistor 100 can include a gate 114 having a T-shaped cross-section. In one embodiment, the transistor 100 can include a connector 154. In one embodiment, the connector 154 can connect the gate 114 to a p-type material contact 118.

[0198] Figure 24 shows a cross-sectional view of another embodiment of the transistor according to this disclosure.

[0199] In particular, Figure 24 shows a transistor 100 that can include one or more embodiments of the present disclosure described herein. In particular, in some embodiments, the transistor 100 of Figure 24 can include the p+ layer 106 described above. In other embodiments, the p+ layer 106 may not be used. In one embodiment of Figure 24, the transistor 100 can be implemented by the p+ layer 106 alone. In one embodiment of Figure 24, the transistor 100 can be implemented by the p+ layer 106 and a p-type material layer 120 (not shown). In one embodiment of Figure 24, the transistor 100 can be implemented by the p-type material layer 120 (not shown) alone. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be injected as described herein. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be formed as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be injected as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be formed as described herein.

[0200] In particular, Figure 24 shows a transistor 100 that can include a p+ layer 106 within the epitaxial layer 202. In one embodiment shown in Figure 24, the transistor 100 can include a gate 114 having a T-shaped cross-section. In one embodiment, the gate 114 can be a non-T-shaped gate. In one embodiment, the transistor 100 can include a connector 154. In one embodiment, the connector 154 can connect the gate 114 to a p-type material contact 118.

[0201] Figure 25 shows a cross-sectional view of another embodiment of the transistor according to this disclosure.

[0202] In particular, Figure 25 shows a transistor 100 that can include one or more embodiments of the present disclosure described herein. In particular, in some embodiments, the transistor 100 of Figure 25 can include the p+ layer 106 (not shown) described above. In other embodiments, the p+ layer 106 may not be used. In one embodiment of Figure 25, the transistor 100 can be implemented by the p+ layer 106 alone. In one embodiment of Figure 25, the transistor 100 can be implemented by the p+ layer 106 and the p-type material layer 120. In one embodiment of Figure 25, the transistor 100 can be implemented by the p-type material layer 120 alone. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be injected as described herein. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be formed as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be injected as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be formed as described herein.

[0203] In particular, Figure 25 shows a transistor 100 that can include a p-type material layer 120 within a substrate layer 102. In one embodiment, the transistor 100 can include a p-type material layer 120 within an epitaxial layer 202. In one embodiment, the transistor 100 can include a p-type material layer 120 within a substrate layer 102 and can include a p-type material layer 120 within an epitaxial layer 202.

[0204] In one embodiment shown in Figure 25, the transistor 100 may include a gate 114 having a T-shaped cross-section. In one embodiment, the transistor 100 may include a connector 154. In one embodiment, the connector 154 may connect the gate 114 to a p-type material contact 118.

[0205] Figure 26 shows a cross-sectional view of another embodiment of the transistor according to this disclosure.

[0206] In particular, Figure 26 shows a transistor 100 that can include one or more embodiments of the present disclosure described herein. In particular, in some embodiments, the transistor 100 of Figure 26 can include the p+ layer 106 described above. In other embodiments, the p+ layer 106 may not be used. In one embodiment of Figure 26, the transistor 100 can be implemented by the p+ layer 106 alone. In one embodiment of Figure 26, the transistor 100 can be implemented by the p+ layer 106 and the p-type material layer 120. In one embodiment of Figure 26, the transistor 100 can be implemented by the p-type material layer 120 alone. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be injected as described herein. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be formed as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be injected as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be formed as described herein.

[0207] In particular, Figure 26 shows a transistor 100 that can include a p+ layer 106 within the epitaxial layer 202. Figure 26 further shows that the transistor 100 can include a p-type material layer 120 within the epitaxial layer 202. In one embodiment, the transistor 100 can include a p+ layer 106 within the epitaxial layer 202 and can include a p-type material layer 120 within the epitaxial layer 202.

[0208] In one embodiment shown in Figure 26, the transistor 100 may include a gate 114 having a T-shaped cross-section. In one embodiment, the transistor 100 may include a connector 154. In one embodiment, the connector 154 may connect the gate 114 to a p-type material contact 118.

[0209] Figure 27 shows a cross-sectional view of another embodiment of the transistor according to this disclosure.

[0210] In particular, Figure 27 shows a transistor 100 that can include one or more embodiments of the present disclosure described herein. In particular, in some embodiments, the transistor 100 of Figure 27 can include the p+ layer 106 described above. In other embodiments, the p+ layer 106 may not be used. In one embodiment of Figure 27, the transistor 100 can be implemented by the p+ layer 106 alone. In one embodiment of Figure 27, the transistor 100 can be implemented by the p+ layer 106 and the p-type material layer 120. In one embodiment of Figure 27, the transistor 100 can be implemented by the p-type material layer 120 alone. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be injected as described herein. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be formed as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be injected as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be formed as described herein.

[0211] In particular, Figure 27 shows a transistor 100 that can include a p+ layer 106 within the epitaxial layer 202. Figure 27 further shows that the transistor 100 can include a p-type material layer 120 within the epitaxial layer 202. In one embodiment, the transistor 100 can include a p+ layer 106 within the epitaxial layer 202 and can include a p-type material layer 120 within the epitaxial layer 202.

[0212] In one embodiment shown in Figure 27, the transistor 100 may include a gate 114 having a T-shaped cross-section. In one embodiment, the transistor 100 may include a connector 154. In one embodiment, the connector 154 may connect the gate 114 to a p-type material contact 118. In one embodiment shown in Figure 27, the transistor 100 may further include a field plate 132.

[0213] Figure 28 shows a cross-sectional view of another embodiment of the transistor according to this disclosure.

[0214] In particular, Figure 28 shows a transistor 100 that can include one or more embodiments of the present disclosure described herein. In particular, in some embodiments, the transistor 100 of Figure 28 can include the p+ layer 106 (not shown) described above. In other embodiments, the p+ layer 106 may not be used. In one embodiment of Figure 28, the transistor 100 can be implemented by the p+ layer 106 alone. In one embodiment of Figure 28, the transistor 100 can be implemented by the p+ layer 106 and the p-type material layer 120. In one embodiment of Figure 28, the transistor 100 can be implemented by the p-type material layer 120 alone. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be injected as described herein. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be formed as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be injected as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be formed as described herein.

[0215] In particular, Figure 28 shows a transistor 100 that can include a p-type material layer 120 within the epitaxial layer 202. In one embodiment shown in Figure 28, the transistor 100 can include a gate 114 having a T-shaped cross-section.

[0216] In one embodiment, the p-type material layer 120 may include a p-type material contact 118. The p-type material contact 118 can be electrically connected to a connector 166, and the connector 166 can be electrically connected to a contact pad 162. In this regard, the characteristics of the transistor 100 can be adjusted using the contact pad 162.

[0217] Figure 29 shows a cross-sectional view of another embodiment of the transistor according to this disclosure.

[0218] In particular, Figure 29 shows a transistor 100 that can include one or more embodiments of the present disclosure described herein. In particular, in some embodiments, the transistor 100 of Figure 29 can include the p+ layer 106 (not shown) described above. In other embodiments, the p+ layer 106 may not be used. In one embodiment of Figure 29, the transistor 100 can be implemented by the p+ layer 106 alone. In one embodiment of Figure 29, the transistor 100 can be implemented by the p+ layer 106 and the p-type material layer 120. In one embodiment of Figure 29, the transistor 100 can be implemented by the p-type material layer 120 alone. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be injected as described herein. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be formed as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be injected as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be formed as described herein.

[0219] In one embodiment shown in Figure 29, the transistor 100 may include a gate 114 having a T-shaped cross-section. In another embodiment, the gate 114 may not be T-shaped. In another embodiment, the p-type material layer 120 may include a p-type material contact 118. The p-type material contact 118 can be electrically connected to a connector 166, and the connector 166 can be electrically connected to a contact pad 162. In this regard, the characteristics of the transistor 100 can be adjusted using the contact pad 162.

[0220] Figure 30 shows a cross-sectional view of another embodiment of the transistor according to this disclosure.

[0221] In particular, Figure 30 shows a transistor 100 that can include one or more embodiments of the present disclosure described herein. In particular, in some embodiments, the transistor 100 of Figure 30 can include the p+ layer 106 (not shown) described above. In other embodiments, the p+ layer 106 may not be used. In one embodiment of Figure 30, the transistor 100 can be implemented by the p+ layer 106 alone. In one embodiment of Figure 30, the transistor 100 can be implemented by the p+ layer 106 and the p-type material layer 120. In one embodiment of Figure 30, the transistor 100 can be implemented by the p-type material layer 120 alone. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be injected as described herein. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be formed as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be injected as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be formed as described herein.

[0222] In particular, Figure 30 shows a transistor 100 in which a p-type material layer 120 can be included in the substrate layer 102 and the p-type material layer 120 can be included in the epitaxial layer 202. In one embodiment shown in Figure 30, the transistor 100 can include a gate 114 having a T-shaped cross-section.

[0223] In one embodiment, the p-type material layer 120 may include a p-type material contact 118. The p-type material contact 118 can be electrically connected to a connector 166, and the connector 166 can be electrically connected to a contact pad 162. In this regard, the characteristics of the transistor 100 can be adjusted using the contact pad 162.

[0224] Figure 31 shows a cross-sectional view of another embodiment of the transistor according to this disclosure.

[0225] In particular, Figure 31 shows a transistor 100 that can include one or more embodiments of the present disclosure described herein. In particular, in some embodiments, the transistor 100 of Figure 31 can include the p+ layer 106 described above. In other embodiments, the p+ layer 106 may not be used. In one embodiment of Figure 31, the transistor 100 can be implemented by the p+ layer 106 alone. In one embodiment of Figure 31, the transistor 100 can be implemented by the p+ layer 106 and the p-type material layer 120. In one embodiment of Figure 31, the transistor 100 can be implemented by the p-type material layer 120 alone. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be injected as described herein. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be formed as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be injected as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be formed as described herein.

[0226] In particular, Figure 31 shows a transistor 100 that can include a p+ layer 106 within a substrate layer 102. In one embodiment, the transistor 100 can include a p-type material layer 120 within the substrate layer 102. In one embodiment, the transistor 100 can include a p+ layer 106 within the substrate layer 102 and can also include a p-type material layer 120 within the substrate layer 102. In one embodiment shown in Figure 31, the transistor 100 can include a gate 114 having a T-shaped cross-section.

[0227] In one embodiment, the p-type material layer 120 may include a p-type material contact 118. The p-type material contact 118 can be electrically connected to a connector 166, and the connector 166 can be electrically connected to a contact pad 162. In this regard, the characteristics of the transistor 100 can be adjusted using the contact pad 162.

[0228] In one embodiment, the p+ layer 106 may include a p-type material contact 118. The p-type material contact 118 can be electrically connected to a connector 166, and the connector 166 can be electrically connected to a contact pad 162. In this regard, the characteristics of the transistor 100 can be adjusted using the contact pad 162.

[0229] Figure 32 shows a cross-sectional view of another embodiment of the transistor according to this disclosure.

[0230] In particular, Figure 32 shows a transistor 100 that can include one or more embodiments of the present disclosure described herein. In particular, in some embodiments, the transistor 100 of Figure 32 can include the p+ layer 106 described above. In other embodiments, the p+ layer 106 may not be used. In one embodiment of Figure 32, the transistor 100 can be implemented by the p+ layer 106 alone. In one embodiment of Figure 32, the transistor 100 can be implemented by the p+ layer 106 and the p-type material layer 120. In one embodiment of Figure 32, the transistor 100 can be implemented by the p-type material layer 120 alone. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be injected as described herein. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be formed as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be injected as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be formed as described herein.

[0231] In particular, Figure 32 shows a transistor 100 that can include a p+ layer 106 within the substrate layer 102. In one embodiment, the transistor 100 can include a p-type material layer 120 within the substrate layer 102. In one embodiment, the transistor 100 can include a p+ layer 106 within the substrate layer 102 and can also include a p-type material layer 120 within the substrate layer 102.

[0232] In one embodiment, the p-type material layer 120 may include a p-type material contact 118. The p-type material contact 118 can be electrically connected to a connector 166, and the connector 166 can be electrically connected to a contact pad 162. In this regard, the characteristics of the transistor 100 can be adjusted using the contact pad 162. In one embodiment, the transistor 100 may include a field plate 132.

[0233] In one embodiment, the p+ layer 106 may include a p-type material contact 118. The p-type material contact 118 can be electrically connected to a connector 166, and the connector 166 can be electrically connected to a contact pad 162. In this regard, the characteristics of the transistor 100 can be adjusted using the contact pad 162.

[0234] Figure 33 shows a cross-sectional view of another embodiment of the transistor according to this disclosure.

[0235] In particular, Figure 33 shows a transistor 100 that can include one or more embodiments of the present disclosure described herein. In particular, in some embodiments, the transistor 100 of Figure 33 can include the p+ layer 106 described above. In other embodiments, the p+ layer 106 may not be used. In one embodiment of Figure 33, the transistor 100 can be implemented by the p+ layer 106 alone. In one embodiment of Figure 33, the transistor 100 can be implemented by the p+ layer 106 and the p-type material layer 120. In one embodiment of Figure 33, the transistor 100 can be implemented by the p-type material layer 120 alone. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be injected as described herein. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be formed as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be injected as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be formed as described herein.

[0236] In particular, Figure 33 shows a transistor 100 that can include a p+ layer 106 within a substrate layer 102. In one embodiment, the transistor 100 can include a p-type material layer 120 within the substrate layer 102. In one embodiment, the transistor 100 can include a p+ layer 106 within the substrate layer 102 and can include a p-type material layer 120 within the substrate layer 102. In one embodiment, the transistor 100 can include a field plate 132 adjacent to the gate 114. In one embodiment, the transistor 100 can include a gate 114 having a T-shaped cross-section.

[0237] In one embodiment, the p-type material layer 120 may include a p-type material contact 118. The p-type material contact 118 can be electrically connected to a connector 166, and the connector 166 can be electrically connected to a contact pad 162. In this regard, the characteristics of the transistor 100 can be adjusted using the contact pad 162.

[0238] In one embodiment, the p+ layer 106 may include a p-type material contact 118. The p-type material contact 118 can be electrically connected to a connector 166, and the connector 166 can be electrically connected to a contact pad 162. In this regard, the characteristics of the transistor 100 can be adjusted using the contact pad 162.

[0239] Figure 34 shows a cross-sectional view of another embodiment of the transistor according to this disclosure.

[0240] In particular, Figure 34 shows a transistor 100 that can include one or more embodiments of the present disclosure described herein. In particular, in some embodiments, the transistor 100 of Figure 34 can include the p+ layer 106 described above. In other embodiments, the p+ layer 106 may not be used. In one embodiment of Figure 34, the transistor 100 can be implemented by the p+ layer 106 alone. In one embodiment of Figure 34, the transistor 100 can be implemented by the p+ layer 106 and the p-type material layer 120. In one embodiment of Figure 34, the transistor 100 can be implemented by the p-type material layer 120 alone. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be injected as described herein. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be formed as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be injected as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be formed as described herein.

[0241] In particular, Figure 34 shows a transistor 100 that can include a p+ layer 106 within a substrate layer 102. In one embodiment, the transistor 100 can include a p-type material layer 120 within the substrate layer 102. In one embodiment, the transistor 100 can include a p+ layer 106 within the substrate layer 102 and can include a p-type material layer 120 within the substrate layer 102. In one embodiment, the transistor 100 can include a field plate 132. In one embodiment, the transistor 100 can include a gate 114 having a T-shaped cross-section. In one embodiment, the gate 114 can be a non-T-shaped gate. In one embodiment, the transistor 100 can further include a connector 140 for connecting the field plate 132 to a source 110.

[0242] In one embodiment, the p-type material layer 120 may include a p-type material contact 118. The p-type material contact 118 can be electrically connected to a connector 166, and the connector 166 can be electrically connected to a contact pad 162. In this regard, the characteristics of the transistor 100 can be adjusted using the contact pad 162. In one embodiment, the transistor 100 may further include a connector 138 for connecting a field plate 132 and / or a source 110 to the p-type material contact 118. In one embodiment, the transistor 100 may further include connectors 138 and 140 configured to directly connect the field plate 132 to the p-type material contact 118 without connecting to the source 110. In one embodiment, the transistor 100 may further include connectors 138 and 140 configured to connect the field plate 132 directly to the p-type material contact 118 without any intervening connectors.

[0243] In one embodiment, the p+ layer 106 may include a p-type material contact 118. The p-type material contact 118 can be electrically connected to a connector 166, and the connector 166 can be electrically connected to a contact pad 162. In this regard, the characteristics of the transistor 100 can be adjusted using the contact pad 162.

[0244] Figure 35 shows a cross-sectional view of another embodiment of the transistor according to this disclosure.

[0245] In particular, Figure 35 shows a transistor 100 that can include one or more embodiments of the present disclosure described herein. In particular, in some embodiments, the transistor 100 of Figure 35 can include the p+ layer 106 described above. In other embodiments, the p+ layer 106 may not be used. In one embodiment of Figure 35, the transistor 100 can be implemented by the p+ layer 106 alone. In one embodiment of Figure 35, the transistor 100 can be implemented by the p+ layer 106 and the p-type material layer 120. In one embodiment of Figure 35, the transistor 100 can be implemented by the p-type material layer 120 alone. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be injected as described herein. In embodiments utilizing the p-type material layer 120, the p-type material layer 120 can be formed as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be injected as described herein. In embodiments utilizing the p+ layer 106, the p+ layer 106 can be formed as described herein.

[0246] In particular, Figure 35 shows a transistor 100 that can be implemented without the p-type material contact 118. In this regard, the transistor 100 of Figure 35, along with the p-type material layer 120 and / or p+ layer 106, can also reduce the drain delay effect compared to a transistor without such a p-layer.

[0247] Therefore, this disclosure presents a simpler alternative solution for forming a p-type layer within a HEMT. The disclosed structure can be readily fabricated by currently available techniques. Furthermore, the disclosed use of high-purity material minimizes drain delay. In addition, the disclosed p-type material layer provides a decelerating electric field for good electron confinement with low leakage. Moreover, aspects of this disclosure describe in detail transistors having p-type layers and variations of methods for forming those p-type layers. The disclosed transistors maximize RF power, enable efficient discharge, and maximize breakdown.

[0248] According to a further aspect of the present disclosure, transistors such as GaN HEMTs fabricated on a high resistivity substrate can be utilized in high power RF (radio frequency) amplifiers, high power radio frequency (RF) applications, and low frequency high power switching applications. The advantageous electronic and thermal properties of GaN HEMTs are also very attractive for switching high power RF signals. In this regard, the present disclosure describes a structure having an embedded p-layer under the source region in order to obtain a high breakdown voltage in HEMTs for various applications including power amplifiers, while at the same time eliminating the drift of device characteristics caused by trapping in the buffer and / or semi-insulating substrate. The use of the embedded p-layer can also be important for HEMTs for RF switches in order to obtain a high breakdown voltage and good separation between the input and output.

Example

[0249] [ ] (Example 1) An apparatus comprising a substrate, a group III nitride buffer layer on the substrate, a group III nitride barrier layer on the group III nitride buffer layer, the group III nitride barrier layer having a bandgap larger than the bandgap of the group III nitride buffer layer, a source electrically coupled to the group III nitride barrier layer, a gate electrically coupled to the group III nitride barrier layer, a drain electrically coupled to the group III nitride barrier layer, and a p-region located in at least one of the substrate or on the substrate under the group III nitride barrier layer.

[0250] (Example 2) The apparatus according to Example 1, wherein the p-region is located on the substrate under the group III nitride barrier layer.

[0251] (Example 3) The apparatus according to Example 2, wherein the p-region is implanted.

[0252] (Example 4) The apparatus according to Example 2, wherein the p-region comprises at least two p-regions.

[0253] (Example 5) The device according to Example 1, wherein the p-region is located in a substrate under the group-III nitride barrier layer.

[0254] (Example 6) The device according to Example 5, wherein a p-region is implanted.

[0255] (Example 7) The device according to Example 5, wherein the p-region comprises at least two p-regions.

[0256] (Example 8) The device according to Example 1, further comprising an epitaxial layer on a substrate, wherein the p-region is located in the epitaxial layer.

[0257] (Example 9) The device according to Example 8, wherein a p-region is implanted in the epitaxial layer.

[0258] (Example 10) The device according to Example 8, wherein the p-region in the epitaxial layer comprises at least two p-regions.

[0259] (Example 11) The device according to Example 8, wherein the epitaxial layer is located under the group-III nitride barrier layer.

[0260] (Example 12) The device according to Example 1, further comprising an epitaxial layer on a substrate, wherein the p-region is located in the epitaxial layer and the p-region is also located in a substrate under the group-III nitride barrier layer.

[0261] (Example 13) The device according to Example 12, wherein at least one of the p-regions is implanted.

[0262] (Example 14) The device according to Example 12, wherein the p-region comprises at least two p-regions.

[0263] (Example 15) The device according to Example 1, wherein the p-region is located on a substrate under the Group-III nitride barrier layer, and the p-region is also located within the substrate under the Group-III nitride barrier layer.

[0264] (Example 16) The device according to Example 15, wherein at least one of the p-regions is implanted.

[0265] (Example 17) The device according to Example 15, wherein the p-region comprises at least two p-regions.

[0266] (Example 18) The device according to Example 1, further comprising a field plate, wherein the field plate is located at at least one of a vicinity of and on a gate.

[0267] (Example 19) The device according to Example 18, wherein the field plate is electrically coupled to the p-region.

[0268] (Example 20) The device according to Example 18, wherein the field plate is electrically coupled to a source.

[0269] (Example 21) The device according to Example 18, wherein the field plate is electrically coupled to the source and the p-region.

[0270] (Example 22) The device according to Example 21, wherein the p-region is located on a substrate under the Group-III nitride barrier layer.

[0271] (Example 23) The device according to Example 22, wherein the p-region is implanted.

[0272] (Example 24) The device according to Example 22, wherein the p-region comprises at least two p-regions.

[0273] (Example 25) The apparatus according to Example 21, wherein the p region is located within the substrate beneath the group III nitride barrier layer.

[0274] (Example 26) The apparatus described in Example 25, in which the p region is injected.

[0275] (Example 27) The apparatus according to Example 25, wherein the p region comprises at least two p regions.

[0276] (Example 28) The apparatus according to Example 21, further comprising an epitaxial layer on a substrate, wherein the p region is located within the epitaxial layer.

[0277] (Example 29) The apparatus according to Example 28, wherein the p region is injected into the epitaxial layer.

[0278] (Example 30) The apparatus according to Example 28, wherein the p region comprises at least two p regions within the epitaxial layer.

[0279] (Example 31) The apparatus according to Example 28, wherein the epitaxial layer is located below the group III nitride barrier layer.

[0280] (Example 32) The apparatus according to Example 21, further comprising an epitaxial layer on the substrate, wherein the p region is located within the epitaxial layer, and the p region is also located within the substrate beneath the group III nitride barrier layer.

[0281] (Example 33) The apparatus according to Example 32, wherein at least one of the p regions is injected.

[0282] (Example 34) The apparatus according to Example 32, wherein the p region comprises at least two p regions.

[0283] (Example 35) The apparatus according to Example 21, wherein the p region is located on the substrate beneath the group III nitride barrier layer, and the p region is also located within the substrate beneath the group III nitride barrier layer.

[0284] (Example 36) The apparatus according to Example 35, wherein at least one of the p regions is injected.

[0285] (Example 37) The apparatus according to Example 35, wherein the p region comprises at least two p regions.

[0286] (Example 38) The apparatus according to Embodiment 1, further comprising a field plate, wherein the field plate is located near the gate and on the gate, at least one of the above.

[0287] (Example 39) The apparatus according to Example 1, wherein the gate has a T-shaped cross-section.

[0288] (Example 40) The apparatus according to Example 39, wherein the gate is electrically coupled to the p region.

[0289] (Example 41) The apparatus according to Example 39, wherein the p region is located on the substrate below the group III nitride barrier layer.

[0290] (Example 42) The apparatus described in Example 41, in which the p region is injected.

[0291] (Example 43) The apparatus according to Example 41, wherein the p region comprises at least two p regions.

[0292] (Example 44) The apparatus according to Example 39, wherein the p region is located within the substrate beneath the group III nitride barrier layer.

[0293] (Example 45) The apparatus described in Example 44, in which the p region is injected.

[0294] (Example 46) The apparatus according to Example 44, wherein the p region comprises at least two p regions.

[0295] (Example 47) The apparatus according to Example 39, further comprising an epitaxial layer on a substrate, wherein the p region is located within the epitaxial layer.

[0296] (Example 48) The apparatus according to Example 47, wherein the p region is injected into the epitaxial layer.

[0297] (Example 49) The apparatus according to Example 47, wherein the p region comprises at least two p regions within the epitaxial layer.

[0298] (Example 50) The apparatus according to Example 47, wherein the epitaxial layer is located below the group III nitride barrier layer.

[0299] (Example 51) The apparatus according to Example 39, further comprising an epitaxial layer on the substrate, wherein the p region is located within the epitaxial layer, and the p region is also located within the substrate beneath the group III nitride barrier layer.

[0300] (Example 52) The apparatus according to Example 51, wherein at least one of the p regions is injected.

[0301] (Example 53) The apparatus according to Example 51, wherein the p region comprises at least two p regions.

[0302] (Example 54) The apparatus according to Example 39, wherein the p region is located on the substrate beneath the group III nitride barrier layer, and the p region is also located within the substrate beneath the group III nitride barrier layer.

[0303] (Example 55) The apparatus according to Example 54, wherein at least one of the p regions is injected.

[0304] (Example 56) The apparatus according to Example 54, wherein the p region comprises at least two p regions.

[0305] (Example 57) The apparatus according to Example 39, further comprising a field plate, wherein the field plate is located near the gate and on the gate, at least one of the two locations.

[0306] (Example 58) The apparatus according to Example 1, wherein the source is electrically coupled to the p region.

[0307] (Example 59) The apparatus according to Embodiment 58, further comprising a connection portion configured to connect the source to the p region.

[0308] (Example 60) The apparatus according to Example 59, wherein the p region is located on the substrate below the group III nitride barrier layer.

[0309] (Example 61) The apparatus described in Example 60, in which the p region is injected.

[0310] (Example 62) The apparatus according to Example 60, wherein the p region comprises at least two p regions.

[0311] (Example 63) The apparatus according to Example 59, wherein the p region is located within the substrate beneath the group III nitride barrier layer.

[0312] (Example 64) The apparatus described in Example 63, in which the p region is injected.

[0313] (Example 65) The apparatus according to Example 63, wherein the p region comprises at least two p regions.

[0314] (Example 66) The apparatus according to Example 59, further comprising an epitaxial layer on a substrate, wherein the p region is located within the epitaxial layer.

[0315] (Example 67) The apparatus according to Example 66, wherein the p region is injected into the epitaxial layer.

[0316] (Example 68) The apparatus according to Example 66, wherein the p region comprises at least two p regions within the epitaxial layer.

[0317] (Example 69) The apparatus according to Example 66, wherein the epitaxial layer is located below the group III nitride barrier layer.

[0318] (Example 70) The apparatus according to Example 59, further comprising an epitaxial layer on the substrate, wherein the p region is located within the epitaxial layer, and the p region is also located within the substrate beneath the group III nitride barrier layer.

[0319] (Example 71) The apparatus according to Example 70, wherein at least one of the p regions is injected.

[0320] (Example 72) The apparatus according to Example 70, wherein the p region comprises at least two p regions.

[0321] (Example 73) The apparatus according to Example 59, wherein the p region is located on the substrate beneath the group III nitride barrier layer, and the p region is also located within the substrate beneath the group III nitride barrier layer.

[0322] (Example 74) The apparatus according to Example 73, wherein at least one of the p regions is injected.

[0323] (Example 75) The apparatus according to Example 73, wherein the p region comprises at least two p regions.

[0324] (Example 76) The apparatus according to Embodiment 59, further comprising a field plate, wherein the field plate is located near the gate and on the gate at least one of the locations.

[0325] (Example 77) The apparatus according to Example 1, further comprising a contact pad electrically coupled to the p region.

[0326] (Example 78) The apparatus according to Embodiment 77, further comprising a connection portion for electrically connecting a contact pad to the p region.

[0327] (Example 79) The apparatus according to Example 77, wherein the contact pad is configured to receive at least one of a bias and a signal.

[0328] (Example 80) The apparatus according to Embodiment 77, wherein the contact pad is configured to receive at least one of a bias for adjusting the characteristics of the apparatus and a signal for adjusting the characteristics of the apparatus.

[0329] (Example 81) The apparatus according to Example 80, wherein the p region is located on the substrate below the group III nitride barrier layer.

[0330] (Example 82) The apparatus described in Example 81, in which the p region is injected.

[0331] (Example 83) The apparatus according to Example 81, wherein the p region comprises at least two p regions.

[0332] (Example 84) The apparatus according to Example 80, wherein the p region is located within the substrate beneath the group III nitride barrier layer.

[0333] (Example 85) The apparatus described in Example 84, in which the p region is injected.

[0334] (Example 86) The apparatus according to Example 84, wherein the p region comprises at least two p regions.

[0335] (Example 87) The apparatus according to Example 80, further comprising an epitaxial layer on a substrate, wherein the p region is located within the epitaxial layer.

[0336] (Example 88) The apparatus according to Example 87, wherein the p region is injected into the epitaxial layer.

[0337] (Example 89) The apparatus according to Example 87, wherein the p region comprises at least two p regions within the epitaxial layer.

[0338] (Example 90) The apparatus according to Example 87, wherein the epitaxial layer is located below the group III nitride barrier layer.

[0339] (Example 91) The apparatus according to Example 80, further comprising an epitaxial layer on the substrate, wherein the p region is located within the epitaxial layer, and the p region is also located within the substrate beneath the group III nitride barrier layer.

[0340] (Example 92) The apparatus according to Example 91, wherein at least one of the p regions is injected.

[0341] (Example 93) The apparatus according to Example 91, wherein the p region comprises at least two p regions.

[0342] (Example 94) The apparatus according to Example 80, wherein the p region is located on the substrate beneath the group III nitride barrier layer, and the p region is also located within the substrate beneath the group III nitride barrier layer.

[0343] (Example 95) The apparatus according to Example 94, wherein at least one of the p regions is injected.

[0344] (Example 96) The apparatus according to Example 94, wherein the p region comprises at least two p regions.

[0345] (Example 97) The apparatus according to Example 80, further comprising a field plate, wherein the field plate is located near the gate and on the gate, at least one of the locations.

[0346] (Example 98) The apparatus according to Example 1, further comprising a nucleation layer on the substrate, wherein a group III nitride buffer layer is located on the nucleation layer.

[0347] (Example 99) The apparatus according to Example 98, further comprising an intervening layer between the nucleating layer and the group III nitride buffer layer.

[0348] (Example 100) The apparatus described in Example 1, wherein the length of the p region is smaller than the total length of the substrate.

[0349] (Example 101) The apparatus according to Example 1, wherein a p region is provided within the substrate, and the p region contains aluminum injected into the substrate.

[0350] (Example 102) The apparatus according to Example 1, wherein the p region is provided within a layer arranged on a substrate, and this layer is an epitaxial layer, and this layer is at least one of GaN or SiC.

[0351] (Example 103) The apparatus according to Example 1, wherein the thickness of the group III nitride buffer layer, defined as the distance between the upper surface of the substrate and the lower surface of the group III nitride barrier layer, is in the range of 0.7 μm to 0.3 μm.

[0352] (Example 104) The apparatus according to Example 1, wherein the thickness of one or more layers between the upper surface of the substrate and the lower surface of the Group III nitride barrier layer is in the range of 0.7 μm to 0.3 μm.

[0353] (Example 105) An apparatus comprising a substrate, a group III nitride buffer layer on the substrate, a group III nitride barrier layer on the group III nitride buffer layer having a band gap larger than the band gap of the group III nitride buffer layer, a source electrically coupled to the group III nitride barrier layer, a gate electrically coupled to the group III nitride barrier layer, a drain electrically coupled to the group III nitride barrier layer, a p region located in or on the substrate below the group III nitride barrier layer, and a contact pad electrically coupled to the p region.

[0354] (Example 106) The apparatus according to Embodiment 105, further comprising a connection portion for electrically connecting a contact pad to the p region.

[0355] (Example 107) The apparatus according to Example 105, wherein the contact pad is configured to receive at least one of a bias and a signal.

[0356] (Example 108) The apparatus according to Example 105, wherein the contact pad is configured to receive at least one of a bias for adjusting the characteristics of the apparatus and a signal for adjusting the characteristics of the apparatus.

[0357] (Example 109) The apparatus according to Example 105, wherein the p region is located on the substrate below the group III nitride barrier layer.

[0358] (Example 110) The apparatus described in Example 109, in which the p region is injected.

[0359] (Example 111) The apparatus according to Example 105, wherein the p region comprises at least two p regions.

[0360] (Example 112) The apparatus according to Example 105, wherein the p region is located within the substrate beneath the group III nitride barrier layer.

[0361] (Example 113) An apparatus comprising a substrate, a group III nitride buffer layer on the substrate, a group III nitride barrier layer on the group III nitride buffer layer having a band gap larger than the band gap of the group III nitride buffer layer, a source electrically coupled to the group III nitride barrier layer, a gate electrically coupled to the group III nitride barrier layer, a drain electrically coupled to the group III nitride barrier layer, and a p region located in or on the substrate below the group III nitride barrier layer, wherein the gate is electrically coupled to the p region.

[0362] (Example 114) The apparatus according to Embodiment 113, further comprising a connection part for electrically connecting the gate to the p region.

[0363] (Example 115) The apparatus according to Example 113, wherein the p region is located on the substrate below the group III nitride barrier layer.

[0364] (Example 116) The apparatus described in Example 115, in which the p region is injected.

[0365] (Example 117) The apparatus according to Example 113, wherein the p region comprises at least two p regions.

[0366] (Example 118) The apparatus according to Example 113, wherein the p region is located within the substrate beneath the group III nitride barrier layer.

[0367] (Example 119) The apparatus described in Example 118, in which the p region is injected.

[0368] (Example 120) The apparatus according to Example 118, wherein the p region comprises at least two p regions.

[0369] (Example 121) The apparatus according to Example 113, further comprising an epitaxial layer on a substrate, wherein the p region is located within the epitaxial layer.

[0370] (Example 122) A method for fabricating a device, comprising: providing a substrate; providing a group III nitride buffer layer on the substrate; providing a group III nitride barrier layer on the group III nitride buffer layer, wherein the group III nitride barrier layer has a band gap larger than the band gap of the group III nitride buffer layer; electrically coupling a source to the group III nitride barrier layer; electrically coupling a gate to the group III nitride barrier layer; electrically coupling a drain to the group III nitride barrier layer; and providing a p region in or on the substrate below the group III nitride barrier layer.

[0371] (Example 123) A method for fabricating the device according to Example 122, further comprising injecting a p region.

[0372] (Example 124) A method for fabricating the device described in Example 122, wherein the p region is located within the substrate beneath the group III nitride barrier layer.

[0373] (Example 125) A method for fabricating the device according to Example 122, further comprising providing an epitaxial layer on a substrate, wherein the p region is located within the epitaxial layer.

[0374] (Example 126) A method for fabricating the device according to Example 122, further comprising providing an epitaxial layer on a substrate, wherein the p region is located within the epitaxial layer, and the p region is also located within the substrate beneath the group III nitride barrier layer.

[0375] (Example 127) A method for fabricating the device according to Example 122, further comprising providing a field plate, wherein the field plate is electrically coupled to the p region.

[0376] (Example 128) A method for fabricating the device according to Example 127, further comprising providing a field plate, wherein the field plate is electrically coupled to a source.

[0377] (Example 129) A method for fabricating the device according to Example 128, wherein the field plate is electrically coupled to the source and the p region.

[0378] While this disclosure has been described in terms of exemplary embodiments, it will be understood by those skilled in the art that this disclosure can be modified and implemented within the spirit and scope of the attached claims. These examples are merely illustrative and do not constitute an exhaustive list of all possible designs, embodiments, fields of application, or modifications of this disclosure.

Claims

1. circuit board and The Group III nitride buffer layer on the substrate, A group III nitride barrier layer on the group III nitride buffer layer, the group III nitride barrier layer having a band gap larger than the band gap of the group III nitride buffer layer, A source electrically coupled to the group III nitride barrier layer, A gate electrically coupled to the group III nitride barrier layer, A drain electrically coupled to the group III nitride barrier layer, A p region located in or on the substrate below the group III nitride barrier layer A device equipped with the following features.

2. The apparatus according to claim 1, wherein the p region is injected.

3. The apparatus according to claim 1, wherein the p region is located within the substrate below the group III nitride barrier layer.

4. The apparatus according to claim 1, further comprising an epitaxial layer on the substrate, wherein the p region is located within the epitaxial layer.

5. The apparatus according to claim 1, further comprising a field plate.

6. The apparatus according to claim 1, further comprising a field plate, wherein the field plate is electrically coupled to the p region.

7. The apparatus according to claim 6, wherein the field plate is electrically coupled to the source.

8. circuit board and The Group III nitride buffer layer on the substrate, A group III nitride barrier layer on the group III nitride buffer layer, the group III nitride barrier layer having a band gap larger than the band gap of the group III nitride buffer layer, A source electrically coupled to the group III nitride barrier layer, A gate electrically coupled to the group III nitride barrier layer, A drain electrically coupled to the group III nitride barrier layer, A p region located in or on the substrate below the group III nitride barrier layer, A contact pad electrically coupled to the p region and A device equipped with the following features.

9. The apparatus according to claim 8, further comprising a connection portion for electrically connecting a contact pad to the p region.

10. The apparatus according to claim 8, wherein the contact pad is configured to receive at least one of a bias and a signal.

11. The apparatus according to claim 8, wherein the contact pad is configured to receive at least one of a bias for adjusting the characteristics of the apparatus and a signal for adjusting the characteristics of the apparatus.

12. The apparatus according to claim 8, wherein the p region is located on the substrate below the group III nitride barrier layer.

13. The apparatus according to claim 8, wherein the p region is injected.

14. The apparatus according to claim 8, wherein the p region is located within the substrate below the group III nitride barrier layer.

15. circuit board and The Group III nitride buffer layer on the substrate, A group III nitride barrier layer on the group III nitride buffer layer, the group III nitride barrier layer having a band gap larger than the band gap of the group III nitride buffer layer, A source electrically coupled to the group III nitride barrier layer, A gate electrically coupled to the group III nitride barrier layer, A drain electrically coupled to the group III nitride barrier layer, The group III nitride barrier layer comprises a p region located in or on the substrate, at least one of the above, The gate is electrically coupled to the p region. Device.

16. The apparatus according to claim 15, further comprising a connection portion for electrically connecting the gate to the p region.

17. The apparatus according to claim 15, wherein the p region is located on the substrate below the group III nitride barrier layer.

18. The apparatus according to claim 17, wherein the p region is injected.

19. The apparatus according to claim 15, wherein the p region is located within the substrate below the group III nitride barrier layer.

20. The apparatus according to claim 15, further comprising an epitaxial layer on the substrate, wherein the p region is located within the epitaxial layer.

21. A method for fabricating a device, To install a circuit board, A group III nitride buffer layer is provided on the aforementioned substrate, The method involves providing a group III nitride barrier layer on the group III nitride buffer layer, wherein the group III nitride barrier layer has a band gap larger than the band gap of the group III nitride buffer layer. The source is electrically coupled to the group III nitride barrier layer, The gate is electrically coupled to the group III nitride barrier layer, The drain is electrically coupled to the group III nitride barrier layer, A method comprising providing a p region in or on the substrate below the group III nitride barrier layer.

22. A method for fabricating the device according to claim 21, further comprising injecting the p region.

23. A method for manufacturing the device according to claim 21, wherein the p region is located within the substrate below the group III nitride barrier layer.

24. A method for manufacturing the device according to claim 21, further comprising providing an epitaxial layer on the substrate, wherein the p region is located within the epitaxial layer.

25. A method for manufacturing the device according to claim 21, further comprising providing a field plate.

26. A method for manufacturing the device according to claim 21, further comprising providing a field plate, wherein the field plate is electrically coupled to the p region.

27. A method for manufacturing the device according to claim 26, further comprising providing a field plate, wherein the field plate is electrically coupled to the source.

28. A method for manufacturing the device according to claim 27, wherein the field plate is electrically coupled to the source and the p region.

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