Semiconductor equipment

Abstract

To provide a highly integrated semiconductor device. [Solution] A substrate, a prismatic insulator, and a plurality of transistors connected in series. A memory cell string and a prismatic insulator are arranged on a substrate, and the memory cell string The transistors are positioned on the sides of the prismatic insulator, and each of the multiple transistors is a gate It has an insulator and a gate electrode, and the gate insulator comprises a first insulator and a second insulator. The device has a charge storage layer, the charge storage layer is disposed between a first insulator and a second insulator. It is a semiconductor device.

Description

[Technical Field]

[0001] The present invention relates, for example, to semiconductors, transistors and semiconductor devices. Alternatively, the present invention relates to semiconductors, transistors and semiconductor devices. For example, the present invention relates to methods for manufacturing semiconductors, transistors, and semiconductor devices. Examples include semiconductors, display devices, light-emitting devices, lighting devices, energy storage devices, memory devices, and processors. , relating to electronic equipment. Or semiconductors, display devices, liquid crystal display devices, light-emitting devices, memory devices, This relates to a method for manufacturing electronic equipment, or to semiconductor devices, display devices, liquid crystal display devices, and light-emitting devices. The present invention relates to a method for driving memory devices and electronic devices.

[0002] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. One aspect of the technical field relates to a product, method, or method of manufacture. Or, the present invention. One aspect of this is a process, machine, manufacture, or composition. It concerns matter.

[0003] In this specification, a semiconductor device refers to a device that can function by utilizing semiconductor properties. This refers to the general category of display devices, light-emitting devices, lighting devices, electro-optical devices, semiconductor circuits, and electronic equipment. It may have a semiconductor device. [Background technology]

[0004] Semiconductor-based memory devices are attracting attention as large-capacity storage devices used in computers and other devices. In particular, NAND flash memory has a number of wires and electrodes per memory cell. It is known that the number of elements is small and the integration density can be easily increased. Furthermore, technologies such as multi-level cell processing have also been realized. Memory capacity has been increasing year by year. In recent years, high integration has been achieved through the arrangement of planar memory cells. It is reaching the limits of its current form factor and is being replaced by technologies that arrange memory cells in three dimensions. See patent document 1. ). [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2011-96340 [Overview of the project] [Problems that the invention aims to solve]

[0006] One of the challenges is to provide a semiconductor device with a high degree of integration. Alternatively, to provide a three-dimensional memory system. One of the objectives is to provide a semiconductor device with a large memory capacity. One of the objectives is to provide a conductive device, or a device having a memory cell with a long retention period. One of the objectives is to provide semiconductor devices.

[0007] Alternatively, one of the objectives is to provide a module having the semiconductor device. One of the objectives is to provide a semiconductor device or an electronic device having such a module. Alternatively, one of the objectives is to provide a novel semiconductor device. Or, a novel module One of the objectives is to provide... or to provide novel electronic devices... ru.

[0008] Alternatively, one of the objectives is to provide a transistor having normally-off electrical characteristics. Alternatively, one of the objectives is to provide a transistor with low leakage current when not conducting. Alternatively, the objective is to provide transistors with small subthreshold swing values. One of the objectives is to provide a transistor with low short-channel effects. To do so. Or, one of the objectives is to provide a transistor with excellent electrical characteristics. Or One of the challenges is to provide highly reliable transistors, or to achieve high frequency characteristics. One of the objectives is to provide a transistor having [a certain characteristic].

[0009] Furthermore, the description of these problems does not preclude the existence of other problems. The approach does not need to solve all of these problems. This will become clear from the description in the specification, drawings, claims, etc., and the specification, drawings It is possible to extract other issues from the descriptions in the surfaces, claims, etc. [Means for solving the problem]

[0010] (1) One aspect of the present invention comprises a substrate, a prismatic insulator, and a plurality of transistors connected in series. A memory cell string is provided, and a prismatic insulator is placed on a substrate, and the memory is provided. A cell string is a semiconductor device that is positioned on the side of a prismatic insulator.

[0011] (2) One aspect of the present invention comprises a substrate, a prismatic insulator, and a plurality of transistors connected in series. A memory cell string having a zista, and a prismatic insulator are arranged on a substrate. Multiple memory cell strings are arranged on the sides of a prismatic insulator. It is a semiconductor device.

[0012] (3) One aspect of the present invention is that in (1) or (2), a plurality of transistors each have a gate The gate insulator has a gate electrode, and the gate insulator has a first insulator and a second insulator. The device has a charge storage layer, and the charge storage layer is disposed between a first insulator and a second insulator. It is a semiconductor device.

[0013] (4) One aspect of the present invention is, in any one of (1) to (3), a plurality of transistors are acid This is a semiconductor device having an ionized semiconductor.

[0014] (5) One aspect of the present invention is (4), in which the oxide semiconductor is indium, element M (aluminium A semiconductor device having (aluminum, gallium, yttrium, or tin) and zinc.

[0015] (6) One aspect of the present invention is a further arrangement of the substrate in any one of (1) to (5). It has a transistor 1 and a transistor 2, and the source terminal of the first transistor It is electrically connected to the first terminal of the memory cell string and the second transistor. The IN terminal is a semiconductor device that is electrically connected to the second terminal of the memory cell string. .

[0016] (7) In one aspect of the present invention, in (6), the first transistor and the second transistor are This is a semiconductor device having single-crystal silicon. [Effects of the Invention]

[0017] Highly integrated semiconductor devices can be provided. Alternatively, memory cells can be arranged in three dimensions. We can provide a semiconductor device that has a large memory capacity. It is possible to provide a semiconductor device having memory cells with a long retention period. It is possible.

[0018] Alternatively, a module having the semiconductor device can be provided. We can provide electronic equipment that includes or has such a module. Or, a novel semiconductor We can provide a device or a novel module. Alternatively, it may be possible to provide novel electronic devices.

[0019] Alternatively, a transistor having normally-off electrical characteristics can be provided. This can provide a transistor with low leakage current when not conducting. Or, sub It is possible to provide transistors with small threshold swing values. Or, short-range transistors It is possible to provide transistors with small channel effects. Or, transistors with excellent electrical characteristics. We can provide transistors. Or, we can provide reliable transistors. This is possible. Alternatively, it is possible to provide a transistor with high frequency characteristics.

[0020] Furthermore, the description of these effects does not preclude the existence of other effects. The embodiment does not need to have all of these effects. Other effects are described in the specification. This will become clear from the descriptions in the drawings and claims, and the specification, drawings, and claims will be clear from the description, drawings, and claims. It is possible to extract other effects from any of these descriptions. [Brief explanation of the drawing]

[0021] [Figure 1] A cross-sectional view and a circuit diagram of a semiconductor device according to one aspect of the present invention. [Figure 2]A schematic diagram and a cross-sectional view illustrating the operation of a semiconductor device according to one aspect of the present invention. [Figure 3] A circuit diagram illustrating the operation of a semiconductor device according to one aspect of the present invention. [Figure 4] A circuit diagram illustrating the operation of a semiconductor device according to one aspect of the present invention. [Figure 5] A circuit diagram illustrating the operation of a semiconductor device according to one aspect of the present invention. [Figure 6] A circuit diagram illustrating the operation of a semiconductor device according to one aspect of the present invention. [Figure 7] A circuit diagram illustrating the operation of a semiconductor device according to one aspect of the present invention. [Figure 8] A circuit diagram illustrating the operation of a semiconductor device according to one aspect of the present invention. [Figure 9] A circuit diagram illustrating the operation of a semiconductor device according to one aspect of the present invention. [Figure 10] A cross-sectional view of a semiconductor device according to one aspect of the present invention. [Figure 11] A cross-sectional view of a semiconductor device according to one aspect of the present invention. [Figure 12] A band diagram near the channel formation region of a transistor according to one aspect of the present invention. [Figure 13] A triangular diagram illustrating the composition of In-M-Zn oxide. [Figure 14] Figures illustrating the XRD structural analysis of CAAC-OS and single-crystal oxide semiconductors, as well as a figure showing the limited-field electron diffraction pattern of CAAC-OS. [Figure 15] Cross-sectional TEM images of CAAC-OS, as well as planar TEM images and their image analysis results. [Figure 16] Figure showing the electron diffraction pattern of nc-OS, and a cross-sectional TEM image of nc-OS. [Figure 17] Cross-sectional TEM image of an a-like OS. [Figure 18] A diagram showing the changes in the crystalline structure of In-Ga-Zn oxide due to electron irradiation. [Modes for carrying out the invention]

[0022] Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is described below. It is not limited to the above, and its form and details can be easily changed in various ways, as can be easily seen by those skilled in the art. It is understood that the present invention is to be interpreted as being limited to the embodiments described below. No. Furthermore, when explaining the structure of the invention using drawings, the same reference numerals may refer to different things. It is used consistently across drawings. Furthermore, when referring to similar items, the hatch pattern is the same. Furthermore, sometimes no symbol is assigned.

[0023] Note that in the diagram, the size, thickness of the film (layer), or area has been exaggerated for clarity. They may exist.

[0024] In this specification, the terms "membrane" and "layer" are interchangeable. It is possible to do so.

[0025] Furthermore, voltage is defined by a certain potential and a reference potential (e.g., ground potential (GND) or source potential). It often refers to the potential difference between two points. Therefore, it is possible to rephrase voltage as potential. Generally, electric potential (voltage) is relative, and its magnitude is relative to a reference potential. Therefore, it is determined by this. Consequently, even if it is written as "ground potential," The potential is not necessarily 0V. For example, the lowest potential in a circuit may be the "ground potential". There are also cases where the potential in the middle of the circuit becomes the "ground potential." Based on that potential, positive and negative potentials are defined.

[0026] The ordinal numbers "1st" and "2nd" are used for convenience only and do not necessarily indicate the order of processes or layering. It does not indicate order. Therefore, for example, "the first" could be "the second" or "the third." It can be explained by substituting it as appropriate. Also, ordinal numbers as described in this specification, etc. The ordinal numbers used to specify one aspect of the present invention may not always coincide.

[0027] Furthermore, semiconductor impurities refer to components other than the main components that make up the semiconductor, for example, concentration. Elements present in less than 0.1 atomic percent are considered impurities. The presence of impurities can, for example, affect semiconductors. The formation of Density of State (DOS) in the body, and carrier mobility In some cases, the quality may decrease, or the crystallinity may decrease. In the case of semiconductors, impurities that alter the properties of semiconductors include, for example, Group 1 elements and Group 2 elements. These include elements, Group 14 elements, Group 15 elements, and transition metals other than the main component, and in particular, for example, Hydrogen (also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen These are some examples. In the case of oxide semiconductors, for example, the inclusion of impurities such as hydrogen can form oxygen vacancies. This can occur. Also, if the semiconductor is silicon, impurities can change the properties of the semiconductor. In terms of substances, for example, Group 1 elements (excluding oxygen and hydrogen), Group 2 elements, Group 13 elements, and Group 15 elements. There are group elements, etc.

[0028] In this specification, when A is described as having a shape that protrudes from B, the top view is shown. Alternatively, in a cross-sectional view, at least one end of A is located outside at least one end of B. It may be indicated that A has a shape that protrudes from B. If this is the case, for example, in the top view, one end of A is outside the one end of B. It can be reinterpreted as "possessing."

[0029] In this specification, "parallel" means that two straight lines are positioned at an angle of -10° or more and 10° or less. This refers to a state where the temperature is in a certain condition. Therefore, it also includes cases where the temperature is between -5° and 5°. A "row" refers to a state where two straight lines are positioned at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are positioned at an angle of 80° to 100°. Therefore, it also includes cases where the angle is between 85° and 95°. Also, "approximately perpendicular" means two This refers to a state in which two straight lines are arranged at an angle between 60° and 120°.

[0030] Furthermore, in this specification, if a crystal is trigonal or rhombohedral, it will be represented as a hexagonal crystal system. .

[0031] <Semiconductor device> The following describes a semiconductor device according to one aspect of the present invention.

[0032] The following explanation assumes an n-channel transistor. However, p-channel transistors are also discussed. You may substitute terms or symbols as appropriate for application to transistors.

[0033] <Structure of a semiconductor device> The following describes an example of the structure of a semiconductor device according to one aspect of the present invention.

[0034] Figure 1(A) is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. Figure 1(B) is This is a circuit diagram corresponding to the semiconductor device shown in Figure 1(A).

[0035] The semiconductor device shown in Figure 1(A) consists of a substrate 100, an insulator 120, an insulator 122, and an insulating Body 124, insulator 126, insulator 128, insulator 130, conductor 140, conductive Body 142, conductor 144, conductor 146, conductor 148, conductor 132, conductive Body 134, conductor 136, conductor 138, transistor Tr_S1, and transistor Transistor Tr_S2 and transistors Tr_1 through Tr_2n (where n is an integer greater than or equal to 2) ) and have.

[0036] Transistors Tr_S1 and Tr_S2 are provided on the substrate 100. Specifically, transistor Tr_S1 is located in a pair of impurity regions 166 provided on substrate 100. And the channel formation region sandwiched between impurity regions 166, and the region overlapping with the channel formation region A conductor 154, and an insulator 162 sandwiched between the channel-forming region and the conductor 154, It has the following characteristics: Here, the conductor 154 functions as a gate electrode, and the insulator 162 functions as a gate electrode. It functions as an insulator. It functions as the gate electrode of transistor Tr_S1. The power unit 154 is electrically connected to the wiring SEL_1. Also, the transistor Tr_S2 Conductor 154, which functions as a gate electrode, is electrically connected to wiring SEL_2. The transistor Tr_S2 is described as having a similar structure to transistor Tr_S1. Although omitted, they may have different structures. Transistor Tr_S1 and Transistor Tr_S2 is isolated by an insulator 120. The method of element isolation is as follows: STI (Shallow Trench Isolation) method and LOCOS (Loc Examples include the (al Oxidation of Silicon) method. The structure of the transistor Tr_S1 and transistor Tr_S2 is as shown in Figure 1(A). It is not limited to the manufacturing process. For example, SOI (Silicon on Insulator) substrates. It may be a transistor provided in the same location, or it may be a FIN-type transistor.

[0037] An insulator 122 is placed on transistors Tr_S1 and Tr_S2. On the insulator 122 are insulator 130, conductor 144, conductor 146, and conductor 1 48 and are arranged. The insulator 130 is prismatic or wall-shaped, and transistors are on its sides. Transistors Tr_1 through Tr_2n (where n is an integer greater than or equal to 2) are arranged. The channel length direction of each transistor from Tr_1 to Tr_n is relative to the top surface of the substrate. It is parallel to the vertical direction, and is the same as transistor Tr_n+1 to transistor Tr_2n. The length of each channel is parallel to the direction perpendicular to the top surface of the substrate. However, insulator 1 30 does not have to be prismatic or wall-shaped; for example, it may be cylindrical. Note that insulator 1 On one side of 30, transistors Tr_1 to Tr_n are arranged, and on the other side Transistors Tr_n+1 to Tr_2n are placed there. The larger n is, the better. The integration density of semiconductor devices increases. For example, n can be 2, 4, 8, 16, 32, 64, 128. You can use numbers like these.

[0038] Furthermore, the conductor 132 is connected to transistors Tr_1 to T via the insulator 130. It has a region facing r_2n. The conductor 132 is a transistor Tr_1 or a transistor It functions as the back gate electrode (also called the second gate electrode) of Tr_2n. It is electrically connected to wiring BGL.

[0039] For example, transistor Tr_1 consists of an insulator 106a, a semiconductor 106b, and an insulator 106 c, conductor 116a, conductor 116b, insulator 112a, charge storage layer 112b It has an insulator 112c and a conductor 104. The insulator 106a is on the side of the insulator 130. It is arranged along the surface. The semiconductor 106b is on the side of the insulator 130 via the insulator 106a. It is arranged along the semiconductor 106b and the insulator 106a. It is arranged along the side surface of the insulator 130. Insulator 112a, conductor 116a and conductor 116b is insulated through insulator 106c, semiconductor 106b and insulator 106a to insulator 13 It has a region facing 0. The insulator 112a is connected to the conductor 116a and the conductor 116b. It is placed between the insulator 112a, the insulator 106c, and the semiconductor 1. It has a region that faces the insulator 130 via 06b and insulator 106a. Insulator 112 c is the charge storage layer 112b, insulator 112a, insulator 106c, semiconductor 106b and insulating It has a region that faces the insulator 130 via the edge 106a. The conductor 104 is insulator 11 2c, charge storage layer 112b, insulator 112a, insulator 106c, semiconductor 106b and insulating It has a region that faces the insulator 130 via the edge 106a.

[0040] Therefore, in transistor Tr_1, semiconductor 106b is a channel formation region. The conductor 104 has the function of a gate electrode, the insulator 112a, and the charge storage layer 112b and insulator 112c function as gate insulators, and conductor 116a is a so The conductive material 116b functions as a drain electrode. Furthermore, insulators 106a and 106c provide a dense defect level at the interface of semiconductor 106b. It has the function of reducing the degree. Used in insulator 106a, semiconductor 106b and insulator 106c. The combinations of materials that can be used will be discussed later. The gate electrode of transistor Tr_1 will be... The conductor 104, which functions in this way, is electrically connected to the wiring WL_1. Note that the wiring WL_1 is It functions as a word line. Transistor Tr_1 has the structure shown in Figure 1(A). It is not limited to construction. For example, some structures such as insulator 106a and insulator 106c It does not need to have constituent elements.

[0041] Transistor Tr_1 has a charge storage layer 112b between the conductor 104 and the semiconductor 106b. Therefore, transistor Tr_1 has the polarity of the charge of the charge storage layer 112b. This becomes the threshold voltage corresponding to the amount. Transistor Tr_1 is in charge storage layer 112b Because the threshold voltage can be controlled, a memory cell stores data corresponding to the threshold voltage. It functions as a memory element.

[0042] As shown on the left side of Figure 2(A), for example, electrons are not stored in the charge storage layer 112b. In this state, the threshold voltage of transistor Tr_1 is a negative value. And, as shown in Figure 2(B As shown in the diagram, when electrons accumulate in the charge storage layer 112b, the electric field generated from the electrons is generated To eliminate the signal, the threshold voltage fluctuates, and as shown on the right side of Figure 2(A), the threshold voltage is a positive value. Therefore, transistor Tr_1 does not have electrons stored in the charge storage layer 112b. In this state, it conducts electricity, so data "1" is used, but in the state where electrons are accumulated, it does not conduct electricity, so da Take ta"0". Here, we have explained the case where the memory cell is binary, but ( For example, it may be a multi-value memory cell (such as 4-value, 8-value, 16-value, and 32-value). The injection of electrons into the charge storage layer 112b will be described later.

[0043] Note that transistors Tr_2 through Tr_2n are the same as transistor Tr_1. It has the following configuration. However, the gate of transistors Tr_2 to Tr_2n The electrodes are electrically connected to wiring WL_2 to wiring WL_2n, respectively. Note that wiring W L_2 through wiring WL_2n each function as a word line.

[0044] Thus, transistors Tr_1 through Tr_2n each have memory cells It has the function of a transistor. And transistors Tr_1 to Tr_2n are in series. Because they are connected, they can be collectively called a single memory cell string. It is possible. Also, the memory cell string can be arranged in a matrix on the substrate 100, for example. Each memory cell string is electrically connected to a selection transistor. Specifically, multiple straight lines extending in a first direction on the substrate 100, and extending in a second direction. The memory cell strings can be arranged on the points where multiple lines intersect. The angle between this direction and the second direction can typically be 45° or 90°, but for example, 10° to 90°, 30° to 90°, 45° to 90°, or 60° or more. Any angle within 90° or less is sufficient, and the density increases depending on the shape of the memory cell string. A row is preferred. Here, for example, if wiring SL and wiring BL are arranged along a first direction Then, wiring SL and wiring BL are connected between memory cell strings formed along the first direction. It can be shared. However, the arrangement of memory cell strings is limited to a matrix. It is not. Furthermore, wiring SL functions as a source line. Also, wiring BL is a bit It functions as a wire.

[0045] Furthermore, multiple memory cell strings are collectively called a block. One block is, for example... Then, a number of a items (where a is a natural number) in the first direction and b items (where b is a natural number) in the second direction, for a × b items. This is a collection of memory cell strings. However, each block contains memory cell strings The number of blocks may vary. Also, the way blocks are grouped may be determined arbitrarily. Within the box, for example, wiring BGL and conductor 132 are electrically connected to each other. Between blocks, the wiring BGL and the conductor 132 may be electrically isolated. In a block, for example, wiring WL_1 to wiring WL_2n are arranged along a second direction. Then, wiring WL_1 to wiring between memory cell strings formed along the second direction WL_2n can be shared. Wiring WL_1 to WL_2n are per block. It may be divided into sections, or it may be shared between blocks arranged along a second direction. A group of memory cells that share WL_1 through wiring WL_2n is called a page. Lines BL and wiring SL can be shared between blocks arranged along the first direction. Cut.

[0046] Transistor Tr_S1 has its source terminal electrically connected to wiring SL, and its drain terminal is It is electrically connected to the first terminal of the memory cell string. Also, transistor Tr_S In configuration 2, the drain terminal is electrically connected to wiring BL, and the source terminal is connected to the memory cell string. It is electrically connected to the second terminal. In this way, conductivity and non-conductivity with the memory cell string are established. Since it is a transistor that selects the path, transistor Tr_S1 and transistor Tr _S2 can be called a selection transistor.

[0047] The following describes the data writing and reading operations to the semiconductor device shown in Figure 1. I will explain.

[0048] <Reset operation> When writing data to each memory cell, erase the data before the write operation. It is preferable to write "1" to the data. The operation of erasing data is also called a reset operation. The reset operation is performed block by block. For example, select the block whose data you want to erase. As shown in Figure 3(A), the erasure potential V is applied to the wiring BGL that is electrically connected to the conductor 132. E Apply (for example, 15V), and low potential (transistor) is applied to wiring WL_1 to wiring WL_2n. Apply a potential (e.g., 0V) such that transistors Tr_1 to Tr_2n become non-conductive. This can be done by making transistors Tr_S1 and Tr_S2 conduct. If the conductor 132 is not provided, the erasure potential V is set between wiring SL and wiring BL. E Mark A reset operation can also be performed by adding [something]. The reset operation causes transistor T The electrons stored in the charge storage layers 112b of each transistor from r_1 to Tr_2n It can be pulled out.

[0049] On the other hand, for blocks where data is not erased, the electrical relationship between the conductor 132 and wiring BGL Disconnect the connection and apply the erasure potential V to the conductor 132. E The solution is to prevent the application of the signal. Alternatively, see the diagram. As shown in 3(B), the wiring WL_1 to electrically connects to the block that does not erase data. The potential at which transistors Tr_1 through Tr_2n conduct to wiring WL_2n is such that they conduct. For example, the cancellation potential V E Applying this will allow electrons to be extracted from the charge storage layer 112b. You just need to avoid applying a potential difference that would cause this to happen.

[0050] Note that data in memory cells that are not rewritten will be reset before the block reset operation. It is preferable to store it in a separate area.

[0051] <Writing operation> Next, the operation of writing data to each memory cell will be explained using Figures 4, 5, and 6. I will reveal it.

[0052] The data writing operation can be performed page by page as described above. First, write the data. Apply a writing potential (e.g., 15V) to the Word line on the page, and do not write to the page. A positive potential (the potential at which the transistor conducts, for example, 3V) is applied to the word line of the zi. As shown in Figure 4, first a writing potential is applied to wiring WL_1, and then wiring WL_2 to A positive potential is applied to the wire WL_2n. Then, transistor T is electrically connected to the wiring SL. Set r_S1 to a non-conducting state, and transistor Tr_S2, which is electrically connected to wiring BL, to conduct. This is the state. By doing so, the memory cell of the page being written to will have the potential of wiring BL. It is given. Therefore, data corresponding to the potential of wiring BL is written to the memory cell. Specifically, if the potential of wiring BL is low (e.g., 0V), then applied to wiring WL_1. As the potential difference with the written potential increases, electrons are poured into the charge storage layer 112b. It is entered. Also, if the potential of wiring BL is positive, the write applied to wiring WL_1 As the potential difference with the potential decreases, electrons are not injected into the charge storage layer 112b. In other words, when a low potential is applied to the wiring BL, data "0" is written to the memory cell. In rare cases, if a positive potential is applied, the memory cell will remain at data "1".

[0053] Here, by applying a different potential to each memory cell string in the wiring BL, each page It is possible to write the following data. And, similar data can be written as shown in Figure 5. As shown in Figure 6, by also performing this on wiring WL_2 to wiring WL_2n, the block Alternatively, it can write data to the entire semiconductor device.

[0054] Furthermore, it is also possible to write data other than data"0" and data"1" to the memory cell. Yes, it is possible. For example, the potential of the wiring BL and the time the potential is applied can affect the charge storage layer 112 The amount of electrons injected into b should be controlled.

[0055] <Read operation> Next, Figures 7, 8, and 9 show the read operation of the data written to each memory cell. I will explain using this method.

[0056] Data retrieval can also be performed page by page. First, the page to be retrieved... Apply a low potential (e.g., 0V) to the word lines, and to the word lines of pages that are not to be read. A positive potential (the potential at which the transistor conducts, for example, 3V) is applied. This is shown in Figure 7. First, a low potential is applied to wiring WL_1, and then positive voltage is applied to wiring WL_2 through WL_2n. Apply a voltage. Then, connect the wiring SL to the transistor Tr_S1, and the wiring The transistor Tr_S2, which is electrically connected to wire BL, is made to conduct. Also, the wiring BL Apply a readout potential (e.g., 1V) and a lower potential (e.g., 0V) to the wiring SL. At this time, if the memory cell is data "1", current flows through the memory cell string, d If ata"0", no current flows through the memory cell string. Therefore, in this case By detecting the current value or the potential drop in the wiring BL, the data in the memory cell can be read. It can be released.

[0057] Here, by reading the data from each memory cell string to the wiring BL, the data is processed on a page-by-page basis. The data can be read. Similar data reading is shown in Figures 8 and 9. By doing the same for wiring WL_2 to wiring WL_2n, the block or semiconductor It is possible to read data from the entire device.

[0058] As described above, a semiconductor device according to one aspect of the present invention has memory cells arranged in three dimensions. This results in a high degree of integration. Therefore, semiconductor devices with a large memory capacity per projected area. This is the case. For example, a record of 1 Tbyte or more, 3 Tbytes or more, or 10 Tbytes or more. It is a semiconductor device with high capacitance. Furthermore, it can retain data for extended periods, making it non-volatile or It can also be called a semiconductor device that has a memory element that is essentially non-volatile.

[0059] A semiconductor device according to one aspect of the present invention is rewritable, has a large memory capacity, and data Because it can retain data for a long period of time, it is suitable for storage devices such as computers. For example, the main memory (or memory and memory) that stores data inside a computer. Also called a computer. ) or an external storage device (storage, secondary) that stores data outside of the computer. Also called a memory device. It can be used for things like external storage devices such as memory cards. Examples include SSDs (Solid State Drives).

[0060] <Modified examples of semiconductor devices> A semiconductor device according to one aspect of the present invention is not limited to the structure shown in Figure 1(A). For example, as shown in Figure 10, the insulator 106c is replaced with semiconductor 106b and insulator 106a The insulator 112a may be arranged in a shape along the insulator 130 via the insulator. 106c, semiconductor 106b, and insulator 106a are arranged in a shape along the insulator 130. It may also be placed as an insulator 112a, an insulator 106c, and a semiconductor. They may be arranged in a shape along the insulator 130 via 106b and insulator 106a. Furthermore, the conductors 116a and 116b shown in Figure 1(A) are not required.

[0061] Alternatively, as shown in Figure 11, transistors Tr_S1 and Tr_S2 A FIN-type transistor is also acceptable.

[0062] <Components of a semiconductor device> The following describes the components of a semiconductor device.

[0063] Insulator 120, insulator 122, insulator 124, insulator 126, insulator 128 and insulator Examples of 130 include boron, carbon, nitrogen, oxygen, fluorine, magnesium, and aluminum. Um, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium An insulator containing conium, lanthanum, neodymium, hafnium, or tantalum, in a single layer, Alternatively, they can be used in a laminated configuration. For example, aluminum oxide, magnesium oxide, silicon oxide. Silicon oxide nitride, silicon nitride, silicon nitride, gallium oxide, germanium oxide M, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafny oxide You may use tantalum or nitride. Note that silicon oxide nitride film has the following composition: This refers to a film with a higher oxygen content than nitrogen, and silicon nitride film, in terms of its composition, This refers to a membrane with a higher nitrogen content than oxygen content.

[0064] Furthermore, insulators 120, 122, 124, 126, 128 and The insulator 130 may have the function of separating adjacent elements or wiring, therefore, It is preferable to use an insulator with a low dielectric constant. For example, a relative permittivity of 5 or less, preferably 4 or less. Furthermore, preferably, an insulator of 3 or less is used. Specifically, silicon and oxygen are present. It is preferable to use an insulator that contains fluorine, or an insulator that also contains fluorine. 120, insulator 122, insulator 124, insulator 126, insulator 128 and insulator 130 One or more of these may be spaces.

[0065] Insulator 120, insulator 122, insulator 124, insulator 126, insulator 128 and insulator One or more of the 130s have the function of blocking impurities such as hydrogen and oxygen (allowing them to pass through). It is preferable to have an insulator that has (not). Transistor Tr_1 to Transistor Near Tr_2n, an insulator that has the function of blocking impurities such as hydrogen and oxygen is placed. By arranging them, the electrical characteristics of transistors Tr_1 to Tr_2n are It can be made stable.

[0066] For example, when transistors Tr_1 to Tr_2n are transistors using an oxide semiconductor, it is preferable that the adjacent insulator 130 or / and insulator 126 is an insulator having excess oxygen. The excess oxygen can be used to reduce the oxygen deficiency of the oxide semiconductor. Note that the excess oxygen refers to oxygen present in an insulator or the like and not bonded (free) to the insulator or the like, or oxygen having a low binding energy with the insulator or the like. When transistors Tr_1 to Tr_2n are transistors using an oxide semiconductor, it is preferable that the adjacent insulator 130 or / and insulator 126 is an insulator having excess oxygen. The excess oxygen can be used to reduce the oxygen deficiency of the oxide semiconductor. Note that the excess oxygen refers to oxygen present in an insulator or the like and not bonded (free) to the insulator or the like, or oxygen having a low binding energy with the insulator or the like. The excess oxygen can be used to reduce the oxygen deficiency of the oxide semiconductor. Note that the excess oxygen refers to oxygen present in an insulator or the like and not bonded (free) to the insulator or the like, or oxygen having a low binding energy with the insulator or the like. Note that the excess oxygen refers to oxygen present in an insulator or the like and not bonded (free) to the insulator or the like, or oxygen having a low binding energy with the insulator or the like. .

[0067] The insulator having excess oxygen may release 1 × 10 atoms / cm 18 atom s / cm 3 or more, 1 × 10 19 atoms / cm 3 or more, or 1 × 10 20 atoms / cm 3 or more of oxygen (in terms of the number of oxygen atoms) at a surface temperature in the range of 100 ° C or higher

[0068] The method for measuring the amount of oxygen released using TDS analysis will be described below.

[0069] When the measurement sample is subjected to TDS analysis, the total amount of gas released is proportional to the integral value of the ionic strength of the released gas. And by comparing with a standard sample, the total amount of gas released can be calculated. And by comparing with a standard sample, the total amount of gas released can be calculated.

[0070] For example, from the TDS analysis results of a silicon substrate containing hydrogen of a predetermined density as a standard sample, and the TDS analysis results of the measurement sample, the amount of oxygen molecules released from the measurement sample (N ) can be obtained by the following formula O2 . Here, the gas detected with a mass charge ratio of 32 obtained by TDS analysis can be obtained by the following formula. Here, the gas detected with a mass charge ratio of 32 obtained by TDS analysis Assume that all of these originate from oxygen molecules. The mass-to-charge ratio of CH3OH is 32, but the existence of We will not consider this here as it has a low probability. Also, the isotope of the oxygen atom with mass number 17 Regarding oxygen atoms and oxygen molecules containing oxygen atoms with a mass number of 18, the abundance in nature The rate is so small that it will not be considered.

[0071] N O2 =N H2 / S H2 ×S O2 ×α

[0072] N H2 This value represents the density of hydrogen molecules detached from the standard sample. H2 The standard test This is the integral value of the ionic intensity when the material is analyzed by TDS. Here, the reference value of the standard sample is N H2 / S H2 Let's assume that. S O2 This is the integral value of the ionic intensity when the sample is subjected to TDS analysis. Yes, it exists. α is a coefficient that affects the ionic strength in TDS analysis. For details of the formula shown above, see below. For further information, please refer to Japanese Patent Publication No. 6-275697. The amount of oxygen released is determined by the Electronics Science Using the EMD-WA1000S / W temperature-controlled desorption analyzer manufactured by Gaku Co., Ltd., one standard sample was used. The measurement is performed using a silicon substrate containing a quantitative amount of hydrogen atoms.

[0073] Furthermore, in TDS analysis, some oxygen is detected as oxygen atoms. Oxygen molecules and oxygen atoms The ratio of these can be calculated from the ionization rate of oxygen molecules. Note that α above represents the oxygen component. Because it includes the ionization rate of the oxygen atom, by evaluating the amount of oxygen molecule released, the amount of oxygen atom released can be determined. Even if they are present, it can still be estimated.

[0074] Note N O2This is the amount of oxygen molecules released. The amount released when converted to oxygen atoms is the amount of oxygen molecules. This will be twice the amount released.

[0075] Alternatively, insulators that release oxygen through heat treatment may contain peroxide radicals. Specifically, the spin density caused by peroxide radicals is 5 × 10⁻⁶ 17 spins / cm 3 The above is what is meant. Furthermore, insulators containing peroxide radicals are analyzed by electron spin resonance (ES). In R: Electron Spin Resonance, the g value is near 2.01. They may also have symmetrical signals.

[0076] Here, transistors Tr_S1 and Tr_S2 are made of single-crystal silicon or In the case of transistors using silicon such as polycrystalline silicon, excess oxygen affects the electrical properties. This can be a factor that causes degradation. Therefore, transistor Tr_S1 and transistor To prevent excess oxygen from entering the star Tr_S2, the insulator 122 is an insulator with low oxygen permeability. It is preferable that it has a body.

[0077] On the other hand, hydrogen can be used to terminate dangling bonds in silicon. As a result, the electrical characteristics of transistors Tr_S1 and Tr_S2 are improved. This is possible. However, hydrogen is present in transistors Tr_1 to Tr_2n. Because it can be a factor that degrades electrical properties, the insulator 122 is an insulator with low hydrogen permeability. It is preferable that it has a body.

[0078] Hydrogen has a small atomic radius, so it diffuses easily through insulators (it has a high diffusion coefficient). For example... In other words, a low-density insulator has high hydrogen permeability. The permeability decreases. A low-density insulator does not need to have a low density throughout the entire insulator, but only partially. This includes cases where the density is low. This is because the low-density region becomes the pathway for hydrogen. The density at which it can permeate is not uniquely determined, but it is typically 2.6 g / cm³. 3 Examples include less than Examples of low-density insulators include silicon oxide and silicon oxide nitride. Inorganic insulators, as well as polyester, polyolefin, polyamide (nylon, aramid Examples include organic insulators such as polyimide, polycarbonate, and acrylic. Examples of high-density insulators include magnesium oxide, aluminum oxide, and germanium oxide. Nium, gallium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neophosphate oxide Examples include zinc, hafnium oxide, and tantalum oxide. Note that low-density insulators and dense materials are also included. High-grade insulators are not limited to the insulators mentioned above. For example, if these insulators contain boron, It contains one or more elements selected from nitrogen, fluorine, neon, phosphorus, chlorine, or argon. It's fine if you do that.

[0079] Furthermore, insulators with grain boundaries may have high hydrogen permeability. In other words, grain Insulators that do not have boundaries (or have few grain boundaries) are less permeable to hydrogen. For example, non-grain boundaries Crystalline insulators (such as amorphous insulators) have lower hydrogen permeability compared to polycrystalline insulators.

[0080] Furthermore, insulators with high bonding energy to hydrogen may have low hydrogen permeability. For example, An insulator that combines with hydrogen to form hydrogen compounds, during the manufacturing process of the device or during the operation of the device, If a material has a bond energy that does not allow hydrogen to be removed at a certain degree, it can be said to be an insulator with low hydrogen permeability. For example, 200°C to 1000°C, 300°C to 1000°C, or 400°C Insulators that form hydrogen compounds between 100°C and 1000°C may have low hydrogen permeability. For example, the hydrogen desorption temperature is between 200°C and 1000°C, or between 300°C and 1000°C. Insulators that produce hydrogen compounds below, or between 400°C and 1000°C, have hydrogen permeability. It can be low. On the other hand, the hydrogen desorption temperature is between 20°C and 400°C, and between 20°C and 300°C. Insulators that produce hydrogen compounds at temperatures below ℃, or between 20℃ and 200℃, have hydrogen permeability. The levels can be high. Also, hydrogen that easily escapes, and the liberated hydrogen, are sometimes referred to as excess hydrogen. There is.

[0081] For example, the charge storage layer 112b can be boron, carbon, nitrogen, oxygen, fluorine, magnesium Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yt Insulators containing lium, zirconium, lanthanum, neodymium, hafnium, or tantalum It can be used in a single layer or in a laminated form. For example, aluminum oxide, magnesium oxide, Silicon oxide, silicon oxide nitride, silicon nitride, silicon nitride, gallium oxide, acid Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, Hafnium oxide or tantalum oxide can be used.

[0082] Examples of insulators 112a and 112c include boron, carbon, nitrogen, oxygen, and f Electrolyte, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, gel Manium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum An insulator containing aluminum oxide can be used in a single layer or in a multilayer structure. For example, aluminum oxide, acid Magnesium oxide, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide Neodymium oxide, hafnium oxide, or tantalum oxide may be used.

[0083] The charge storage layer 112b is positioned between the insulators 112a and 112c. The charge accumulation layer 112b only needs to have a function for accumulating electrons. For example, it may have an electron trap. Insulators such as [unclear] are preferred. Electron traps are designed to prevent the addition of impurities or damage. It can be formed by the interface between the charge storage layer 112b and the insulator 112a. Alternatively, an electron trap may be present at the interface between the charge storage layer 112b and the insulator 112c. In this case, the charge storage layer 112b and the insulator 112a and the charge storage layer 112b and the insulator 112 c is preferably a dissimilar junction. In the case of an electron trap, it may not be necessary to provide an insulator 112c. If there is an electron trap at the interface between the storage layer 112b and the insulator 112c, the insulator 112a In some cases, it may not be necessary to provide it. Note that the charge storage layer 112b is between adjacent memory cells. Because it is shared, it is preferable that electron movement within the charge storage layer 112b is less likely to occur. However, if the adjacent memory cell and the charge storage layer 112b are separated, the charge storage layer Electron movement may occur within 112b. That is, if the charge storage layer 112b is a semiconductor or conductive It may also be an electronic body.

[0084] In order to inject electrons into the charge storage layer 112b, the insulators 112a and 112c are provided. The thickness must be such that electron tunneling occurs due to the gate voltage or back gate voltage. This is preferable. However, it is preferable to suppress the outflow of electrons while the memory cell is holding data. Therefore, electron tunneling when no gate voltage or back gate voltage is applied. It is preferable that the thickness does not cause tunneling. However, it is preferable that electron tunneling is completely eliminated. Because this is difficult, the thickness is such that electron tunneling does not occur to the extent that the data can be retained. For example, the thickness of insulator 112a and insulator 112c should be 3 nm or more. The wavelength should be 5 nm or less, preferably between 4 nm and 10 nm. Furthermore, electron outflow should be suppressed. Therefore, it is preferable to use an insulator with a large energy gap. For example, an insulating The energy gap between body 112a and insulator 112c is between 6 eV and 10 eV, which is preferable. Ideally, it should be between 7eV and 10eV, and more preferably between 8eV and 10eV. stomach.

[0085] Specifically, the charge storage layer 112b is silicon nitride with a high defect level density, or silicon nitride oxide. Silicon or hafnium oxide is preferred. Also, insulator 112a and insulator 112 For c, silicon oxide or silicon oxide nitride is preferred.

[0086] Conductor 154, Conductor 140, Conductor 142, Conductor 144, Conductor 146, Conductor 14 8, Conductor 104, Conductor 116a, Conductor 116b, Conductor 132, Conductor 134, Conductor Examples of the electrolytic element 136 and the conductor 138 include boron, nitrogen, oxygen, fluorine, and silica. N, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, Gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, s A conductor containing one or more of the following: oz, tantalum, and tungsten, used in a single layer or in a multilayer structure. For example, it may be an alloy or compound, such as a conductor containing aluminum, copper and tungsten. Conductors containing tan, conductors containing copper and manganese, indium, tin and oxygen Conductors, titanium, and nitrogen-containing conductors may also be used.

[0087] The insulator 106a, semiconductor 106b, and insulator 106c will be described below.

[0088] By arranging insulators 106a and 106c above and below semiconductor 106b, In some cases, it may be possible to improve the electrical properties of the zista.

[0089] The insulator 106a preferably has CAAC-OS. The semiconductor 106b is CAAC- It is preferable that the OS is present. It is preferable that the insulator 106c has CAAC-OS. .

[0090] Semiconductor 106b is, for example, an indium-containing oxide. Semiconductor 106b is, for example When indium is included, the carrier mobility (electron mobility) increases. Also, semiconductor 106 b preferably contains element M. Element M is preferably aluminum, gallium, or y. This may include thorium or tin. Other elements that can be applied to element M include boron. Silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum These include cerium, neodymium, hafnium, tantalum, and tungsten. However, elements In some cases, element M can be a combination of multiple elements as mentioned above. Element M can be, for example, acid It is an element with a high binding energy with a constituent element. For example, it is an element with a higher binding energy with oxygen than indium. Alternatively, the element M is, for example, an element having a function of increasing the energy gap of an oxide. Further, it is preferable that the semiconductor 106b contains zinc. The oxide may be more likely to crystallize when it contains zinc.

[0091] However, the semiconductor 106b is not limited to an indium-containing oxide. The semiconductor 106b may be, for example, an oxide that does not contain indium and contains zinc, such as zinc tin oxide or gallium tin oxide, an oxide that contains gallium, an oxide that contains tin, etc.

[0092] For the semiconductor 106b, for example, an oxide having a large energy gap is used. The energy gap of the semiconductor 106 b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 [[ID=二十一]] eV or more and 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less.

[0093] For example, the insulator 106a and the insulator 106c are oxides composed of one or more, or two or more, elements other than oxygen that constitute the semiconductor 106b. Since the insulator 106a and the insulator 106c are composed of one or more, or two or more, elements other than oxygen that constitute the semiconductor 106b, it is difficult to form defect levels at the interface between the insulator 106a and the semiconductor 106b and at the interface between the semiconductor 106b and the insulator 106c.

[0094] It is preferable that the insulator 106a, the semiconductor 106b, and the insulator 106c contain at least indium. When the insulator 106a is an In-M-Zn oxide, the sum of In and M When set to 100 atomic%, preferably In is less than 50 atomic and M is 50 Higher than atomic%, and more preferably less than 25 atomic% of In and 75% of M. It is assumed to be higher than tomic%. Also, when semiconductor 106b is In-M-Zn oxide, When the sum of n and M is taken as 100 atomic%, preferably In is 25 atomic. Higher than %, M is less than 75 atomic%, and more preferably In is 34 atomic% The ratio should be higher, and M should be less than 66 atomic%. Also, the insulator 106c should be In-M-Zn. When it is an oxide, if the sum of In and M is 100 atomic%, preferably In is Less than 50 atomic%, M is higher than 50 atomic%, and more preferably In is 2 Less than 5 atomic%, M should be higher than 75 atomic%. Note that insulator 106c You may use an oxide of the same type as insulator 106a. However, insulator 106a or / And the insulator 106c may not need to contain indium. For example, the insulator 106a and / or insulator 106c may be gallium oxide. The number of atoms of each element contained in material 106a, semiconductor 106b, and insulator 106c is simple It doesn't have to be an integer ratio.

[0095] Semiconductor 106b has a greater electron affinity than insulators 106a and 106c. Materials are used. For example, as semiconductor 106b, from insulator 106a and insulator 106c The electron affinity is 0.07 eV to 1.3 eV, preferably 0.1 eV to 0.7 eV. Furthermore, it is more preferable to use an oxide with a voltage of 0.15 eV or more and 0.4 eV or less. Electron affinity is the energy difference between the vacuum level and the lower end of the conduction band.

[0096] Furthermore, indium gallium oxide has low electron affinity and high oxygen blocking properties. Therefore, it is preferable that the insulator 106c contains indium gallium oxide. The ratio of particles [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more, and further Preferably, it should be 90% or more.

[0097] When a gate voltage is applied at this time, the insulator 106a, semiconductor 106b, and insulator 106c Of these, a channel is formed in semiconductor 106b, which has a high electron affinity.

[0098] Here, between the insulator 106a and the semiconductor 106b, It may have a mixed region with . Also, between semiconductor 106b and insulator 106c, It may have a mixed region of semiconductor 106b and insulator 106c. The mixed region is a defect zone. The density of the insulator 106a, semiconductor 106b, and insulator 106c becomes lower. In a laminate, the energy changes continuously near each interface (also known as continuous bonding). This is the band diagram (see Figure 12). Note that the insulator 106a and semiconductor 106b are approximately In some cases, the interfaces between the insulator 106c may not be clearly distinguishable.

[0099] At this time, the electrons are not in the insulator 106a and insulator 106c, but in semiconductor 106b. It primarily moves within the structure. Note that insulators 106a and 106c existed independently. In some cases, it can take on the properties of a conductor, semiconductor, or insulator, but when a transistor is in operation... In this region, there is a region that does not form a channel. Specifically, the insulator 106a and semiconductor 1 Channels are formed only near the interfaces with 06b and near the interface between the insulator 106c and the semiconductor 106b, and no channels are formed in other regions. Therefore, since it can be called an insulator in terms of the operation of the transistor, in this specification, it is denoted as an insulator rather than a semiconductor or a conductor. However, the insulator 106a, the semiconductor 106b, and the insulator 106c are only distinguishable as a semiconductor and an insulator due to the difference in relative physical properties. For example, an insulator that can be used as the insulator 106a or the insulator 106c may be used as the semiconductor 106b. As described above, by reducing the density of defect levels at the interface between the insulator 106a and the semiconductor 106b and the density of defect levels at the interface between the semiconductor 106b and the insulator 106c, the movement of electrons in the semiconductor 106b is less inhibited, and the on-current of the transistor can be increased. Also, the on-current of the transistor can be increased as the factors inhibiting the movement of electrons are reduced. For example, when there are no factors inhibiting the movement of electrons, it is presumed that electrons move efficiently. The movement of electrons is inhibited, for example, when the physical unevenness of the channel formation region is large. To increase the on-current of the transistor, for example, the root mean square (RMS) roughness in the range of 1 μm × 1 μm on the upper or lower surface (the surface to be formed, here the upper surface of the insulator 106a) of the semiconductor 106b is less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. However, the insulator 106a, the semiconductor 106b, and the insulator 106c are only distinguishable as a semiconductor and an insulator due to the difference in relative physical properties. For example, an insulator that can be used as the insulator 106a or the insulator 106c may be used as the semiconductor 106b. As described above, by reducing the density of defect levels at the interface between the insulator 106a and the semiconductor 106b and the density of defect levels at the interface between the semiconductor 106b and the insulator 106c, the movement of electrons in the semiconductor 106b is less inhibited, and the on-current of the transistor can be increased. For example, an insulator that can be used as the insulator 106a or the insulator 106c may be used as the semiconductor 106b. As described above, by reducing the density of defect levels at the interface between the insulator 106a and the semiconductor 106b and the density of defect levels at the interface between the semiconductor 106b and the insulator 106c, the movement of electrons in the semiconductor 106b is less inhibited, and the on-current of the transistor can be increased. As described above, by reducing the density of defect levels at the interface between the insulator 106a and the semiconductor 106b and the density of defect levels at the interface between the semiconductor 106b and the insulator 106c, the movement of electrons in the semiconductor 106b is less inhibited, and the on-current of the transistor can be increased. Also, the on-current of the transistor can be increased as the factors inhibiting the movement of electrons are reduced. For example, when there are no factors inhibiting the movement of electrons, it is presumed that electrons move efficiently. The movement of electrons is inhibited, for example, when the physical unevenness of the channel formation region is large. To increase the on-current of the transistor, for example, the root mean square (RMS) roughness in the range of 1 μm × 1 μm on the upper or lower surface (the surface to be formed, here the upper surface of the insulator 106a) of the semiconductor 106b is less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm.

[0100] Also, the on-current of the transistor can be increased as the factors inhibiting the movement of electrons are reduced. For example, when there are no factors inhibiting the movement of electrons, it is presumed that electrons move efficiently. The movement of electrons is inhibited, for example, when the physical unevenness of the channel formation region is large. For example, when there are no factors inhibiting the movement of electrons, it is presumed that electrons move efficiently. The movement of electrons is inhibited, for example, when the physical unevenness of the channel formation region is large. The movement of electrons is inhibited, for example, when the physical unevenness of the channel formation region is large. Also, the on-current of the transistor can be increased as the factors inhibiting the movement of electrons are reduced. For example, when there are no factors inhibiting the movement of electrons, it is presumed that electrons move efficiently. The movement of electrons is inhibited, for example, when the physical unevenness of the channel formation region is large.

[0101] To increase the on-current of the transistor, for example, the root mean square (RMS) roughness in the range of 1 μm × 1 μm on the upper or lower surface (the surface to be formed, here the upper surface of the insulator 106a) of the semiconductor 106b is less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. This is sufficient. Also, the average surface roughness (also called Ra) in a 1 μm × 1 μm area is 1 n Less than m, preferably less than 0.6 nm, more preferably less than 0.5 nm, more It should be less than 0.4 nm. Also, the maximum height difference (PV) in a 1 μm × 1 μm area. Also called.) is less than 10 nm, preferably less than 9 nm, and more preferably less than 8 nm. Preferably, it should be less than 7 nm. RMS roughness, Ra and PV are SII Using the Nanotechnology Co., Ltd. scanning probe microscope system SPA-500, etc. It can be measured.

[0102] Furthermore, in order to increase the on-current of the transistor, the thickness of the insulator 106c should be small. It is preferable to have a size of less than 10 nm, preferably 5 nm or less, and even more preferably 3 nm or less. The insulator 106c having the lower region is suitable. On the other hand, the insulator 106c has the shape of a channel. The semiconductor 106b is then treated with elements other than oxygen that constitute the adjacent insulator (hydrogen, silicon). It has a function to block the entry of (etc.). Therefore, the insulator 106c is It is preferable that it has a thickness of a certain degree. For example, 0.3 nm or more, preferably 1 nm or more. More preferably, the insulator 106c has a region with a thickness of 2 nm or more. Insulator 106c suppresses the outward diffusion of oxygen released from other insulators, It is preferable that it has the property of blocking.

[0103] Furthermore, in order to increase reliability, the insulator 106a should be thick and the insulator 106c should be thin. Preferred. For example, 10 nm or more, preferably 20 nm or more, and more preferably 40 nm. More preferably, the insulator 106a has a region with a thickness of 60 nm or more. By increasing the thickness of the insulator 106a, the interface between adjacent insulators and insulator 106a The distance to the semiconductor 106b where the channel is formed can be increased. However, the semiconductor The productivity of the device may decrease, for example, 200 nm or less, preferably 120 nm. The insulator 106a has a thickness of m or less, and more preferably 80 nm or less. stomach.

[0104] For example, between semiconductor 106b and insulator 106a, for example, secondary ion mass spectrometry (S In IMS (Secondary Ion Mass Spectrometry) , 1 x 10 16 atoms / cm 3 The above 1 x 10 19 atoms / cm 3 The following is preferable is 1 x 10 16 atoms / cm 3 The above 5 x 10 18 atoms / cm 3 Below, further good Mashiku is 1 x 10 16 atoms / cm 3 The above 2 x 10 18 atoms / cm 3 The following It has a region where the concentration of SI is present. In MS, 1 × 10 16 atoms / cm 3 The above 1 x 10 19 atoms / cm 3 Below Below, preferably 1 × 10 16 atoms / cm 3 The above 5 x 10 18 atoms / cm 3 Below Below, more preferably 1 × 10 16 atoms / cm 3 The above 2 x 10 18 ate / c m 3 It has a region with the following silicon concentrations.

[0105] Furthermore, semiconductor 106b is 1 × 10 in SIMS. 16 atoms / cm 3 The above 2× 10 20 atoms / cm 3 The following is preferably 1 × 10 16 atoms / cm 3 The above 5x 10 19 atoms / cm 3 More preferably 1 × 10 16 atoms / cm 3 That's all. 1 x 10 19 atoms / cm 3 More preferably 1 × 10 16 atoms / cm 3 The above 5 x 10 18 atoms / cm 3 It has a region with the following hydrogen concentrations. In order to reduce the hydrogen concentration of body 106b, the hydrogen concentration of insulators 106a and 106c It is preferable to reduce the degree. Insulators 106a and 106c are, in SIMS, 1 x 10 16 atoms / cm 3 The above 2 x 10 20 atoms / cm 3 The following, preferably 1 x 10 16 atoms / cm 3 The above 5 x 10 19 atoms / cm 3 The following are more preferable ku is 1 x 10 16 atoms / cm 3 The above 1 x 10 19 atoms / cm 3 Below, further Preferably 1 × 10 16 atoms / cm 3 The above 5 x 10 18atoms / cm 3 has a region with the following hydrogen concentration. Also, in SIMS, semiconductor 106b has a hydrogen concentration of 1×10 1 5 atoms / cm 3 or more and 5×10 19 atoms / cm 3 or less, preferably 1×10 1 5 atoms / cm 3 or more and 5×10 18 atoms / cm 3 or less, more preferably 1×1 0 15 atoms / cm 3 or more and 1×10 18 atoms / cm 3 or less, even more preferably 1×10 15 atoms / cm 3 or more and 5×10 17 atoms / cm 3 or less nitrogen concentration and has a region with such nitrogen concentration. Also, in order to reduce the nitrogen concentration of semiconductor 106b, it is preferable to reduce the nitrogen concentration of insulator 106a and insulator 106c. The nitrogen concentration of insulator 106a and insulator 1 06c is 1×10 15 atoms / cm 3 or more and 5×10 19 ato ms / cm 3 or less, preferably 1×10 15 atoms / cm 3 or more and 5×10 18 ato ms / cm 3 or less, more preferably 1×10 15 atoms / cm 3 or more and 1×10 18 a toms / cm 3 or less, even more preferably 1×10 15 atoms / cm 3 or more and 5×10 17 atoms / cm 3 It has a region with the following nitrogen concentrations.

[0106] The three-layer structure described above is just one example. For example, a two-layer structure without insulator 106a or insulator 106c. The structure is also acceptable. Alternatively, it can be above or below insulator 106a, or insulator 106c. Examples of insulator 106a, semiconductor 106b, and insulator 106c are shown above or below. It may also be a four-layer structure having one of the semiconductors. Alternatively, on top of the insulator 106a, At two or more locations below insulator 106a, above insulator 106c, or below insulator 106c any of the semiconductors exemplified as insulator 106a, semiconductor 106b, and insulator 106c. It may also be an n-layer structure (where n is an integer greater than or equal to 5) with one layer.

[0107] <Composition> The composition of In-M-Zn oxide is described below. Note that element M is aluminum. Examples include tincture, gallium, yttrium, or tin. Other elements applicable to element M. Examples include boron, silicon, titanium, iron, nickel, germanium, zirconium, and Ribdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, etc. be.

[0108] Figure 13 is a triangular diagram with In, M, or Zn placed at each vertex. Also, [In] in the figure [ ] indicates the atomic concentration of In, [M] indicates the atomic concentration of element M, and [Zn] indicates the atomic concentration of Zn. This indicates.

[0109] In-M-Zn oxide crystals are known to have a homologous structure, and InMO3 (ZnO) m It is shown as (where m is a natural number). Furthermore, it is possible to substitute In for M. Therefore, In 1+α M 1-α O3(ZnO) m This can also be shown as (-1≦α≦1). This is [In]:[M]:[Zn]=1+α:1-α:1,[In]:[M]:[Zn ]=1+α:1-α:2, [In]:[M]:[Zn]=1+α:1-α:3, [In] :[M]:[Zn]=1+α:1-α:4, and [In]:[M]:[Zn]=1+α The composition is shown by the dashed line denoted as :1-α:5. Note that the thick lines on the dashed line represent, for example, the original This composition can form a solid solution when the oxides used as materials are mixed and fired at 1350°C.

[0110] Therefore, by bringing the composition closer to that of a solid solution as described above, the crystallinity can be increased. Furthermore, when depositing In-M-Zn oxide by sputtering, the target The composition and the composition of the film may differ. For example, the atomic ratio of the target may be "1:1: 1", 1:1:1.2", 3:1:2", 4:2:4.1", 1:3:2", When using In-M-Zn oxides in a 1:3:4 or 1:4:5 ratio, the atomic ratio of the film is These are "1:1:0.7 (approximately 0.5 to 0.9)" and "1:1:0.9 (approximately 0.8 to 1 0.1 (approx.), 3:1:1.5 (approx. 1 to 1.8), 4:2:3 (2.6 to 3 Approximately 0.6), 1:3:1.5 (approximately 1 to 1.8), 1:3:3 (approximately 2.5 to 3 The ratios are approximately 0.5, 1:4:4 (approximately 3.4 to 4.4). Therefore, the desired pair To obtain the desired film, the target composition should be selected while considering the changes in composition.

[0111] <Oxide semiconductor structure> The structure of oxide semiconductors will be described below.

[0112] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (c-axis-aligned (crystalline oxide semiconductor), polycrystalline oxide Semiconductors, nc-OS (nanocrystalline oxide semiconductor) uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-l Examples include oxide semiconductors and amorphous oxide semiconductors. ru.

[0113] From another perspective, oxide semiconductors include amorphous oxide semiconductors and other crystalline oxide semiconductors. It can be divided into conductors and crystalline oxide semiconductors. As for crystalline oxide semiconductors, there are single-crystal oxide semiconductors, CAAC- Examples include OS, polycrystalline oxide semiconductors, and nc-OS.

[0114] Amorphous structures are generally isotropic and lack heterogeneous structures, representing a metastable state of atomic arrangement. It is not fixed, the bonding angle is flexible, and it has short-range order but not long-range order. It is said that...

[0115] In other words, a stable oxide semiconductor is completely amorphous. ) It cannot be called an oxide semiconductor. Also, it is not isotropic (for example, periodic structure in a minute region). Oxide semiconductors (which have a structure) cannot be called perfectly amorphous oxide semiconductors. On the other hand, a-li ke OS is an unstable structure that is not isotropic but contains voids (also called porous structures). In terms of instability, a-like OSs are physically similar to amorphous oxide semiconductors. .

[0116] <caac-os> First, let me explain CAAC-OS.

[0117] CAAC-OS is an oxide semiconductor having multiple c-axis oriented crystalline portions (also called pellets). It is a type of conductor.

[0118] CAAC-OS can be analyzed by X-ray diffraction (XRD). Let's explain the case of analysis. For example, InGaZnO4, which is classified as space group R-3m Structural analysis of crystalline CAAC-OS is performed using the out-of-plane method. As shown in Figure 14(A), a peak appears near a diffraction angle (2θ) of 31°. Since the 'k' is attributed to the (009) plane of the InGaZnO4 crystal, CAAC-OS The crystal has c-axis orientation, and the c-axis is the surface that forms the CAAC-OS film (also called the surface to be formed). It can be confirmed that it is facing in a direction approximately perpendicular to the top surface. Note that 2θ is 31° In addition to the nearby peak, a peak may also appear when 2θ is near 36°. The adjacent peak is due to a crystal structure classified as space group Fd-3m. Therefore, CAAC -OS preferably does not show the peak.

[0119] On the other hand, in CAAC-OS, X-rays are incident from a direction parallel to the surface being formed. Structural analysis using the ne method reveals a peak near 2θ = 56°. This peak corresponds to I It is attributed to the (110) plane of the nGaZnO4 crystal. Then, 2θ is fixed near 56°. The analysis (φ-scan) is performed while rotating the sample around the normal vector of the sample surface as the axis (φ-axis). Even when this is done, no clear peak appears, as shown in Figure 14(B). On the other hand, single crystal InGaZ When φ scanning is performed on nO4 with 2θ fixed near 56°, the result is shown in Figure 14(C). Six peaks are observed that belong to a crystal plane equivalent to the (110) plane. Therefore, X Structural analysis using RD revealed that CAAC-OS has irregular orientations in its a-axis and b-axis. This can be confirmed.

[0120] Next, we will explain CAAC-OS analyzed by electron diffraction. For example, InGaZ For CAAC-OS having nO4 crystals, a probe is applied parallel to the surface of the CAAC-OS being formed. When an electron beam with a diameter of 300 nm is incident, a diffraction pattern like the one shown in Figure 14(D) (control) is observed. This is also called a limited-field electron diffraction pattern. A diffraction pattern may appear. This diffraction pattern includes In The spot contains a location originating from the (009) plane of the GaZnO4 crystal. Therefore, the electron rotation Depending on the circumstances, the pellets contained in CAAC-OS may have c-axis orientation, and the c-axis may be the surface to be formed. Alternatively, it can be seen that it is oriented in a direction approximately perpendicular to the upper surface. On the other hand, for the same sample, on the sample surface Figure 14(E) shows the diffraction pattern when an electron beam with a probe diameter of 300 nm is incident perpendicularly. As shown in Figure 14(E), a ring-shaped diffraction pattern can be observed. Therefore, Electron diffraction using an electron beam with a diameter of 300 nm also revealed the presence of peridotites in CAAC-OS. It can be seen that the a-axis and b-axis of the net do not have orientation. Note that in Figure 14(E) The ring is caused by the (010) and (100) planes of the InGaZnO4 crystal, among other things. It is thought that the second ring in Figure 14(E) is caused by the (110) plane, etc. It's possible.

[0121] Furthermore, a transmission electron microscope (TEM) A composite image of the bright-field image and diffraction pattern of CAAC-OS obtained by (croscope) analysis. When observing a high-resolution TEM image (also known as a TEM image), multiple pellets can be identified. On the other hand, even in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries, are not visible. Also called "Nandaly." ) There are cases where it is not possible to clearly confirm this. Therefore, CAAC -OS can be said to be less prone to the decrease in electron mobility caused by grain boundaries.

[0122] Figure 15(A) shows a high-resolution T of the cross-section of CAAC-OS observed from a direction approximately parallel to the sample surface. The EM image is shown. For observing high-resolution TEM images, spherical aberration correction is required. The aberration correction function was used. High-resolution analysis was performed using the spherical aberration correction function. High-resolution TEM images are specifically called Cs-corrected high-resolution TEM images. For example, using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by JEOL Ltd. This can be observed.

[0123] From Figure 15(A), we can see the pellet, which is a region in which metal atoms are arranged in layers. Yes, it is possible. It has been found that the size of a single pellet can be 1 nm or larger, or even 3 nm or larger. Therefore, pellets are called nanocrystals (nc). It is also possible to use CAAC-OS with CANC(C-Axis Aligned nan It can also be called an oxide semiconductor containing ocrystals. The pellet is CAAC -Reflects the unevenness of the surface or top surface of the OS, and the surface or top surface of the CAAC-OS It becomes parallel to the plane.

[0124] Furthermore, Figures 15(B) and 15(C) show CAAC observed from a direction approximately perpendicular to the sample surface. -Shows a Cs-corrected high-resolution TEM image of the OS plane. Figures 15(D) and 15(E) are shown. These are images obtained by image processing Figure 15(B) and Figure 15(C), respectively. The following describes the image processing. Let's explain the method. First, Figure 15(B) is converted to the Fast Fourier Transform (FFT). The FFT image is obtained by performing a Fourier Transform (FFT) process. Next, the acquisition In the resulting FFT image, with the origin as the reference point, 2.8 nm -1 from 5.0nm -1 Leave the range between Next, the masked FFT image is subjected to the inverse Fast Fourier Transform (IFFT: By processing the image (Inverse Fast Fourier Transform), The processed image is obtained. The image obtained in this way is called an FFT filtered image. The filtered image is an image obtained by extracting the periodic component from the Cs-corrected high-resolution TEM image, and is a grid image. This shows the array.

[0125] In Figure 15(D), areas with disordered grid arrangement are indicated by dashed lines. The area enclosed by the dashed lines is It is a single pellet. The dotted line indicates the connection point between the pellets. The dashed line indicates a hexagonal shape, showing that the pellet is hexagonal. The shape of the net is not always a regular hexagon; it is often a non-regular hexagon.

[0126] In Figure 15(E), a dotted line is drawn between a region with a aligned grid arrangement and another region with a aligned grid arrangement. As shown, even near the dotted line, a clear grain boundary cannot be confirmed. Connecting the surrounding grid points to a central grid point creates a distorted hexagon, or a pentagon and / or heptagon. Shapes and other features can be formed. That is, by distorting the lattice arrangement, the formation of grain boundaries can be suppressed. It can be seen that CAAC-OS has a dense atomic arrangement in the ab plane. Due to the absence of certain elements, or because the substitution of metal elements changes the bond distance between atoms, This is thought to be because it allows for distortion to be tolerated.

[0127] As described above, CAAC-OS has c-axis orientation and multiple properties in the ab-plane direction. A number of pellets (nanocrystals) are linked together, forming a distorted crystalline structure. Therefore, CA AC-OS, CAA crystal(c-axis-aligned ab-pl It can also be called an oxide semiconductor having an anchored crystal. ru.

[0128] CAAC-OS is a highly crystalline oxide semiconductor. The crystallinity of oxide semiconductors depends on the presence of impurities. CAAC-OS may decrease due to impurities and defects ( It can be described as an oxide semiconductor with few oxygen vacancies, etc.

[0129] Impurities are elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition metals. There are elements, for example. For instance, oxygen is more abundant than the metallic elements that make up oxide semiconductors such as silicon. Elements with strong bonding forces can alter the atomic arrangement of oxide semiconductors by removing oxygen from them. It disrupts the crystallinity and causes a decrease in its properties. Also, heavy metals such as iron and nickel, argon, and nickel... Because carbon oxides and other elements have a large atomic radius (or molecular radius), they affect the atomic arrangement of oxide semiconductors. This disrupts the crystallinity and reduces its properties.

[0130] When oxide semiconductors contain impurities or defects, their properties may change due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps, or carriers A can become a source of emissions. For example, oxygen vacancies in oxide semiconductors can trap carriers and In some cases, it may become a carrier source by capturing hydrogen.

[0131] CAAC-OS, with its low impurity and oxygen vacancies, is an oxide semiconductor with a low carrier density. Specifically, 8 x 10 11 pieces / cm 3 Less than 1 × 10 11 / cm 3 less than, More preferably 1 × 10 10 pieces / cm 3 It is less than 1 × 10 -9 pieces / cm 3 The above It can be made into an oxide semiconductor with a carrier density. Such an oxide semiconductor can be made into a high-purity intrinsic Alternatively, it is called a substantially high-purity intrinsic oxide semiconductor. CAAC-OS has a low impurity concentration. Furthermore, it has a low defect level density. In other words, it can be said to be an oxide semiconductor with stable properties.

[0132] <nc-os> Next, I will explain nc-OS.

[0133] This section describes the case of analyzing nc-OS using XRD. For example, for nc-OS When structural analysis is performed using the out-of-plane method, no peaks indicating orientation appear. In other words, nc-OS crystals do not have orientation.

[0134] Furthermore, for example, nc-OS having an InGaZnO4 crystal is thinned to a thickness of 34 nm. When an electron beam with a probe diameter of 50 nm is incident on the region parallel to the surface to be formed, Figure 16 A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in (A) was observed. Furthermore, the diffraction pattern when an electron beam with a probe diameter of 1 nm is incident on the same sample (na The beam electron diffraction pattern is shown in Figure 16(B). From Figure 16(B), a ring-shaped region is visible. Multiple spots are observed within. Therefore, nc-OS has a probe diameter of 50 nm. Order is not confirmed by irradiating with an electron beam, but when an electron beam with a probe diameter of 1 nm is irradiated... Order can be confirmed by having them shoot.

[0135] Furthermore, when an electron beam with a probe diameter of 1 nm is incident on a region with a thickness of less than 10 nm, As shown in Figure 16(C), an electron diffraction pattern was observed in which the spots were arranged in a roughly regular hexagonal shape. This may occur. Therefore, in the range of thickness less than 10 nm, nc-OS is ordered. It can be seen that there is a region with high fissure, i.e., a crystal. Furthermore, the crystals are oriented in various directions. Therefore, there are also regions where a regular electron diffraction pattern is not observed.

[0136] Figure 16(D) shows the Cs-corrected elevation of the cross-section of nc-OS observed from a direction approximately parallel to the surface being formed. High-resolution TEM images are shown. nc-OS refers to areas indicated by auxiliary lines in the high-resolution TEM image. As shown, there are regions where the crystalline structure can be observed and regions where the crystalline structure cannot be clearly observed. It has a region and a crystal portion contained in nc-OS, with a size of 1 nm to 10 nm. Yes, and they are often between 1 nm and 3 nm in size. Oxide semiconductors with a wavelength greater than 0 nm and less than or equal to 100 nm are called microcrystalline oxide semiconductors (micro It is sometimes called a crystalline oxide semiconductor. nc-OS may, for example, make it difficult to clearly identify grain boundaries in high-resolution TEM images. Yes. Furthermore, the nanocrystals may share the same origin as the pellets in CAAC-OS. Yes, it exists. Therefore, in the following, the crystalline portion of nc-OS may be referred to as a pellet.

[0137] Thus, nc-OS is suitable for minute regions (for example, regions between 1 nm and 10 nm, particularly The atomic arrangement has periodicity in the region between 1 nm and 3 nm. Furthermore, nc-OS is Furthermore, no regularity is observed in the crystal orientation between different pellets. Therefore, orientation is not observed throughout the entire film. Therefore, nc-OS can be analyzed using methods that produce a-like OS or amorphous OS. It can sometimes be indistinguishable from oxide semiconductors.

[0138] Furthermore, since there is no regularity in the crystal orientation between pellets (nanocrystals), nc-OS is used. Oxides containing RANC (Random Aligned nanocrystals) semiconductors, or containing NANC (Non-Aligned nanocrystals) It can also be called an oxide semiconductor.

[0139] nc-OS is an oxide semiconductor with higher orderliness than amorphous oxide semiconductors. Therefore, nc-OS has a lower defect level density than a-like OS and amorphous oxide semiconductors. However, nc-OS does not show any regularity in crystal orientation between different pellets. nc-OS has a higher defect level density compared to CAAC-OS.

[0140] <a-like OS> a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. It is a conductor.

[0141] Figure 17 shows a high-resolution cross-sectional TEM image of an a-like OS. Here, Figure 17(A) is This is a high-resolution cross-sectional TEM image of a-like OS at the start of electron irradiation. Figure 17(B) ) is 4.3 × 10 8 e - / nm 2 electrons (e - ) High a-like OS after irradiation These are high-resolution cross-sectional TEM images. From Figures 17(A) and 17(B), a-like OS It can be seen that, from the start of electron irradiation, striped bright regions extending in the vertical direction are observed. The bright regions show a change in shape after electron irradiation. Furthermore, the bright regions are either porous or low-density. It is presumed to be in the degree range.

[0142] Because it has porosity, a-like OS has an unstable structure. Below, a-like To demonstrate that the OS has a less stable structure compared to CAAC-OS and nc-OS. This shows the structural changes caused by electron irradiation.

[0143] As samples, prepare a-like OS, nc-OS, and CAAC-OS. The sample is also an In-Ga-Zn oxide.

[0144] First, high-resolution cross-sectional TEM images are obtained for each sample. All of them have a crystalline portion.

[0145] Furthermore, the unit cell of the InGaZnO4 crystal has three In-O layers, and Ga-Zn- It is known to have a structure in which a total of nine layers, including six O layers, are stacked in layers along the c-axis. The spacing between these adjacent layers is the same as the spacing between the grid planes of the (009) plane (also called the d value). It is approximately [value], and from crystal structure analysis, its value has been determined to be 0.29 nm. Therefore, Below, areas where the spacing of the grid stripes is between 0.28 nm and 0.30 nm are represented as InGaZn. This was considered to be the crystalline portion of O4. Note that the lattice fringes correspond to the ab-plane of the InGaZnO4 crystal. ru.

[0146] Figure 18 shows an example of investigating the average size of the crystalline regions (22 to 30 locations) in each sample. The length of the lattice fringes mentioned above is used to define the size of the crystal portion. Figure 18 shows a-like The crystalline portion of the OS grows larger in proportion to the cumulative amount of electrons irradiated during TEM image acquisition, etc. It can be seen that, as shown in Figure 18, the size is about 1.2 nm in the initial stages of TEM observation. The crystal region (also called the initial nucleus) is then transformed into an electron (e - The cumulative radiation dose was 4.2 × 10⁻⁶ 8 e - / nm 2 In this case, it can be seen that it has grown to a size of about 1.9 nm. On the other hand, nc -OS and CAAC-OS are defined as the cumulative electron dose from the start of electron irradiation being 4.2 × 10⁻⁶. 8 e - / nm 2 Within this range, it can be seen that there is no change in the size of the crystal portion. (Figure 18) Furthermore, regardless of the cumulative electron irradiation dose, the size of the crystal region in nc-OS and CAAC-OS is, It can be seen that they are approximately 1.3 nm and 1.8 nm, respectively. TEM observations were performed using a Hitachi transmission electron microscope H-9000NAR. Electron beam irradiation conditions The acceleration voltage is 300kV and the current density is 6.7 × 10⁻⁶. 5 e - / (nm 2 ·s), irradiation area The diameter was set to 230 nm.

[0147] Thus, in a-like OS, crystalline growth can sometimes be observed upon electron irradiation. On the other hand, nc-OS and CAAC-OS show almost no crystal growth due to electron irradiation. It cannot be seen. In other words, a-like OS is different from nc-OS and CAAC-OS. It is clear that the structure is unstable.

[0148] Furthermore, because it has porosity, a-like OS is superior to nc-OS and CAAC-OS. It has a low-density structure. Specifically, the density of a-like OS is the same as that of a single crystal of the same composition. The density is between 78.6% and 92.3%. Also, the density of nc-OS and CAAC - The density of OS is between 92.3% and 100% of the density of a single crystal of the same composition. Oxide semiconductors with a density of less than 78% are inherently difficult to deposit.

[0149] For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], The density of single-crystal InGaZnO4 with a faceted crystal structure is 6.357 g / cm³. 3 That's right. For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio] The density of a-like OS is 5.0 g / cm³. 3 More than 5.9g / cm 3 It is less than. For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], The density of nc-OS and CAAC-OS is 5.9 g / cm³. 3 More than 6.3g / cm 3 It is less than.

[0150] If single crystals with the same composition do not exist, single crystals with different compositions can be combined in any proportion. By doing so, the density equivalent to a single crystal at the desired composition can be estimated. The density corresponding to a single crystal of the desired composition is, with respect to the ratio of single crystals with different compositions combined, The density can be estimated using a weighted average. However, the density should be calculated using as few types of single crystals as possible. It is preferable to estimate by combining the costs.

[0151] As described above, oxide semiconductors can take on various structures, each possessing a variety of properties. Oxide semiconductors include, for example, amorphous oxide semiconductors, a-like OS, nc-OS, The multilayer film may have two or more types of CAAC-OS. [Explanation of Symbols]

[0152] 100 circuit boards 104 Conductors 106a Insulator 106b Semiconductor 106c insulator 112a Insulator 112b Charge storage layer 112c insulator 116a Conductor 116b Conductor 120 Insulator 122 Insulator 124 Insulator 126 Insulator 128 Insulator 130 Insulator 132 Conductors 134 Conductors 136 Conductors 138 Conductors 140 Conductors 142 Conductors 144 Conductors 146 Conductors 148 Conductors 154 Conductors 162 Insulator 166 Impurity region

Claims

[Claim 1] It has a substrate and multiple transistors, The channel formation regions of the aforementioned plurality of transistors are provided in the same oxide semiconductor. The plurality of transistors are arranged in a manner that is stacked perpendicular to the substrate. The oxide semiconductor is a semiconductor device having an oxide containing indium.

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