Multilayer ceramic capacitor

Abstract

The present invention provides a multilayer ceramic capacitor that can reduce the likelihood of delamination occurring between the internal electrode layer and the dielectric layer within the laminate during sintering. [Solution] The multilayer ceramic capacitor 100 comprises a laminate 101, the laminate 101 including a plurality of laminated dielectric layers 140 and a plurality of internal electrode layers 150, the laminate 101 having a first main surface 111 and a second main surface 112 facing each other in the lamination direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the lamination direction, and a first end surface 115 and a second end surface 116 facing each other in the length direction perpendicular to the lamination direction and the width direction, an external electrode electrically connected to at least one of the plurality of internal electrode layers 150 is arranged so as to cover at least a portion of the first end surface 115 and at least a portion of the second end surface 116, at least a portion of the plurality of internal electrode layers 150 has a plurality of grooves, and at least a portion of the plurality of dielectric layers 140 is embedded in the plurality of grooves.

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic capacitor.

Background Art

[0002] An example of a multilayer ceramic capacitor including a laminate formed by laminating a plurality of dielectric layers and a plurality of internal electrode layers is described in Japanese Patent Application Laid-Open No. 2021-40120 (Patent Document 1). In manufacturing this laminate, first, an internal electrode layer is printed on the surface of a ceramic green sheet to be a dielectric layer as needed. The ceramic green sheets after these processes are laminated to form a laminate. The laminate is sintered by heating it.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Since the internal electrode layer is formed of metal while the dielectric layer is formed of ceramic, their thermal shrinkage rates are different. When the laminate is sintered by heating, there is a problem that peeling occurs inside the laminate due to the difference in the degree of thermal shrinkage between the internal electrode layer and the dielectric layer.

[0005] Therefore, an object of the present invention is to provide a multilayer ceramic capacitor capable of making peeling that may occur between the internal electrode layer and the dielectric layer inside the laminate during sintering less likely to occur.

Means for Solving the Problems

[0006] To achieve the above objective, a multilayer ceramic capacitor according to the present invention comprises a laminate, the laminate includes a plurality of laminated dielectric layers and a plurality of internal electrode layers, the laminate has a first main surface and a second main surface facing each other in the lamination direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the lamination direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the lamination direction and the width direction, an external electrode electrically connected to at least one of the plurality of internal electrode layers is arranged so as to cover at least a portion of the first end surface and at least a portion of the second end surface, at least a portion of the plurality of internal electrode layers has a plurality of grooves, and at least a portion of the plurality of dielectric layers is embedded in the plurality of grooves. [Effects of the Invention]

[0007] According to the present invention, since at least a portion of the multiple dielectric layers are embedded in multiple grooves, the bonding between the dielectric layer and the internal electrode layer becomes strong, and as a result, delamination that may occur between the internal electrode layer and the dielectric layer within the laminate during sintering can be made less likely. [Brief explanation of the drawing]

[0008] [Figure 1] This is a perspective view of a multilayer ceramic capacitor according to Embodiment 1 of the present invention. [Figure 2] This is a perspective view of the element portion included in the multilayer ceramic capacitor according to Embodiment 1 of the present invention. [Figure 3] This is a cross-sectional view taken along the line III-III in Figure 1. [Figure 4] Figure 1 shows a cross-sectional view taken along the line IV-IV. [Figure 5] This is a plan view showing the degree of overlap between the internal electrode layer and the dielectric layer in a multilayer ceramic capacitor according to Embodiment 1 of the present invention. [Figure 6] Figure 5 shows a cross-sectional view taken along the line VI-VI. [Figure 7]This is a plan view showing the degree of overlap between the internal electrode layer and the dielectric layer, which is included in a modified example of the multilayer ceramic capacitor in Embodiment 1 of the present invention. [Figure 8] This is a cross-sectional view taken along the line VIII-VIII in Figure 7. [Modes for carrying out the invention]

[0009] The dimensional ratios shown in the drawings do not necessarily accurately reflect reality, and may be exaggerated for illustrative purposes. In the following explanation, the concepts of "up" or "down" do not necessarily refer to absolute up or down, but rather to relative up or down within the illustrated orientation.

[0010] (Embodiment 1) (composition) A multilayer ceramic capacitor in Embodiment 1 according to the present invention will be described with reference to Figures 1 to 6.

[0011] Figure 1 shows the external appearance of the multilayer ceramic capacitor 100 in this embodiment. Figure 2 shows the base body portion 110, which is part of the multilayer ceramic capacitor 100. Figure 3 shows a cross-sectional view taken along the line III-III in Figure 1. Figure 4 shows a cross-sectional view taken along the line IV-IV in Figure 1.

[0012] As shown in Figure 1, the multilayer ceramic capacitor 100 comprises a base body 110 and external electrodes. The multilayer ceramic capacitor 100 includes a first external electrode 120 and a second external electrode 130 as external electrodes.

[0013] As shown in Figure 1, the base body 110 has a substantially rectangular parallelepiped shape. As shown in Figures 1 and 2, the base body 110 has a first main surface 111 and a second main surface 112 that are opposite to the thickness direction T, a first side surface 113 and a second side surface 114 that are opposite to the width direction W which intersects the thickness direction T, and a first end surface 115 and a second end surface 116 that are opposite to the length direction L which intersects the thickness direction T and the width direction W.

[0014] The base body portion 110 preferably has rounded corners and ridgelines. Here, the corner is the part where three surfaces of the base body portion 110 meet, and the ridgeline is the part where two surfaces of the base body portion 110 meet.

[0015] As shown in FIGS. 1 and 3, the first external electrode 120 is provided on the first end face 115. Specifically, the first external electrode 120 is formed over the entire first end face 115 and is formed so as to wrap around from the first end face 115 to the first main face 111, the second main face 112, the first side face 113, and the second side face 114.

[0016] As shown in FIGS. 1 and 3, the second external electrode 130 is provided on the second end face 116. Specifically, the second external electrode 130 is formed over the entire second end face 116 and is formed so as to wrap around from the second end face 116 to the first main face 111, the second main face 112, the first side face 113, and the second side face 114.

[0017] As shown in FIG. 2, the base body portion 110 includes a laminate 101, a first side margin portion S1, and a second side margin portion S2.

[0018] As shown in FIGS. 3 to 4, the laminate 101 has a plurality of dielectric layers 140 and a plurality of internal electrode layers 150 alternately laminated along the thickness direction T. The plurality of internal electrode layers 150 includes a plurality of first internal electrode layers 151 and a plurality of second internal electrode layers 152. The plurality of first internal electrode layers 151 and the plurality of second internal electrode layers 152 are alternately laminated in the thickness direction T.

[0019] The plurality of first internal electrode layers 151 are drawn out to the first end face 115. The plurality of first internal electrode layers 151 are connected to the first external electrode 120. The plurality of second internal electrode layers 152 are drawn out to the second end face 116. The plurality of second internal electrode layers 152 are connected to the second external electrode 130.

[0020] In Figures 3 and 4, examples are shown in which seven first internal electrode layers 151 and seven second internal electrode layers 152 are provided, but the number of each of the first internal electrode layers 151 and second internal electrode layers 152 is not limited to seven.

[0021] The multiple dielectric layers 140 consist of an outer dielectric layer located between the first main surface 111 and the internal electrode layer 150 located closest to the first main surface 111 in the thickness direction T, and between the internal electrode layer 150 located closest to the second main surface 112 in the thickness direction T and the second main surface 112, and an inner dielectric layer located between adjacent internal electrode layers 150 in the thickness direction T.

[0022] The number of dielectric layers 140 is preferably between 100 and 1000. Each of the dielectric layers 140 may be made of a dielectric ceramic material containing, for example, BaTiO3, CaTiO3, SrTiO3, or CaZrO3. The dielectric layers 140 may also have components added in a smaller amount than the main component. The added components may be, for example, Mn compounds, Fe compounds, Cr compounds, Co compounds, Ni compounds, etc. The thickness of the dielectric layer is preferably between 0.5 μm and 30 μm.

[0023] Each of the first internal electrode layer 151 and the second internal electrode layer 152 contains Ni as its main component. Each of the first internal electrode layer 151 and the second internal electrode layer 152 may further contain a dielectric material of the same composition as the ceramic contained in the dielectric layer 140. In addition, each of the first internal electrode layer 151 and the second internal electrode layer 152 may contain Sn or the like at the interface with the dielectric layer 140.

[0024] As shown in Figure 3, the laminate 101 is divided into an inner layer C, a first outer layer X1 and a second outer layer X2, and a first end margin E1 and a second end margin E2. The inner layer C has capacitance because a part of the first internal electrode layer 151 and a part of the second internal electrode layer 152 are laminated in the thickness direction T.

[0025] The first outer layer X1 and the second outer layer X2 sandwich the inner layer C in the thickness direction T. The first outer layer X1 is located outside the inner layer C in the thickness direction T and is located on the first main surface 111 side. The second outer layer X2 is located outside the inner layer C in the thickness direction T and is located on the second main surface 112 side.

[0026] Each of the first outer layer X1 and the second outer layer X2 is an outer dielectric layer. The first outer layer X1 and the second outer layer X2 may be made of the same dielectric ceramic material as the plurality of dielectric layers 140, or they may be made of a different dielectric ceramic material than the plurality of dielectric layers 140.

[0027] The thickness of the first outer layer X1 and the second outer layer X2 is preferably 10 μm or more and 300 μm or less.

[0028] The first end margin portion E1 and the second end margin portion E2 sandwich the inner layer portion C in the longitudinal direction L. The first end margin portion E1 is located outside the inner layer portion C in the longitudinal direction L and is located on the first end face 115 side. The second end margin portion E2 is located outside the inner layer portion C in the longitudinal direction L and is located on the second end face 116 side.

[0029] The side margins are located in the base body 110 between the first side surface 113 and the multiple internal electrode layers 150, and between the second side surface 114 and the multiple internal electrode layers 150, in the width direction W. The side margins consist of a first side margin S1 and a second side margin S2.

[0030] The first side margin portion S1 is provided to cover the entire surface of one side of the laminate 101. In the base body portion 110, the first side margin portion S1 extends from one end of the internal electrode layer 150 located on one side in the width direction W to the first side surface 113.

[0031] The second side margin portion S2 is provided to cover the entire other side surface of the laminate 101. In the base body portion 110, the second side margin portion S2 extends from the other end of the internal electrode layer 150 located on the other side in the width direction W to the second side surface 114.

[0032] The first side margin portion S1 and the second side margin portion S2 may be made of the same dielectric ceramic material as the plurality of dielectric layers 140, or they may be made of a dielectric ceramic material different from the plurality of dielectric layers 140.

[0033] The first side margin portion S1 and the second side margin portion S2 may be composed of multiple layers. In the case of multiple layers, it is not necessary for any interfaces between the layers to be observed.

[0034] As described above, the size of the multilayer ceramic capacitor 100, which includes the base body 110 and the first external electrode 120 and the second external electrode 130, is not particularly limited, but for example, the following range can be adopted.

[0035] As shown in Figure 3, the length dimension L of the multilayer ceramic capacitor 100 (length dimension L0) is, for example, 0.1 mm or more and 1.0 mm or less. The thickness dimension T of the multilayer ceramic capacitor 100 (thickness dimension T0) is, for example, 0.05 mm or more and 0.5 mm or less. As shown in Figure 4, the width dimension W of the multilayer ceramic capacitor 100 (width dimension W0) is, for example, 0.05 mm or more and 0.5 mm or less. Note that the dimensions shown here are values ​​excluding dimensional tolerances. In practice, dimensional tolerances are added to the dimensions shown here.

[0036] Figure 5 shows a plan view of the overlapping state of the internal electrode layer 150 in the multilayer ceramic capacitor 100 relative to the dielectric layer 140. Here, the first internal electrode layer 151 is shown as an example of the internal electrode layer 150. In the case of the second internal electrode layer 152, the degree of overlap with the dielectric layer 140 is reversed left to right compared to that shown in Figure 5. In Figures 3 and 4, grooves on the surface of the multiple internal electrode layers 150 were omitted from the illustration, but in reality, as shown in Figure 5, multiple grooves 7 are provided on the surface of the internal electrode layer 150. The multiple grooves 7 are provided parallel to each other. In the example shown here, the multiple grooves 7 extend along the length direction L. Figure 6 shows a cross-sectional view taken along the line VI-VI in Figure 5. In Figure 6, only a part of the laminate 101 is shown.

[0037] The multilayer ceramic capacitor 100 in this embodiment comprises a laminate 101. The laminate 101 includes a plurality of laminated dielectric layers 140 and a plurality of internal electrode layers 150. The laminate 101 has a first main surface 111 and a second main surface 112 facing each other in the lamination direction, a first side surface 113 and a second side surface 114 facing each other in the width direction W perpendicular to the lamination direction, and a first end surface 115 and a second end surface 116 facing each other in the length direction L perpendicular to the lamination direction and the width direction W. External electrodes are arranged to cover at least a portion of the first end surface 115 and at least a portion of the second end surface 116, and are electrically connected to at least one of the plurality of internal electrode layers 150. Here, "external electrodes" refers to a first external electrode 120 and a second external electrode 130. At least a portion of the plurality of internal electrode layers 150 has a plurality of grooves 7, and at least a portion of the plurality of dielectric layers 140 is embedded in the plurality of grooves 7.

[0038] (Effects / Actions) In this embodiment, at least a portion of the multiple internal electrode layers 150 have multiple grooves 7, and at least a portion of the multiple dielectric layers 140 are embedded in the multiple grooves 7, resulting in a strong bond between the dielectric layers 140 and the internal electrode layers 150. This makes it less likely for delamination to occur between the internal electrode layers and the dielectric layers within the laminate during sintering.

[0039] As shown in this embodiment, the multiple grooves 7 may extend along the longitudinal direction L.

[0040] Alternatively, as shown in Figures 7 and 8, the multiple grooves 7 may extend along the width direction W. Figure 8 is a cross-sectional view taken along the line VIII-VIII in Figure 7. Only a portion of the laminate 101 is shown in Figure 8.

[0041] The width of each of the multiple grooves 7 is preferably between 5 μm and 100 μm. The depth of each of the multiple grooves 7 is preferably between 0.5 μm and 30 μm. If the depth of the grooves 7 is less than 0.5 μm, the delamination suppression effect cannot be sufficiently obtained. If the depth of the grooves 7 exceeds 30 μm, the dielectric layer does not penetrate sufficiently into the grooves 7. Therefore, it can be said that the depth of each of the multiple grooves 7 is preferably between 0.5 μm and 30 μm.

[0042] The thickness of each of the multiple dielectric layers 140 is preferably 0.5 μm or more and 30 μm or less.

[0043] The thickness of each of the multiple internal electrode layers 150 is preferably 0.5 μm or more and 3 μm or less.

[0044] The number of grooves 7 formed in one internal electrode layer 150 is preferably between 5 and 1000. This is because if the number of grooves is less than 5, the peeling suppression effect cannot be sufficiently obtained.

[0045] (Manufacturing method for multilayer ceramic capacitors) Furthermore, the following manufacturing methods can be used to obtain multilayer ceramic capacitors.

[0046] First, a dielectric sheet is prepared to form the dielectric layer 140. The dielectric sheet is, for example, a ceramic green sheet. Next, a conductive paste is prepared to form the internal electrode layer 150. The dielectric sheet and conductive paste used here contain a binder and a solvent. Known binders and organic solvents can be used for this.

[0047] Next, a conductive paste is printed on the surface of the dielectric sheet in a predetermined pattern using known techniques such as screen printing or gravure printing. This forms the pattern of the internal electrode layer. At this time, grooves 7 are formed on the surface of the pattern of the internal electrode layer. The method for forming grooves 7 in the internal electrode layer will be described later.

[0048] A predetermined number of dielectric sheets without printed internal electrode layers are stacked. This portion becomes the second outer layer X2. A predetermined number of dielectric sheets with printed patterns for the internal electrode layers are stacked on top of this stack. A portion of this becomes the inner layer C. Furthermore, a predetermined number of dielectric sheets without printed internal electrode layers are stacked on top of that. This portion becomes the first outer layer X1. The stack obtained in this way is pressed in the stacking direction by processing such as hydrostatic pressing. During this pressing, the dielectric layer 140 can deform, so the dielectric layer 140 enters the grooves 7 formed in the pattern of the internal electrode layer. In this way, a stack block is obtained. A stack chip is obtained by cutting the stack block to a predetermined size. The corners and edges of the stack chip may be rounded by barrel polishing or the like. The stack chip is fired to obtain a stack 101. The firing temperature is selected according to the type of material of the dielectric layer and the internal electrode layer. The firing temperature is preferably between 900°C and 1300°C. A conductive paste for forming external electrodes is applied to both end faces of the laminate 101 and fired. This forms a fired layer for the external electrodes. The firing temperature is preferably between 700°C and 900°C. If necessary, plating is applied to the surface of the fired layer. In this way, the first external electrode 120 and the second external electrode 130 are formed.

[0049] (Method for forming grooves) A method for forming grooves 7 in the internal electrode layer will be described. When a conductive paste is printed onto the surface of a ceramic green sheet, which will become the dielectric layer 140, in order to form the internal electrode layer 150, the following method can be used to form the grooves 7. First, a conductive paste is printed onto the surface of the ceramic green sheet. Before the conductive paste dries, a mold with slits is pressed onto it. In the areas corresponding to the slits, the conductive paste remains thick without being pressed, but in the areas other than the slits, the conductive paste is pressed and thinned, so these areas become grooves. In this mold, it is preferable to set the width of the areas other than the slits to approximately 90% of the width of the desired groove. By doing so, a groove of the desired width can be obtained.

[0050] Alternatively, when screen printing a conductive paste onto the surface of a ceramic green sheet that will form the dielectric layer in order to create an internal electrode layer, it is possible to mask the areas of the screen printing mesh that correspond to the grooves. In this way, the thickness of the conductive paste in the areas corresponding to the grooves will be thinner than in other areas, thus making it possible to create the desired grooves.

[0051] Alternatively, a conductive paste may be printed with an inkjet head to form an internal electrode layer. In this case, the desired grooves can be formed by adjusting the spacing between the nozzles of the inkjet head.

[0052] (The reverse configuration) Up to this point, we have described the configuration assuming that grooves are provided in the internal electrode layer 150 and the dielectric layer 140 is fitted into these grooves. However, the opposite configuration is also possible, where grooves are provided in the dielectric layer 140 and the internal electrode layer 150 is fitted into these grooves. In that case, grooves can be formed in advance on the surface of the dielectric layer 140 using known techniques. By printing with conductive paste on the surface of the dielectric layer 140 with grooves formed in this way, a structure can be obtained in which the internal electrode layer is fitted into the grooves of the internal electrode layer 150.

[0053] (Method for determining thickness) When discussing the thickness of the internal electrode layer and the dielectric layer, "thickness" refers to the average thickness. The average thickness is measured as follows: First, a cross-section perpendicular to the length L of the laminate, exposed by polishing, is observed using a scanning electron microscope. Next, the thickness is measured along a center line passing through the center of the cross-section of the laminate along the lamination direction, and along a total of five lines drawn at equal intervals on both sides of this center line. The average of these five measurements is taken as the average thickness. To obtain a more accurate average thickness, the above five measurements are taken for the top, middle, and bottom sections in the lamination direction, and the average of these measurements is taken as the average thickness.

[0054] Furthermore, multiple embodiments of the above-described model may be combined and adopted as appropriate. The embodiments disclosed herein are illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims and includes all modifications in the sense and scope equivalent to the claims. [Explanation of symbols]

[0055] 7 groove, 100 multilayer ceramic capacitor, 101 laminate, 110 base body, 111 first main surface, 112 second main surface, 113 first side surface, 114 second side surface, 115 first end surface, 116 second end surface, 120 first external electrode, 130 second external electrode, 140 dielectric layer, 150 internal electrode layer, 151 first internal electrode layer, 152 second internal electrode layer.

Claims

1. Equipped with a laminate, The laminate includes a plurality of stacked dielectric layers and a plurality of internal electrode layers. The laminate has a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction. An external electrode is arranged so as to cover at least a portion of the first end face and at least a portion of the second end face, and is electrically connected to at least one of the plurality of internal electrode layers. A multilayer ceramic capacitor in which at least a portion of the plurality of internal electrode layers has a plurality of grooves, and at least a portion of the plurality of dielectric layers is embedded in the plurality of grooves.

2. The multilayer ceramic capacitor according to claim 1, wherein the plurality of grooves extend along the width direction.

3. The multilayer ceramic capacitor according to claim 1, wherein the plurality of grooves extend along the longitudinal direction.

4. The multilayer ceramic capacitor according to claim 1 or 2, wherein the width of each of the plurality of grooves is 5 μm or more and 100 μm or less.

5. The multilayer ceramic capacitor according to claim 1 or 2, wherein the depth of each of the plurality of grooves is 0.5 μm or more and 30 μm or less.

6. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the thickness of each of the plurality of dielectric layers is 0.5 μm or more and 30 μm or less.

7. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the thickness of each of the plurality of internal electrode layers is 0.5 μm or more and 3 μm or less.

Images