Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device that can achieve both improved voltage resistance and reduced switching losses. [Solution] The semiconductor element 1 comprises a substrate 10, a main drift layer 11, a second conductivity type block layer 20, a sub-drift layer 12, a second conductivity type body layer 30, and a first conductivity type impurity high-concentration containing layer 13. The second conductivity type block layer 20 is provided with a second conductivity type connecting layer 21 containing a second conductivity type impurity at a higher concentration than that of the second conductivity type block layer 20. The gate trench T is formed in a groove shape so that it reaches at least the sub-drift layer 12 from the first conductivity type impurity high-concentration containing layer 13 and exposes at least a portion of the side surface of the second conductivity type connecting layer 21. The side surface of the second conductivity type connecting layer 21 exposed in the gate trench T is covered by a gate insulating film 14 along the bottom surface and side surface of the gate trench T. The gate electrode GM is provided along the bottom surface and side surface of the gate trench T via the gate insulating film 14.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. [Background technology]

[0002] In semiconductor devices with a gate trench structure, when the gate voltage is below a threshold in the off state, leakage current is easily generated due to electrolytic concentration at the bottom of the gate trench, resulting in a tendency for low breakdown voltage. Therefore, in the configuration disclosed in Patent Document 1, a p-type block layer is provided between the p-type body layer and the n-type drift layer to mitigate electrolytic concentration at the bottom of the gate trench and suppress current leakage, thereby improving breakdown voltage. Furthermore, since the p-type block layer becomes electrically detached, causing charge to accumulate in the p-type block layer and increasing switching losses in the semiconductor, the p-type block layer is connected to the source electrode to allow the charge to dissipate. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2019-054174 [Overview of the project] [Problems that the invention aims to solve]

[0004] In the configuration disclosed in Patent Document 1, a deep trench, which is a groove leading from the source electrode to the p-type block layer, is formed to connect the p-type block layer and the source electrode, and a p-type connection layer containing p-type impurities is formed in the deep trench. However, when forming the p-type connection layer, the wall surface of the deep trench is exposed to the atmosphere, causing impurities such as Si to adhere to the wall surface, forming a high-concentration N region containing a high concentration of n-type impurities. This high-concentration n-type region then becomes a leak path that conducts current between the source electrode and the drain electrode, so when a voltage is applied between the two electrodes, a leakage current is generated and the breakdown voltage decreases. It is conceivable to prevent the adhesion of impurities to the wall surface of the deep trench or to clean the wall surface of the deep trench before forming the p-type connection layer to remove any impurities that have adhered to it, but such work is not easy and is not practical. Therefore, there is room for improvement in semiconductor devices having a gate trench structure to achieve both improved breakdown voltage and reduced switching loss.

[0005] This invention was made in view of the above background, and aims to provide a semiconductor element that can achieve both improved voltage resistance and reduced switching losses. [Means for solving the problem]

[0006] One aspect of the present invention is, A semiconductor substrate containing a first-type impurity, A main drift layer provided on the substrate and containing a first conductivity type impurity at a lower concentration than that of the substrate, A second conductivity type block layer containing a second conductivity type impurity is provided in contact with the main drift layer and has an opening formed therein. A second conductivity type connecting layer is provided on the second conductivity type block layer and contains a second conductivity type impurity at a higher concentration than the second conductivity type block layer, A source electrode connected to the second conductivity type connecting layer, A sub-drift layer is provided on the second conductivity type block layer and fills the aforementioned opening, and contains a first conductivity type impurity at the same concentration as the main drift layer or at a higher concentration than the main drift layer, A second-conductivity-type body layer provided on the sub-drift layer and the second-conductivity-type block layer, and containing a second-conductivity-type impurity having the same concentration as the second-conductivity-type block layer or a lower concentration than the second-conductivity-type block layer, A first-conductivity-type impurity high-concentration-containing layer provided on the second-conductivity-type body layer and containing a first-conductivity-type impurity having a higher concentration than the sub-drift layer, A gate trench formed in a groove shape so as to reach at least the sub-drift layer from the first-conductivity-type impurity high-concentration-containing layer and to expose at least a part of the side surface of the second-conductivity-type connection layer, A gate insulating film provided in a film shape so as to cover the bottom surface and the side surface of the gate trench and the side surface of the second-conductivity-type connection layer exposed in the gate trench, A gate electrode provided along the bottom surface and the side surface of the gate trench through the gate insulating film, which is included in a semiconductor device.

[0007] Another aspect of the present invention is a method for manufacturing the above semiconductor device, comprising: a preparation step of preparing a laminate in which the substrate, the main drift layer, the second-conductivity-type block layer, the sub-drift layer, the second-conductivity-type body layer, and the first-conductivity-type impurity high-concentration-containing layer are laminated; a deep trench forming step of forming a deep trench which is a groove reaching at least from the first-conductivity-type impurity high-concentration-containing layer to the second-conductivity-type block layer in the laminate; a second-conductivity-type connection layer forming step of forming the second-conductivity-type connection layer so as to fill the deep trench; a gate trench forming step of removing at least from the first-conductivity-type impurity high-concentration-containing layer to the sub-drift layer in a region including a joint portion between the peripheral surface of the second-conductivity-type connection layer and the wall surface of the deep trench to form a gate trench and expose at least a part of the side surface of the second-conductivity-type connection layer; a gate insulating film forming step of forming the gate insulating film covering the bottom surface and the side surface of the gate trench; A gate electrode formation step in which the gate electrode is formed along the bottom surface and side surface of the gate trench via the gate insulating film, A source electrode formation step in which the source electrode connected to the second conductivity type connecting layer is formed, The invention relates to a method for manufacturing semiconductor devices, including [the aforementioned method]. [Effects of the Invention]

[0008] In the semiconductor device according to the above embodiment, a second conductivity type block layer is provided between the second conductivity type body layer and the main drift layer to mitigate electrolytic concentration at the bottom of the gate trench and suppress current leakage, thereby improving the breakdown voltage. Furthermore, by connecting the second conductivity type block layer and the source electrode with a second conductivity type connecting layer, the electrical floating of the second conductivity type block layer is prevented, thereby suppressing the occurrence of switching losses. The gate trench is formed such that at least a portion of the side surface of the second conductivity type connecting layer is exposed, and the side surface of the second conductivity type connecting layer exposed in the gate trench is covered by a gate insulating film covering the wall surface of the gate trench. As a result, at least a portion of the high-density n-type region on the side surface of the second conductivity type connecting layer can be removed and the side surface can be insulated. Consequently, the formation of a leak path is suppressed, and the decrease in breakdown voltage can be suppressed. Therefore, according to the above embodiment, it is possible to provide a semiconductor device that can achieve both improved breakdown voltage and reduced switching losses.

[0009] Furthermore, in the manufacturing method of the semiconductor device according to the other embodiment described above, a gate trench is formed by removing at least the sub-drift layer from the first conductivity type impurity high-concentration layer in the region including the junction between the circumferential surface of the second conductivity type connecting layer and the wall surface of the deep trench, exposing at least a portion of the side surface of the second conductivity type connecting layer to the wall surface of the gate trench, and covering the side surface of the second conductivity type connecting layer exposed to the wall surface of the gate trench with a gate insulating film. As a result, according to the manufacturing method of the other embodiment described above, it is possible to manufacture a semiconductor device according to one embodiment that can achieve both improved breakdown voltage and reduced switching loss. [Brief explanation of the drawing]

[0010] [Figure 1] A cross-sectional view showing the configuration of a semiconductor element in Embodiment 1, wherein the cross-sectional view is perpendicular to the main surface of the substrate at the position A-A' in Figure 2(a). [Figure 2] (a) A figure showing an example of the planar pattern of the trench, second conductivity type connecting layer and second conductivity type body layer in Embodiment 1; (b) A figure showing another example of the planar pattern of the trench, second conductivity type connecting layer and second conductivity type body layer; (c) A figure showing yet another example of the planar pattern of the trench, second conductivity type connecting layer and second conductivity type body layer. [Figure 3] A flowchart illustrating the manufacturing method of a semiconductor device in Embodiment 1. [Figure 4] A diagram showing the manufacturing process of a semiconductor device in Embodiment 1. [Figure 5] A diagram showing the manufacturing process of a semiconductor device in Embodiment 1. [Figure 6] A diagram showing the manufacturing process of a semiconductor device in Embodiment 1. [Figure 7] A diagram showing the manufacturing process of a semiconductor device in Embodiment 1. [Figure 8] A diagram showing the manufacturing process of a semiconductor device in Embodiment 1. [Figure 9] A diagram showing the manufacturing process of a semiconductor device in Embodiment 1. [Figure 10] A diagram showing the manufacturing process of a semiconductor device in Embodiment 1. [Figure 11] A diagram showing the manufacturing process of a semiconductor device in Embodiment 1. [Figure 12] A diagram showing the manufacturing process of a semiconductor device in Embodiment 1. [Figure 13] A cross-sectional view showing the configuration of a semiconductor element in Embodiment 2, wherein the cross-sectional view is perpendicular to the main surface of the substrate. [Figure 14] A cross-sectional view showing the configuration of a semiconductor element in modified form 1, wherein the cross-sectional view is perpendicular to the main surface of the substrate. [Figure 15] A cross-sectional view showing the configuration of a semiconductor element in Embodiment 3, wherein the cross-sectional view is perpendicular to the main surface of the substrate. [Figure 16]A flowchart illustrating the manufacturing method of a semiconductor device in Embodiment 3. [Figure 17] A diagram showing the manufacturing process of a semiconductor device in Embodiment 3. [Figure 18] A diagram showing the manufacturing process of a semiconductor device in Embodiment 3. [Figure 19] A diagram showing the manufacturing process of a semiconductor device in Embodiment 3. [Modes for carrying out the invention]

[0011] In the semiconductor device described above, the second conductivity type connecting layer has a protruding portion that extends toward the opening along the bottom surface of the gate trench, and it is preferable that the amount of protrusion of the protruding portion from the side surface of the gate trench is smaller than the width of the bottom surface of the gate trench. In this case, the function of the transistor portion formed in the region including the opening in the semiconductor can be ensured.

[0012] In the semiconductor device described above, it is preferable that the bottom surface of the second conductivity type connecting layer is located on the side of the first conductivity type impurity high concentration containing layer that is located, rather than on the bottom surface of the gate trench. In this case, the second conductivity type connecting layer does not protrude outwards from the bottom surface of the gate trench, thus further improving the breakdown voltage.

[0013] In the above semiconductor device, it is preferable that the entire side surface of the second conductivity type connecting layer is exposed to the gate trench and covered by the gate insulating film. In this case, it is possible to further improve both the breakdown voltage and the reduction of switching losses.

[0014] Preferably, the semiconductor device comprises a groove-shaped recess extending from the first conductivity type impurity high-concentration layer to the second conductivity type body layer, and a second conductivity type void-filling layer provided to fill the recess and containing a higher concentration of second conductivity type impurities than the second conductivity type block layer, wherein the source electrode is the first source electrode and a second source electrode provided to cover the second conductivity type void-filling layer. In this case, the breakdown voltage of the semiconductor device can be further improved.

[0015] The above-described method for manufacturing a semiconductor device includes, after the deep trench formation step, a recess formation step in which the region above the opening is formed by removing the layer from the first conductivity type impurity high concentration layer to the second conductivity type body layer, It is preferable that, after the recess formation step, in the second conductivity type connection layer formation step, the deep trench is filled to form the second conductivity type connection layer, and the recess is filled to form the second conductivity type hole-filling layer. In this case, the breakdown voltage of the semiconductor device can be further improved.

[0016] (Embodiment 1) 1. Semiconductor device configuration Figure 1 is a cross-sectional view showing the configuration of a semiconductor element in Embodiment 1, and is a cross-sectional view perpendicular to the main surface of the substrate. The semiconductor element in Embodiment 1 is a MOSFET having a gate trench structure. Furthermore, in a plan view, the semiconductor element in Embodiment 1 can have a structure in which the gate trench and p-type connection layer, described later, are arranged in a stripe pattern, as shown in Figure 2(a), or a structure in which regular hexagonal unit cells are arranged in a honeycomb pattern, as shown in Figures 2(b) and 2(c), with each unit cell connected in parallel.

[0017] As shown in FIG. 1, the semiconductor device in Embodiment 1 includes a substrate 10, a main drift layer 11, a sub-drift layer 12, a second-conductivity-type block layer 20, a second-conductivity-type connection layer 21, a second-conductivity-type body layer 30, a first-conductivity-type impurity high-concentration-containing layer 13, a gate trench T, a recess R, a gate insulating film 14, a gate electrode GM, a source electrode SM, and a drain electrode DM. The gate trench T, the gate insulating film 14, and the gate electrode GM form a gate trench structure. All the gate trench structures are MIS structures.

[0018] The substrate 10 is a semiconductor containing a first-conductivity-type impurity. In this embodiment, it is Si-doped n + -GaN having a c-plane as the main surface. The Si concentration of the substrate 10 can be 5×10 17 ~5×10 20 / cm 3 and is 2×10 18 / cm 3 in this embodiment. The thickness of the substrate 10 can be 100 - 500 μm and is 300 μm in this embodiment. The material of the substrate 10 may be other than GaN, and any material can be used as long as it can grow a nitride semiconductor and has conductivity. For example, Si, SiC, ZnO, etc. can be used. However, it is particularly preferable to use GaN as in Embodiment 1.

[0019] The main drift layer 11 is provided on the substrate 10 and contains a first-conductivity-type impurity with a lower concentration than the substrate 10. In this embodiment, the main drift layer 11 is made of Si-doped n - -GaN. The Si concentration of the main drift layer 11 can be 3×10 15 ~3×10 16 / cm 3 and is 1×10 16 / cm 3 in this embodiment. Also, the thickness of the main drift layer 11 can be 0.5 - 20 μm and is 10 μm in this embodiment.

[0020] The second conductivity type block layer 20 contains a second conductivity type impurity and is provided on the main drift layer 11. In this embodiment, the second conductivity type block layer 20 is made of Mg-doped p-GaN and is also called the p-type block layer 20. The Mg concentration of the p-type block layer 20 is 5 × 10⁻¹⁶. 17 ~5×10 19 / cm 3 This can be done, and in this embodiment, 1 × 10 19 / cm 3 Furthermore, the thickness of the p-type block layer 20 can be 0.3 to 1.0 μm, and in this embodiment, it is set to 0.5 μm.

[0021] An opening 20a is formed in the second conductive block layer (p-type block layer) 20. In this embodiment, the opening 20a is located below Y2 of the recess R, which will be described later. Also, in this embodiment, the lateral X end of the opening 20a does not reach the lateral X position of the wall surface of the gate trench T, which will be described later.

[0022] The second conductivity type connecting layer 21 is provided on the second conductivity type blocking layer (p-type blocking layer) 20 and contains a higher concentration of second conductivity type impurities than the second conductivity type blocking layer 20. In this embodiment, the second conductivity type connecting layer 21 is made of Mg-doped p-GaN and is also called the p-type connecting layer 21. The Mg concentration of the p-type connecting layer 21 is 1 × 10⁻⁶. 18 ~6×10 19 / cm 3 This can be done, and in this embodiment, 3 × 10 19 / cm 3 Furthermore, the thickness of the p-type connecting layer 21 can be 0.4 to 4.0 μm, and in this embodiment, it is set to 1.3 μm. The second conductive connecting layer 21 has a first source electrode SM1, which will be described later, formed on it.

[0023] In this embodiment, the second conductive connecting layer 21 has an overhang portion 21a that extends toward the opening 20a along the bottom surface of the gate trench T, which will be described later. The amount of overhang L1 of the overhang portion 21a is smaller than the width W1 of the bottom surface of the gate trench T. The width W1 of the bottom surface of the gate trench T can be 0.5 to 3.0 μm, and in this embodiment, it is set to 1.5 μm. The amount of overhang L1 can be 0 to 3 μm, and in this embodiment, it is set to 0.7 μm.

[0024] The sub-drift layer 12 fills the opening 20a and is provided on the second conductivity type block layer 20, and contains the same concentration as the main drift layer 11 or a higher concentration than the main drift layer 11 of the first conductivity type impurity. In this embodiment, the sub-drift layer 12 is Si-doped n - -It consists of GaN. The Si concentration of the sub-drift layer 12 is 3 × 10⁻¹⁰ 15 ~3×10 16 / cm 3 This can be done, and in this embodiment, 1 × 10 16 / cm 3 Furthermore, the thickness of the sub-drift layer 12 can be 0.1 to 1.5 μm, and in this embodiment, it is set to 1.0 μm.

[0025] The second conductive body layer 30 is provided on the sub-drift layer 12 and the p-type block layer 20. The second conductive body layer 30 contains the same concentration as the p-type block layer 20 or a lower concentration. In this embodiment, the second conductive body layer 30 is made of Mg-doped p-GaN and is also called the p-type body layer 30. The Mg concentration of the p-type body layer 30 is 1 × 10⁻⁶ 17 ~4×10 19 / cm 3 This can be done, and in this embodiment, 5 × 10 18 / cm 3 Furthermore, the thickness of the p-type body layer 30 can be 0.2 to 1.0 μm, and in this embodiment, it is set to 0.4 μm.

[0026] The first conductivity type impurity high-concentration layer 13 is provided on the p-type body layer 30. The first conductivity type impurity high-concentration layer 13 contains the first conductivity type impurity at a higher concentration than the sub-drift layer 12 and at the same concentration as or lower than that of the substrate 10. In this embodiment, the first conductivity type impurity high-concentration layer 13 is Si-doped n + -It consists of GaN and is also called the n-type layer 13. The Si concentration of the n-type layer 13 is 5 × 10 17 ~1 × 10 19 / cm 3 This can be done, and in this embodiment, 2 × 10 18 / cm 3 Furthermore, the thickness of the n-type layer 13 can be 0.1 to 0.5 μm, and in this embodiment, it is set to 0.2 μm.

[0027] The gate trench T is formed in a groove shape so as to reach at least the sub-drift layer 12 from the first conductive type impurity high-concentration layer 13 and expose at least a portion of the side surface of the second conductive type connecting layer (p-type connecting layer) 21. In this embodiment, the sub-drift layer 12 and the protruding portion 21a of the p-type connecting layer 21 are exposed on the bottom surface of the gate trench T. In addition, the side surface of the p-type connecting layer 21 is exposed on one side surface of the gate trench T, and on the other side surface of the gate trench T, the sub-drift layer 12, the p-type body layer 30, and the n-type layer 13 are exposed in order from the bottom surface. The p-type body layer 30 exposed on the other side surface of the gate trench T acts as a channel.

[0028] As described above, the width W1 of the gate trench T can be 0.5 to 3 μm, and in this embodiment it is 1.5 μm. The cell pitch can be 3 to 10 μm, and in this embodiment it is 6 μm. The trench width can also be 0.5 to 3 μm, and in this embodiment it is 2 μm. The trench angle is not limited, and in this embodiment it is perpendicular to the substrate 10. In this embodiment, the planar pattern of the gate trench T is a stripe shape in which the gate trench T, p-type body layer 30, and p-type connecting layer 21 are arranged in parallel in sequence, as shown in Figure 2.

[0029] The recess R is a recess that penetrates the n-type layer 13 and reaches the p-type body layer 30. The recess R is provided to bring the source electrode SM into contact with the p-type body layer 30.

[0030] The gate insulating film 14 is continuously provided in a film-like manner along the bottom, side, and top surfaces of the gate trench T (the top surfaces of the n-type layer 13 and p-type connecting layer 21 near the gate trench T). The material of the gate insulating film 14 is SiO2, SiN, SiON, Al2O3, etc., and its thickness is, for example, 50 nm.

[0031] The gate electrode GM is provided as a continuous film along the bottom, side, and top surfaces of the gate trench T via the gate insulating film 14. The material of the gate electrode GM is TiN, for example.

[0032] The source electrode SM includes a first source electrode SM1 and a second source electrode SM2. The first source electrode SM1 is formed on the p-type connecting layer 21 as described above. The second source electrode SM2 is connected to the second conductivity type body layer 30 via a groove-shaped recess R that extends from the first conductivity type impurity high-concentration layer 13 to the second conductivity type body layer 30. The materials of the first source electrode SM1 and the second source electrode SM2 are, for example, Ti / Al, Ti / Al / Ti, V / Al / Ti, and Pd / Al / Ti.

[0033] The drain electrode DM is provided across the entire back surface of the substrate 10. The material of the drain electrode DM is, for example, Ti / Al, Ti / Al / Ti, V / Al / Ti, or Pd / Al / Ti.

[0034] 2. Method for manufacturing semiconductor devices Next, the method for manufacturing the semiconductor device in Embodiment 1 will be described with reference to Figures 3 to 12.

[0035] First, in the preparation step S1 shown in Figure 3, as shown in Figure 4, a main drift layer 11 and a p-type block layer 20 are stacked on the substrate 10 in order from the substrate 10 side. Each layer is formed by vapor phase growth methods such as MOCVD, HVPE, MBE, or sputtering, so that Si as the first conductivity type impurity or Mg as the second conductivity type impurity reaches a predetermined doping concentration.

[0036] Next, a predetermined mask pattern (not shown) is formed on the p-type block layer 20, and then etching is performed to remove the p-type block layer 20 until the main drift layer 11 is exposed, as shown in Figure 5, thereby forming an opening 20a. Etching can be performed by dry etching such as RIE, wet etching such as PEC, or polishing. After etching, the mask pattern (not shown) is removed.

[0037] Then, as shown in Figure 5, a sub-drift layer 12, a p-type block layer 20, and an n-type layer 13 are sequentially formed on the p-type block layer 20 and the opening 20a. Each layer is formed by vapor phase growth methods such as MOCVD, HVPE, MBE, or sputtering, so that Si as the first conductivity type impurity or Mg as the second conductivity type impurity reaches a predetermined doping concentration. As a result, the opening 20a is filled with the sub-drift layer 12. This prepares a laminate 1a in which the substrate 10, the main drift layer 11, the p-type block layer 20, the sub-drift layer 12, the p-type body layer 30, and the n-type layer 13 are stacked.

[0038] Next, in the deep trench formation step S2 shown in Figure 3, a predetermined mask pattern (not shown) is formed on the n-type layer 13 of the laminate 1a, and as shown in Figure 7, deep trenches DT, which are grooves that reach at least from the n-type layer 13 to the p-type block layer in the laminate 1a, are etched and formed. Etching can be performed by dry etching such as RIE, wet etching such as PEC, or polishing. After etching, the mask pattern (not shown) is removed.

[0039] Next, in the second conductivity type connecting layer formation step S3 shown in Figure 3, a second conductivity type connecting layer (p-type connecting layer) 21 is formed to fill the deep trench DT, as shown in Figure 8. The second conductivity type connecting layer 21 is formed by vapor phase growth methods such as MOCVD, HVPE, MBE, and sputtering, so that the Mg as the second conductivity type impurity reaches a predetermined doping concentration. After that, as shown in Figure 9, the excess second conductivity type connecting layer 21 formed on the n-type layer 13 is removed by etching.

[0040] Next, in the gate trench formation step S4 shown in Figure 3, as shown in Figure 10, in the region including the junction between the circumferential surface of the second conductivity type connecting layer 21 and the wall surface of the deep trench DT, the first conductivity type impurity high concentration containing layer 13 is removed up to the sub-drift layer 12 to form a gate trench T, exposing at least a portion of the side surface of the second conductivity type connecting layer 21.

[0041] Next, in the gate insulating film formation step S5 shown in Figure 3, a gate insulating film 14 is formed to cover the bottom and sides of the gate trench T, as shown in Figure 11. Examples of methods for forming the gate insulating film 14 include the ALD method and the CVD method. Subsequently, in the gate electrode formation step S6 shown in Figure 3, a gate electrode GM is formed along the bottom and sides of the gate trench T via the gate insulating film 14, as shown in Figure 12. In order to form the gate electrode GM on the gate insulating film 14, first, a uniform metal layer with the same stacked structure as the gate electrode GM is formed on the gate insulating film 14, and the uniform metal layer and the gate insulating film 14 are partially removed by etching using a resist or the like. As a result, the gate electrode GM and the gate insulating film 14 are formed, as shown in Figure 12.

[0042] Then, in the source electrode formation step S7, a first source electrode SM1 is formed, which is connected to the second conductivity type connecting layer 21. A second source electrode SM2 is also formed, which is connected to the p-type body layer 30 via a groove-shaped recess R formed in the n-type layer 13 located above the opening 20a. Finally, a drain electrode DM is formed on the back surface of the substrate 10, completing the semiconductor device 1 as shown in Figure 1. The source electrode SM and drain electrode DM are formed by methods such as vapor deposition.

[0043] 3. Effects In the semiconductor element 1 of this embodiment, a second conductivity type block layer 20 is provided between the second conductivity type body layer 30 and the main drift layer 11 to mitigate electrolytic concentration at the bottom of the gate trench T and suppress current leakage, thereby improving the breakdown voltage. Furthermore, by connecting the second conductivity type block layer 20 and the source electrode SM1 with a second conductivity type connecting layer 21, the electrical floating of the second conductivity type block layer 20 is prevented, thereby suppressing the occurrence of switching losses. The gate trench T is formed so that at least a portion of the side surface of the second conductivity type connecting layer 21 is exposed, and the side surface of the second conductivity type connecting layer 21 exposed in the gate trench is covered by the gate insulating film 14 covering the wall surface of the gate trench T. As a result, at least a portion of the high-concentration n-type region on the side surface of the second conductivity type connecting layer 21 can be removed and the side surface can be insulated. Consequently, the formation of a leak path is suppressed, and the decrease in breakdown voltage can be suppressed. Therefore, the semiconductor element 1 of this embodiment can achieve both improved breakdown voltage and reduced switching losses.

[0044] Furthermore, in this embodiment, the semiconductor element 1 has a protruding portion 21a that extends along the bottom surface of the gate trench T toward the opening 20a, and the amount L1 of the protruding portion 21a from the side surface of the gate trench T is smaller than the width W1 of the bottom surface of the gate trench T. This ensures the function of the transistor portion formed in the region including the opening 20a in the semiconductor element 1.

[0045] Furthermore, in the manufacturing method of the semiconductor element 1 of this embodiment, a gate trench T is formed by removing at least the sub-drift layer 12 from the first conductivity type impurity high-concentration layer 13 in the region including the junction between the circumferential surface of the second conductivity type connecting layer 21 and the wall surface of the deep trench DT, exposing at least a portion of the side surface of the second conductivity type connecting layer 21 to the wall surface of the gate trench T, and covering the side surface of the second conductivity type connecting layer 21 exposed to the wall surface of the gate trench T with the gate insulating film 14. This makes it possible to manufacture a semiconductor element 1 that can achieve both improved breakdown voltage and reduced switching loss.

[0046] As described above, this embodiment provides a semiconductor element 1 that can achieve both improved voltage resistance and reduced switching losses.

[0047] (Embodiment 2) In the semiconductor element 1 of Embodiment 1, as shown in Figure 1, the bottom surface 21b of the second conductivity type connecting layer 21 was located on the side of the first conductivity type impurity high concentration layer 13 that was located, relative to the bottom surface of the gate trench T. However, in the semiconductor element 1 of Embodiment 2, as shown in Figure 13, the bottom surface 21b of the second conductivity type connecting layer 21 is located on the side of the first conductivity type impurity high concentration layer 13 that was located, relative to the bottom surface of the gate trench T. As a result, the second conductivity type connecting layer 21 does not protrude from the bottom surface of the gate trench T, thereby further improving the breakdown voltage.

[0048] Furthermore, in the semiconductor element 1 of Embodiment 2, the entire side surface of the second conductivity type connecting layer 21 is exposed to the gate trench T and covered by the gate insulating film 14. This makes it possible to further improve both the breakdown voltage and the reduction of switching losses.

[0049] Furthermore, the other components in Embodiment 2 are the same as those in Embodiment 1, and are denoted by the same reference numerals as in Embodiment 1, and their descriptions are omitted. Embodiment 2 also produces the same effects and advantages as Embodiment 1.

[0050] Furthermore, in the semiconductor element 1 of Embodiment 2, as shown in Figure 13, the end face 21c in the lateral X direction of the second conductivity type block layer 20 is located on the side of the opening 20a relative to the wall surface of the gate trench T. In contrast, in the semiconductor element 1 of Modified Embodiment 1, as shown in Figure 14, the end face 20b in the lateral X direction of the second conductivity type block layer 20 is located on the side of the opening 20a relative to the wall surface of the gate trench T. As a result, the electric field strength under the gate trench increases, which reduces the breakdown voltage, but it is possible to secure a wider current path, thereby reducing the on-resistance.

[0051] (Embodiment 3) In the semiconductor element 1 of Embodiment 1, as shown in Figure 1, the second source electrode SM2 enters into a recess R and is directly connected to the second conductivity type body layer 30. However, in the semiconductor element 1 of Embodiment 3, as shown in Figure 15, a second conductivity type hole-filling layer 22 is provided to fill a groove-shaped recess R that extends from the first conductivity type impurity high-concentration layer 13 to the second conductivity type body layer 30 and contains a second conductivity type impurity at a higher concentration than the second conductivity type body layer 30. The second source electrode SM2 is provided to cover the second conductivity type hole-filling layer 22. This further improves the breakdown voltage of the semiconductor element 1.

[0052] In this embodiment, the second conductivity type pore-filling layer 22 is made of Mg-doped p-GaN and is also called the p-type pore-filling layer 22. The Mg concentration of the p-type pore-filling layer 22 can be the same as that of the second conductivity type connecting layer 21, and is 1 × 10⁻⁶ 18 ~6×10 19 / cm 3 This can be done, and in this embodiment, 3 × 10 19 / cm 3 That is what they say.

[0053] Furthermore, in the manufacturing method of the semiconductor element 1 of Embodiment 3, as shown in Figure 16, a recess formation step S20 is performed after the deep trench formation step S2. In the recess formation step S20, as shown in Figure 17, a recess R is formed in the region above the opening 20a by removing the layer from the first conductivity type impurity high concentration layer 13 to the second conductivity type body layer 30.

[0054] Then, after the recess formation step S20 shown in Figure 16, in the second conductivity type connecting layer formation step S3, as shown in Figure 18, the deep trench DT is filled to form the second conductivity type connecting layer 21, and the recess R is filled to form the second conductivity type hole-filling layer 22. As shown in Figure 19, the excess second conductivity type connecting layer 21 and second conductivity type hole-filling layer 22 of the first conductivity type impurity high concentration-containing layer 13 are removed by etching. Therefore, in this embodiment, the second conductivity type hole-filling layer 22 is formed from the same material as the second conductivity type connecting layer 21.

[0055] Then, in the source electrode formation step S7 shown in Figure 16, as shown in Figure 15, a first source electrode SM1 connected to the second conductivity type connecting layer 21 is formed, and a second source electrode SM2 is formed so as to cover the second conductivity type hole filling layer 22, thereby forming a drain electrode DM and completing the semiconductor device 1.

[0056] The manufacturing method for the semiconductor element 1 of Embodiment 3 can further improve the breakdown voltage of the semiconductor element 1. Note that the other steps shown in Figure 16 of Embodiment 3 are the same as those shown in Figure 3 of Embodiment 1, and are denoted by the same reference numerals, and their descriptions are omitted. Furthermore, the manufacturing method for the semiconductor element 1 of Embodiment 3 also provides the same effects and advantages as the manufacturing method of the semiconductor element 1 of Embodiment 1.

[0057] Furthermore, in Embodiments 1 to 3 and Modified Embodiment 1, the first conductivity type impurity was n-type and the second conductivity type impurity was p-type, but these can be swapped so that the first conductivity type impurity is p-type and the second conductivity type impurity is n-type. [Explanation of symbols]

[0058] 1: Semiconductor element 10: Circuit board 11: Main drift layer 12: Sub-drift layer 13: First conductivity type impurity high concentration layer (n-type layer) 14: Gate Insulator 20: Second conductive block layer (p-type block layer) 21: Second conductive type connecting layer (p-type connecting layer) 22: Second conductive hole-filling layer (p-type hole-filling layer) 30: Second conductive body layer (p-type body layer) DM: Drain electrode GM: Gate Shuttle R: Recess SM: Source electrode T: Gate Trench

Claims

1. A substrate which is a semiconductor containing a first-type conductivity impurity, A main drift layer provided on the substrate and containing a first conductivity type impurity at a lower concentration than that of the substrate, A second conductivity type block layer containing a second conductivity type impurity is provided in contact with the main drift layer and has an opening formed therein. A second conductivity type connecting layer is provided on the second conductivity type block layer and contains a second conductivity type impurity at a higher concentration than the second conductivity type block layer, A source electrode connected to the second conductivity type connecting layer, A sub-drift layer is provided on the second conductivity type block layer and fills the aforementioned opening, and contains a first conductivity type impurity at the same concentration as the main drift layer or at a higher concentration than the main drift layer, A second conductivity body layer is provided on the sub-drift layer and the second conductivity block layer, and contains a second conductivity impurity at the same concentration as or lower than that of the second conductivity block layer, A first conductivity type impurity high-concentration layer is provided on the second conductivity type body layer and contains a first conductivity type impurity at a higher concentration than the sub-drift layer, A gate trench is formed in a groove shape so as to reach at least the sub-drift layer from the first conductivity type impurity high concentration layer and expose at least a portion of the side surface of the second conductivity type connecting layer, A gate insulating film is provided in a film-like manner along the bottom and sides of the gate trench and covering the side surfaces of the second conductive type connecting layer exposed in the gate trench, A gate electrode provided along the bottom and side surfaces of the gate trench via the gate insulating film, Semiconductor devices, including those mentioned above.

2. The second conductive connecting layer has a protruding portion that extends along the bottom surface of the gate trench toward the opening, The semiconductor element according to claim 1, wherein the amount of protrusion of the protruding portion is smaller than the width of the bottom surface of the gate trench.

3. The semiconductor element according to claim 1 or 2, wherein the bottom surface of the second conductivity type connecting layer is located on the side of the first conductivity type impurity high concentration containing layer that is located, relative to the bottom surface of the gate trench.

4. The semiconductor element according to claim 1 or 2, wherein the entire side surface of the second conductive type connecting layer is exposed to the gate trench and is covered by the gate insulating film.

5. A recess formed so as to extend from the first conductive impurity high-concentration layer to the second conductive body layer, A second conductivity type void-filling layer is provided to fill the recess and contains a second conductivity type impurity at a higher concentration than the second conductivity type block layer, Equipped with, The semiconductor element according to claim 1 or 2, wherein the source electrode is provided so as to cover the second conductivity type hole-filling layer.

6. A method for manufacturing a semiconductor device according to claim 1 or 2, Preparation steps for preparing a laminate comprising the substrate, the main drift layer, the second conductivity type block layer, the sub-drift layer, the second conductivity type body layer, and the first conductivity type impurity high concentration containing layer, A deep trench forming step in which a deep trench, which is a groove, is formed in the laminate that extends from the first conductivity type impurity high concentration layer to at least the second conductivity type block layer, A second conductivity type connecting layer formation step, in which the second conductivity type connecting layer is formed to fill the deep trench, A gate trench forming step is performed in a region including the junction between the circumferential surface of the second conductivity type connecting layer and the wall surface of the deep trench, by removing at least the sub-drift layer from the first conductivity type impurity high-concentration layer to form a gate trench, thereby exposing at least a portion of the side surface of the second conductivity type connecting layer. A gate insulating film forming step, which involves forming the gate insulating film that covers the bottom surface and side surface of the gate trench, A gate electrode formation step in which the gate electrode is formed along the bottom surface and side surface of the gate trench via the gate insulating film, A source electrode formation step in which the source electrode connected to the second conductivity type connecting layer is formed, A method for manufacturing semiconductor devices, including

7. After the deep trench forming step, the process includes a recess forming step in which the first conductive impurity high-concentration-containing layer is removed from the second conductive body layer in the region above the opening to form a recess, A method for manufacturing a semiconductor device according to claim 6, wherein, after the recess formation step, in the second conductivity type connection layer formation step, the deep trench is filled to form the second conductivity type connection layer and the recess is filled to form the second conductivity type hole filling layer.

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