Semiconductor equipment

Abstract

This suppresses the discharge current when interlayer cracks occur at the edges of a semiconductor substrate. [Solution] The semiconductor device comprises a semiconductor substrate (10) and a molding resin (7) covering the upper surface and end surface of the semiconductor substrate (10). The semiconductor substrate (10) has an effective region (1) through which the main current flows, a voltage-resistant holding region (2) provided outside the effective region (1) and having a p-type voltage-resistant holding structure (15) formed thereon, and an outer peripheral region (3) provided outside the voltage-resistant holding region (2). At least a part of the surface layer of the outer peripheral region (3) has n + An impurity layer (11) is formed. + At least a portion of the surface layer of the impurity layer (11) contains p + An impurity layer (12) is formed.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device, and more particularly to a semiconductor device having a structure sealed with a molded resin. [Background technology]

[0002] For example, a highly concentrated n-type impurity layer is formed on the outer periphery of a semiconductor chip used for power control, which functions as a channel stopper to keep the depletion layer within the semiconductor chip (see, for example, Patent Document 1 below). [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2004-335739 [Overview of the project] [Problems that the invention aims to solve]

[0004] In THB (temperature humidity bias) reliability tests, semiconductor devices can be damaged (e.g., by cracking) due to expansion and contraction stress. This damage is likely to occur at the interface between the semiconductor substrate and the molding resin, starting from the edges of the semiconductor chip where expansion and contraction stress is concentrated. Cracks that occur between different layers in this way are called "interlayer cracks."

[0005] In semiconductor devices equipped with a semiconductor chip having a high-concentration n-type impurity layer on its outer periphery, the surface at the edge of the semiconductor substrate is electron-rich. Therefore, if an interlayer crack occurs at the edge of the semiconductor substrate during a THB test, the discharge current is likely to flow to foreign matter probabilistically present on the surface of the semiconductor substrate. When a discharge current flows, the formation of oxides on the surface of the semiconductor substrate is promoted, and the interlayer crack further progresses.

[0006] The present disclosure has been made to solve the above problems, and an object thereof is to suppress a discharge current when an interlayer crack occurs at an end portion of a semiconductor substrate in a semiconductor device including a semiconductor substrate provided with a high-concentration n-type impurity layer in an outer peripheral portion.

Means for Solving the Problems

[0007] The semiconductor device according to the present disclosure includes a semiconductor substrate having an effective region through which a main current flows, a breakdown voltage holding region provided outside the effective region and having a p-type breakdown voltage holding structure formed therein, and an outer peripheral region provided outside the breakdown voltage holding region, an n-type impurity layer formed in at least a part of a surface layer portion of the outer peripheral region, a p-type impurity layer formed in at least a part of a surface layer portion of the n-type impurity layer, and a molding resin covering an upper surface and an end surface of the semiconductor substrate.

Effects of the Invention

[0008] According to the present disclosure, it is possible to suppress a discharge current when an interlayer crack occurs at an end portion of a semiconductor substrate.

Brief Description of the Drawings

[0009] [Figure 1] FIG. 1 is a diagram showing a configuration of a semiconductor device according to Embodiment 1. [Figure 2] FIG. 2 is a diagram showing a modification of the semiconductor device according to Embodiment 1. [Figure 3] FIG. 3 is a diagram showing a planar configuration of the semiconductor device according to Embodiment 1. [Figure 4] FIG. 4 is a diagram showing a modification of the semiconductor device according to Embodiment 1. [Figure 5] FIG. 5 is a diagram showing a modification of the semiconductor device according to Embodiment 1. [Figure 6] FIG. 6 is a diagram showing a configuration of a semiconductor device according to Embodiment 2. [Figure 7] FIG. 7 is a diagram showing a configuration of a semiconductor device according to Embodiment 3.

Modes for Carrying Out the Invention

[0010] In the following embodiments, "n" and "p" represent the conductivity type of the semiconductor. Furthermore, an n-type semiconductor with a relatively high impurity concentration is referred to as "n + ", n-type with a relatively low impurity concentration is called "n - ", and P-type with a relatively high impurity concentration is called "p + ", and p-type with a relatively low impurity concentration is called "p - It is sometimes written as "[...]". The level of impurity concentration in each region is determined by the peak concentration of the impurity. In other words, a region with high (or low) impurity concentration means a region with high (or low) peak concentration of impurity.

[0011] <Embodiment 1> Figure 1 shows the configuration of a semiconductor device according to Embodiment 1. As shown in Figure 1, the semiconductor device includes a semiconductor chip made of a semiconductor substrate 10. The semiconductor substrate 10 consists of a SiC substrate 9 and a SiC epitaxial layer 8 formed thereon. Here, an example is shown in which the semiconductor substrate 10 is made of SiC (silicon carbide), but the semiconductor substrate 10 may be made of, for example, Si (silicon).

[0012] The semiconductor substrate 10 comprises an effective region 1 through which the main current flows, a withstand voltage holding region 2 located outside the effective region 1, and an outer peripheral region 3 located further outside the withstand voltage holding region 2.

[0013] In the active region 1, semiconductor elements such as, for example, MOSFET (Metal Oxide Semiconductor Field Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), Schottky barrier diode (SBD), and PN junction diode are formed. In the present embodiment, it is assumed that the semiconductor element formed on the semiconductor substrate 10 is a MOSFET. In FIG. 1, the ends of the source electrode 13 and the base layer 14 of the MOSFET are depicted. When the semiconductor element formed in the active region 1 is a MOSFET, the SiC epitaxial layer 8 becomes an n-type drift layer, and the SiC substrate 9 becomes an n-type drain layer. When the semiconductor element formed in the active region 1 is an IGBT, the SiC epitaxial layer 8 becomes an n-type drift layer, and the SiC substrate 9 becomes a p-type collector layer.

[0014] In the breakdown voltage holding region 2 of the semiconductor substrate 10, a p-type breakdown voltage holding structure 15 (for example, a guard ring, etc.) is formed.

[0015] The outer peripheral region 3 is the outermost peripheral portion of the semiconductor substrate 10, that is, the region at the end of the semiconductor chip. In the outer peripheral region 3, an n + impurity layer 11, which is a high-concentration n-type impurity layer functioning as a channel stopper, is formed in at least a part of the surface layer portion of the semiconductor substrate 10. Also, an n + impurity layer 11, and in at least a part of the surface layer portion of the p + impurity layer 12, which is a high-concentration p-type impurity layer, is formed. In FIG. 1, the n + impurity layer 11 reaches the end of the semiconductor substrate 10 (the end of the semiconductor chip), but the n + impurity layer 11 does not have to reach the end of the semiconductor substrate 10.

[0016] A field oxide film 4 is formed on the upper surface of the semiconductor substrate 10, extending from the outer periphery of the effective region 1 to the inner periphery of the outer periphery region 3. A nitride film 5 is formed on top of the field oxide film 4. Furthermore, a protective film 6 made of polyimide resin is formed on top of the field oxide film 4 and the nitride film 5. The nitride film 5 covers the outer edge of the field oxide film 4, and the protective film 6 covers the outer edge of the nitride film 5. Therefore, not only the field oxide film 4, but also the nitride film 5 and the protective film 6 have portions that are in contact with the semiconductor substrate 10. Note that the nitride film 5 may be omitted.

[0017] The semiconductor device is sealed by a molding resin 7 that covers the top and end surfaces of the semiconductor substrate 10.

[0018] Thus, the upper surface of the outer peripheral region 3 of the semiconductor substrate 10 is covered with a field oxide film 4, a nitride film 5, a protective film 6, and a mold resin 7. For example, n + If only the impurity layer 11 is formed, the upper surface of the outer peripheral region 3 becomes electron-rich. In this state, if interlayer cracks occur between the semiconductor substrate 10 and the field oxide film 4, nitride film 5, protective film 6, or mold resin 7 covering it due to expansion and contraction stress, a discharge current flows through that area, generating oxides and making the interlayer cracks more likely to propagate further.

[0019] In contrast, in this embodiment, n + p + An impurity layer 12 is formed, which reduces the electron-rich region. As a result, the discharge current when interlayer cracks occur is suppressed, and the generation of oxides is inhibited, thus suppressing the propagation of interlayer cracks. Consequently, the semiconductor device is less likely to fail to withstand voltage.

[0020] Here, among the field oxide film 4, nitride film 5, protective film 6, and mold resin 7, the adhesion to the semiconductor substrate 10 is highest for the field oxide film 4 or nitride film 5, followed by the protective film 6, and then the mold resin 7. Therefore, interlayer cracks are likely to occur at the interface between the semiconductor substrate 10 and the mold resin 7. Therefore, p + It is preferable that the impurity layer 12 is positioned such that at least a portion of its upper surface is in contact with the mold resin 7.

[0021] Furthermore, the above effect is p + The higher the impurity concentration in the impurity layer 12, the better the result. In this embodiment, p + The lateral impurity concentration in the impurity layer 12 is uniform, but for example, as shown in Figure 2, p + When the impurity layer 12 is divided into a first region 12a whose upper surface is in contact with the mold resin 7, a second region 12b whose upper surface is in contact with the field oxide film 4, a third region 12c whose upper surface is in contact with the nitride film 5, and a fourth region 12d whose upper surface is in contact with the protective film 6, the region with lower adhesion to the upper layer has a lower p + The impurity concentration in the impurity layer 12 may be increased. That is, p in the first region 12a + The impurity concentration of the impurity layer 12 is set to p in the second region 12b. + The impurity concentration in the impurity layer 12 may be higher than that of the impurity layer 12. p in the first region 12a + The impurity concentration of the impurity layer 12 is set to p in the third region 12c. + The impurity concentration in the impurity layer 12 may be higher than that of the impurity layer 12. p in the first region 12a + The impurity concentration of the impurity layer 12 is set to p in the fourth region 12d. + The impurity concentration in the impurity layer 12 may be higher than that of the impurity layer 12. p in the fourth region 12d + The impurity concentration of the impurity layer 12 is set to p in the second region 12b. + The impurity concentration in the impurity layer 12 may be higher than that of the impurity layer 12. p in the fourth region 12d + The impurity concentration of the impurity layer 12 is set to p in the third region 12c. + The impurity concentration may be higher than that of the impurity layer 12.

[0022] Figure 3 is a diagram showing the planar configuration of the semiconductor device according to Embodiment 1. In Figure 3, the element labeled "16" is a gate pad for inputting a signal to the gate electrode (not shown) of the MOSFET. Generally, n as a channel stopper + The impurity layer 11 is formed in a ring shape on the outer periphery of the semiconductor substrate 10. Therefore, as shown in Figure 3, p + The impurity layer 12 is also n + It is preferable that it be formed in a ring shape on the surface of the impurity layer 11. However, p + The impurity layer 12 does not necessarily have to be ring-shaped. For example, if the semiconductor substrate 10 is rectangular in plan view, expansion and contraction stresses are concentrated at the corners of the semiconductor substrate 10, so interlayer cracks are likely to occur at the corners of the semiconductor substrate 10. Therefore, at least at the corners of the semiconductor substrate 10, p + If the impurity layer 12 is formed, a certain effect can be obtained. For example, as shown in Figure 4 or Figure 5, p is formed only at the corners of the semiconductor substrate 10. + An impurity layer 12 may be formed.

[0023] In this embodiment, an example is shown in which the semiconductor substrate 10 is composed of a material containing SiC (silicon carbide). SiC semiconductor devices have excellent operation at high temperatures, and since they are intended for use in high-temperature environments, the effect of preventing the failure of the semiconductor device due to expansion and contraction stress is particularly effective for SiC semiconductor devices.

[0024] <Embodiment 2> Figure 6 is a diagram showing the configuration of the semiconductor device according to Embodiment 2. The configuration of the semiconductor device according to Embodiment 2 is different from the configuration of Embodiment 1 (Figure 1), p + The outer edge of the impurity layer 12 is n + p + The impurity layer 12 is stretched. In this embodiment, p + The impurity layer 12 has at least n + It is formed on the surface layer at the outer edge of the impurity layer 11. The other components are the same as in Embodiment 1, so their description is omitted here.

[0025] Interlayer cracks often originate from the edges of the semiconductor substrate 10. + p + By providing the impurity layer 12, the effect of suppressing the propagation of interlayer cracks is improved.

[0026] <Embodiment 3> Figure 7 is a diagram showing the configuration of a semiconductor device according to Embodiment 3. The configuration of the semiconductor device according to Embodiment 3 is different from the configuration of Embodiment 1 (Figure 1), p + The impurity layer 12 is n + This is formed on the entire surface layer of the impurity layer 11. The other components are the same as in Embodiment 1, so their description is omitted here.

[0027] In this embodiment, n + p + Because the impurity layer 12 is formed, there are no electron-rich regions on the upper surface of the outer peripheral region 3. Therefore, it is possible to prevent the generation of discharge current when interlayer cracks occur, and thus prevent the formation of oxides. Thus, the effect of suppressing the propagation of interlayer cracks is further improved compared to embodiments 1 and 2.

[0028] Furthermore, it is possible to freely combine each embodiment, or to modify or omit each embodiment as appropriate.

[0029] <Note> The various aspects of this disclosure are summarized below as an appendix.

[0030] (Note 1) A semiconductor substrate having an effective region through which the main current flows, a voltage-resistant region provided outside the effective region and having a p-type voltage-resistant holding structure formed thereon, and an outer peripheral region provided outside the voltage-resistant holding region, An n-type impurity layer formed in at least a portion of the surface layer of the outer peripheral region, A p-type impurity layer formed on at least a portion of the surface layer of the n-type impurity layer, A molding resin covering the upper surface and end surface of the semiconductor substrate, Equipped with, Semiconductor equipment.

[0031] (Note 2) The p-type impurity layer is formed at least on the surface layer of the outer edge of the n-type impurity layer. The semiconductor device described in Appendix 1.

[0032] (Note 3) The p-type impurity layer is formed over the entire surface layer of the n-type impurity layer. The semiconductor device described in Appendix 1.

[0033] (Note 4) At least a portion of the upper surface of the p-type impurity layer is in contact with the mold resin. A semiconductor device described in any one of the appendices 1 through 3.

[0034] (Note 5) The semiconductor substrate is rectangular in plan view. The n-type impurity layer is formed in an annular shape on the outer periphery of the semiconductor substrate. The p-type impurity layer is formed at least on the surface of the n-type impurity layer at the rectangular corners. A semiconductor device described in any one of the appendices 1 through 4.

[0035] (Note 6) The n-type impurity layer is formed in an annular shape on the outer periphery of the semiconductor substrate. The p-type impurity layer is formed in an annular shape on the surface of the n-type impurity layer. A semiconductor device described in any one of the appendices 1 through 4.

[0036] (Note 7) The aforementioned semiconductor substrate is made of a material containing silicon carbide. A semiconductor device as described in any one of the appendices 1 through 5. [Explanation of symbols]

[0037] 1 Effective area, 2 Pressure-bearing area, 3 Outer peripheral area, 4 Field oxide film, 5 Nitride film, 6 Protective film, 7 Molding resin, 8 SiC epitaxial layer, 9 SiC substrate, 10 Semiconductor substrate, 11 n + Impurity layer, 12p + 13 Impurity layer, 14 Source electrode, 15 Base layer, 16 Pressure-resistant holding structure, 12a First region, 12b Second region, 12c Third region, 12d Fourth region.

Claims

1. A semiconductor substrate having an effective region through which the main current flows, a voltage-resistant region provided outside the effective region and having a p-type voltage-resistant holding structure, and an outer peripheral region provided outside the voltage-resistant holding region, An n-type impurity layer formed in at least a portion of the surface layer of the outer peripheral region, A p-type impurity layer formed on at least a portion of the surface layer of the n-type impurity layer, A molding resin covering the upper surface and end surface of the semiconductor substrate, Equipped with, Semiconductor equipment.

2. The p-type impurity layer is formed at least on the surface layer of the outer edge of the n-type impurity layer. The semiconductor device according to claim 1.

3. The p-type impurity layer is formed over the entire surface layer of the n-type impurity layer. The semiconductor device according to claim 1.

4. At least a portion of the upper surface of the p-type impurity layer is in contact with the mold resin. The semiconductor device according to any one of claims 1 to 3.

5. The semiconductor substrate is rectangular in plan view. The n-type impurity layer is formed in an annular shape on the outer periphery of the semiconductor substrate. The p-type impurity layer is formed at least on the surface of the n-type impurity layer at the corners of the rectangle. The semiconductor device according to any one of claims 1 to 3.

6. The n-type impurity layer is formed in an annular shape on the outer periphery of the semiconductor substrate. The p-type impurity layer is formed in an annular shape on the surface of the n-type impurity layer. The semiconductor device according to any one of claims 1 to 3.

7. The aforementioned semiconductor substrate is made of a material containing silicon carbide. The semiconductor device according to any one of claims 1 to 3.

Images