Differential amplifier circuit

Abstract

This invention provides a differential amplifier circuit with high voltage resistance and a wide common-mode input range. [Solution] The differential amplifier circuit 1 comprises a tail current source 23, a P-type differential input section 24, a tail current source 25, and an N-type differential input section 26. A common-mode tracker circuit 21 tracks the common-mode components of the input voltages INM and INP and generates a tracking voltage VT1 that is higher than the common-mode components. The tracking voltage VT1 is supplied to the tail current source 23. The folded cascode circuit 27 has transistors M21 and M22 that fold back the current flowing through the N-type differential input section 26 and add it to the output of the P-type differential input section 24, and transistors M23 and M24 that are cascode-connected to the supply line L1 and transistors M21 and M22, respectively.

Description

Technical Field

[0001] The present invention relates to a differential amplifier circuit.

Background Art

[0002] Conventionally, as a differential amplifier circuit, the one shown in FIG. 12 has been proposed (Non-Patent Document 1). As shown in the figure, the differential amplifier circuit 100 includes a tail current source 101 and differential transistors M101 and M102 that shunt the current supplied from the tail current source 101. Input voltages INM and INP are input to the gates of the differential transistors M101 and M102. Further, the differential amplifier circuit 100 includes high-voltage-tolerant transistors M103 and M104 that are cascode-connected to the differential transistors M101 and M102, respectively. These high-voltage-tolerant transistors M103 and M104 protect the low-voltage-tolerant differential transistors M101 and M102 from high voltages.

[0003] However, the differential amplifier circuit 100 shown in FIG. 12 has a problem that the common-mode input voltage range is narrow. As a method of widening the common-mode input range, a Rail-to-Rail configuration including a P-type differential transistor and an N-type differential transistor is known (Patent Documents 1 to 3).

[0004] However, there is a problem that a high-voltage-tolerant N-type differential transistor is greatly affected by the substrate bias effect because its bulk terminal is connected to a negative power supply voltage VSS (for example, 0V).

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Patent Document 3

Non-Patent Document

[0006] [Non-Patent Document 1] V. Schaffer, MFSnoeij, and MV Ivanov, “A 36 V Programmable Instrumentation Amplifier With Sub-20 μV Offset and a CMRR in Excess of 120dB at All Gain Settings”, IEEE J. Solid-State Circuits, vol.44, no. 7, pp.2036-2046, July 2009. [Overview of the project] [Problems that the invention aims to solve]

[0007] The present invention has been made in view of the above circumstances, and its purpose is to provide a differential amplifier circuit with high voltage resistance and a wide common-mode input range. [Means for solving the problem]

[0008] To achieve the aforementioned objectives, the differential amplifier circuit according to the present invention is characterized by the following [1] to

[13] . [1] A differential amplifier circuit that amplifies the difference between a first input voltage and a second input voltage, A first tracking voltage generation circuit that fluctuates in accordance with either the first input voltage or the second input voltage and generates a first tracking voltage that is higher than either of the first or second input voltages, or a first tracking voltage that fluctuates in accordance with the common-mode component of the first input voltage and the second input voltage and generates a first tracking voltage that is higher than the common-mode component, A first current source, one end of which is connected to the supply line of the first tracking voltage, A first differential input section having a first P-type differential transistor and a second differential transistor, the source or emitter of which is connected to the other end of the first current source, and the gate or base of which are supplied with the first input voltage and the second input voltage, respectively, A second current source to which power supply voltage is supplied, A second differential input section having a third N-type differential transistor and a fourth differential transistor, the source or emitter of which is connected to the other end of the second current source, and the gate or base of which are supplied with the first input voltage and the second input voltage, A folded cascode circuit comprising: a first transistor that folds back the current flowing through the third differential transistor and adds it to the output of the first differential input section; a second transistor that folds back the current flowing through the fourth differential transistor and adds it to the output of the first differential input section; a third transistor cascode-connected between the supply line of the first tracking voltage and the first transistor; and a fourth transistor cascode-connected between the supply line of the first tracking voltage and the second transistor, It is a differential amplifier circuit. [2] In the differential amplifier circuit described in [1], The first current source has the supply line for the first tracking voltage and a fifth transistor connected between the source or emitter of the first differential transistor and the second differential transistor. The difference voltage between the first tracking voltage and the tracking voltage is set to be greater than or equal to the sum of the voltage at which the drain-source voltage of the fifth transistor satisfies the saturation condition or the collector-emitter voltage satisfies the activation condition, and the threshold voltage of the gate-source voltage or base-emitter voltage of the first differential transistor and the second differential transistor. It is a differential amplifier circuit. [3] In the differential amplifier circuit described in [1], The third and fourth differential transistors are composed of N-type electrolytic effect transistors, and use HVDeepNWELL elements. It is a differential amplifier circuit. [4] In the differential amplifier circuit described in [3], The bulk terminals of the third differential transistor and the fourth differential transistor are connected to the source terminals. It is a differential amplifier circuit. [5] In the differential amplifier circuit according to [3], The bulk terminals of the third differential transistor and the fourth differential transistor are connected to a voltage lower than the source terminal. It is a differential amplifier circuit. [6] In the differential amplifier circuit according to [1], A first high-breakdown-voltage transistor having a higher breakdown voltage than the first differential transistor, which is cascode-connected to the first differential transistor; A second high-breakdown-voltage transistor having a higher breakdown voltage than the second differential transistor, which is cascode-connected to the second differential transistor, further comprising: It is a differential amplifier circuit. [7] In the differential amplifier circuit according to [6], The first high-breakdown-voltage transistor and the second high-breakdown-voltage transistor are composed of depletion transistors. It is a differential amplifier circuit. [8] In the differential amplifier circuit according to [7], A second follower voltage generation circuit that varies following either one of the first input voltage and the second input voltage, and generates a second follower voltage lower than the one, or varies following the common-phase component of the first input voltage and the second input voltage, and generates a second follower voltage lower than the common-phase component, is provided. The second follower voltage is supplied to the gates of the first high-breakdown-voltage transistor and the second high-breakdown-voltage transistor. It is a differential amplifier circuit. [9] In the differential amplifier circuit according to [7], The gate of the first high-breakdown-voltage transistor is connected to the gate of the first differential transistor. The gate of the second high-voltage transistor is connected to the gate of the second differential transistor. It is a differential amplifier circuit.

[10] In the differential amplifier circuit according to [1], The first transistor and the second transistor included in the folded cascode circuit are composed of high-voltage transistors with a higher breakdown voltage than the third transistor and the fourth transistor. It is a differential amplifier circuit.

[11] In the differential amplifier circuit according to [1], A clamp protection circuit that limits the voltage between the drain or collector of the first differential transistor and the supply line of the first follower voltage, and the voltage between the drain or collector of the second differential transistor and the supply line of the first follower voltage. It is a differential amplifier circuit.

[12] In the differential amplifier circuit according to

[11] , The clamp protection circuit is composed of a plurality of diodes. It is a differential amplifier circuit.

[13] In the differential amplifier circuit according to

[12] , The diode is composed of a diode-connected transistor. It is a differential amplifier circuit.

Effect of the Invention

[0009] According to the present invention, a differential amplifier circuit with high breakdown voltage and a wide common-phase input range can be provided.

[0010] The present invention has been briefly described above. Further, the details of the present invention will be further clarified by reading through the embodiments for carrying out the invention described below (hereinafter referred to as "embodiments") with reference to the attached drawings.

Brief Description of the Drawings

[0011] [Figure 1] Figure 1 is a circuit diagram showing a differential amplifier circuit in the first embodiment. [Figure 2] Figure 2 is a circuit diagram showing the circuit that generates the tracking voltage VT1_1 shown in Figure 1. [Figure 3] Figure 3 is a circuit diagram showing the circuit that generates the tracking voltages VT1_2 and VT1_3 shown in Figure 1. [Figure 4] Figure 4 is a circuit diagram showing an example of the common-mode tracker circuit shown in Figure 1. [Figure 5] Figure 5 is a circuit diagram showing a differential amplifier circuit in the second embodiment. [Figure 6] Figure 6 is a circuit diagram showing a differential amplifier circuit in the third embodiment. [Figure 7] Figure 7 is a circuit diagram showing a differential amplifier circuit in the fourth embodiment. [Figure 8] Figure 8 is a circuit diagram showing a differential amplifier circuit in the fifth embodiment. [Figure 9] Figure 9 is a circuit diagram showing a differential amplifier circuit in the sixth embodiment. [Figure 10] Figure 10 is a circuit diagram showing a differential amplifier circuit in the seventh embodiment. [Figure 11] Figure 11 is a circuit diagram showing a differential amplifier circuit in the eighth embodiment. [Figure 12] Figure 12 is a circuit diagram showing an example of a conventional differential amplifier circuit. [Modes for carrying out the invention]

[0012] Specific embodiments of the present invention will be described below with reference to the figures.

[0013] (First Embodiment) First, the differential amplifier circuit 1 of the first embodiment will be described with reference to Figure 1. The differential amplifier circuit 1 shown in the figure is a circuit that amplifies the difference between the input voltage INM (first input voltage) input to input terminal T1 and the input voltage INP (second input voltage) input to input terminal T2, and outputs it as an output signal VOUT from output terminal T3.

[0014] The differential amplifier circuit 1 comprises an input section 2, a Class AB output section 3, and a control circuit 4. The input section 2 outputs a differential current corresponding to the difference between the input voltages INM and INP. The input section 2 includes a common-mode tracker circuit 21 (first tracking voltage generation circuit), a common-mode tracker circuit 22 (second tracking voltage generation circuit), a tail current source 23 (first current source), a differential input section 24 (first differential input section), a tail current source 25 (second current source), a differential input section 26 (second differential input section), and an aliasing cascode circuit 27.

[0015] The common-mode tracker circuit 21 fluctuates in accordance with the common-mode input voltage, which is the common-mode component of the input voltages INM and INP, and generates a tracking voltage VT1 (first tracking voltage) that is higher than the common-mode input voltage and supplies it to the supply line L1. The common-mode tracker circuit 21 outputs a level-shifted voltage obtained by adding a predetermined voltage to the common-mode input voltage as the tracking voltage VT1. The common-mode tracker circuit 22 fluctuates in accordance with the common-mode input voltage and generates a tracking voltage VT2 (second tracking voltage) that is lower than the common-mode input voltage. The common-mode tracker circuit 22 outputs a level-shifted voltage obtained by subtracting a predetermined voltage from the common-mode input voltage as the tracking voltage VT2.

[0016] The tail current source 23 consists of a transistor M25. Transistor M25 is a P-type electrolytic effect transistor. The source of transistor M25 is connected to supply line L1. The gate of transistor M25 is supplied with a tracking voltage VT1_1, which is generated based on the tracking voltage VT1 generated from the common-mode tracker circuit 22.

[0017] More specifically, as shown in Figure 2, the differential amplifier circuit 1 further comprises a transistor M4 and a current source 29. Transistor M4 is a P-type electrolytic effect transistor. The source of transistor M4 is connected to the supply line L1, and the gate and drain are connected. The current source 29 is connected between the gate and drain of transistor M4 and the negative power supply terminal T4. The gate of transistor M25 is connected to the gate and drain of transistor M4. Transistor M25 is supplied with a tracking voltage VT1_1, which is the tracking voltage VT1 minus the gate-source voltage of transistor M4, and the current flowing through transistor M4 is folded back. By supplying such a tracking voltage VT1_1 to the gate of transistor M25, the gate-source voltage of transistor M25 remains constant even when the common-mode input voltage fluctuates, and the drain current of transistor M25 remains constant.

[0018] The differential input section 24 outputs a differential current corresponding to the input voltages INM and INP. The differential input section 24 includes a differential transistor M11 (first differential transistor) and a differential transistor M12 (second differential transistor), and high-voltage transistors M31 (first high-voltage transistor M31) and M32 (second high-voltage transistor).

[0019] The differential transistors M11 and M12 are composed of P-type electrolytic effect transistors. The sources of the differential transistors M11 and M12 are connected to the drain of transistor M25. The gate of differential transistor M11 is connected to input terminal T1 and supplied with input voltage INM. The gate of differential transistor M12 is connected to input terminal T2 and supplied with input voltage INP.

[0020] The current supplied from the tail current source 23 is divided among the differential transistors M11 and M12. The current ratio (division ratio) flowing through the differential transistors M11 and M12 is a value corresponding to the input voltages INM and INP. The difference in current flowing through these differential transistors M11 and M12 is output as the differential current.

[0021] The high-voltage transistors M31 and M32 are composed of transistors with higher voltage ratings than the differential transistors M11 and M12. Furthermore, the high-voltage transistors M31 and M32 are composed of depletion transistors that can conduct current even when the gate potential equals the source potential. The source of high-voltage transistor M31 is connected to the drain of differential transistor M11, and its drain is connected to the input of control circuit 4. High-voltage transistor M31 is cascode-connected to differential transistor M11. The source of high-voltage transistor M32 is connected to the drain of differential transistor M12, and its drain is connected to the input of control circuit 4. High-voltage transistor M32 is cascode-connected to differential transistor M12. The gates of high-voltage transistors M31 and M32 are connected to each other, and a tracking voltage VT2 is supplied.

[0022] One end of the tail current source 25 is connected to the negative power supply terminal T4. The negative power supply terminal T4 is supplied with a negative power supply voltage VSS (e.g., 0V) that is lower than the tracking voltages VT1 and VT2.

[0023] The differential input section 26 outputs a differential current corresponding to the input voltages INM and INP. The differential input section 26 has a differential transistor M13 (third differential transistor) and a differential transistor M14 (fourth differential transistor). Differential transistors M13 and M14 are composed of N-type electrolytic effect transistors. The sources of differential transistors M13 and M14 are connected to the other end of the tail current source 25. The gate of differential transistor M13 is connected to input terminal T1 and supplied with input voltage INM. The gate of differential transistor M14 is connected to input terminal T2 and supplied with input voltage INP.

[0024] In this embodiment, high-voltage HVDeepNWELL elements are used as differential transistors M13 and M14. The bulk terminals of differential transistors M13 and M14 are connected to the source terminals or to a voltage lower than the source terminals to prevent current from flowing between the source and bulk terminals.

[0025] The current supplied from the tail current source 25 is divided among the differential transistors M13 and M14. The current ratio (division ratio) flowing through the differential transistors M13 and M14 is a value corresponding to the input voltages INM and INP. The difference in current flowing through these differential transistors M13 and M14 is output as the differential current.

[0026] The folded cascode circuit 27 has transistors M21 (first transistor), M22 (second transistor), M23 (third transistor), and M24 (fourth transistor). Transistors M21 to M24 are composed of P-type electrolytic effect transistors.

[0027] Transistor M21 has its source connected to the drain of differential transistor M13, and its drain connected to the drain of differential transistor M11. Transistor M22 has its source connected to the drain of differential transistor M14, and its drain connected to the drain of differential transistor M12. Transistors M21 and M22 have their gates connected to each other and are supplied with a tracking voltage VT1_2.

[0028] Transistor M23 has its source connected to supply line L1 and its drain connected to the source of transistor M21. Transistors M21 and M23 are cascode-connected. Transistor M24 has its source connected to supply line L1 and its drain connected to the source of transistor M22. Transistors M22 and M24 are cascode-connected. Transistors M23 and M24 have their gates connected to each other and are supplied with a tracking voltage VT1_3.

[0029] The tracking voltages VT1_2 and VT1_3 are generated based on the tracking voltage VT1 generated from the common-mode tracker circuit 22. The generation of the tracking voltages VT1_2 and VT1_3 will be explained with reference to Figure 3. Note that in Figure 3, transistors M22 and M24 are omitted for simplicity. As shown in the figure, the differential amplifier circuit 1 further includes transistor M5, current source 210, transistor M6, and current source 211.

[0030] Transistors M5 and M6 are P-type electrolytic effect transistors. Transistors M5 and M6 have their sources connected to supply line L1 and their gates and drains connected. Current source 210 is connected between the gate and drain of transistor M5 and the negative power supply terminal T4. Current source 211 is connected between the gate and drain of transistor M6 and the negative power supply terminal T4.

[0031] Transistors M21 and M22 have their gates connected to the gate-drain of transistor M5. Transistors M21 and M22 are supplied with a tracking voltage VT1_2, which is obtained by subtracting the gate-source voltage of transistor M5 from the tracking voltage VT1. Transistors M23 and M24 have their gates connected to the gate-drain of transistor M6. Transistors M23 and M24 are supplied with a tracking voltage VT1_3, which is obtained by subtracting the gate-source voltage of transistor M6 from the tracking voltage VT1.

[0032] The drain current of differential transistor M13 is folded back into transistor M21, and this folded drain current is added to the drain current of differential transistor M11. The drain current of differential transistor M14 is folded back into transistor M22, and this folded drain current is added to the drain current of transistor M12. In other words, the differential current output from differential input section 24 and the differential current output from differential input section 26 are added together and supplied to control circuit 4.

[0033] The Class AB output section 3 includes transistors M41 and M42, and capacitors C1 and C2. Transistor M41 is a P-type electrolytic effect transistor. The source of transistor M41 is connected to the positive power supply terminal T5, and the drain is connected to the output terminal T3. The positive power supply voltage VDD is supplied to the positive power supply terminal T5. Capacitor C1 is connected between the gate and drain of transistor M41. The source of transistor M42 is connected to the negative power supply terminal T4, and the drain is connected to the output terminal T3. Capacitor C2 is connected between the gate and drain of transistor M42.

[0034] The control circuit 4 is a circuit that controls the current flowing through transistors M41 and M42, which constitute the Class AB output section 3, in accordance with the differential current input to the control circuit 4 from the input section 2. More specifically, the control circuit 4 has a bias circuit 41. The bias circuit 41 outputs the bias voltage of transistor M41 and the bias voltage of transistor M42. The control circuit 4 controls the current to flow through one of transistors M41 and M42 by lowering the bias voltage of one of transistors M41 and M42 in accordance with the differential current. When the bias voltage of one of transistors M41 and M42 is lowered, the bias circuit 41 raises the bias voltage of the other transistor M41 and M42 to control the current to flow through the other transistor M41 and M42 to increase.

[0035] Next, the detailed configuration of the common-mode tracker circuits 21 and 22 described above will be explained with reference to Figure 4. The common-mode tracker circuit 21 has a source follower configuration with a current source 211 and transistors M51 and M52. One end of the current source 211 is connected to the positive power supply terminal T5. Transistors M51 and M52 are made up of P-type electrolytic effect transistors.

[0036] Transistors M51 and M52 have their sources connected to the other end of the current source 211. Input terminal T1 is connected to the gate of transistor M51, supplying the input voltage INM. Input terminal T2 is connected to the gate of transistor M52, supplying the input voltage INP. The drains of transistors M51 and M52 are connected to the negative power supply terminal T4. The source potential of transistors M51 and M52 is the input common-mode voltage {(INM+INP) / 2} plus the average value of the gate-source voltages of transistors M51 and M52, and this is output as the tracking voltage VT1.

[0037] Here, the value added to the input common-mode voltage (= the average value of the gate-source voltages of transistors M51 and M52) must be set to a value that satisfies the following equation (1).

[0038] The sum of the values ​​is greater than or equal to the voltage at which the drain-source voltage of transistor M25 satisfies the saturation condition + the threshold voltage of the gate-source voltages of differential transistors M11 and M12…(1)

[0039] By setting the summation value as shown in equation (1), differential transistors M11 and M12 can be turned on. In addition, transistor M25 can supply a constant drain current to differential transistors M11 and M12.

[0040] The common-mode tracker circuit 22 has a source follower configuration comprising a current source 221 and transistors M61 and M62. One end of the current source 221 is connected to the negative power supply terminal T4. Transistors M61 and M62 are composed of N-type electrolytic effect transistors.

[0041] Transistors M61 and M62 have their sources connected to the other end of the current source 221. Input terminal T1 is connected to the gate of transistor M61, supplying the input voltage INM. Input terminal T2 is connected to the gate of transistor M62, supplying the input voltage INP. The drains of transistors M61 and M62 are connected to the sources of transistors M51 and M52. The source potential of transistors M61 and M62 is the common-mode input voltage minus the average of the gate-source voltages of transistors M61 and M62, and this is output as the tracking voltage VT2.

[0042] In the embodiment described above, the drains of transistors M61 and M62 are connected to the sources of transistors M51 and M52. Therefore, the drain-source voltage of transistors M61 and M62 remains constant regardless of the common-mode input voltage, protecting transistors M61 and M62 from high voltage. In this embodiment, transistors M51 and M52 are made of high-voltage transistors with higher voltage ratings than transistors M61 and M62, thus protecting them from high voltage.

[0043] Next, the operation of the differential amplifier circuit 1 with the above configuration will be explained. We will explain the case when the common-mode input voltage is low and close to the negative power supply voltage VSS. In this case, the gate-source voltage of the differential transistors M13 and M14 cannot be made above the threshold voltage, and the N-type differential transistors M13 and M14 cannot be turned on. On the other hand, the gate-source voltage of the P-type differential transistors M11 and M12 can be made above the threshold voltage, and only the drain current supplied by the differential transistors M11 and M12 becomes the differential current, which is supplied to the control circuit 4.

[0044] When the common-mode input voltage rises and the gate-source voltages of differential transistors M13 and M14 exceed the threshold voltage, the drain currents of differential transistors M11 and M12 and the drain currents of differential transistors M13 and M14 are added together to form a differential current, which is supplied to the control circuit 4.

[0045] Next, we will explain the case where the common-mode input voltage rises further and approaches the positive power supply voltage VDD. The tracking voltage VT1 cannot track beyond the positive power supply voltage VDD. Therefore, the gate-source voltage of differential transistors M11 and M12 cannot be raised above the threshold voltage, and the P-type differential transistors M11 and M12 cannot be turned on. On the other hand, the gate-source voltage of N-type differential transistors M13 and M14 can be raised above the threshold voltage, and only the drain current supplied by differential transistors M13 and M14 becomes the differential current, which is supplied to the control circuit 4.

[0046] In this way, by configuring the differential input sections 24 and 26 in a so-called rail-to-rail configuration, the common-mode input voltage range of the input voltages INM and INP can be widened.

[0047] Furthermore, in this embodiment, by providing a common-mode tracker circuit 21 and a folded cascode circuit 27, the drain-source voltages of the differential transistors M11, M12, M13, and M14 can be kept constant even if the common-mode input voltage fluctuates. This reduces the application of high voltages to the differential transistors M11, M12, M13, and M14.

[0048] When the common-mode input voltage fluctuates, the source potentials of differential transistors M11, M12, M13, and M14 also fluctuate in accordance with the common-mode input voltage. The drain potentials of differential transistors M11 and M12 are obtained by subtracting the drain-source voltages of transistors M21 and M22 and the drain-source voltages of transistors M23 and M24 from the tracking voltage VT1, as determined by the folded cascode circuit 27.

[0049] The drain potentials of differential transistors M13 and M14 are obtained by subtracting the drain-source voltages of transistors M23 and M24 from the tracking voltage VT1 via the folded cascode circuit 27. In other words, the drain potentials of differential transistors M11, M12, M13, and M14 also fluctuate in accordance with the common-mode input voltage. Therefore, the drain-source voltages of differential transistors M11, M12, M13, and M14 can be kept constant.

[0050] Furthermore, the common-mode tracker circuit 21 can keep the voltage across the tail current source 23 constant. This improves the common-mode input voltage dependence of the current supplied from the tail current source 23.

[0051] Furthermore, in this embodiment, by providing high-voltage transistors M31 and M32, the differential transistors M11 and M12 can be protected from high voltage. The tracking voltage VT2 output from the common-mode tracker circuit 22 falls below the negative power supply voltage VSS and cannot track the common-mode input voltage. Therefore, when the common-mode input voltage falls to a value close to the negative power supply voltage VSS, the gate-source voltage of the high-voltage transistors M31 and M32 cannot be secured, and the high-voltage transistors M31 and M32 cannot operate. In this embodiment, the high-voltage transistors M31 and M32 are composed of depletion transistors. Therefore, even if the common-mode input voltage is close to the negative power supply voltage VSS and the gate potential and source potential of the high-voltage transistors M31 and M32 become equal, the high-voltage transistors M31 and M32 can remain ON, and the common-mode input voltage range can be widened.

[0052] (Second Embodiment) Next, the differential amplifier circuit 1B of the second embodiment will be described with reference to Figure 5. In Figure 5, parts equivalent to the differential amplifier circuit 1 shown in Figure 1, which was already described in the first embodiment, are given the same reference numerals and detailed descriptions are omitted. Note that in Figure 5, the drain sides of transistors M11 and M12 and the drain sides of transistors M21 and M22 are enclosed in dotted lines for simplification, but this is the same as in the first embodiment.

[0053] The main difference between the first and second embodiments lies in the configuration of the common-mode tracker circuit 21B provided in the input section 2B. In the second embodiment, the common-mode tracker circuit 21B generates a tracking voltage VT1 by adding a predetermined voltage to the input voltage INM. In this case as well, similar to the first embodiment, a differential amplifier circuit 1B with high voltage resistance and a wide common-mode input range can be provided.

[0054] In the second embodiment, the common-mode tracker circuit 21B may generate a tracking voltage VT1 by adding a predetermined voltage to the input voltage INP. Similarly, the common-mode tracker circuit 22 shown in Figure 1 may generate a tracking voltage VT2 by subtracting a predetermined voltage from the input voltage INM or input voltage INP.

[0055] (Third embodiment) Next, the differential amplifier circuit 1C of the third embodiment will be described with reference to Figure 6. In Figure 6, parts equivalent to the differential amplifier circuit 1 shown in Figure 1, which was already described in the first embodiment described above, are given the same reference numerals and their detailed description is omitted.

[0056] The main difference between the first and third embodiments lies in the configuration of the differential input section 24C and the folded cascode circuit 27C provided in the input section 2C. The differential input section 24C has differential transistors M11C and M12C, which are composed of high-voltage transistors with higher voltage ratings than the differential transistors M13 and M14. In the differential input section 24C, the drains of the differential transistors M11C and M12C are connected to the inputs of the control circuit 4, respectively, and the high-voltage transistors M31 and M32 shown in Figure 1 are not included. As a result, even if the common-mode input voltage fluctuates sharply and the tracking voltage VT1 cannot keep up, and a high voltage is applied to the differential transistors M13 and M14, protection can be provided.

[0057] Furthermore, the folded cascode circuit 27C includes transistors M21C, M22C, and transistors M23, M24. Transistors M21C and M22C are composed of high-voltage transistors with higher voltage ratings than transistors M23 and M24. This protects transistors M23 and M24 from high voltage.

[0058] (Fourth Embodiment) Next, the differential amplifier circuit 1D of the fourth embodiment will be described with reference to Figure 7. In Figure 7, parts equivalent to the differential amplifier circuit 1 shown in Figure 1, which was already described in the first embodiment described above, are given the same reference numerals and their detailed description is omitted.

[0059] The main difference between the first and fourth embodiments lies in the configuration of the input section 2D. The input section 2D of the fourth embodiment includes common-mode tracker circuits 21 and 22, tail current sources 23 and 25, differential input sections 24 and 26, a folded cascode circuit 27D, and a clamp protection circuit 28.

[0060] The common-mode tracker circuits 21, 22, the tail current sources 23, 25, and the differential input sections 24, 26 are the same as in the first embodiment, so a detailed explanation is omitted here. The folded cascode circuit 27D includes transistors M21D, M22D, transistors M23, M24, and high-voltage transistors M33, M34 which have a higher voltage rating than transistors M21D, M22D, M23, and M24.

[0061] Transistors M21D and M22D are composed of P-type electrolytic effect transistors. Transistor M21D has its source connected to the drain of differential transistor M13, and its drain is connected to the source of high-voltage transistor M33, which will be described later. Transistor M22D has its source connected to the drain of differential transistor M14, and its drain is connected to the source of high-voltage transistor M34, which will be described later. The gates of transistors M21D and M22D are connected to each other, and a tracking voltage VT1_2 is supplied.

[0062] High-voltage transistor M33 has its source connected to the drain of transistor M21D, and its drain connected to the drain of high-voltage transistor M31. High-voltage transistor M34 has its source connected to the drain of transistor M22D, and its drain connected to the drain of high-voltage transistor M32. The gates of high-voltage transistors M33 and M34 are connected to each other, and a tracking voltage VT2 is supplied. High-voltage transistors M33 and M34, like high-voltage transistors M31 and M32, are composed of depletion transistors.

[0063] The drain current from differential transistor M13 is folded back into transistor M21D, and this folded drain current is supplied to the input of control circuit 4 via high-voltage transistor M33. The drain current from differential transistor M14 is folded back into transistor M22D, and this folded drain current is supplied to the input of control circuit 4 via high-voltage transistor M34.

[0064] By cascode-connecting high-voltage transistors M33 and M34 to transistors M21D and M22D, transistors M21D, M22D, M23, and M24 can be protected from high voltage.

[0065] The clamp protection circuit 28 has multiple diodes D1 and multiple diodes D2. The multiple diodes D1 are connected between the drain of differential transistor M11 and the supply line L1, and between the drain of differential transistor M12 and the supply line L1. Note that diode-connected transistors may be used as diodes D1. In this embodiment, two diodes D1 are connected in series on the supply line L1 side. In addition, one diode D1 is connected between the two diodes D1 and the drain of differential transistor M11. One diode D1 is connected between the two diodes D1 and the drain of differential transistor M12. These diodes D1 limit the voltage between the supply line L1 and the drains of differential transistors M11 and M12, thereby protecting transistor M25 and differential transistors M11 and M12 from high voltage.

[0066] Multiple diodes D2 are connected between the drain of transistor M22D and the supply line L1, and between the drain of transistor M21D and the supply line L1. In this embodiment, two diodes D2 are connected in series on the supply line L1 side. Additionally, one diode D2 is connected between the two diodes D2 and the drain of transistor M21D. Another diode D2 is connected between the two diodes D2 and the drain of transistor M22D. These diodes D2 limit the drain voltage of transistors M21D and M22D, protecting differential transistors M13 and M14, transistors M21D and M22D, and transistors M23 and M24 from high voltage.

[0067] (Fifth embodiment) Next, the differential amplifier circuit 1E of the fifth embodiment will be described with reference to Figure 8. In Figure 8, parts equivalent to the differential amplifier circuit 1D shown in Figure 7, which was already described in the fourth embodiment, are given the same reference numerals and detailed descriptions will be omitted.

[0068] The main difference between the fifth embodiment and the fourth embodiment lies in the configuration of the clamp protection circuit 28E and the folded cascode circuit 27E provided in the input section 2E. The clamp protection circuit 28E consists only of diode D1 which limits the drain voltage of differential transistors M11 and M12, and diode D2 is not provided. The folded cascode circuit 27E has transistors M21E and M22E and transistors M23 and M24.

[0069] Transistors M21E and M22E are composed of high-voltage transistors with higher voltage ratings than transistors M23 and M24. This allows transistors M23 and M24 to be protected from high voltage, similar to the third embodiment. Unlike transistors M21C and M22C in the third embodiment, the drains of transistors M21E and M22E are connected to the drains of high-voltage transistors M31 and M32, respectively.

[0070] (Sixth Embodiment) Next, the differential amplifier circuit 1F of the sixth embodiment will be described with reference to Figure 9. In Figure 9, parts equivalent to the differential amplifier circuit 1 shown in Figure 1, which was already described in the first embodiment described above, are given the same reference numerals and their detailed description is omitted.

[0071] The input section 2F of the differential amplifier circuit 1F of the sixth embodiment further includes the clamp protection circuit 28E already described in the fifth embodiment, in addition to the input section 2 of the first embodiment. The diode D1 can limit the drain voltages of transistors M21 and M22, in addition to the drain voltages of differential transistors M11 and 12.

[0072] (Seventh Embodiment) Next, the differential amplifier circuit 1G of the seventh embodiment will be described with reference to Figure 10. In Figure 10, parts equivalent to the differential amplifier circuit 1F shown in Figure 9, which was already described in the sixth embodiment, are given the same reference numerals and detailed descriptions will be omitted.

[0073] The main difference between the sixth and seventh embodiments lies in the configuration of the differential input section 24G provided in the input section 2G. The gates of the high-voltage transistors M31G and M32G provided in the differential input section 24G are connected to input terminals T1 and T2 instead of the common-mode tracker circuit 22. Since the high-voltage transistors M31G and M32G are depletion transistors, they can operate even if their gates are connected to input terminals T1 and T2.

[0074] (Eighth embodiment) Next, the differential amplifier circuit 1H of the eighth embodiment will be described with reference to Figure 11. In Figure 11, parts equivalent to the differential amplifier circuit 1G shown in Figure 10, which was already described in the seventh embodiment, are given the same reference numerals and detailed descriptions will be omitted.

[0075] The main difference between the seventh and eighth embodiments lies in the configuration of the differential input section 24H provided in the input section 2H. In addition to the differential transistors M11 and M12, which are the same as in the first embodiment, the differential input section 24H includes high-voltage transistors M311, M312, M321, and M322. The high-voltage transistors M311, M312, M321, and M322 are composed of depletion transistors.

[0076] The high-voltage transistors M311 and M312 have their sources connected to the drain of differential transistor M11, their drains connected to each other, and are connected to the input of control circuit 4. The gate of high-voltage transistor M311 is connected to input terminal T1, and the gate of high-voltage transistor M312 is connected to input terminal T2.

[0077] The high-voltage transistors M321 and M322 have their sources connected to the drain of the differential transistor M12, their drains are connected to each other, and are connected to the input of the control circuit 4. The gate of the high-voltage transistor M321 is connected to input terminal T1, and the gate of the high-voltage transistor M322 is connected to input terminal T2. In the embodiment described above, high-voltage transistors M311 and M312 and high-voltage transistors M321 and M322 are provided instead of transistors M31 and M32. As a result, the differential components input to high-voltage transistors M311 and M312, and high-voltage transistors M321 and M322 can be canceled out, and the impact on the signal characteristics can be reduced.

[0078] Furthermore, the present invention is not limited to the embodiments described above, and can be modified, improved, etc., as appropriate. In addition, the material, shape, dimensions, number, placement, etc. of each component in the embodiments described above are arbitrary and not limited, as long as they can achieve the present invention.

[0079] In the embodiments described above, a MOS (microelectronics-optical) transistor was used as the transistor, but it is not limited to this. A bipolar transistor may also be used as the transistor. In this case, the gate is read as the base, the source as the emitter, and the drain as the collector.

[0080] According to the embodiment described above, the differential amplifier circuit 1 includes a common-mode tracker circuit 22, but is not limited to this. If transistors M11 and M12 are connected directly to the control circuit 4 without providing transistors M31 and M32, the common-mode tracker circuit 22 may be omitted. [Explanation of symbols]

[0081] 1,1B~1H Differential Amplifier Circuit 21,21B Common-mode tracker circuit (first tracking voltage generation circuit) 22. Common-mode tracker circuit (second tracking voltage generation circuit) 23. Tail current source (first current source) 24, 24C, 24G, 24H Differential Input Section (First Differential Input Section) 25. Tail current source (second current source) 26 Differential input section (second differential input section) 27, 27C~27E Folded Cascode Circuit 28,28E Clamp Protection Circuit D1 diode INM Input Voltage (First Input Voltage) INP Input Voltage (Second Input Voltage) L1 supply line M11, M11C differential transistor (first differential transistor) M12, M12C differential transistor (second differential transistor) M13 Differential Transistor (Third Differential Transistor) M14 Differential Transistor (Fourth Differential Transistor) M21, M21C~M21E Transistors (First Transistors) M22, M22C~M22E Transistors (Second Transistors) M23 transistor (third transistor) M24 transistor (fourth transistor) M25 transistor (the fifth transistor) M31, M31G, M311, M312 High-voltage transistors (first-generation high-voltage transistors) M32, M32G, M321, M322 High-voltage transistors (second-generation high-voltage transistors) VSS Negative Power Supply Voltage (Power Supply Voltage) VT1 Tracking voltage (first tracking voltage) VT2 Tracking Voltage (Second Tracking Voltage)

Claims

1. A differential amplifier circuit that amplifies the difference between a first input voltage and a second input voltage, A first tracking voltage generation circuit that fluctuates in accordance with either the first input voltage or the second input voltage and generates a first tracking voltage that is higher than either of the first or second input voltages, or a first tracking voltage that fluctuates in accordance with the in-phase components of the first and second input voltages and generates a first tracking voltage that is higher than the in-phase components, A first current source, one end of which is connected to the supply line of the first tracking voltage, A first differential input section having a first P-type differential transistor and a second differential transistor, the source or emitter of which is connected to the other end of the first current source, and the gate or base of which are supplied with the first input voltage and the second input voltage, respectively, A second current source to which power supply voltage is supplied, A second differential input section having a third N-type differential transistor and a fourth differential transistor, the source or emitter of which is connected to the other end of the second current source, and the gate or base of which are supplied with the first input voltage and the second input voltage, The folded cascode circuit comprises a first transistor that folds back the current flowing through the third differential transistor and adds it to the output of the first differential input section, a second transistor that folds back the current flowing through the fourth differential transistor and adds it to the output of the first differential input section, a third transistor cascode-connected between the supply line of the first tracking voltage and the first transistor, and a fourth transistor cascode-connected between the supply line of the first tracking voltage and the second transistor. Differential amplifier circuit.

2. In the differential amplifier circuit described in claim 1, The first current source has the supply line for the first tracking voltage and a fifth transistor connected between the source or emitter of the first differential transistor and the second differential transistor. The difference voltage between the first tracking voltage and the tracking voltage is set to be greater than or equal to the sum of the voltage at which the drain-source voltage of the fifth transistor satisfies the saturation condition or the collector-emitter voltage satisfies the activation condition, and the threshold voltage of the gate-source voltage or base-emitter voltage of the first differential transistor and the second differential transistor. Differential amplifier circuit.

3. In the differential amplifier circuit described in claim 1, The third differential transistor and the fourth differential transistor are composed of N-type electrolytic effect transistors, and use HVDeepNWELL elements. Differential amplifier circuit.

4. In the differential amplifier circuit described in claim 3, The bulk terminals of the third differential transistor and the fourth differential transistor are connected to the source terminals. Differential amplifier circuit.

5. In the differential amplifier circuit described in claim 3, The bulk terminals of the third differential transistor and the fourth differential transistor are connected to a voltage lower than the source terminal. Differential amplifier circuit.

6. In the differential amplifier circuit described in claim 1, A first high-voltage transistor having a higher voltage rating than the first differential transistor is cascode-connected to the first differential transistor, The present invention further comprises a second high-voltage transistor having a higher voltage rating than the second differential transistor, which is cascode-connected to the second differential transistor. Differential amplifier circuit.

7. In the differential amplifier circuit described in claim 6, The first high-voltage transistor and the second high-voltage transistor are composed of depletion transistors. Differential amplifier circuit.

8. In the differential amplifier circuit described in claim 7, The system includes a second tracking voltage generation circuit that generates a second tracking voltage that fluctuates in accordance with either the first input voltage or the second input voltage and is lower than the first or second input voltage, or a second tracking voltage that fluctuates in accordance with the in-phase component of the first input voltage and the second input voltage and is lower than the in-phase component. The first high-voltage transistor and the second high-voltage transistor are supplied with the second tracking voltage to their gates. Differential amplifier circuit.

9. In the differential amplifier circuit described in claim 7, The gate of the first high-voltage transistor is connected to the gate of the first differential transistor. The gate of the second high-voltage transistor is connected to the gate of the second differential transistor. Differential amplifier circuit.

10. In the differential amplifier circuit described in claim 1, The first and second transistors in the aforementioned folded cascode circuit are composed of high-voltage transistors that have a higher voltage rating than the third and fourth transistors. Differential amplifier circuit.

11. In the differential amplifier circuit described in claim 1, The system includes a clamp protection circuit that limits the voltage between the drain or collector of the first differential transistor and the supply line for the first tracking voltage, and the voltage between the drain or collector of the second differential transistor and the supply line for the first tracking voltage. Differential amplifier circuit.

12. In the differential amplifier circuit according to claim 11, The clamp protection circuit is composed of multiple diodes, Differential amplifier circuit.

13. In the differential amplifier circuit according to claim 12, The diode is composed of diode-connected transistors. Differential amplifier circuit.

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