Non-volatile memory cell, and its memory

Abstract

This relates to non-volatile memory cells and their memory. [Solution] The memory cell includes a first well and a second well of different types that are placed adjacent to each other, one first transistor located in the first well and including a floating gate and its gate oxide, one capacitor located in the second well and including one coupling region located in the second well, the floating gate and its gate oxide extending from the first well to the second well and constituting the gate and its gate oxide of the capacitor, the floating gate includes two parts with different electrical properties, a PN junction is formed at the boundary between the two parts and is close to one end of the floating gate, and the distance between the PN junction and the adjacent floating gate end is less than 150 nm.

Description

Technical Field

[0001] The present invention generally relates to non-volatile memory cells and their memories, and specifically to electrically programmable and erasable non-volatile memory cells that can be programmed and erased multiple times, and their memories.

Background Art

[0002] With the continuous geometric scaling down of semiconductor manufacturing processes, the number of transistors integrated in silicon chips has been continuously increasing. By integrating the entire system into one chip, many applications can be realized. However, a multi-system includes many independent elements, such as EEPROM, DRAM, and FLASH, which are generally manufactured by special processes. These special processes are not compatible with the general-purpose logic manufacturing processes used to fabricate logic elements, such as microprocessors and system logic devices.

[0003] In order to integrate these special memory parts (e.g., EEPROM, DRAM, and FLASH) in a logic process, it is usually necessary to add an additional manufacturing process based on the existing logic process. The additional process steps will increase the manufacturing cost of the entire chip including the logic circuit part, which conflicts with the fact that chip manufacturers usually need to compress the manufacturing process to the maximum extent. Based on this, the memory circuit needs to be designed to be compatible with the logic process, especially for chips where the logic circuit occupies most of the area, such compatibility is particularly necessary.

[0004] A logic process is used to fabricate compatible non-volatile memory (e.g., EEPROM and FLASH), where a kind of effective solution and structure is to separate the memory cell from the substrate using deep wells, as described, for example, in US7983081B2, the substrate being grounded or 0V in most cases, and the memory cell containing one MOS transistor and one MOS capacitor, each constructed in two different types of wells, the two wells being juxtaposed adjacent to each other in a deep well, the transistor and capacitor having one floating gate and below it Sharing a gate oxide layer, the MOS capacitor includes a low-concentration doped region located within the well and an adjacent coupling region. The capacitor-side end of the shared floating gate partially overlaps with the low-concentration doped region in the capacitor well. The structure of the coupling capacitor consists of a floating gate partially overlapping with the capacitor's doped region in the well, a gate oxide below it, and a MOS channel. The coupling region of the capacitor connects the control word line (CWL) to the control gate of the memory cell, and the control gate is formed by the channel region of the MOS capacitor. To improve the efficiency of the coupling gate, the coupling capacitor is made much larger than the capacitor of the MOS gate.

[0005] Such a solution is compatible with logic processes, does not require special circuits, is easy to manufacture, has a small memory cell size, and offers excellent performance. However, in such a structure, the MOS transistor and MOS capacitor share a single floating gate. As a result, both ends of the floating gate are adjacent to transistor active regions and capacitor active regions with different electrical properties in different wells. When forming the active regions, corresponding doped ions enter from the side of the floating gate adjacent to the active region. Consequently, two parts with different electrical properties are formed in the floating gate, a PN junction is formed at the boundary between the two parts, and the potential within the floating gate becomes unstable. This affects the performance, stability, and reliability of the memory cell and its operation.

[0006] Therefore, a new non-volatile memory cell and its memory are needed that can solve the above problems. [Overview of the project] [Means for solving the problem]

[0007] A first aspect of the present application relates to a non-volatile memory cell comprising a first well and a second well of different types arranged adjacent to each other, one first transistor located in the first well, the first transistor comprising a floating gate and its gate oxide, one capacitor located in the second well, the capacitor comprising a coupling region located in the second well, the floating gate and its gate oxide extending from the first well to the second well, constituting the gate and its gate oxide of the capacitor, the floating gate comprising two parts having different electrical properties, the boundary between the two parts having different electrical properties being close to one end of the floating gate, the distance between the boundary and the adjacent floating gate end being less than 150 nm, preferably 5 to 100 nm, and more preferably 10 to 70 nm.

[0008] In one preferred embodiment, the floating gate end where the boundary between two portions of the floating gate with different electrical properties is in close proximity is the end of the floating gate that is close to the capacitor and away from the first transistor. More preferably, the first transistor includes a source and a drain, each of which includes a high-concentration doped ion region, and / or the coupling region of the capacitor is a low-concentration doped ion region.

[0009] In another preferred embodiment, the non-volatile memory cell further includes a second transistor, the second transistor being of the same type as the first transistor, and also located in the first well, and connected in series with the first transistor.

[0010] In a further preferred embodiment, the first well and the second well in the non-volatile memory cell are an N well and a P well, respectively, the first transistor is a PMOS transistor, the capacitor is an NMOS capacitor, and the coupling region of the capacitor in the second well is an N coupling region.

[0011] A second aspect of the present application relates to a non-volatile memory, which comprises at least one non-volatile memory cell constructed on a substrate, the substrate comprising one deep well, the first well and the second well in the non-volatile memory cell being located within the deep well. Preferably, the substrate is a P-type substrate, the deep well is a deep N-well, the first well and the second well are an N-well and a P-well, respectively, the first transistor is a PMOS transistor, the capacitor is an NMOS capacitor, and the coupling region of the capacitor in the second well is an N-coupling region.

[0012] In one preferred embodiment, the non-volatile memory is a non-volatile memory that can be electrically programmable and erased multiple times. [Brief explanation of the drawing]

[0013] [Figure 1] This shows a top view of a non-volatile memory cell in one embodiment of the present invention. [Figure 2] Figure 1 shows a cross-sectional view of the memory cell along the cross-sectional line AA in the embodiment shown. [Figure 3] Figure 1 shows a cross-sectional view of the memory cell along the cross-sectional line BB in the embodiment shown. [Figure 4] Figure 1 shows a cross-sectional view of the memory cell along the cross-sectional line CC in the embodiment shown. [Figure 5] Figure 1 shows a partial plan view including the floating gate of the memory cell. [Figure 6] This shows a partial plan view of the floating gate of a conventional memory cell whose structure is similar to that of the memory cell shown in Figure 1. [Figure 7] Figures 5 and 6 show the volt-ampere characteristic curves of the floating gates of the two types of memory cells. [Figure 8] The steps for sequentially forming the active region of the memory cell shown in Figure 1 are illustrated. [Figure 9] The steps for sequentially forming the active region of the memory cell shown in Figure 1 are illustrated. [Figure 10] The steps for sequentially forming the active region of the memory cell shown in Figure 1 are illustrated. [Modes for carrying out the invention]

[0014] The same number in the drawing indicates the same or similar element.

[0015] The non-volatile storage cell and its memory of the present invention are preferably non-volatile storage cells and its memory that can be electrically programmable and erased multiple times.

[0016] In the non-volatile memory cell described herein, the first transistor includes a floating gate and a gate oxide below it, the floating gate being preferably a polycrystalline silicon gate. The floating gate and its gate oxide extend from the first well to the second well, constituting the gate and its gate oxide of a capacitor. The floating gate slightly overlaps with the edge of the active region (capacitor coupling region) in the second well. The capacitor coupling region connects the control word line (WL) to the control gate of the memory cell. The control gate is formed by the channel region of the capacitor. Thus, the structure of the coupling capacitor consists of a floating gate slightly overlapping with the active region in the second well, a lower gate oxide, and a capacitor channel. To improve the efficiency of the coupling gate, the coupling capacitor is made much larger than the capacitor of the first transistor gate.

[0017] The programming and erasure of the above memory cell are performed within the first transistor, with programming occurring when thermionic electrons (or holes) in the channel of the first transistor tunnel into the floating gate. The erasure operation is based on the FN tunneling mechanism, tunneling electrons (or holes) in the floating gate into the channel. The tunneling oxide used in both programming and erasure operations is the gate oxide located above the channel region of the first transistor. During the operation, the potential applied to the capacitor-coupled region of the control word line is coupled to the floating gate by the capacitor, thereby allowing the floating gate to acquire the required potential.

[0018] In a non-volatile memory cell similar in structure to that of the present invention in the prior art, a first transistor and a capacitor located in different types of wells share a single floating gate, and the source and drain of the first transistor have different electrical properties from the coupling region of the capacitor. When doping ions are injected into the active regions on both sides of the floating gate to form the source and drain of the transistor and the coupling region of the capacitor, corresponding doped ions penetrate the sides of the floating gate adjacent to the active region. As a result, two parts with different electrical properties are formed on the floating gate, and a PN junction is formed at the boundary between the two parts (approximately in the center of the floating gate). In particular, when a high-concentration doped ion region is included in the source and drain of the first transistor and the coupling region of the capacitor, it is necessary to repeatedly inject doped ions into predetermined active regions on both sides of the floating gate during the manufacturing process. This results in a relatively large number of doped ions penetrating the sides of the floating gate, and a relatively large PN junction being formed on the floating gate. When the memory cell operates, it applies a potential to the capacitor coupling region. The coupling capacitor is larger than the gate capacitor of the first transistor, and as a result, the applied potential is coupled to the floating gate by the capacitor, allowing the floating gate to acquire the required potential. Due to the presence of a PN junction in the center of the floating gate, the floating gate body is no longer a P-type or N-type gate in terms of net electrical properties, and the floating gate has an internal electric field within the PN junction. Consequently, the coupling potential acquired by the floating gate and its uniformity decrease, as does the stability of the coupling potential.

[0019] In the present application, by moving the position of the boundary (PN junction) between two portions with different electrical properties in the floating gate from the central portion of the floating gate to near the end of the floating gate, the floating gate body exhibits a net electrical property of P or N, thereby weakening or eliminating the adverse effect of the PN junction on the floating gate. The PN junction may be close to the end on the capacitor side in the floating gate, or may be close to the end on the first transistor side, and preferably is close to the end on the capacitor side.

[0020] The proximity of the PN junction in the floating gate of the present application to one end of the floating gate can be realized by the following method.

[0021] The source-drain of the first transistor and the capacitor coupling region are each located within the active region in their respective wells, and there is a thick field oxide (FOX) isolation region that serves as a separation between the two active regions, and the thick field oxide isolation region is located at the boundary between the two wells. In the process of fabricating the memory cell, when forming the capacitor and the active region of the first transistor, the boundary adjacent to the isolation region of the capacitor active region is made close to the end of the floating gate on the capacitor side, or the boundary adjacent to the isolation region of the active region of the first transistor is made close to the end of the floating gate on the first transistor side, and thereby corresponding ions are implanted in a predetermined region to realize the proximity of the PN junction in the floating gate to the end of the floating gate.

[0022] The non-volatile memory cell of the present invention comprises two different types of first and second wells arranged adjacent to each other, a first transistor and a capacitor located in the first and second wells, respectively, the first transistor and the capacitor sharing one floating gate and its gate oxide, the floating gate comprising two portions having different electrical properties, the boundary between the two portions (i.e., a PN junction) being close to one end of the floating gate, and the distance between the boundary (PN junction) and the adjacent floating gate end being greater than 0 and less than 150 nm, preferably 2 to 130 nm, more preferably 5 to 100 nm, and even more preferably 10 to 70 nm.

[0023] The distance between the PN junction and the adjacent end of the floating gate in a floating gate refers to the distance along the length of the floating gate. The length of the floating gate is from the end on the first transistor side to the end on the capacitor side, and this direction is perpendicular to the length of the first transistor (from the source to the drain of the first transistor).

[0024] In this application, the length of the floating gate is the length from the end of the floating gate on the first transistor side to the end on the capacitor side, and is 1000 to 6000 nm.

[0025] The PN junction in the floating gate may be close to one of the two ends of the floating gate. Preferably, it is the end close to the capacitor side of the floating gate, i.e., the end close to the capacitor of the floating gate and away from the first transistor.

[0026] The memory cell relating to the first embodiment of the present application has a floating gate in which the PN junction is close to the capacitor-side end of the floating gate, where preferably, each of the source and drain of the first transistor includes a high-concentration doped ion region, or the capacitor coupling region is a low-concentration doped ion region. In this way, the net electrical properties of the floating gate body can be further enhanced, and in this case the net electrical properties of the floating gate body are the same as the type of high-concentration doped ions in the source and drain of the first transistor. More preferably, each of the source and drain of the first transistor includes a high-concentration doped ion region, while the capacitor coupling region is a low-concentration doped ion region.

[0027] In this embodiment, more preferably, the first well and the second well are an N well and a P well, respectively, the first transistor is a PMOS transistor, the source and drain include a P+ high-concentration doped ion region, and the capacitor is an NMOS capacitor, the coupling region in the second well is an N-type low-concentration doped ion region. In this case, the PN junction in the floating gate is close to the end of the floating gate near the capacitor, and the floating gate body exhibits P+ net electrical properties. The operating modes of the memory cell are as follows. When the memory cell is programmed, a positive potential is applied to the N-coupled region of the NMOS capacitor, and the floating gate, whose body exhibits a net P+ electrical property, is forward-biased by the capacitor coupling. Opposite-phase potentials are applied to the source and drain of the PMOS transistor, respectively, thereby creating a strong transverse electric field between its source and drain. Holes are accelerated along the channel of the first transistor in the strong electric field, impact ionization occurs in the drain depletion region, and the resulting thermionic electrons are attracted to the forward-biased floating gate and injected into it. The injection of electrons into the floating gate results in a decrease in the threshold voltage of the PMOS transistor, making it more easily conductive and causing a higher read current during the read operation period. When the memory cell performs an erase operation, a negative potential is applied to the N-coupled region of the NMOS capacitor. The floating gate, whose body exhibits a P+ net electrical property, obtains the necessary negative potential through capacitive coupling, such that its absolute value is less than the value of the potential applied to the capacitive coupling region. Applying the same positive potential to the source and drain of the PMOS transistor creates a high electric field on both sides of the gate oxide layer of the first transistor, which is sufficient to cause electrons confined within the floating gate to tunnel into the channel of the PMOS transistor. The electrons are emitted from the floating gate, causing the threshold voltage of the first transistor to rise, thereby making it less conductive and lowering the read current.

[0028] In this embodiment, the first well and the second well may be a P well and an N well, respectively, the first transistor is an NMOS transistor, the source and drain include N+ high-concentration doped ion regions, and the capacitor is a PMOS capacitor, the coupling region in the second well being a P-type low-concentration doped ion region. In this case, the PN junction in the floating gate is still close to the capacitor-side end of the floating gate, and at this time the floating gate body exhibits N+ net electrical properties. The operating mode of the memory cell is different from that described above. When the memory cell is programmed, a negative potential is applied to the P-coupled region of the PMOS capacitor, and the floating gate, whose body exhibits N+ net electrical properties, is reverse-biased by the capacitor coupling, applying opposite-phase potentials to the source and drain of the NMOS transistor, thereby creating a strong transverse electric field between its source and drain. Electrons are accelerated along the channel of the first transistor in the strong electric field, causing impact ionization in the pole (e.g., source) depletion region. The resulting holes are attracted to the reverse-biased floating gate and injected into it. The injection of holes into the floating gate results in a decrease in the threshold voltage of the NMOS transistor, thereby making it more easily conductive and causing a higher read current during the read operation period. When the memory cell performs an erase operation, a positive potential is applied to the P-coupled region of the PMOS capacitor, and the floating gate, whose body exhibits N+ net electrical properties, obtains the necessary positive potential through capacitive coupling, such that its absolute value is less than the value of the potential applied to the capacitive coupling region. Applying the same negative potential to the source and drain of the NMOS transistor, this creates a high electric field on both sides of the gate oxide layer of the first transistor, which is sufficient to cause holes confined within the floating gate to tunnel into the channel of the NMOS transistor. The holes are released from the floating gate, causing the threshold voltage of the first transistor to rise, thereby making it less conductive and lowering the read current.

[0029] In a second embodiment of the memory cell of the present invention, the PN junction in the floating gate may be close to the transistor-side end of the floating gate, i.e., the end that is close to the first transistor of the floating gate and away from the capacitor. In this case, preferably, the source and drain of the first transistor are low-concentration doped ion regions, or the capacitor coupling region includes a high-concentration doped ion region. In this way, the net electrical properties of the floating gate body can be further enhanced, and the net electrical properties of the floating gate body are the same as the type of high-concentration doped ions in the capacitor coupling region. Even more preferably, the source and drain of the first transistor are low-concentration doped ion regions, while the capacitor coupling region includes a high-concentration doped ion region.

[0030] In this embodiment, more preferably, the first well and the second well are an N well and a P well, respectively, the first transistor is a PMOS transistor, the source and drain are low-concentration P-doped ion regions, the capacitor is an NMOS capacitor, and the coupling region is a high-concentration N+-doped ion region. In such a case, the PN junction in the floating gate is close to the terminal on the first transistor side of the floating gate, and the floating gate body exhibits net N+ electrical properties. The structure of the memory cell is similar to that of the first memory cell in the first embodiment (i.e., the first and second wells are N-wells and P-wells, respectively; the first transistor is a PMOS transistor, and the source and drain include P+ high-concentration doped ion regions; the capacitor is an NMOS capacitor, and its coupling region is an N low-concentration doped ion region), the difference being that the PN junctions in the floating gates are located in different positions, that is, they are close to different ends of the floating gates, and one of the floating gate bodies exhibits N+ net electrical properties, while the other exhibits P+ net electrical properties. Compared to the memory cell in the first embodiment, the distance between the PN junction in the floating gate and the floating gate end (the end on the first transistor side) in this embodiment must not be too small; otherwise, the active region of the first transistor will be too narrow, affecting the performance of the first transistor. In this case, preferably, the distance between the PN junction and the transistor-side end of the floating gate is 30 to 150 nm, and more preferably 50 to 130 nm. This embodiment can partially reduce the adverse effects of the PN junction on the floating gate, but the effect is not as great as that of the first embodiment. Furthermore, the operating mode of this embodiment is similar to that of the first structure memory cell in the first embodiment, with one floating gate body exhibiting N+ net electrical properties and the other exhibiting P+ net electrical properties, and although the specific numerical values ​​for applying potential to the capacitor coupling region during programming or erasing operations are slightly different, the operating principles and modes of both are similar.

[0031] In this embodiment, the first well and the second well may still be a P well and an N well, respectively, the first transistor is an NMOS transistor, the source and drain include N-low concentration doped ion regions, the capacitor is a PMOS capacitor, and its coupling region in the second well is a P+ high concentration doped ion region. In this case, the PN junction in the floating gate is still close to the first transistor side end of the floating gate, and the floating gate body exhibits P+ net electrical properties. The structure of this embodiment is similar to the memory cell of the second structure in the first embodiment (i.e., the first well and the second well are a P well and an N well, respectively, the first transistor is an NMOS transistor, the source and drain include N+ high concentration doped ion regions, the capacitor is a PMOS capacitor, and the coupling region is a P-low concentration doped ion region). The difference lies in the position of the PN junctions in the floating gates of the two embodiments; that is, they are located near different ends of the floating gate, and one floating gate body exhibits a net P+ electrical property while the other exhibits a net N+ electrical property. Compared to a similar memory cell structure in the first embodiment, the distance between the PN junction in the floating gate and the end of the floating gate on the first transistor side in this embodiment must not be too small; otherwise, the active region of the first transistor will be too narrow, affecting the performance of the first transistor. In this case, preferably, the distance between the PN junction in the floating gate and the end of the floating gate on the first transistor side is 30 to 150 nm, and more preferably 50 to 130 nm. This embodiment can partially mitigate the adverse effects of the PN junction on the floating gate, and its effect is not as pronounced as in the first embodiment.Furthermore, the operating mode of this embodiment is similar to that of the first memory cell in the first embodiment described above, with one floating gate body exhibiting a net P+ electrical property and the other exhibiting a net N+ electrical property. Although the specific numerical values ​​for applying potential to the capacitor coupling region during programming or erasing operations differ slightly, the operating principles and modes of both are similar.

[0032] The non-volatile memory cell of the present invention may further include a second transistor, which is of the same type as the first transistor, is also located in the first well, and is connected in series with the first transistor. The second transistor acts as the gate transistor for the programmable first transistor to minimize programming interference problems.

[0033] The present invention further relates to a non-volatile memory comprising at least one of the above non-volatile memory cells constructed on a substrate, the substrate having one deep well, the first well and the second well located within the deep well. Preferably, the substrate is a P-type substrate, and the deep well is a deep N-well. More preferably, the first well and the second well are an N-well and a P-well, respectively, the first transistor is a PMOS transistor, the capacitor is an NMOS capacitor, and the coupling region of the capacitor in the second well is an N-coupling region. The memory is preferably a non-volatile memory that can be programmed and erased multiple times.

[0034] The memory cell and its memory according to the present invention are manufactured by a method common in the prior art. However, when forming the capacitor and the active region of the first transistor, the boundary adjacent to the isolation region of the capacitor active region is brought close to the capacitor-side end of the floating gate, or the boundary adjacent to the isolation region of the first transistor active region is brought close to the first transistor-side end of the floating gate, thereby enabling the injection of doped ions into a predetermined active region and ensuring that the PN junction in the floating gate is close to the capacitor-side end of the floating gate or the first transistor-side end of the floating gate. If, when the boundary adjacent to the isolation region of the capacitor active region is close to the capacitor-side end of the floating gate, the boundary adjacent to the capacitor in the isolation region also moves to the capacitor-side end of the floating gate along with the above boundary of the capacitor active region, the size of the capacitor coupling region along the length of the floating gate becomes narrower, and as a result, the capacitor coupling ratio decreases. To avoid reducing the capacitor's coupling ratio, preferably, the boundary adjacent to the capacitor in the isolation region moves along with the boundary of the capacitor active region, and without approaching the capacitor-side end of the floating gate, an ion-doped region of the same type as the active region (source / drain) of the first transistor is added juxtaposed between the isolation region and the capacitor active region. In this way, it is possible to ensure that the effective area and coupling ratio of the capacitor do not decrease, and the net electrical properties of the floating gate body can be further enhanced. In this case, the net electrical properties of the floating gate body are the same as the electrical properties of the source / drain of the first transistor.

[0035] In the memory cell of the present invention, the PN junction within the floating gate is located close to the end of the floating gate, which weakens or eliminates the adverse effects of the PN junction on the floating gate, increases the coupling potential acquired by the floating gate, improves the uniformity and stability of the coupling potential acquired by the floating gate, reduces the degree of coupling discreteness, and improves the average value of the threshold voltage of the first transistor after erasure. All of these contribute to improving the stability and reliability of the memory.

[0036] The memory cells and their memory of the present invention will be described in detail below with reference to specific embodiments. As will be apparent, various adjustments and modifications can be made to these embodiments without departing from the spirit and scope of the present invention.

[0037] Figure 1 shows a plan view of the non-volatile memory cell 100 of the present invention. Figures 2 to 4 are cross-sectional views along the cross-sectional lines AA, BB, and CC in Figure 1, respectively. The CC cross-sectional line in the drawings is the boundary line between two parts of the floating gate 116 with different electrical properties, and is also the position line of the PN junction, which is close to the end of the floating gate 116 on the capacitor 120 side. The left and right sides of the CC line are the P-type and N-type electrical property parts of the floating gate 116, respectively, and are called the P-gate and N-gate.

[0038] In this embodiment, the non-volatile memory cell 100 is constructed on a P-type silicon substrate 101. A deep N-well 104 is provided on the P-substrate 101, which electrically isolates the memory cell 100 from the substrate 101. An N-well 102 and a P-well 103 are located immediately adjacent to each other and are situated in the deep N-well 104. One first transistor 110 (which is a PMOS readout transistor in this embodiment) is located in the N-well 102, and one capacitor 120 (which is an NMOS capacitor in this embodiment) is located in the P-well 103. The first transistor 110 includes a P-type drain 112 and a source 111. The drain 112 includes a drain low-concentration doped region 112A and a drain high-concentration doped P+ contact region 112B. The source 111 includes a source low-concentration doped region 111A and a source high-concentration doped P+ contact region 111B.

[0039] Source 111 is connected to the common line (COM), and drain 112 is connected to the bit line (BL). The first transistor 110 is surrounded by a shallow trench, which is filled with a thick field oxide 114 (FOX). Between source 111 and drain 112 is a channel 113 region. The gate oxide 115 covering the channel 113 is 7 nm thick. A conductive doped polycrystalline silicon gate is placed on top of the gate oxide 115 to form the floating gate 116 of the first transistor 110.

[0040] The floating gate 116 and gate oxide 115 extend to the P well 103, forming the upper plate and dielectric of the capacitor 120. In the P well 103, the three boundaries of the N gate portion of the floating gate 116 adjacent to the capacitor active region 122 all slightly overlap with the edge of the capacitor active region 122 (the overlap width is h). The capacitor active region 122 is also the coupling region of the capacitor 120 and may also be called the charge injection element; it is a low-concentration N-doped region. The gate capacitance value of the capacitor 120 is approximately 2.5 times the gate capacitance value of the first transistor 110.

[0041] The charge injection element is connected to the word line (WL), which is also connected to the P well 103 by a P+ contact region (not shown). During the memory operation period, the word line WL is used to control the voltage of the floating gate 116. During the operation period, if the potential of the floating gate 116 is greater than WL, the voltage difference is greater than the threshold voltage of the capacitor 120, causing the capacitor channel region 121 below the floating gate 116 to invert within the P well 103 region. Electrons emitted from the charge injection element form an electron inversion layer within the capacitor channel region 121, thereby causing the capacitor channel region 121 to form the lower plate of the capacitor 120. The lower plate is connected to WL by the charge injection element.

[0042] The floating gate 116 is surrounded by sidewall spacers 117, which are generally made of silicon nitride or silicon oxide. When forming the P+ region, the sidewall spacers 117 prevent the P+ injector from entering the low-concentration doped P region.

[0043] Figure 5 is a partial plan view including the floating gate 116 of the memory cell 100 described in Figure 1. Figure 6 is a partial plan view including the floating gate of a memory cell whose structure is similar to that of the memory cell 100 in the prior art.

[0044] Compared to the conventional memory cell shown in Figure 6, the position of the PN junction (at the CC demarcation line) in the floating gate 116 of the memory cell 100 of the present application shown in Figure 5 is moved from the central part of the floating gate 116 to the end of the floating gate 116 that is close to the capacitor 120 side. The distance between the PN junction and the end of the floating gate 116 that is close to the capacitor 120 side is H, which is specifically 30 nm. Along the length of the floating gate 116, the size of the P gate portion of the floating gate 116 is much larger than the N gate portion, and as a result, the floating gate 116 body exhibits P+ net electrical properties and may also be called an approximate P gate. The P+ high-concentration doped ion region located in the N well 102 (NW) is the active region of the first transistor 110, and the N low-concentration doped ion region located in the P well 103 (PW) is the capacitor coupling region. Between them are a thick field oxide 114 (FOX) isolation region located at the boundary between the two wells, and a newly added P+ high-concentration doped ion region in the P well 103. The newly added P+ high-concentration doped ion region is located between the isolation region and the capacitor coupling region, which not only ensures that the effective area and coupling ratio of the capacitor 120 do not decrease, but also contributes to the floating gate 116 body exhibiting P+ net electrical properties.

[0045] As can be further seen from Figure 5, in the P-well 103, the three boundaries adjacent to the capacitor coupling region of the N-gate portion of the floating gate 116 of the memory cell 100 all slightly overlap with the edge of the N-coupling region of the capacitor 120, with an overlap width of h. This overlap width is advantageous for the capacitor coupling region (i.e., the charge injection element) to inject electrons into the capacitor channel region 121 during the erase operation, forming a stable state inversion layer, and facilitating the realization of a coupling potential to the floating gate 116.

[0046] Figure 7 shows the volt-ampere characteristic curves of the floating gates of the two types of memory cells shown in Figures 5 and 6. This is a diagram illustrating the relationship between the current I and voltage U from the N gate to the P gate, and also a resistance characteristic curve. As can be seen from Figure 7, in the floating gate of the conventional memory cell, the resistance distribution from the N gate to the P gate is not uniform and is clearly higher than that of the floating gate 116 of the memory cell 100 in this application. The reason for this is that the conventional floating gate has a PN junction located in the center of the floating gate between the P gate and the N gate. The PN junction has an internal electric field, which results in an initial potential of 0.5V being displayed on the volt-ampere curve. Current (electrons) only moves in the floating gate after overcoming this initial potential. This results in the potential acquired by the coupling within the floating gate not being high and lacking uniformity. As can be further seen from Figure 7, the resistance in the floating gate 116 of the memory cell 100 in this application is constant, the distribution is uniform, and its resistance value is clearly lower than that of the floating gate in the conventional technology. The reason for this is that the PN junction in the floating gate 116 of the memory cell 100 of the present invention is close to the end, and the floating gate 116 body exhibits P+ net electrical properties, so the floating gate 116 approximates a P-type gate. As a result, the potential acquired by the coupling within the floating gate 116 of the present invention is relatively high and uniform, and the degree of coupling, the uniformity of the potential acquired by the coupling, and stability can all be improved, which is advantageous for uniform erasure in erasure operations.

[0047] The memory cell 100 described in this embodiment is manufactured using a 130nm logic process. All processing steps required to form the memory cell 100 are conventional steps used in logic manufacturing processes to form circuits on other chips, and no further processing steps are required. Furthermore, the manufacturing process for the memory cell 100 is compatible with standard CMOS processes.

[0048] The manufacturing process for the memory cell 100 of the present invention is basically the same as the manufacturing process for the prior art memory cell shown in Figure 6. The only difference is that when forming the active regions of the NMOS capacitor 120 and the first transistor 110, the boundary of the capacitor active region 122 adjacent to the FOX isolation region is brought closer to the capacitor 120 side end of the floating gate 116, the distance between the above boundary of the capacitor active region 122 and the capacitor side end of the floating gate 116 is 30 nm, and one P+ active region is added between the FOX isolation region and the capacitor active region 122 in the P well 103, thereby performing dope ion injection for the predetermined active region. As shown in Figures 8 to 10, these are partial plan views of the memory cell 100 including the floating gate 116 in each step of sequentially forming the active regions (the active region of the first transistor 110 and the capacitor active region 122).

[0049] As shown in Figure 8, before the step of implanting doped ions, first the gate oxide 115 and floating gate 116 are formed in N well 102 and P well 103, and then the layout is formed based on the positions of predetermined FOX regions (i.e., isolation regions) and active regions (P+ region and N region) shown in Figure 8. In Figure 8, the P+ region in N well 102 is the active region of the first transistor 110, the intermediate FOX region spans N well 102 and P well 103, the N region in P well 103 is the N active region of NMOS capacitor 120, and the P+ region in P well 103 is a P+ active region added between the intermediate FOX region and the N active region of NMOS capacitor 120.

[0050] A photomask is used to expose the regions where doped ions need to be implanted, and then doped ions of the type corresponding to each predetermined active region are implanted to form the P+ source and drain of the first transistor 110, the N-coupled region of the NMOS capacitor 120, and the P+ active region in the newly added P-well 103, as shown in Figure 9.

[0051] During the process of implanting doped ions into the active region, ions implanted onto the surface of the floating gate 116 from directly above the portion adjacent to the active region of the floating gate 116 penetrate less into the floating gate 116, which is determined by the material of the floating gate 116. On the other hand, doped ions implanted into the active region from both sides of the portion adjacent to the active region of the floating gate 116 can penetrate into the floating gate 116 from its sides. As shown in Figure 10, P+ doped ions implanted into the two P+ active regions penetrate into the floating gate 116 from its sides adjacent to the active region, move into the conductor of the floating gate 116, and form the P-gate portion of the floating gate 116. N-doped ions implanted into the N active region penetrate into the floating gate 116 from its sides and form the N-gate portion of the floating gate 116. The CC line is the demarcation line between the P gate and the N gate in the floating gate 116, and is also the location of the PN junction in the floating gate 116. The distance H between it and the end of the floating gate 116 that is close to the capacitor 120 is 30 nm.

[0052] When doped ions are injected into the active region, the formed NMOS capacitor coupling region is adjacent to the three boundaries of the N gate. Doped ions at the edges of the NMOS capacitor coupling region adjacent to the N gate boundaries undergo rapid thermal annealing, causing thermal lateral diffusion. They penetrate into the P well 103 region below the three boundaries of the N gate, forming an overlap region between the floating gate 116 of width h and the NMOS capacitor coupling region.

[0053] During the programming period of the memory cell 100, electrons are injected into the floating gate 116 of the first transistor 110, resulting in a decrease in the threshold voltage of the first transistor 110, which makes it easier to conduct and causes a higher read current during the read operation period. For example, the memory cell 100 can be programmed by driving WL to 2V, BL to 2.5V, and COM to -2V. At the same time, the N well 102 and the deep N well 104 are driven to a potential of 3.3V. In the first transistor 110, the voltage difference between the source 111 and the drain 112 is 4.5V, and the transverse electric field from source 111 to drain 112 is much stronger than the longitudinal electric field from source 111 to floating gate 116. Therefore, holes are accelerated from one side of the channel 113 to the other (for example, channel 113 in Figures 2-3), resulting in impact ionization occurring in the depletion region of drain 112. Thermionic electrons generated by impact ionization are attracted to and injected into the forward-biased floating gate 116. The negative bias of source 111 (-2.0V) attracts most of the thermal holes, thereby tunneling a very small number of thermal holes into the floating gate 116. Consequently, the number of electrons in the floating gate 116 increases significantly during the programming period.

[0054] During the erase operation period of the memory cell 100, electrons are emitted from the floating gate 116 of the first transistor 110, causing the threshold voltage of the first transistor 110 to rise, thereby making it less conductive and reducing the read current during the read operation period. For example, the memory cell 100 performs an erase operation by driving WL to -4V and both BL and COM to 5V. Under these bias conditions, the lower plate of the NMOS capacitor 120 forms an inversion layer, and the floating gate 116 is coupled to a potential of approximately -3.5V. When the source 111 and drain 112 of the first transistor 110 are driven to 5V, an inversion layer is also formed within the channel region of the first transistor 110. The inverted channel connects the source 111 and the drain 112 and receives a voltage of 5V. As a result, the total voltage applied to the gate oxide 115 of the first transistor 110 is approximately 8.5V, which is sufficient to form a high electric field and cause electrons confined within the floating gate 116 to tunnel into an inverted channel filled with positive carriers. The high electric field may exceed approximately 10 MeV, and the tunneling mechanism is direct tunneling and / or Fowler-Nordheim tunneling. In this operation, the P well 103 can be driven to a negative potential value less than the bias (0V) of the substrate 101 because the P well 103 is separated from the deep N well 104 by the substrate 101. The N well 102 and the deep N well 104 are driven to 5V during the erasure period.

[0055] In a read operation, the first transistor 110 in the programmed and erased memory cell 100 has threshold voltages of approximately 0V and -1.5V, respectively. For example, when the memory cell 100 is programmed, the common line (COM) is driven to 1.2V, the bit line (BL) is pre-charged to 0V, the N wells 102 and deep N wells 104 are driven to 1.5V, and the word line WL is driven to 0V. The first transistor 110 of the memory cell 100 conducts, pulling BL up to 1.2V. The high voltage at BL is then detected by a sense amplifier and driven to output a data signal of one state "1".

[0056] In practical applications, multiple non-volatile memory cells 100 can be arranged together to form a memory array or memory.

[0057] In the storage array, the WL lines of the storage cells 100 in each row are connected, and the common line (COM) and bit line (BL) of the storage cells 100 in each column are connected, respectively. The storage array is constructed on a P-type substrate 101. The deep N wells 104 of the storage cells 100 are all merged to form a single deep N well. The N wells 102 and P wells 103 of the storage cells 100 within a single storage row are merged, respectively. As a result, each storage row contains one N well and one P well. By merging the wells within a row, most of the space between wells is eliminated, allowing for a higher density implementation of the storage cells 100 in the array. The storage array is constructed on a substrate 101 which is the same as the logic circuitry on other chips, and the logic circuitry requires the substrate 101 to be grounded or 0V.

[0058] The memory cell 100 is located in the N well 102 and may further include a second PMOS transistor connected in series with the first transistor 110. The drain of the second PMOS transistor is connected to the BL word line, its source overlaps with the drain 112 of the first transistor 110, and the source 111 of the first transistor 110 is still connected to the COM common line. The gate of the second PMOS transistor is connected to the word line WL, and the NMOS capacitor coupling region is connected to a control gate signal CG. During the memory operation period, the control gate signal CG is used to control the voltage of the floating gate 116.

[0059] When the memory cell 100 includes a second PMOS transistor, the programming, erasing, and reading operations and principles are the same as in the case without the second PMOS transistor. That is, the memory cell 100 is programmed by thermionic electrons from the channel of the first transistor 110 tunneling from the channel to the floating gate 116, and the erasing operation is completed by the FN mechanism, which tunnels electrons from the floating gate 116 of the first transistor 110 to the channel 113. For example, in the programming operation, programming is performed by driving WL to 0V, BL to 2.5V, CG to 2V, and COM to -2V. At the same time, the N well 102 and the deep N well 104 are driven to a potential of 2.5V. In the erasing operation, erasing is performed by driving WL to 5V, BL to 3.3V, CG to -4V, COM to 5V, and the N well 102 and the deep N well 104 to 5V. During the read operation, when the memory cell 100 is in a programmed state, WL, BL, and CG are driven to 0V, COM to 1.2V, and N-well 102 and deep N-well 104 to 1.5V.

[0060] In applications, multiple memory cells 100, including a second PMOS transistor, can also form a memory array or memory.

[0061] In the storage array, the WL and CG lines of the storage cells 100 in each row are connected, and the common line and bit line of the storage cells 100 in each column are connected. The storage array is constructed on a P-type substrate 101. The deep N wells 104 of the storage cells 100 are all merged to form a single deep N well. The N wells 102 and P wells 103 of the storage cells 100 within a single storage row are merged, respectively. As a result, each storage row contains one N well and one P well. By merging the wells within a row, most of the space between wells is eliminated, allowing for a higher density of storage cells 100 in the array. The storage array is constructed on a substrate 101 which is the same as the logic circuitry on other chips, and the logic circuitry requires the substrate 101 to be grounded or 0V.

[0062] The scope of protection for the technical solution of the present application in the specific embodiment is not limited, but merely illustrative. [Explanation of symbols]

[0063] 100 - Memory cell, 101 - Substrate, 102 - N-well, 103 - P-well, 104 - Deep N-well, 110 - First transistor, 111 - Source, 111A - Source low-concentration doped region, 111B - Source heavy-concentration doped P+ contact region, 112 - Drain, 112A - Drain low-concentration doped region, 112B - Drain heavy-concentration doped P+ contact region, 113 - Channel, 114 - Thick field oxide, 115 - Gate oxide, 116 - Floating gate, 117 - Sidewall spacer, 120 - Capacitor, 121 - Capacitor channel region, 122 - Capacitor active region

Claims

1. Non-volatile memory cell, It includes two different types of first and second wells placed side by side, One first transistor is located in the first well, and the first transistor includes a floating gate and its gate oxide. One capacitor is located in the second well, and the capacitor includes one coupling region located in the second well, and the floating gate and its gate oxide extend from the first well to the second well, constituting the gate and its gate oxide of the capacitor, A non-volatile memory cell characterized in that the floating gate includes two parts with different electrical properties, the boundary between the two parts with different electrical properties is close to one end of the floating gate, and the distance between the boundary and the adjacent end of the floating gate is less than 150 nm.

2. The non-volatile memory cell according to claim 1, characterized in that the distance between the boundary between two portions of the floating gate with different electrical properties and the adjacent floating gate end is 5 to 100 nm.

3. The non-volatile memory cell according to claim 1, characterized in that the distance between the boundary between two portions of the floating gate with different electrical properties and the adjacent end of the floating gate is 10 to 70 nm.

4. The non-volatile memory cell according to claim 1, characterized in that the floating gate end where the boundary between two parts of the floating gate with different electrical properties are in close proximity is the end of the floating gate that is close to the capacitor and far from the first transistor.

5. The non-volatile memory cell according to claim 4, characterized in that the first transistor includes a source and a drain, each of the source and drains includes a high-concentration doped ion region, and / or the coupling region of the capacitor is a low-concentration doped ion region.

6. A non-volatile storage cell according to any one of claims 1 to 5, further comprising a second transistor, the second transistor being of the same type as the first transistor, and also located in the first well, and connected in series with the first transistor.

7. The non-volatile storage cell according to any one of claims 1 to 5, characterized in that the first well and the second well are an N well and a P well, respectively, the first transistor is a PMOS transistor, the capacitor is an NMOS capacitor, and the coupling region in the second well of the capacitor is an N coupling region.

8. A non-volatile memory comprising at least one non-volatile storage cell according to claim 1 constructed on a substrate, wherein the substrate includes one deep well, and the first well and the second well in the non-volatile storage cell are located within the deep well.

9. The non-volatile memory according to claim 8, characterized in that the substrate is a P-type substrate, the deep well is a deep N-well, the first well and the second well are an N-well and a P-well, respectively, the first transistor is a PMOS transistor, the capacitor is an NMOS capacitor, and the coupling region in the second well of the capacitor is an N-coupling region.

10. The non-volatile memory according to any one of claims 8 to 9, characterized in that the non-volatile memory is a non-volatile memory that can be programmably erased multiple times.

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