Structure and its manufacturing method, semiconductor chip package and its manufacturing method, and semiconductor device

Abstract

The present invention provides a structure that can suppress warping of semiconductor chips after mounting, and a method for manufacturing the same. [Solution] A method for manufacturing a structure for mounting semiconductor chips; The structure comprises a core substrate, a chip-side build-up layer formed on the first side surface of the core substrate, and an opposite-side build-up layer formed on the second side surface of the core substrate opposite to the first side surface; The chip-side build-up layer comprises multiple insulating layers, wherein all of the multiple insulating layers comprising the chip-side build-up layer do not contain a fibrous substrate, or a portion of the multiple insulating layers comprising the chip-side build-up layer contain a fibrous substrate; The opposite build-up layer comprises multiple insulating layers, and a portion of the multiple insulating layers comprising the opposite build-up layer includes a fibrous substrate; A method for manufacturing a structure includes a plurality of steps (i) of forming an insulating layer on the first side surface of a core substrate and a plurality of steps (ii) of forming an insulating layer on the second side surface of a core substrate; A method for manufacturing a structure, wherein the number of insulating layers containing a fibrous substrate in the opposite build-up layer is 5% or more and 80% or less of the total number of insulating layers in the opposite build-up layer (100%), and the number of insulating layers containing a fibrous substrate in the opposite build-up layer is greater than the number of insulating layers containing a fibrous substrate in the chip-side build-up layer.

Description

[Technical Field]

[0001] The present invention relates to a structure for mounting a semiconductor chip on one side and a method for manufacturing the same. The present invention also relates to a semiconductor chip package comprising the said structure, a method for manufacturing the same, and a semiconductor device. [Background technology]

[0002] When mounting semiconductor chips onto a printed circuit board, structures such as package substrates are sometimes used. For example, a semiconductor chip is mounted on a structure to form a semiconductor chip package, and this semiconductor chip package is then placed on the printed circuit board. Generally, structures have wiring. Therefore, the semiconductor chip and the printed circuit board are electrically connected through the wiring of the structure, thus enabling the mounting of the semiconductor chip onto the printed circuit board.

[0003] The aforementioned structure may be manufactured, for example, by a method that includes forming a conductive layer on both sides of a core substrate via an insulating layer (Patent Documents 1 and 2). In this case, the conductive layer may form wiring that connects a semiconductor chip and a wiring board. The insulating layer may also be manufactured using a prepreg containing a fibrous substrate (Patent Document 3). [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2015-122386 [Patent Document 2] Japanese Patent Publication No. 2024-125831 [Patent Document 3] International Publication No. 2009 / 119621 [Overview of the project] [Problems that the invention aims to solve]

[0005] The above-described structure may include a build-up layer including a plurality of insulating layers. This build-up layer usually includes a plurality of insulating layers and conductor layers respectively, and is provided, for example, by a method of alternately forming insulating layers and conductor layers. In recent years, the number of layers included in this build-up layer has increased, and thus the thickness of the build-up layer may have become large. When the thickness of the build-up layer is large, a large warp may occur in a semiconductor chip package obtained by mounting a semiconductor chip on the structure.

[0006] The present invention was conceived in view of the above problems, and aims to provide a structure and a manufacturing method thereof that can suppress warping after mounting a semiconductor chip; a semiconductor chip package including the structure and a manufacturing method thereof; and a semiconductor device including the above semiconductor chip package.

Means for Solving the Problems

[0007] The inventor of the present invention has intensively studied to solve the above problems. As a result, the inventor has found that when an insulating layer containing a fiber base material is introduced into a part of the build-up layer so as to satisfy specific requirements, the above problems can be solved, and the present invention has been completed. That is, the present invention includes the following.

[0008] <1> A method for manufacturing a structure for mounting a semiconductor chip, comprising: The structure includes a core substrate, a chip-side build-up layer formed on a first side surface of the core substrate, and an opposite-side build-up layer formed on a second side surface opposite to the first side surface of the core substrate, and the chip-side build-up layer includes a plurality of insulating layers; either all of the plurality of insulating layers included in the chip-side build-up layer do not contain a fiber base material, or a part of the plurality of insulating layers included in the chip-side build-up layer contains a fiber base material; the opposite-side build-up layer includes a plurality of insulating layers; Some of the multiple insulating layers of the opposite build-up layer include a fibrous substrate; The method for manufacturing the structure is Multiple steps (i) to form an insulating layer on the first side surface of the core substrate and Multiple steps (ii) to form an insulating layer on the second side surface of the core substrate, Includes; The number of insulating layers containing fibrous substrates in the opposite build-up layer is between 5% and 80% of the total number of insulating layers in the opposite build-up layer (100%); A method for manufacturing a structure, wherein the number of insulating layers containing fibrous substrates in the opposite build-up layer is greater than the number of insulating layers containing fibrous substrates in the chip-side build-up layer. <2> A method for manufacturing a structure for mounting semiconductor chips; The structure is core substrate and A chip-side build-up layer formed on the first side surface of the core substrate, The core substrate comprises a second side surface formed on the opposite side to the first side surface, and a reverse build-up layer formed on the second side surface opposite to the first side surface; The chip-side build-up layer comprises multiple insulating layers; Either all of the multiple insulating layers of the chip-side build-up layer do not contain a fibrous substrate, or some of the multiple insulating layers of the chip-side build-up layer contain a fibrous substrate; The opposite build-up layer comprises multiple insulating layers; Some of the multiple insulating layers of the opposite build-up layer include a fibrous substrate; The method for manufacturing the structure is Multiple steps (i) to form an insulating layer on the first side surface of the core substrate and Multiple steps (ii) to form an insulating layer on the second side surface of the core substrate, Includes; The total thickness of the insulating layers, including the fibrous substrate, in the opposite build-up layer is between 5% and 80% of the total thickness of the multiple insulating layers in the opposite build-up layer, with the total thickness being 100%. A method for manufacturing a structure, wherein the total thickness of the insulating layer containing the fibrous substrate in the opposite build-up layer is greater than the total thickness of the insulating layer containing the fibrous substrate in the chip-side build-up layer. <3> Multiple steps (ii) for forming an insulating layer on the second side surface of the core substrate include a step for forming an insulating layer including a fibrous substrate; The step of forming an insulating layer including a fibrous substrate includes laminating a fibrous sheet having a prepreg layer; The prepreg layer comprises a fibrous substrate and a resin composition impregnated into the fibrous substrate. <1> or <2> A method for manufacturing the structure described above. <4> The lamination of fiber-reinforced sheets is carried out by the lamination method. <3> A method for manufacturing the structure described above. <5> The fiber-reinforced sheet comprises a prepreg layer and a cured layer formed on one side of the prepreg layer. The cured layer contains a cured product of a thermosetting resin composition. <3> or <4> A method for manufacturing the structure described above. <6> The minimum melt viscosity of the prepreg layer in the temperature range of 100°C to 140°C is 10,000 poise or less. <3> ~ <5> A method for manufacturing the structure described in any one of the items. <7> The glass transition temperature of the cured sample obtained by curing the fiber-reinforced sheet is 250°C or lower. <3> ~ <6> A method for manufacturing the structure described in any one of the items. <8> Multiple steps (ii) for forming an insulating layer on the second side surface of the core substrate include a step for forming an insulating layer that does not contain a fiber substrate; The step of forming an insulating layer that does not contain a fibrous substrate includes laminating a resin composition layer that does not contain a fibrous substrate; The absolute difference between the glass transition temperature of a cured sample obtained by curing a fiber-reinforced sheet and the glass transition temperature of a cured sample obtained by curing a resin composition layer is 80°C or less. <3> ~ <7> A method for manufacturing the structure described in any one of the items. <9> The core substrate has a thickness of 0.1 mm or more and 2 mm or less. <1> ~ <8> A method for manufacturing the structure described in any one of the items. <10> The opposite build-up layer has four or more insulating layers. <1> ~ <9> A method for manufacturing the structure described in any one of the items. <11> The opposite build-up layer has a thickness of 60 μm to 700 μm. <1> ~ <10> A method for manufacturing the structure described in any one of the items. <12> The number of insulating layers on the chip-side build-up layer is the same as the number of insulating layers on the opposite-side build-up layer. <1> ~ <11> A method for manufacturing the structure described in any one of the items. <13> A structure for mounting semiconductor chips; The structure is core substrate and A chip-side build-up layer formed on the first side surface of the core substrate, The core substrate comprises a second side surface formed on the opposite side to the first side surface, and a reverse build-up layer formed on the second side surface opposite to the first side surface; The chip-side build-up layer comprises multiple insulating layers; Either all of the multiple insulating layers of the chip-side build-up layer do not contain a fibrous substrate, or some of the multiple insulating layers of the chip-side build-up layer contain a fibrous substrate; The opposite build-up layer comprises multiple insulating layers; Some of the multiple insulating layers of the opposite build-up layer include a fibrous substrate; The number of insulating layers containing fibrous substrates in the opposite build-up layer is between 5% and 80% of the total number of insulating layers in the opposite build-up layer (100%); A structure in which the number of insulating layers containing fibrous substrates in the opposite build-up layer is greater than the number of insulating layers containing fibrous substrates in the chip-side build-up layer. <14> A structure for mounting semiconductor chips; The structure is core substrate and A chip-side build-up layer formed on the first side surface of the core substrate, The core substrate comprises a second side surface formed on the opposite side to the first side surface, and a reverse build-up layer formed on the second side surface opposite to the first side surface; The chip-side build-up layer comprises multiple insulating layers; Either all of the multiple insulating layers of the chip-side build-up layer do not contain a fibrous substrate, or some of the multiple insulating layers of the chip-side build-up layer contain a fibrous substrate; The opposite build-up layer comprises multiple insulating layers; Some of the multiple insulating layers of the opposite build-up layer include a fibrous substrate; The total thickness of the insulating layers, including the fibrous substrate, in the opposite build-up layer is between 5% and 80% of the total thickness of the multiple insulating layers in the opposite build-up layer, with the total thickness being 100%. A structure in which the total thickness of the insulating layer, including the fibrous substrate, in the opposite build-up layer is greater than the total thickness of the insulating layer, including the fibrous substrate, in the chip-side build-up layer. <15> <13> or <14> A method for manufacturing a semiconductor chip package, comprising the step of mounting a semiconductor chip on the chip-side build-up layer of the structure described above. <16> <13> or <14> A semiconductor chip package comprising the structure described above and a semiconductor chip mounted on the chip-side build-up layer of the said structure. <17> <16> A semiconductor device comprising the semiconductor chip package described above. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide a structure that can suppress warping of a semiconductor chip after mounting and a method for manufacturing the same; a semiconductor chip package including the structure and a method for manufacturing the same; and a semiconductor device equipped with the semiconductor chip package. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a schematic cross-sectional view showing a structure according to one embodiment of the present invention. [Figure 2] Figure 2 is a schematic plan view showing a portion of a fibrous substrate, as seen from the thickness direction, as an example. [Figure 3] Figure 3 is a schematic cross-sectional view illustrating the manufacturing process of an example structure. [Figure 4]Figure 4 is a schematic cross-sectional view illustrating the manufacturing process of an example structure. [Figure 5] Figure 5 is a schematic cross-sectional view illustrating the manufacturing process of an example structure. [Figure 6] Figure 6 is a schematic cross-sectional view illustrating the manufacturing process of an example structure. [Figure 7] Figure 7 is a schematic cross-sectional view illustrating the manufacturing process of an example structure. [Figure 8] Figure 8 is a schematic cross-sectional view showing a semiconductor chip package according to one embodiment of the present invention. [Figure 9] Figure 9 is a schematic cross-sectional view showing an intermediate stack obtained in the process of manufacturing a semiconductor chip package according to one embodiment of the present invention. [Figure 10] Figure 10 is a schematic cross-sectional view showing a semiconductor chip package according to one embodiment of the present invention. [Modes for carrying out the invention]

[0011] The present invention will be described below with reference to embodiments and examples. However, the present invention is not limited to the embodiments and examples shown below, and may be modified and implemented without departing from the scope of the claims and their equivalents.

[0012] In the following description, unless otherwise specified, "parallel" and "perpendicular" are preferably error-free, but may contain errors. The error range is typically ±5°, preferably ±3°, more preferably ±1°, and even more preferably ±0.5°.

[0013] <Overview of the structural embodiment> Figure 1 is a schematic cross-sectional view showing a structure 10 according to one embodiment of the present invention. As shown in Figure 1, the structure 10 according to one embodiment of the present invention comprises a core substrate 100, a chip-side build-up layer 200 formed on the first side surface 100U of the core substrate 100, and an opposite side build-up layer 300 formed on the second side surface 100D opposite to the first side surface 100U of the core substrate 100. This structure 10 is a component for mounting a semiconductor chip (not shown) on one side thereof, and specifically, a semiconductor chip is mounted on the chip-side build-up layer 200. Therefore, the first side surface 100U of the core substrate 100 corresponds to the chip-side surface, and the second side surface 100D corresponds to the opposite side. Hereinafter, the first side surface 100U may be referred to as the "chip side" 100U, and the second side surface 100D may be referred to as the "opposite side" 100D.

[0014] The chip-side build-up layer 200 comprises a plurality of insulating layers 211, 212, 213, and 214. Hereinafter, the insulating layers 211, 212, 213, and 214 of the chip-side build-up layer 200 may be referred to as "chip-side insulating layers" 211, 212, 213, and 214. In this embodiment, an example is shown of the chip-side build-up layer 200 comprising chip-side insulating layer 211, chip-side insulating layer 212, chip-side insulating layer 213, and chip-side insulating layer 214 in that order from the core substrate 100 side.

[0015] Furthermore, the opposite side build-up layer 300 comprises a plurality of insulating layers 311, 312, 313, and 314. Hereinafter, the insulating layers 311, 312, 313, and 314 provided by the opposite side build-up layer 300 may be referred to as "opposite side insulating layers" 311, 312, 313, and 314. In this embodiment, an example is shown of the opposite side build-up layer 300 comprising opposite side insulating layer 311, opposite side insulating layer 312, opposite side insulating layer 313, and opposite side insulating layer 314 in this order from the core substrate 100 side. Therefore, in the thickness direction, the structure 10 comprises opposite side insulating layer 314, opposite side insulating layer 313, opposite side insulating layer 312, opposite side insulating layer 311, core substrate 100, chip side insulating layer 211, chip side insulating layer 212, chip side insulating layer 213, and chip side insulating layer 214 in this order.

[0016] The chip-side insulating layers 211-214 and the opposite-side insulating layers 311-314 all contain a cured resin composition. Furthermore, a portion of the opposite-side insulating layers 311-314 contains a fiber substrate 400. In this case, the fiber substrate 400 is used such that the number of opposite-side insulating layers containing the fiber substrate 400 in the opposite-side build-up layer 300 is greater than the number of chip-side insulating layers containing the fiber substrate 400 in the chip-side build-up layer 200. Therefore, a portion of the multiple chip-side insulating layers 211-214 in the chip-side build-up layer 200 may contain the fiber substrate 400. Also, not all of the multiple chip-side insulating layers 211-214 contain the fiber substrate 400.

[0017] Furthermore, the ratio of the number of opposite-side insulating layers 314 containing the fibrous substrate 400 in the opposite-side build-up layer 300 to 100% of the total number of opposite-side insulating layers 311 to 314 in the opposite-side build-up layer 300 is within a specific range. This ratio may hereafter be referred to as the "fibrous substrate content ratio" or the "fiberus substrate content ratio based on the number of layers." The fiberus substrate content ratio based on the number of layers in the opposite-side build-up layer 300 is usually 5% or more, preferably 8% or more, more preferably 12% or more, preferably 80% or less, more preferably 65% ​​or less, and even more preferably 50% or less.

[0018] Figure 1 shows an example in which the outermost opposite-side insulating layer 314 of the opposite-side build-up layer 300 contains the fiber substrate 400, while the other opposite-side insulating layers 311-313 and all chip-side insulating layers 211-214 do not contain the fiber substrate 400. Therefore, in the example shown in Figure 1, the opposite-side build-up layer 300 has four opposite-side insulating layers 311-314, and one of these opposite-side insulating layers 314 contains the fiber substrate 400, so the fiber substrate content ratio based on the number of layers is 25%.

[0019] According to the structure 10, warping after mounting a semiconductor chip on the chip-side build-up layer 200 of the structure 10 can be suppressed. Specifically, according to the structure 10 of this embodiment, warping can be suppressed after the reflow process in which the semiconductor chip is mounted.

[0020] Some or all of the chip-side insulating layers 211-214 provided by the chip-side build-up layer 200 may have holes 221-224, such as via holes. The chip-side build-up layer 200 may also have any additional layers in combination with the chip-side insulating layers 211-214, for example, it may have conductive layers 231, 232, 233 and 234. The conductive layers 231-234 may be formed on the surface of the insulating layers 211-214 or within the holes 221-224.

[0021] The opposite side build-up layer 300 may have some or all of the opposite side insulating layers 311-314 with holes 321-324, such as via holes. The opposite side build-up layer 300 may also have any other layer in combination with the opposite side insulating layers 311-314, for example, it may have conductor layers 331, 332, 333 and 334. The conductor layers 331-334 may be formed on the surface of the insulating layers 311-314 or within the holes 321-324.

[0022] In the above, a preferred embodiment of the present invention has been described based on the fiber substrate ratio on a layer-by-layer basis. However, the present invention may also be specified by the ratio of the thickness of insulating layers containing fiber substrates instead of the ratio of the number of insulating layers containing fiber substrates. Therefore, in another embodiment of the present invention, the total thickness of the opposite insulating layers containing fiber substrates 400 in the opposite build-up layer 300 is greater than the total thickness of the chip-side insulating layers containing fiber substrates 400 in the chip-side build-up layer 200, and the ratio of the total thickness of the opposite insulating layers 314 containing fiber substrates 400 in the opposite build-up layer 300 to the total thickness of the multiple opposite insulating layers 311 to 314 in the opposite build-up layer 300 is within a specific range. The above ratio may hereinafter be referred to as the "thickness-based fiber substrate content ratio". The thickness-based fiber substrate content ratio of the opposite insulating layer 314 containing fiber substrates 400 in the opposite build-up layer 300 is usually 5% or more, preferably 8% or more, more preferably 12% or more, preferably 80% or less, more preferably 65% ​​or less, and even more preferably 50% or less. In this embodiment, the fibrous substrate 400 is used such that the total thickness of the opposite insulating layer including the fibrous substrate 400 in the opposite build-up layer 300 is greater than the total thickness of the chip-side insulating layer including the fibrous substrate 400 in the chip-side build-up layer 200. In this embodiment as well, some of the multiple chip-side insulating layers 211 to 214 provided in the chip-side build-up layer 200 may include the fibrous substrate 400, and not all of the multiple chip-side insulating layers 211 to 214 include the fibrous substrate 400. The present invention only needs to satisfy at least one of the following conditions (1) and (2). (1) The number of opposite-side insulating layers containing fiber substrate 400 in the opposite-side build-up layer 300 is greater than the number of chip-side insulating layers containing fiber substrate 400 in the chip-side build-up layer 200, and the "layer-based fiber substrate ratio" in the opposite-side build-up layer 300 is within the above-specified range. (2) The total thickness of the opposite side insulating layer, including the fibrous substrate 400 in the opposite side build-up layer 300, is greater than the total thickness of the chip side insulating layer, including the fibrous substrate 400 in the chip side build-up layer 200, and the "thickness-based fibrous substrate content ratio" in the opposite side build-up layer 300 is within the above-mentioned specific range.

[0023] <Core substrate 100> The core substrate 100 is a base material for the structure 10, and examples include glass epoxy substrates, metal substrates, polyester substrates, polyimide substrates, BT resin substrates, thermosetting polyphenylene ether substrates, etc. The core substrate 100 may also have conductive layers 120 and 130 on one or both sides. For example, the core substrate 100 may comprise a support substrate 110 and conductive layers 120 and 130 formed on the support substrate 110. The conductive layers 120 and 130 of the core substrate 100 may be patterned. Such conductive layers 120 and 130 can function as circuits. Furthermore, a core substrate 100 equipped with components (not shown) may be used.

[0024] The thickness of the core substrate 100 is preferably 2 mm or less, more preferably 1 mm or less, and even more preferably 0.5 mm or less. Conventionally, when such a thin core substrate is used, warping tends to occur easily, but according to the structure 10 of this embodiment, warping can be suppressed even when such a thin core substrate 100 is used. The lower limit of the thickness of the core substrate 100 is preferably 0.1 mm or more, more preferably 0.2 mm or more. When the lower limit of the thickness of the core substrate 100 is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed.

[0025] <Opposite side build-up layer 300> As described above, the opposite side build-up layer 300 comprises a plurality of opposite side insulating layers 311 to 314. Specifically, the range of the number of opposite side insulating layers 311 to 314 comprising the opposite side build-up layer 300 is typically two or more layers, preferably three or more layers, more preferably four or more layers, preferably 20 or fewer layers, more preferably 15 or fewer layers, even more preferably 10 or fewer layers, and particularly preferably 8 or fewer layers.

[0026] Each of the multiple opposite insulating layers 311 to 314 contains a cured product obtained by curing a resin composition. The resin composition is usually a thermosetting resin composition, and therefore the cured product may be obtained by thermosetting the resin composition. Details of the resin composition will be described later.

[0027] A portion of the opposite-side insulating layer 314 of the opposite-side build-up layer 300 is combined with the cured resin composition to form a fibrous substrate 400. The fibrous substrate 400 generally includes a plurality of filaments 411 and 421. Gaps are formed between these filaments 411 and 421, and the cured resin composition can be held in these gaps. For example, after the fibrous substrate 400 is impregnated with the resin composition, the resin composition hardens to form a cured product, resulting in a state where the cured product is held in the gaps between the filaments 411 and 421. Furthermore, the cured product may be held not only in the gaps between the filaments 411 and 421 of the fibrous substrate 400, but also around the filaments 411 and 421.

[0028] The fibrous base material 400 may be, for example, a nonwoven fabric. Alternatively, for example, the fibrous base material 400 may include yarns 410 and 420 that are bundles of multiple filaments 411 and 412. Figure 2 is a schematic plan view showing a part of an example of the fibrous base material 400 as seen from its thickness direction. As shown in Figure 2, the fibrous base material 400 may be a cloth material woven from warp threads 410 and weft threads 420. In this embodiment, as shown in Figure 2, the fibrous base material 400 as a cloth material including multiple warp threads 410 and multiple weft threads 420 will be described as an example.

[0029] The warp thread 410 is a yarn made by bundling multiple filaments 411, and therefore contains multiple filaments 411. Similarly, the weft thread 420 is a yarn made by bundling multiple filaments 421, and therefore contains multiple filaments 421. As shown in Figure 2, the fibrous base material 400 is formed by weaving the warp thread 410 and the weft thread 420 together. Therefore, when viewed from the thickness direction, the warp thread 410 and the weft thread 420 can be arranged to intersect perpendicularly.

[0030] The range of the number of threads per unit dimension contained in the fiber base material 400 is preferably 50 threads / 25 mm or more, more preferably 55 threads / 25 mm or more, even more preferably 60 threads / 25 mm or more, even more preferably 70 threads / 25 mm or more, preferably 150 threads / 25 mm or less, more preferably 130 threads / 25 mm or less, and even more preferably 120 threads / 25 mm or less. "Number of threads per unit dimension" refers to the number of threads per unit dimension in the in-plane direction perpendicular to the direction in which the thread extends. Therefore, for example, the number of warp threads 410 per unit dimension refers to the number of warp threads 410 per unit dimension in the in-plane direction perpendicular to the direction in which the warp threads 410 extend (usually the direction in which the weft threads extend). Hereinafter, the number of warp threads 410 per unit dimension may be called the "warp density". Similarly, the number of weft threads 420 per unit dimension may be called the "weft density". The warp density and weft density may be the same or different. When the number of threads per unit length falls within the aforementioned range, warping after mounting of semiconductor chips can be effectively suppressed.

[0031] As the material for the filaments 411 and 421, insulating materials are preferred, and materials with a small dielectric loss tangent are even more preferred. Preferred examples of materials for the filaments 411 and 421 include glass materials; resin materials such as aramid resin and liquid crystal polymer; and among these, glass materials are preferred. When using glass materials, the fiber base material 400 may be glass cloth, and the filaments 411 and 421 may be glass filaments.

[0032] The fibrous substrate 400 may be surface-treated with a surface treatment agent. By performing surface treatment, the formation of voids in the insulating layer (in the example shown in this embodiment, the opposite insulating layer 414) containing the fibrous substrate 400 can be suppressed. Examples of surface treatment agents include coupling agents such as silane coupling agents and titanate coupling agents; silane compounds such as alkoxysilanes and organosilazane compounds, among which coupling agents are preferred, and silane coupling agents are more preferred. Examples of silane coupling agents include aminosilane coupling agents, fluorine-containing silane coupling agents, epoxysilane coupling agents, and mercaptosilane coupling agents, with aminosilane coupling agents being more preferred. The surface treatment agent may be used alone or in combination of two or more types.

[0033] The weight per unit area of ​​the fiber base material 400 is sometimes referred to as the "fabric weight." The fabric weight of the fiber base material 400 is preferably in the range of 5 g / m². 2 Above, a comfortable 10g / m 2 More preferably 15 g / m² 2 The above is preferable, with a density of 50 g / m². 2 More preferably 40 g / m 2 More preferably 30 g / m 2 The following applies: When the fabric weight is within the aforementioned range, warping after semiconductor chip mounting can be effectively suppressed.

[0034] Commercially available products may be used as the fiber base material 400. Examples of commercially available fiber base materials 400 include: glass cloths "Style WEA1017", "Style WEA1024", "Style WEA1010", "Style WEA1027", "Style WEA1035", and "Style WEA1037" manufactured by Nitto Boseki Co., Ltd.; glass cloths "Style 1027MS" and "Style 1037MS" manufactured by Asahi Schwebel Co., Ltd.; glass cloths "1078", "1037NS", "1027NS", "1015NS", and "1000NS" manufactured by Arisawa Seisakusho Co., Ltd.; and nonwoven fabrics "Veclus" and "Vectran" manufactured by Kuraray Co., Ltd.

[0035] The fibrous base material 400 is preferably thin. The specific thickness range of the fibrous base material 400 is preferably 50 μm or less, more preferably 40 μm or less, even more preferably 30 μm or less, and even more preferably 20 μm or less. The lower limit may be, for example, 5 μm or more or 10 μm or more.

[0036] The number of opposite-side insulating layers (such as the opposite-side insulating layer 314) containing a fibrous substrate can be set so that the fibrous substrate content falls within the aforementioned range. Specifically, the number of opposite-side insulating layers containing a fibrous substrate is usually one or more, preferably three or fewer, and more preferably two or fewer. When the number of opposite-side insulating layers containing a fibrous substrate is within the aforementioned range, warping after mounting of the semiconductor chip can be effectively suppressed.

[0037] The opposite side build-up layer 300 preferably includes a fibrous substrate 400 in the opposite side insulating layer 314, which is furthest from the core substrate 100, as shown in Figure 1. In this case, warping after mounting of the semiconductor chip can be effectively suppressed.

[0038] The opposite insulating layer (e.g., opposite insulating layer 314) containing the fibrous substrate preferably has a small linear thermal expansion coefficient in the high-temperature measurement range corresponding to the reflow temperature. Specifically, the range of the linear thermal expansion coefficient CTE(FOh) of the opposite insulating layer containing the fibrous substrate in the high-temperature measurement range is preferably 25 ppm / °C or less, more preferably 20 ppm / °C or less, and even more preferably 16 ppm / °C or less. The lower limit may be, for example, 5 ppm / °C or more. The "high-temperature measurement range" may be, for example, a temperature range of 150°C to 240°C, and the same applies to the following description. When the linear thermal expansion coefficient CTE(FOh) of the opposite insulating layer containing the fibrous substrate is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed. When the opposite build-up layer 300 comprises multiple opposite insulating layers containing fibrous substrates, the linear thermal expansion coefficients CTE(FOh) of each of these opposite insulating layers may be different, but it is preferable that they be the same.

[0039] It is preferable that the difference between the linear thermal expansion coefficient CTE(FOh) of the opposite insulating layer (opposite insulating layer 314, etc.) containing the fibrous substrate in the high-temperature measurement range and the linear thermal expansion coefficient CTE(FOl) in the low-temperature measurement range, which is lower than the high-temperature measurement range, is small. Specifically, the range of the difference "CTE(FOh)-CTE(FOl)" between the linear thermal expansion coefficient CTE(FOh) of the opposite insulating layer containing the fibrous substrate in the high-temperature measurement range and its linear thermal expansion coefficient CTE(FOl) in the low-temperature measurement range is preferably 10 ppm / °C or less, more preferably 5 ppm / °C or less, and even more preferably 2 ppm / °C or less. In this case, it is even more preferable that the linear thermal expansion coefficient CTE(FOh) of the opposite insulating layer containing the fibrous substrate in the high-temperature measurement range is smaller than the linear thermal expansion coefficient CTE(FOl) in the low-temperature measurement range. Therefore, the difference "CTE(FOh)-CTE(FOl)" is even more preferably less than 0 ppm / °C, and particularly preferably -1 ppm / °C or less. The lower limit may be, for example, -10 ppm / °C or higher, or -5 ppm / °C or higher. The "low temperature measurement range" may be, for example, a temperature range of 25°C to 150°C, and the same applies to the following explanation. When the difference in the linear thermal expansion coefficients of the opposite insulating layer including the fibrous substrate, "CTE(FOh)-CTE(FOl)", is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed.

[0040] Preferably, the linear thermal expansion coefficient CTE(FOh) of the opposite insulating layer containing the fibrous substrate (e.g., opposite insulating layer 314) in the high-temperature measurement range is smaller than the linear thermal expansion coefficient CTE(ROh) of the opposite insulating layer not containing the fibrous substrate (e.g., opposite insulating layers 311-313) in the high-temperature measurement range. In this case, it is preferable that the difference "CTE(ROh)-CTE(FOh)" between the linear thermal expansion coefficient CTE(ROh) of the opposite insulating layer not containing the fibrous substrate in the high-temperature measurement range and the linear thermal expansion coefficient CTE(FOh) of the opposite insulating layer containing the fibrous substrate in the high-temperature measurement range is within a specific range. Specifically, the range of the above-mentioned difference in linear thermal expansion coefficients "CTE(ROh)-CTE(FOh)" is preferably 10 ppm / °C or more, more preferably 15 ppm / °C or more, even more preferably 20 ppm / °C or more, preferably 70 ppm / °C or less, more preferably 50 ppm / °C or less, and even more preferably 35 ppm / °C or less. When the difference in linear thermal expansion coefficients, "CTE(ROh)-CTE(FOh)," falls within the aforementioned range, warping of semiconductor chips after mounting can be effectively suppressed.

[0041] Preferably, the linear thermal expansion coefficient CTE(FOh) of the opposite insulating layer containing the fibrous substrate (e.g., opposite insulating layer 314) in the high-temperature measurement range is smaller than the linear thermal expansion coefficient CTE(RCh) of the chip-side insulating layer not containing the fibrous substrate (e.g., chip-side insulating layers 211-214) in the high-temperature measurement range. In this case, it is preferable that the difference "CTE(RCh)-CTE(FOh)" between the linear thermal expansion coefficient CTE(RCh) of the chip-side insulating layer not containing the fibrous substrate in the high-temperature measurement range and the linear thermal expansion coefficient CTE(FOh) of the opposite insulating layer containing the fibrous substrate in the high-temperature measurement range is within a specific range. Specifically, the range of the difference "CTE(RCh)-CTE(FOh)" may be the same as the range of the difference "CTE(ROh)-CTE(FOh)" between the linear thermal expansion coefficient CTE(ROh) of the opposite insulating layer not containing the fibrous substrate in the high-temperature measurement range and the linear thermal expansion coefficient CTE(FOh) of the opposite insulating layer containing the fibrous substrate in the high-temperature measurement range. When the difference in linear thermal expansion coefficients, "CTE(RCh)-CTE(FOh)", falls within the aforementioned range, warping of the semiconductor chip after mounting can be effectively suppressed.

[0042] When the chip-side build-up layer 200 includes a chip-side insulating layer (not shown in Figure 1) containing a fiber substrate, the linear thermal expansion coefficient CTE(FOh) of the opposite insulating layer containing the fiber substrate in the high-temperature measurement range and the linear thermal expansion coefficient CTE(FCh) of the chip-side insulating layer containing the fiber substrate in the high-temperature measurement range may be different, but it is preferable that the difference is small. In one example, the range of the absolute value of the difference between the linear thermal expansion coefficient CTE(FOh) of the opposite insulating layer containing the fiber substrate in the high-temperature measurement range and the linear thermal expansion coefficient CTE(FCh) of the chip-side insulating layer containing the fiber substrate in the high-temperature measurement range, "CTE(FOh)-CTE(FCh)", is preferably 10 pm / °C or less, more preferably 5 ppm / °C or less, even more preferably 3 ppm / °C or less, and particularly preferably 0 ppm / °C. Therefore, it is particularly preferable that the linear thermal expansion coefficient CTE(FCh) of the chip-side insulating layer including the fiber substrate in the high-temperature measurement range and the linear thermal expansion coefficient CTE(FOh) of the opposite insulating layer including the fiber substrate in the high-temperature measurement range are the same.

[0043] Preferably, the opposite insulating layer (opposite insulating layer 314, etc.) containing the fibrous substrate has a small linear thermal expansion coefficient in a low-temperature measurement range lower than the high-temperature measurement range. Specifically, the range of the linear thermal expansion coefficient CTE(FOl) of the opposite insulating layer (opposite insulating layer 314, etc.) containing the fibrous substrate in the low-temperature measurement range is preferably 30 ppm / °C or less, more preferably 25 ppm / °C or less, even more preferably 20 ppm / °C or less, and particularly preferably 19 ppm / °C or less. The lower limit may be, for example, 5 ppm / °C or more. When the linear thermal expansion coefficient CTE(FOl) of the opposite insulating layer containing the fibrous substrate in the low-temperature measurement range is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed. When the opposite build-up layer 300 comprises a plurality of opposite insulating layers containing fibrous substrates, the linear thermal expansion coefficients CTE(FOl) of each of these opposite insulating layers may be different, but are preferably the same.

[0044] Preferably, the linear thermal expansion coefficient CTE(FOl) of the opposite insulating layer containing the fibrous substrate (e.g., opposite insulating layer 314) in the low-temperature measurement range is close to the linear thermal expansion coefficient CTE(ROl) of the opposite insulating layer not containing the fibrous substrate (e.g., opposite insulating layers 311-313) in the low-temperature measurement range. In this case, the absolute value |CTE(ROl)-CTE(FOl)| of the difference "CTE(ROl)-CTE(FOl)" between the linear thermal expansion coefficient CTE(ROl) of the opposite insulating layer not containing the fibrous substrate and the linear thermal expansion coefficient CTE(FOl) of the opposite insulating layer containing the fibrous substrate in the low-temperature measurement range is preferably 25 ppm / °C or less, more preferably 20 ppm / °C or less, and even more preferably 10 ppm / °C or less. When the absolute value |CTE(ROl)-CTE(FOl)| of the difference in linear thermal expansion coefficients is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed.

[0045] Preferably, the linear thermal expansion coefficient CTE(FOl) of the opposite insulating layer containing the fibrous substrate (e.g., opposite insulating layer 314) in the low-temperature measurement range is close to the linear thermal expansion coefficient CTE(RCl) of the chip-side insulating layer (e.g., chip-side insulating layers 211-214) in the low-temperature measurement range. In this case, the range of the absolute value |CTE(RCl)-CTE(FOl)| of the difference "CTE(RCl)-CTE(FOl)" between the linear thermal expansion coefficient CTE(RCl) of the chip-side insulating layer without the fibrous substrate in the low-temperature measurement range and the linear thermal expansion coefficient CTE(FOl) of the opposite insulating layer containing the fibrous substrate in the low-temperature measurement range may be the same as the range of the absolute value |CTE(ROl)-CTE(FOl)| of the difference "CTE(ROl)-CTE(FOl)" between the linear thermal expansion coefficient CTE(ROl) of the opposite insulating layer without the fibrous substrate in the low-temperature measurement range and the linear thermal expansion coefficient CTE(FOl) of the opposite insulating layer containing the fibrous substrate in the low-temperature measurement range. When the absolute value of the difference in linear thermal expansion coefficients |CTE(RCl)-CTE(FOl)| is within the aforementioned range, warping after mounting of the semiconductor chip can be effectively suppressed.

[0046] When the chip-side build-up layer 200 includes a chip-side insulating layer (not shown in Figure 1) containing a fiber substrate, the linear thermal expansion coefficient CTE(FOl) of the opposite insulating layer containing the fiber substrate in the low-temperature measurement range and the linear thermal expansion coefficient CTE(FCl) of the chip-side insulating layer containing the fiber substrate in the low-temperature measurement range may be different, but it is preferable that the difference be small. In one example, the absolute value range of the difference "CTE(FOl)-CTE(FCl)" between the linear thermal expansion coefficient CTE(FOl) of the opposite insulating layer containing the fiber substrate in the low-temperature measurement range and the linear thermal expansion coefficient CTE(FCl) of the chip-side insulating layer containing the fiber substrate in the low-temperature measurement range is preferably 10 pm / ℃ or less, more preferably 5 ppm / ℃ or less, even more preferably 3 ppm / ℃ or less, and particularly preferably 0 ppm / ℃. Therefore, it is particularly preferable that the linear thermal expansion coefficient CTE(FOl) of the opposite insulating layer including the fibrous substrate in the low-temperature measurement range and the linear thermal expansion coefficient CTE(FCl) of the chip-side insulating layer including the fibrous substrate in the low-temperature measurement range are the same.

[0047] The opposite insulating layer having the above-mentioned linear thermal expansion coefficients CTE(FOh) and CTE(FOl) can be formed by a cured product of a resin composition containing a fiber substrate. In particular, it is difficult to form an opposite insulating layer having the above-mentioned preferred range of linear thermal expansion coefficients CTE(FOh) in the high-temperature measurement range using a cured product of a resin composition that does not contain a fiber substrate. One of the technical significances of the fiber substrate is that it enables the smooth acquisition of an insulating layer having such a preferred linear thermal expansion coefficient.

[0048] The linear thermal expansion coefficients CTE(FOh) and CTE(FOl) of the opposite insulating layer containing the fibrous substrate can be measured by thermomechanical analysis. Such thermomechanical analysis can be performed using a tensile loading method with a load of 1N and a heating rate of 5°C / min. Two measurements are performed: the first measurement in the temperature range of 25°C to 200°C, and the second measurement in the temperature range of 25°C to 260°C. The linear thermal expansion coefficient can then be calculated from the results of the second measurement. Specifically, the linear thermal expansion coefficient CTE(FOl) [ppm / °C] in the low-temperature measurement range can be calculated from the results of the second measurement in the 25°C to 150°C range, and the linear thermal expansion coefficient CTE(FOh) [ppm / °C] in the high-temperature measurement range can be calculated from the results of the 150°C to 240°C range.

[0049] The glass transition temperature range of the opposite insulating layer (opposite insulating layer 314, etc.) containing the fibrous substrate is preferably 250°C or less, more preferably 200°C or less, even more preferably 180°C or less, preferably 140°C or higher, more preferably 150°C or higher, and even more preferably 160°C or higher. When the glass transition temperature of the opposite insulating layer containing the fibrous substrate is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed. When the opposite build-up layer 300 comprises multiple opposite insulating layers containing fibrous substrates, the glass transition temperatures of each of these opposite insulating layers may be different, but are preferably the same.

[0050] The glass transition temperature of the opposite insulating layer containing the fiber substrate (e.g., opposite insulating layer 314) is preferably close to the glass transition temperature of the opposite insulating layer not containing the fiber substrate (e.g., opposite insulating layers 311-313). In this case, the glass transition temperature of the opposite insulating layer containing the fiber substrate may be higher, lower, or the same as the glass transition temperature of the opposite insulating layer not containing the fiber substrate. The absolute value range of the difference between the glass transition temperature of the opposite insulating layer containing the fiber substrate and the glass transition temperature of the opposite insulating layer not containing the fiber substrate is preferably 80°C or less, more preferably 60°C or less, even more preferably 40°C or less, even more preferably 20°C or less, and even more preferably 10°C or less. The lower limit is 0°C or higher, and may be 1°C or higher, 2°C or higher, or 3°C or higher. When the absolute value of the difference in glass transition temperatures is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed.

[0051] Furthermore, it is preferable that the glass transition temperature of the opposite insulating layer containing the fiber substrate (e.g., opposite insulating layer 314) is close to the glass transition temperature of the chip-side insulating layer not containing the fiber substrate (e.g., chip-side insulating layers 211-214). In this case, the glass transition temperature of the opposite insulating layer containing the fiber substrate may be higher, lower, or the same as the glass transition temperature of the chip-side insulating layer not containing the fiber substrate. The range of the absolute value of the difference between the glass transition temperature of the opposite insulating layer containing the fiber substrate and the glass transition temperature of the chip-side insulating layer not containing the fiber substrate may be the same as the range of the absolute value of the difference between the glass transition temperature of the opposite insulating layer containing the fiber substrate and the glass transition temperature of the opposite insulating layer not containing the fiber substrate. When the absolute value of the difference in glass transition temperatures is within the above range, warping after mounting the semiconductor chip can be effectively suppressed.

[0052] When the chip-side build-up layer 200 includes a chip-side insulating layer (not shown in Figure 1) containing a fiber substrate, the glass transition temperature of the opposite insulating layer containing the fiber substrate and the glass transition temperature of the chip-side insulating layer containing the fiber substrate may be different, but it is preferable that the difference is small. In one example, the absolute value range of the difference between the glass transition temperature of the opposite insulating layer containing the fiber substrate and the glass transition temperature of the chip-side insulating layer containing the fiber substrate is preferably 80°C or less, more preferably 60°C or less, even more preferably 40°C or less, even more preferably 20°C or less, even more preferably 10°C or less, and particularly preferably 0°C. Therefore, it is particularly preferable that the glass transition temperature of the opposite insulating layer containing the fiber substrate and the glass transition temperature of the chip-side insulating layer containing the fiber substrate are the same.

[0053] The glass transition temperature of the opposite insulating layer, including the fibrous substrate, can be measured by thermomechanical analysis using the tensile loading method. This thermomechanical analysis involves measuring the storage modulus and loss modulus under measurement conditions of a load of 200 mN and a heating rate of 5°C / min. The glass transition temperature Tg (°C) can be obtained from the peak of the temperature-dependent curve of tanδ (ratio of storage modulus to loss modulus) obtained as a result of heating up to 260°C.

[0054] The opposite insulating layer (e.g., opposite insulating layer 314) containing the fibrous substrate preferably has a high tensile modulus at high temperatures corresponding to the reflow temperature. Specifically, the range of the tensile modulus E(FOh) of the opposite insulating layer containing the fibrous substrate at 260°C is preferably 2 GPa or more, more preferably 3 GPa or more, and even more preferably 4 GPa or more. The upper limit may be, for example, 15 GPa or less, 10 GPa or less, etc. When the tensile modulus E(FOh) of the opposite insulating layer containing the fibrous substrate is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed. When the opposite build-up layer comprises multiple opposite insulating layers containing fibrous substrates, the tensile modulus E(FOh) of each of these opposite insulating layers may be different, but it is preferable that they be the same.

[0055] Generally, the tensile modulus of an insulating layer can decrease as the temperature rises. Here, it is preferable that the opposite insulating layer containing the fibrous substrate (e.g., opposite insulating layer 314) exhibits a small decrease in tensile modulus due to temperature increases. Specifically, the range of the ratio "E(FOh) / E(FOl)" of the tensile modulus E(FOh) of the opposite insulating layer containing the fibrous substrate at 260°C to the tensile modulus E(FOl) of the opposite insulating layer containing the fibrous substrate at 23°C is preferably 0.1 or higher, more preferably 0.15 or higher, and even more preferably 0.2 or higher. The upper limit is usually less than 1, and may be 0.8 or lower or 0.6 or lower. When the ratio "E(FOh) / E(FOl)" of the tensile modulus of the opposite insulating layer containing the fibrous substrate is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed.

[0056] Preferably, the tensile modulus at high temperature of the opposite insulating layer containing the fibrous substrate (e.g., opposite insulating layer 314) is greater than the tensile modulus at high temperature of the opposite insulating layer without the fibrous substrate (e.g., opposite insulating layers 311-313). In this case, it is preferable that the difference "E(FOh)-E(ROh)" between the tensile modulus E(FOh) of the opposite insulating layer containing the fibrous substrate at 260°C and the tensile modulus E(ROh) of the opposite insulating layer without the fibrous substrate at 260°C is within a specific range. Specifically, the range of the difference in tensile modulus "E(FOh)-E(ROh)" is preferably 1 GPa or more, more preferably 2 GPa or more, even more preferably 3 GPa or more, preferably 15 GPa or less, more preferably 10 GPa or less, and even more preferably 8 GPa or less. When the difference in tensile modulus "E(FOh)-E(ROh)" is within the above range, warping after mounting the semiconductor chip can be effectively suppressed.

[0057] Preferably, the tensile modulus at high temperature of the opposite insulating layer containing the fibrous substrate (e.g., opposite insulating layer 314) is greater than the tensile modulus at high temperature of the chip-side insulating layer without the fibrous substrate (e.g., chip-side insulating layers 211-214). In this case, it is preferable that the difference "E(FOh)-E(RCh)" between the tensile modulus E(FOh) of the opposite insulating layer containing the fibrous substrate at 260°C and the tensile modulus E(RCh) of the chip-side insulating layer without the fibrous substrate at 260°C is within a specific range. Specifically, the range of the difference "E(FOh)-E(RCh)" may be the same as the range of the difference "E(FOh)-E(ROh)" between the tensile modulus E(FOh) of the opposite insulating layer containing the fibrous substrate at 260°C and the tensile modulus E(ROh) of the opposite insulating layer without the fibrous substrate at 260°C. When the difference "E(FOh)-E(RCh)" is within the above range, warping after mounting the semiconductor chip can be effectively suppressed.

[0058] When the chip-side build-up layer 200 includes a chip-side insulating layer containing a fiber substrate (not shown in Figure 1), the tensile modulus of the opposite insulating layer containing the fiber substrate at high temperature and the tensile modulus of the chip-side insulating layer containing the fiber substrate at high temperature may be different, but it is preferable that the difference is small. In one example, the range of the absolute value of "E(FOh)-E(FCh)"|, which is the difference between the tensile modulus E(FOh) of the opposite insulating layer containing the fiber substrate at 260°C and the tensile modulus E(FCh) of the chip-side insulating layer containing the fiber substrate at 260°C, is preferably 5 GPa or less, more preferably 3 GPa or less, even more preferably 1 GPa or less, and particularly preferably 0 GPa. Therefore, it is particularly preferable that the tensile modulus E(FCh) of the chip-side insulating layer containing the fiber substrate at 260°C and the tensile modulus E(FOh) of the opposite insulating layer containing the fiber substrate at 260°C are the same.

[0059] Preferably, the opposite insulating layer (opposite insulating layer 314, etc.) containing the fibrous substrate has a large tensile modulus at a low temperature lower than the reflow temperature. Specifically, the range of the tensile modulus E(FOl) at 23°C of the opposite insulating layer (opposite insulating layer 314, etc.) containing the fibrous substrate is preferably 10 GPa or more, more preferably 12 GPa or more, even more preferably 14 GPa or more, preferably 30 GPa or less, more preferably 25 GPa or less, and even more preferably 22 GPa or less. When the tensile modulus E(FOl) at 23°C of the opposite insulating layer containing the fibrous substrate is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed. When the opposite build-up layer 300 comprises a plurality of opposite insulating layers containing fibrous substrates, the tensile modulus E(FOl) of each of these opposite insulating layers may be different, but it is preferable that they be the same.

[0060] Preferably, the tensile modulus E(FOl) at 23°C of the opposite insulating layer containing the fibrous substrate (e.g., opposite insulating layer 314) is greater than the tensile modulus E(ROl) at 23°C of the opposite insulating layer not containing the fibrous substrate (e.g., opposite insulating layers 311-313). In this case, the range of the difference "E(FOl)-E(ROl)" between the tensile modulus E(FOl) of the opposite insulating layer containing the fibrous substrate and the tensile modulus E(ROl) of the opposite insulating layer not containing the fibrous substrate at 23°C is preferably 0.5 GPa or more, more preferably 1 GPa or more, even more preferably 1.5 GPa or more, preferably 10 GPa or less, more preferably 8 GPa or less, and even more preferably 5 GPa or less. When the difference in tensile modulus "E(FOl)-E(ROl)" is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed.

[0061] Preferably, the tensile modulus E(FOl) at 23°C of the opposite insulating layer containing the fibrous substrate (e.g., opposite insulating layer 314) is greater than the tensile modulus E(RCl) at 23°C of the chip-side insulating layer not containing the fibrous substrate (e.g., chip-side insulating layers 211-214). In this case, the range of the difference "E(FOl)-E(RCl)" between the tensile modulus E(FOl) of the opposite insulating layer containing the fibrous substrate and the tensile modulus E(RCl) of the chip-side insulating layer not containing the fibrous substrate at 23°C may be the same as the range of the difference "E(FOl)-E(ROl)" between the tensile modulus E(FOl) of the opposite insulating layer containing the fibrous substrate and the tensile modulus E(ROl) of the opposite insulating layer not containing the fibrous substrate at 23°C. When the difference in tensile modulus "E(FOl)-E(RCl)" is within the above range, warping after mounting the semiconductor chip can be effectively suppressed.

[0062] When the chip-side build-up layer 200 includes a chip-side insulating layer (not shown in Figure 1) containing a fiber substrate, the tensile modulus E(FOl) at 23°C of the opposite insulating layer containing the fiber substrate and the tensile modulus E(FCl) at 23°C of the chip-side insulating layer containing the fiber substrate may be different, but it is preferable that the difference be small. In one example, the range of the absolute value |E(FOl)-E(FCl)| of the difference "E(FOl)-E(FCl)" between the tensile modulus E(FOl) at 23°C of the opposite insulating layer containing the fiber substrate and the tensile modulus E(FCl) at 23°C of the chip-side insulating layer containing the fiber substrate is preferably 5 GPa or less, more preferably 3 GPa or less, even more preferably 1 GPa or less, and particularly preferably 0 GPa. Therefore, it is particularly preferable that the tensile modulus E(FOl) at 23°C of the opposite insulating layer containing the fiber substrate and the tensile modulus E(FCl) at 23°C of the chip-side insulating layer containing the fiber substrate are the same.

[0063] The opposite insulating layer having the tensile moduli E(FOh) and E(FOl) described above can be formed by a cured product of a resin composition containing a fiber substrate. In particular, it is difficult to form an opposite insulating layer having the above-mentioned preferred range of tensile moduli E(FOh) in the high-temperature measurement range using a cured product of a resin composition that does not contain a fiber substrate. One of the technical significances of the fiber substrate is that it enables the smooth acquisition of an insulating layer having such a preferred tensile modulus.

[0064] The tensile moduli E(FOh) and E(FOl) of the opposite insulating layer, including the fibrous base material, can be measured by a tensile test in accordance with the Japanese Industrial Standard JIS K7127.

[0065] The opposite insulating layer (e.g., opposite insulating layer 314) containing the fibrous substrate preferably has a low dielectric loss tangent Df. The range of the dielectric loss tangent Df of the opposite insulating layer containing the fibrous substrate is preferably 0.0200 or less, more preferably 0.0180 or less, and even more preferably 0.0150 or less. There is no particular limit to the lower limit of the dielectric loss tangent Df, and it may be, for example, 0.0010 or more. The dielectric loss tangent Df of the opposite insulating layer containing the fibrous substrate can be measured by the cavity resonance perturbation method under measurement conditions of a measurement frequency of 5.8 GHz and a measurement temperature of 23 °C.

[0066] The thickness range per layer of the opposite insulating layer (opposite insulating layer 314, etc.) containing the fibrous substrate is preferably 5 μm or more, more preferably 10 μm or more, even more preferably 20 μm or more, preferably 100 μm or less, more preferably 80 μm or less, and even more preferably 60 μm or less. When the opposite build-up layer 300 comprises multiple opposite insulating layers containing the fibrous substrate, the thicknesses of each of these opposite insulating layers may be different, but are preferably the same.

[0067] In structure 10, a conductive layer can generally be formed on the surface of each insulating layer (chip-side insulating layers 211-214 and opposite-side insulating layers 311-314, etc.). Therefore, the thickness of the insulating layer may be measured using the core substrate-side surface of the conductive layer (i.e., the interface between the insulating layer and the conductive layer formed on the insulating layer) as a guide. For example, as shown in Figure 1, when opposite-side insulating layer 313 and opposite-side insulating layer 314 are joined, it may be difficult to determine the interface between them by optical observation. Even in this case, since a conductive layer 333 is generally formed on opposite-side insulating layer 313, the position of the interface between opposite-side insulating layer 313 and opposite-side insulating layer 314 can be determined from the position of the interface between opposite-side insulating layer 313 and conductive layer 333. Therefore, the thickness of opposite-side insulating layer 314 can be measured.

[0068] Of the multiple opposite-side insulating layers 311 to 314 provided by the opposite-side build-up layer 300, the opposite-side insulating layers 311 to 313, other than the opposite-side insulating layer 314 containing the fiber substrate as described above, do not contain the fiber substrate. Typically, these opposite-side insulating layers 311 to 313 that do not contain the fiber substrate contain only the cured resin composition. The cured resin composition contained in the opposite-side insulating layers 311 to 313 that do not contain the fiber substrate may be the same as or different from the cured resin composition contained in the opposite-side insulating layer 314 containing the fiber substrate.

[0069] The opposite insulating layer without a fibrous substrate (e.g., opposite insulating layers 311-313) generally has a larger linear thermal expansion coefficient than the opposite insulating layer containing a fibrous substrate in the high-temperature measurement range. The range of the linear thermal expansion coefficient CTE(ROh) of the opposite insulating layer without a fibrous substrate in the high-temperature measurement range is usually greater than 25 ppm / °C, preferably 26 ppm / °C or higher, more preferably 28 ppm / °C or higher, preferably 100 ppm / °C or lower, more preferably 80 ppm / °C or lower, and even more preferably 60 ppm / °C or lower. When the linear thermal expansion coefficient CTE(ROh) of the opposite insulating layer without a fibrous substrate is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed. When the opposite build-up layer 300 comprises multiple opposite insulating layers without a fibrous substrate, the linear thermal expansion coefficients CTE(ROh) of each of these opposite insulating layers may be different, but are preferably the same.

[0070] The linear thermal expansion coefficient CTE(ROh) in the high-temperature measurement range of the opposite insulating layer that does not contain a fiber substrate (opposite insulating layers 311-313, etc.) and the linear thermal expansion coefficient CTE(RCh) in the high-temperature measurement range of the chip-side insulating layer that does not contain a fiber substrate (chip-side insulating layers 211-214) may be different, but it is preferable that the difference be small. In one example, the absolute value range of the difference "CTE(ROh)-CTE(RCh)" between the linear thermal expansion coefficient CTE(ROh) in the high-temperature measurement range of the opposite insulating layer that does not contain a fiber substrate and the linear thermal expansion coefficient CTE(RCh) in the high-temperature measurement range of the chip-side insulating layer that does not contain a fiber substrate is preferably 30 pm / ℃ or less, more preferably 25 ppm / ℃ or less, even more preferably 20 ppm / ℃ or less, and even more preferably 10 ppm / ℃ or less. It is particularly preferable that the linear thermal expansion coefficient CTE(ROh) of the opposite insulating layer without the fiber substrate in the high-temperature measurement range and the linear thermal expansion coefficient CTE(RCh) of the chip-side insulating layer without the fiber substrate in the high-temperature measurement range are the same.

[0071] The range of the linear thermal expansion coefficient CTE(ROl) in the low-temperature measurement range of the opposite insulating layer (opposite insulating layers 311-313, etc.) that does not contain a fibrous substrate is preferably 40 ppm / °C or less, more preferably 30 ppm / °C or less, and even more preferably 25 ppm / °C or less. The lower limit is, for example, 5 ppm / °C or more, 10 ppm / °C or more, or 15 ppm / °C or more, and may be greater than 19 ppm / °C. When the linear thermal expansion coefficient CTE(ROl) in the low-temperature measurement range of the opposite insulating layer that does not contain a fibrous substrate is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed. When the opposite build-up layer 300 comprises multiple opposite insulating layers that do not contain a fibrous substrate, the linear thermal expansion coefficient CTE(ROl) of each of these opposite insulating layers may be different, but it is preferable that they be the same.

[0072] The linear thermal expansion coefficient CTE(ROl) in the low-temperature measurement range of the opposite insulating layer (opposite insulating layers 311-313, etc.) that does not contain a fiber substrate and the linear thermal expansion coefficient CTE(RCl) in the low-temperature measurement range of the chip-side insulating layer (chip-side insulating layers 211-214) that does not contain a fiber substrate may be different, but it is preferable that the difference be small. In one example, the absolute value range of the difference "CTE(ROl)-CTE(RCl)" between the linear thermal expansion coefficient CTE(ROl) in the low-temperature measurement range of the opposite insulating layer that does not contain a fiber substrate and the linear thermal expansion coefficient CTE(RCl) in the low-temperature measurement range of the chip-side insulating layer that does not contain a fiber substrate is preferably 10 pm / ℃ or less, more preferably 5 ppm / ℃ or less, even more preferably 3 ppm / ℃ or less, and particularly preferably 0 ppm / ℃. Therefore, it is particularly preferable that the linear thermal expansion coefficient of the opposite insulating layer that does not contain a fiber substrate and the linear thermal expansion coefficient of the chip-side insulating layer that does not contain a fiber substrate are the same.

[0073] The linear thermal expansion coefficient of the opposite insulating layer without the fibrous substrate can be measured by the same method as the linear thermal expansion coefficient of the opposite insulating layer with the fibrous substrate.

[0074] The glass transition temperature range of the opposite insulating layer (opposite insulating layers 311-313, etc.) that does not contain a fiber substrate is preferably 250°C or less, more preferably 200°C or less, even more preferably 180°C or less, preferably 140°C or more, more preferably 150°C or more, and even more preferably 160°C or more. When the glass transition temperature of the opposite insulating layer that does not contain a fiber substrate is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed. When the opposite build-up layer 300 comprises multiple opposite insulating layers that do not contain a fiber substrate, the glass transition temperatures of each of these opposite insulating layers may be different, but are preferably the same.

[0075] The glass transition temperature of the opposite insulating layer that does not contain the fiber substrate (e.g., opposite insulating layers 311-313) and the glass transition temperature of the chip-side insulating layer that does not contain the fiber substrate (e.g., chip-side insulating layers 211-214) may be different, but it is preferable that the difference be small. In one example, the absolute value range of the difference between the glass transition temperature of the opposite insulating layer that does not contain the fiber substrate and the glass transition temperature of the chip-side insulating layer that does not contain the fiber substrate is preferably 80°C or less, more preferably 60°C or less, even more preferably 40°C or less, even more preferably 20°C or less, even more preferably 10°C or less, and particularly preferably 0°C. Therefore, it is particularly preferable that the glass transition temperature of the opposite insulating layer that does not contain the fiber substrate and the glass transition temperature of the chip-side insulating layer that does not contain the fiber substrate are the same.

[0076] The glass transition temperature of the opposite insulating layer without the fibrous substrate can be measured using the same measurement method as the glass transition temperature of the opposite insulating layer with the fibrous substrate.

[0077] The opposite insulating layer without a fibrous substrate (e.g., opposite insulating layers 311-313) generally has a lower tensile modulus of elasticity than the opposite insulating layer containing a fibrous substrate at high temperatures corresponding to the reflow temperature. The range of the tensile modulus E(ROh) of the opposite insulating layer without a fibrous substrate at 260°C is usually 0.1 GPa or higher, preferably 0.2 GPa or higher, more preferably 0.3 GPa or higher, preferably less than 2 GPa, more preferably 1.5 GPa or lower, and even more preferably 1 GPa or lower. When the tensile modulus E(ROh) of the opposite insulating layer without a fibrous substrate is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed. When the opposite build-up layer 300 comprises multiple opposite insulating layers without a fibrous substrate, the tensile modulus E(ROh) of each of these opposite insulating layers may be different, but it is preferable that they be the same.

[0078] The tensile modulus E(ROh) at 260°C of the opposite insulating layer (opposite insulating layers 311-313, etc.) that does not contain a fiber substrate and the tensile modulus E(RCh) at 260°C of the chip-side insulating layer (chip-side insulating layers 211-214) that does not contain a fiber substrate may be different, but it is preferable that the difference be small. In one example, the range of the absolute value of the difference "E(ROh)-E(RCh)" between the tensile modulus E(ROh) at 260°C of the opposite insulating layer (opposite insulating layer) that does not contain a fiber substrate and the tensile modulus E(RCh) at 260°C of the chip-side insulating layer that does not contain a fiber substrate is preferably 5 GPa or less, more preferably 3 GPa or less, even more preferably 1 GPa or less, and particularly preferably 0 GPa. Therefore, it is particularly preferable that the tensile modulus E(ROh) at 260°C of the opposite insulating layer (opposite insulating layer) that does not contain a fiber substrate and the tensile modulus E(RCh) at 260°C of the chip-side insulating layer that does not contain a fiber substrate are the same.

[0079] The range of the tensile modulus E(ROl) at 23°C of the opposite insulating layer (opposite insulating layers 311-313, etc.) that does not contain a fibrous base material is preferably 5 GPa or more, more preferably 10 GPa or more, even more preferably 12 GPa or more, preferably 30 GPa or less, more preferably 20 GPa or less, and even more preferably 15 GPa or less. When the tensile modulus E(ROl) at 23°C of the opposite insulating layer that does not contain a fibrous base material is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed. When the opposite build-up layer 300 comprises multiple opposite insulating layers that do not contain a fibrous base material, the tensile modulus E(ROl) of each of these opposite insulating layers may be different, but it is preferable that they be the same.

[0080] The tensile modulus E(ROl) at 23°C of the opposite insulating layer (opposite insulating layers 311-313, etc.) that does not contain a fiber substrate and the tensile modulus R(RCl) at 23°C of the chip-side insulating layer (chip-side insulating layers 211-214) that does not contain a fiber substrate may be different, but it is preferable that the difference be small. In one example, the range of the absolute value |E(ROl)-E(RCl)| of the difference "E(ROl)-E(RCl)" between the tensile modulus E(ROl) at 23°C of the opposite insulating layer that does not contain a fiber substrate and the tensile modulus E(RCl) at 23°C of the chip-side insulating layer that does not contain a fiber substrate is preferably 5 GPa or less, more preferably 3 GPa or less, even more preferably 1 GPa or less, and particularly preferably 0 GPa. Therefore, it is particularly preferable that the tensile modulus E(ROl) at 23°C of the opposite insulating layer that does not contain a fiber substrate and the tensile modulus E(RCl) at 23°C of the chip-side insulating layer that does not contain a fiber substrate are the same.

[0081] The tensile modulus of the opposite insulating layer without the fibrous substrate can be measured using the same measurement method as the tensile modulus of the opposite insulating layer with the fibrous substrate.

[0082] The opposite insulating layer (e.g., opposite insulating layers 311-313) that does not contain a fibrous substrate preferably has a low dielectric loss tangent Df. The range of the dielectric loss tangent Df of the opposite insulating layer that does not contain a fibrous substrate may be the same as the range of the dielectric loss tangent Df of the opposite insulating layer that contains a fibrous substrate. The dielectric loss tangent Df of the opposite insulating layer that does not contain a fibrous substrate can be measured by the same measurement method as the dielectric loss tangent Df of the opposite insulating layer that contains a fibrous substrate.

[0083] The range of thickness per layer of the opposite insulating layer that does not contain a fiber substrate (opposite insulating layers 311 to 313, etc.) may be the same as the range of thickness per layer of the opposite insulating layer that does contain a fiber substrate (opposite insulating layer 314, etc.). If the opposite build-up layer 300 comprises multiple opposite insulating layers that do not contain a fiber substrate, the thickness of each of these opposite insulating layers may be different, but it is preferable that they be the same.

[0084] Holes 321 to 324 may be formed in some or all of the above-mentioned opposite-side insulating layers 311 to 314. Examples of such holes 321 to 324 include via holes and through holes. The position, dimensions, and shape of the holes 321 to 324 may be determined as appropriate according to the design of the structure 10.

[0085] The opposite side build-up layer 300 may include conductive layers 331 to 334. In this embodiment, an example is shown in which the conductive layers 331 to 334 are formed on the surfaces 311D, 312D, 313D, and 314D of the opposite side insulating layers 311, 312, 313, and 314 that are opposite to the core substrate 100, and within the holes 321, 322, 323, and 324.

[0086] Conductor layers 331-334 are usually formed from a conductive material and therefore include a conductive material. Examples of conductive materials include one or more metals selected from the group consisting of gold, platinum, palladium, silver, copper, aluminum, cobalt, chromium, zinc, nickel, titanium, tungsten, iron, tin, and indium. Conductor layers 331-334 may be single-metal layers or alloy layers. Examples of alloy layers include layers formed from alloys of two or more metals selected from the above group (e.g., nickel-chromium alloy, copper-nickel alloy, and copper-titanium alloy). In particular, from the viewpoint of versatility in forming the conductive layers 331 to 334, cost, and ease of patterning, single metal layers of chromium, nickel, titanium, aluminum, zinc, gold, palladium, silver, or copper, or alloy layers of nickel-chromium alloy, copper-nickel alloy, or copper-titanium alloy are preferred; single metal layers of chromium, nickel, titanium, aluminum, zinc, gold, palladium, silver, or copper, or alloy layers of nickel-chromium alloy are more preferred; and single metal layers of copper are even more preferred.

[0087] The conductive layers 331 to 334 may have a single-layer structure, or they may have a multi-layer structure including two or more single-metal layers or alloy layers made of different types of metals or alloys. If the conductive layers 331 to 334 have a multi-layer structure, the layer in contact with the insulating layers 311 to 314 on the core substrate 100 side of the conductive layers 331 to 334 is preferably a single-metal layer of chromium, zinc, or titanium, or an alloy layer of nickel-chromium alloy.

[0088] The thickness of each conductive layer 331 to 334 depends on the design of the structure 10, but is preferably 3 μm to 35 μm, and more preferably 5 μm to 30 μm.

[0089] The thickness range of the opposite-side build-up layer 300 is preferably 60 μm or more, more preferably 80 μm or more, and still more preferably 100 μm or more. Conventionally, when such a thick build-up layer was used, warping tended to occur. However, according to the structure 10 according to the present embodiment, even when such a thick opposite-side build-up layer 300 is used, warping can be suppressed, and the effects according to the present embodiment can be effectively utilized. The upper limit of the thickness of the opposite-side build-up layer 300 is preferably 700 μm or less, more preferably 500 μm or less, and still more preferably 300 μm or less. When the upper limit of the thickness of the opposite-side build-up layer 300 is within the above range, warping after mounting the semiconductor chip can be effectively suppressed.

[0090] The thickness T of the core substrate 100 100 and the thickness T of the opposite-side build-up layer 300 300 The thickness ratio T 300 / T 100 is preferably 0.1 or more, more preferably 0.2 or more, and still more preferably 0.3 or more. Conventionally, when the build-up layer is thicker than the core substrate as represented by the above thickness ratio, warping tended to occur. In contrast, according to the structure 10 according to the present embodiment, even when the thickness ratio T 300 / T 100 is large, warping can be suppressed, so the effects according to the present embodiment can be effectively utilized. The upper limit of the thickness ratio T 300 / T 100 is preferably 1.5 or less, more preferably 1.2 or less, and still more preferably 1.0 or less. When the thickness ratio T 300 / T 100 is within the above range, warping after mounting the semiconductor chip can be effectively suppressed.

[0091] <Chip-side build-up layer 200> As described above, the chip-side build-up layer 200 comprises a plurality of chip-side insulating layers 211 to 214. The range of the number of chip-side insulating layers 211 to 214 in the chip-side build-up layer 200 is usually the same as the range of the number of opposite-side insulating layers 311 to 314 in the opposite-side build-up layer 300. The number of chip-side insulating layers 211 to 214 in the chip-side build-up layer 200 and the number of opposite-side insulating layers 311 to 314 in the opposite-side build-up layer 300 may differ to the extent that warping can be suppressed, but it is preferable that they be the same.

[0092] Each of the multiple chip-side insulating layers 211 to 214 contains a cured resin composition. The resin composition is usually a thermosetting resin composition, and therefore the cured product may be a material obtained by thermosetting the resin composition. The cured resin composition contained in the chip-side insulating layers 211 to 214 may be the same as or different from the cured resin composition contained in the opposite insulating layers 311 to 314. Details of the resin composition will be described later.

[0093] A portion of the chip-side insulating layer of the chip-side build-up layer 200 may include a fibrous substrate (not shown) in combination with the cured resin composition. The range of the fibrous substrate included in the chip-side insulating layer may be the same as the range of the fibrous substrate 400 included in the opposite insulating layer 314. Therefore, cloth material may be used as the fibrous substrate included in the chip-side insulating layer. Furthermore, the range of the number of threads per unit dimension, the range of the filament material, the range of the fabric weight, and the range of the thickness included in the fibrous substrate included in the chip-side insulating layer may be the same as those ranges for the fibrous substrate 400 included in the opposite insulating layer 314. In particular, it is preferable that the fibrous substrate included in the chip-side insulating layer and the fibrous substrate 400 included in the opposite insulating layer 314 are the same.

[0094] The number of chip-side insulating layers containing the fiber substrate can be set to be less than the number of opposite-side insulating layers (opposite-side insulating layer 314, etc.) containing the fiber substrate. Specifically, the number of chip-side insulating layers containing the fiber substrate is preferably 2 or less, and more preferably 1 or less. When the number of chip-side insulating layers containing the fiber substrate is within the above range, warping of the semiconductor chip after mounting can be effectively suppressed.

[0095] When the chip-side build-up layer 200 includes a chip-side insulating layer containing a fiber substrate, it is preferable that the chip-side insulating layer containing the fiber substrate is located closest to the core substrate 100. Therefore, it is preferable that the first chip-side insulating layer 211, counted from the core substrate 100 side, contains a fiber substrate. In this case, warping of the semiconductor chip after mounting can be effectively suppressed.

[0096] The range of the linear thermal expansion coefficient CTE(FCh) of the chip-side insulating layer (not shown in Figure 1) containing a fibrous substrate in the high-temperature measurement range may be the same as the range of the linear thermal expansion coefficient CTE(FOh) of the opposite insulating layer (opposite insulating layer 314, etc.) containing a fibrous substrate in the high-temperature measurement range. When the linear thermal expansion coefficient CTE(FCh) of the chip-side insulating layer containing a fibrous substrate is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed. When the chip-side build-up layer 200 comprises multiple chip-side insulating layers containing fibrous substrates, the linear thermal expansion coefficients CTE(FCh) of each of these chip-side insulating layers may be different, but it is preferable that they be the same.

[0097] Preferably, the linear thermal expansion coefficient CTE(FCh) of the chip-side insulating layer containing a fibrous substrate (not shown in Figure 1) in the high-temperature measurement range is smaller than the linear thermal expansion coefficient CTE(RCh) of the chip-side insulating layer without a fibrous substrate (chip-side insulating layers 211-214, etc.) in the high-temperature measurement range. In this case, the range of the difference "CTE(RCh)-CTE(FCh)" between the linear thermal expansion coefficient CTE(RCh) of the chip-side insulating layer without a fibrous substrate in the high-temperature measurement range and the linear thermal expansion coefficient CTE(FCh) of the chip-side insulating layer containing a fibrous substrate in the high-temperature measurement range may be the same as the range of the difference "CTE(ROh)-CTE(FOh)" between the linear thermal expansion coefficient CTE(ROh) of the opposite insulating layer without a fibrous substrate in the high-temperature measurement range and the linear thermal expansion coefficient CTE(FOh) of the opposite insulating layer containing a fibrous substrate in the high-temperature measurement range. When the difference in linear thermal expansion coefficients "CTE(RCh)-CTE(FCh)" is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed.

[0098] Preferably, the linear thermal expansion coefficient CTE(FCh) of the chip-side insulating layer containing the fibrous substrate (not shown in Figure 1) in the high-temperature measurement range is smaller than the linear thermal expansion coefficient CTE(ROh) of the opposite insulating layer (opposite insulating layers 311-313, etc.) in the high-temperature measurement range. In this case, the range of the difference "CTE(ROh)-CTE(FCh)" between the linear thermal expansion coefficient CTE(ROh) of the opposite insulating layer without the fibrous substrate in the high-temperature measurement range and the linear thermal expansion coefficient CTE(FCh) of the chip-side insulating layer containing the fibrous substrate in the high-temperature measurement range may be the same as the range of the difference "CTE(ROh)-CTE(FOh)" between the linear thermal expansion coefficient CTE(ROh) of the opposite insulating layer without the fibrous substrate in the high-temperature measurement range and the linear thermal expansion coefficient CTE(FOh) of the opposite insulating layer containing the fibrous substrate in the high-temperature measurement range. When the difference in linear thermal expansion coefficients "CTE(ROh)-CTE(FCh)" is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed.

[0099] The range of the linear thermal expansion coefficient CTE(FCl) of the chip-side insulating layer (not shown in Figure 1) containing a fibrous substrate in the low-temperature measurement range may be the same as the range of the linear thermal expansion coefficient CTE(FOl) of the opposite insulating layer (opposite insulating layer 314, etc.) containing a fibrous substrate in the low-temperature measurement range. When the linear thermal expansion coefficient CTE(FCl) of the chip-side insulating layer containing a fibrous substrate is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed. When the chip-side build-up layer 200 comprises multiple chip-side insulating layers containing fibrous substrates, the linear thermal expansion coefficients CTE(FCl) of each of these chip-side insulating layers may be different, but it is preferable that they be the same.

[0100] Preferably, the linear thermal expansion coefficient CTE(FCl) of the chip-side insulating layer containing a fibrous substrate (not shown in Figure 1) in the low-temperature measurement range is close to the linear thermal expansion coefficient CTE(RCl) of the chip-side insulating layer without a fibrous substrate (chip-side insulating layers 211-214, etc.) in the low-temperature measurement range. In this case, the range of the absolute value |CTE(RCl)-CTE(FCl)| of the difference "CTE(RCl)-CTE(FCl)" between the linear thermal expansion coefficient CTE(RCl) of the chip-side insulating layer without a fibrous substrate in the low-temperature measurement range and the linear thermal expansion coefficient CTE(FCl) of the chip-side insulating layer containing a fibrous substrate in the low-temperature measurement range may be the same as the range of the absolute value |CTE(ROl)-CTE(FOl)| of the difference "CTE(ROl)-CTE(FOl)" between the linear thermal expansion coefficient CTE(ROl) of the opposite insulating layer without a fibrous substrate in the low-temperature measurement range and the linear thermal expansion coefficient CTE(FOl) of the opposite insulating layer containing a fibrous substrate in the low-temperature measurement range. When the absolute value of the difference in linear thermal expansion coefficients |CTE(RCl)-CTE(FCl)| is within the aforementioned range, warping after mounting of the semiconductor chip can be effectively suppressed.

[0101] Preferably, the linear thermal expansion coefficient CTE(FCl) of the chip-side insulating layer (not shown in Figure 1) containing a fibrous substrate in the low-temperature measurement range is close to the linear thermal expansion coefficient CTE(ROl) of the opposite insulating layer (opposite insulating layers 311-313, etc.) in the low-temperature measurement range. In this case, the range of the absolute value |CTE(ROl)-CTE(FCl)| of the difference "CTE(ROl)-CTE(FCl)" between the linear thermal expansion coefficient CTE(ROl) of the opposite insulating layer without a fibrous substrate in the low-temperature measurement range and the linear thermal expansion coefficient CTE(FCl) of the chip-side insulating layer containing a fibrous substrate in the low-temperature measurement range may be the same as the range of the absolute value |CTE(ROl)-CTE(FOl)| of the difference "CTE(ROl)-CTE(FOl)" between the linear thermal expansion coefficient CTE(ROl) of the opposite insulating layer without a fibrous substrate in the low-temperature measurement range and the linear thermal expansion coefficient CTE(FOl) of the opposite insulating layer containing a fibrous substrate in the low-temperature measurement range. When the absolute value of the difference in linear thermal expansion coefficients |CTE(ROl)-CTE(FCl)| is within the aforementioned range, warping after mounting of the semiconductor chip can be effectively suppressed.

[0102] The linear thermal expansion coefficient of the chip-side insulating layer, which includes a fibrous substrate, can be measured using the same method as the linear thermal expansion coefficient of the opposite insulating layer, which also includes a fibrous substrate.

[0103] The glass transition temperature range of the chip-side insulating layer (not shown in Figure 1) containing a fiber substrate may be the same as the glass transition temperature range of the opposite insulating layer (opposite insulating layer 314, etc.) containing a fiber substrate. When the glass transition temperature of the chip-side insulating layer containing a fiber substrate is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed. When the chip-side build-up layer 200 comprises multiple chip-side insulating layers containing fiber substrates, the glass transition temperatures of each of these chip-side insulating layers may be different, but it is preferable that they be the same.

[0104] The glass transition temperature of the chip-side insulating layer containing the fiber substrate (not shown in Figure 1) is preferably close to the glass transition temperature of the chip-side insulating layer without the fiber substrate (chip-side insulating layers 211-214, etc.). In this case, the glass transition temperature of the chip-side insulating layer containing the fiber substrate may be higher, lower, or the same as the glass transition temperature of the chip-side insulating layer without the fiber substrate. The range of the absolute value of the difference between the glass transition temperature of the chip-side insulating layer containing the fiber substrate and the glass transition temperature of the chip-side insulating layer without the fiber substrate may be the same as the range of the absolute value of the difference between the glass transition temperature of the opposite insulating layer containing the fiber substrate and the glass transition temperature of the opposite insulating layer without the fiber substrate. When the absolute value of the difference in glass transition temperatures is within the above range, warping after mounting the semiconductor chip can be effectively suppressed.

[0105] Furthermore, it is preferable that the glass transition temperature of the chip-side insulating layer containing the fiber substrate (not shown in Figure 1) is close to the glass transition temperature of the opposite insulating layer that does not contain the fiber substrate (opposite insulating layers 311-313, etc.). In this case, the glass transition temperature of the chip-side insulating layer containing the fiber substrate may be higher, lower, or the same as the glass transition temperature of the opposite insulating layer that does not contain the fiber substrate. The range of the absolute value of the difference between the glass transition temperature of the chip-side insulating layer containing the fiber substrate and the glass transition temperature of the opposite insulating layer that does not contain the fiber substrate may be the same as the range of the absolute value of the difference between the glass transition temperature of the opposite insulating layer containing the fiber substrate and the glass transition temperature of the opposite insulating layer that does not contain the fiber substrate. When the absolute value of the difference in glass transition temperatures is within the above range, warping after mounting the semiconductor chip can be effectively suppressed.

[0106] The glass transition temperature of the chip-side insulating layer, which includes the fibrous substrate, can be measured using the same method as the glass transition temperature of the opposite insulating layer, which also includes the fibrous substrate.

[0107] The range of the tensile modulus E(FCh) at 260°C of the chip-side insulating layer (not shown in Figure 1), which includes a fibrous substrate, may be the same as the range of the tensile modulus E(FOh) at 260°C of the opposite insulating layer (opposite insulating layer 314, etc.), which also includes a fibrous substrate. When the tensile modulus E(FCh) of the chip-side insulating layer, which includes a fibrous substrate, is within the aforementioned range, warping after mounting the semiconductor chip can be effectively suppressed. When the chip-side build-up layer 200 comprises multiple chip-side insulating layers, the tensile modulus E(FCh) of each of these chip-side insulating layers may be different, but it is preferable that they be the same.

[0108] Preferably, the tensile modulus E(FCh) at 260°C of the chip-side insulating layer containing the fibrous substrate (not shown in Figure 1) is greater than the tensile modulus E(RCh) at 260°C of the chip-side insulating layer without the fibrous substrate (chip-side insulating layers 211-214, etc.). In this case, the range of the difference "E(FCh)-E(RCh)" between the tensile modulus E(FCh) of the chip-side insulating layer containing the fibrous substrate and the tensile modulus E(RCh) of the chip-side insulating layer without the fibrous substrate at 260°C may be the same as the range of the difference "E(FOh)-E(ROh)" between the tensile modulus E(FOh) of the opposite insulating layer containing the fibrous substrate and the tensile modulus E(ROh) of the opposite insulating layer without the fibrous substrate at 260°C. When the difference in tensile modulus "E(FCh)-E(RCh)" is within the above range, warping after mounting the semiconductor chip can be effectively suppressed.

[0109] Preferably, the tensile modulus E(FCh) at 260°C of the chip-side insulating layer containing the fibrous substrate (not shown in Figure 1) is greater than the tensile modulus E(ROh) at 260°C of the opposite insulating layer without the fibrous substrate (opposite insulating layers 311-313, etc.). In this case, the range of the difference "E(FCh)-E(ROh)" between the tensile modulus E(FCh) of the chip-side insulating layer containing the fibrous substrate and the tensile modulus E(ROh) of the opposite insulating layer without the fibrous substrate at 260°C may be the same as the range of the difference "E(FOh)-E(ROh)" between the tensile modulus E(FOh) of the opposite insulating layer containing the fibrous substrate and the tensile modulus E(ROh) of the opposite insulating layer without the fibrous substrate at 260°C. When the difference in tensile modulus "E(FCh)-E(ROh)" is within the above range, warping after mounting the semiconductor chip can be effectively suppressed.

[0110] The range of the tensile modulus E(FCl) at 23°C of the chip-side insulating layer (not shown in Figure 1), which includes a fibrous substrate, may be the same as the range of the tensile modulus E(FOl) at 23°C of the opposite insulating layer (opposite insulating layer 314, etc.), which also includes a fibrous substrate. When the tensile modulus E(FCl) of the chip-side insulating layer, which includes a fibrous substrate, is within the aforementioned range, warping after mounting of the semiconductor chip can be effectively suppressed. When the chip-side build-up layer 200 comprises multiple chip-side insulating layers, the tensile modulus E(FCl) of each of these chip-side insulating layers may be different, but it is preferable that they be the same.

[0111] Preferably, the tensile modulus E(FCl) at 23°C of the chip-side insulating layer containing the fibrous substrate (not shown in Figure 1) is greater than the tensile modulus E(RCl) at 23°C of the chip-side insulating layer without the fibrous substrate (chip-side insulating layers 211-214, etc.). In this case, the range of the difference "E(FCl)-E(RCl)" between the tensile modulus E(FCl) of the chip-side insulating layer containing the fibrous substrate and the tensile modulus E(RCl) of the chip-side insulating layer without the fibrous substrate at 23°C may be the same as the range of the difference "E(FOl)-E(ROl)" between the tensile modulus E(FOl) of the opposite insulating layer containing the fibrous substrate and the tensile modulus E(ROl) of the opposite insulating layer without the fibrous substrate at 23°C. When the difference in tensile modulus "E(FCl)-E(RCl)" is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed.

[0112] Preferably, the tensile modulus E(FCl) at 23°C of the chip-side insulating layer containing the fibrous substrate (not shown in Figure 1) is greater than the tensile modulus E(ROl) at 23°C of the opposite insulating layer without the fibrous substrate (opposite insulating layers 311-313, etc.). In this case, the range of the difference "E(FCl)-E(ROl)" between the tensile modulus E(FCl) of the chip-side insulating layer containing the fibrous substrate and the tensile modulus E(ROl) of the opposite insulating layer without the fibrous substrate at 23°C may be the same as the range of the difference "E(FOl)-E(ROl)" between the tensile modulus E(FOl) of the opposite insulating layer containing the fibrous substrate and the tensile modulus E(ROl) of the opposite insulating layer without the fibrous substrate at 23°C. When the difference in tensile modulus "E(FCl)-E(ROl)" is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed.

[0113] The tensile modulus of the insulating layer on the chip side, which includes the fibrous substrate, can be measured using the same measurement method as the tensile modulus of the insulating layer on the opposite side, which also includes the fibrous substrate.

[0114] The insulating layer on the chip side, which includes a fibrous substrate, preferably has a low dielectric loss tangent Df. The range of the dielectric loss tangent Df of the insulating layer on the chip side, which includes a fibrous substrate, may be the same as the range of the dielectric loss tangent Df of the insulating layer on the opposite side, which includes a fibrous substrate. The dielectric loss tangent Df of the insulating layer on the chip side, which includes a fibrous substrate, can be measured by the same measurement method as the dielectric loss tangent Df of the insulating layer on the opposite side, which includes a fibrous substrate.

[0115] The range of thickness per layer of the chip-side insulating layer (not shown in Figure 1) containing the fiber substrate may be the same as the range of thickness per layer of the opposite-side insulating layer (opposite-side insulating layer 314, etc.) containing the fiber substrate. When the chip-side build-up layer 200 comprises multiple chip-side insulating layers containing the fiber substrate, the thicknesses of each of these chip-side insulating layers may be different, but it is preferable that they be the same.

[0116] Of the multiple chip-side insulating layers 211 to 214 provided by the chip-side build-up layer 200, the chip-side insulating layers 211 to 214 other than the chip-side insulating layer containing the fiber substrate (not shown in Figure 1) described above do not contain the fiber substrate. Typically, these chip-side insulating layers 211 to 214 that do not contain the fiber substrate contain only the cured resin composition. The cured resin composition contained in the chip-side insulating layers 211 to 214 that do not contain the fiber substrate may be the same as or different from the cured resin composition contained in the chip-side insulating layer containing the fiber substrate.

[0117] The range of the linear thermal expansion coefficient of the chip-side insulating layer (chip-side insulating layers 211-214, etc.) that does not contain a fiber substrate may be the same as the range of the linear thermal expansion coefficient of the opposite insulating layer (opposite insulating layers 311-313, etc.) that does not contain a fiber substrate. Therefore, the range of the linear thermal expansion coefficient CTE(RCh) of the chip-side insulating layer without a fiber substrate in the high-temperature measurement range may be the same as the range of the linear thermal expansion coefficient CTE(ROh) of the opposite insulating layer without a fiber substrate in the high-temperature measurement range. Furthermore, the range of the linear thermal expansion coefficient CTE(RCl) of the chip-side insulating layer without a fiber substrate in the low-temperature measurement range may be the same as the range of the linear thermal expansion coefficient CTE(ROl) of the opposite insulating layer without a fiber substrate in the low-temperature measurement range. When the linear thermal expansion coefficients CTE(RCh) and CTE(RCl) of the chip-side insulating layer without a fiber substrate are within the above ranges, warping after mounting of the semiconductor chip can be effectively suppressed. When the chip-side build-up layer 200 comprises multiple chip-side insulating layers that do not contain a fiber substrate, the linear thermal expansion coefficients CTE(RCh) and CTE(RCl) of each of these chip-side insulating layers may be different, but are preferably the same.

[0118] The linear thermal expansion coefficient of the chip-side insulating layer, which does not contain a fibrous substrate, can be measured using the same method as the linear thermal expansion coefficient of the opposite insulating layer, which contains a fibrous substrate.

[0119] The glass transition temperature range of the chip-side insulating layer (chip-side insulating layers 211-214, etc.) that does not contain a fiber substrate may be the same as the glass transition temperature range of the opposite-side insulating layer (opposite-side insulating layers 311-313, etc.) that does not contain a fiber substrate. When the glass transition temperature of the chip-side insulating layer that does not contain a fiber substrate is within the above range, warping after mounting of the semiconductor chip can be effectively suppressed. When the chip-side build-up layer 200 comprises multiple chip-side insulating layers that do not contain a fiber substrate, the glass transition temperatures of each of these chip-side insulating layers may be different, but it is preferable that they be the same.

[0120] The glass transition temperature of the chip-side insulating layer, which does not contain the fibrous substrate, can be measured using the same method as the glass transition temperature of the opposite insulating layer, which contains the fibrous substrate.

[0121] The range of tensile modulus of the chip-side insulating layer (chip-side insulating layers 211-214, etc.) that does not contain a fiber substrate may be the same as the range of tensile modulus of the opposite insulating layer (opposite insulating layers 311-313, etc.) that does not contain a fiber substrate. Therefore, the range of tensile modulus E(RCh) at 260°C for the chip-side insulating layer that does not contain a fiber substrate may be the same as the range of tensile modulus E(ROh) at 260°C for the opposite insulating layer that does not contain a fiber substrate. Also, the range of tensile modulus E(RCl) at 23°C for the chip-side insulating layer that does not contain a fiber substrate may be the same as the range of tensile modulus E(ROl) at 23°C for the opposite insulating layer that does not contain a fiber substrate. When the tensile moduli E(RCh) and E(RCl) of the chip-side insulating layer that does not contain a fiber substrate are within the above ranges, warping after mounting of the semiconductor chip can be effectively suppressed. When the chip-side build-up layer 200 comprises multiple chip-side insulating layers that do not contain a fiber substrate, the tensile moduli E(RCh) and E(RCl) of each of these chip-side insulating layers may be different, but are preferably the same.

[0122] The tensile modulus of the insulating layer on the tip side, which does not contain the fibrous base material, can be measured using the same measurement method as the tensile modulus of the insulating layer on the opposite side, which contains the fibrous base material.

[0123] It is preferable that the chip-side insulating layer (chip-side insulating layers 211-214, etc.) without a fibrous substrate has a low dielectric loss tangent Df. The range of the dielectric loss tangent Df of the chip-side insulating layer without a fibrous substrate may be the same as the range of the dielectric loss tangent Df of the opposite insulating layer containing a fibrous substrate. The dielectric loss tangent Df of the chip-side insulating layer without a fibrous substrate can be measured by the same measurement method as the dielectric loss tangent Df of the opposite insulating layer containing a fibrous substrate.

[0124] The range of thickness per layer of the chip-side insulating layer that does not contain a fiber substrate (chip-side insulating layers 211 to 214, etc.) may be the same as the range of thickness per layer of the opposite-side insulating layer that contains a fiber substrate (opposite-side insulating layer 314, etc.). If the chip-side build-up layer 200 comprises multiple chip-side insulating layers that do not contain a fiber substrate, the thicknesses of each of these chip-side insulating layers may be different, but it is preferable that they be the same.

[0125] Holes 221 to 224 may be formed in some or all of the chip-side insulating layers 211 to 214 described above. Examples of such holes 221 to 224 include via holes and through holes. The position, dimensions, and shape of the holes 221 to 224 may be determined as appropriate according to the design of the structure 10.

[0126] The chip-side build-up layer 200 may include conductive layers 231 to 234. In this embodiment, an example is shown in which the conductive layers 231 to 234 are formed on the surfaces 211U, 212U, 213U, and 214U of the chip-side insulating layers 211, 212, 213, and 214 opposite to the core substrate 100, and within the holes 221, 222, 223, and 224.

[0127] Conductor layers 231-234 are typically formed using a conductive material, similar to the conductor layers 331-334 of the opposite build-up layer 300. Therefore, the conductive material, layer structure, and thickness of the conductor layers 231-234 of the chip-side build-up layer 200 can be similar to those of the conductor layers 331-334 of the opposite build-up layer 300.

[0128] The thickness range of the chip-side build-up layer 200 may be the same as that of the opposite-side build-up layer 300 for the same reasons. The thickness of the chip-side build-up layer 200 and the thickness of the opposite-side build-up layer 300 may be different, but it is preferable that the difference be small. The difference in thickness between the chip-side build-up layer 200 and the thickness of the opposite-side build-up layer 300 is preferably 10 μm or less, more preferably 5 μm or less. Therefore, it is particularly preferable that the thickness of the chip-side build-up layer 200 and the thickness of the opposite-side build-up layer 300 be the same.

[0129] Thickness T of core substrate 100 100 and the thickness T of the chip-side build-up layer 200 200 Thickness ratio T 200 / T 100 The range is the thickness T of the core substrate 100. 100On the opposite side, the build-up layer has a thickness of 300 T. 300 Thickness ratio T 300 / T 100 For the same reasons, the thickness ratio T 300 / T 100 It can be the same as the range.

[0130] <Method for manufacturing the structure> The structure 10 according to this embodiment is A process (i) comprising forming multiple chip-side insulating layers 211 to 214 on the chip side (first side) 100U of the core substrate 100, Multiple steps (ii) to form opposite-side insulating layers 311-314 on the opposite side (second side) 100D of the core substrate 100, It can be manufactured by a manufacturing method that includes [the specified element].

[0131] Typically, one of the multiple chip-side insulating layers 211 to 214 can be formed in a single step (i). Therefore, a chip-side build-up layer 200 comprising multiple chip-side insulating layers 211 to 214 can be formed by a method that includes repeating step (i) multiple times. Furthermore, typically, one of the multiple opposite-side insulating layers 311 to 314 can be formed in a single step (ii). Therefore, by a method that includes repeating step (ii) multiple times, an opposite-side build-up layer 300 comprising multiple opposite-side insulating layers 311 to 314 can be formed.

[0132] The structure 10 includes an insulating layer 314 containing a fiber substrate 400 and insulating layers 211-214 and 311-313 that do not contain a fiber substrate, in combination as described above. Therefore, step (ii) includes the step of forming the opposite side insulating layer 314 containing the fiber substrate 400 and the step of forming the opposite side insulating layers 311-313 that do not contain a fiber substrate. Step (i) also includes the step of forming the chip-side insulating layers 211-214 that do not contain a fiber substrate. Furthermore, step (i) may also include the step of forming a chip-side insulating layer (not shown in Figure 1) containing a fiber substrate.

[0133] Insulating layers containing a fibrous substrate (such as the opposite insulating layer 314) are preferably formed by a method that includes laminating a (a1) fiber-reinforced sheet comprising a (a11) prepreg layer. This method typically includes laminating the (a1) fiber-reinforced sheet and curing the (a1) fiber-reinforced sheet. Insulating layers not containing a fibrous substrate (such as the chip-side insulating layers 211-214 and the opposite insulating layers 311-313) are preferably formed by a method that includes laminating a (b1) resin composition layer. This method typically includes laminating the (b1) resin composition layer and curing the (b1) resin composition layer. The following describes each of these preferred methods.

[0134] (Method for forming an insulating layer including a fibrous substrate) First, a method for forming an insulating layer including a fibrous substrate will be described. The insulating layer including a fibrous substrate is preferably formed by a method that includes laminating a (a1) fiber-reinforced sheet having a (a11) prepreg layer, as described above.

[0135] (a11) The prepreg layer represents a layer comprising a fibrous substrate and a resin composition impregnated into the fibrous substrate. Hereinafter, the resin composition contained in the (a11) prepreg layer may be referred to as the "first resin composition". The (a11) prepreg layer may contain only the fibrous substrate and the first resin composition. The fibrous substrate is as described above. Typically, the first resin composition is thermosetting, so by curing the first resin composition, an insulating layer containing the fibrous substrate can be formed. For example, an insulating layer containing the fibrous substrate can be formed on the core substrate 100 by a method that includes laminating a (a1) fiber-reinforced sheet on the core substrate 100 and curing the first resin composition contained in the (a11) prepreg layer of the (a1) fiber-reinforced sheet. Furthermore, for example, an insulating layer containing a fiber substrate (the (n+1) insulating layer) can be formed on the insulating layer (the nth insulating layer) by a method that includes laminating a fiber-reinforced sheet (a1) onto an insulating layer (the nth insulating layer) and curing the first resin composition contained in the (a1) fiber-reinforced sheet (a11) prepreg layer. The above "n" represents a natural number.

[0136] The minimum melt viscosity range of the (a11) prepreg layer in the temperature range of 100°C to 140°C is preferably 100 poise or more, more preferably 200 poise or more, even more preferably 400 poise or more, preferably 10000 poise or less, more preferably 7000 poise or less, and even more preferably 4000 poise or less. Typically, the minimum melt viscosity of the (a11) prepreg layer in the temperature range of 100°C to 140°C corresponds to the minimum melt viscosity of the first resin composition contained in the (a11) prepreg layer in the temperature range of 100°C to 140°C. When the (a11) prepreg layer has a minimum melt viscosity within the above range in the temperature range of 100°C to 140°C, the conductive layer on the surface joined to (a11) can be well embedded by the (a11) prepreg layer.

[0137] (a11) When the temperature of the prepreg layer is increased, the melt viscosity of the (a11) prepreg layer generally decreases gradually with increasing temperature, reaching a lowest value at a certain temperature, and then may increase. In this case, it is preferable that the temperature at which the melt viscosity of the (a11) prepreg layer is lowest is in a specific temperature range that is lower than conventional. Specifically, the temperature range at which the melt viscosity of the (a11) prepreg layer is lowest is preferably 100°C or higher and 150°C or lower. When the temperature at which the melt viscosity of the (a11) prepreg layer is lowest is in the above range, lamination of the (a1) fiber-reinforced sheet comprising the (a11) prepreg layer can be carried out successfully.

[0138] (a11) The melt viscosity of the prepreg layer can be measured using a dynamic viscoelasticity measuring device. The measurement can be performed by raising the temperature in the range from a starting temperature of 60°C to 200°C and measuring the dynamic viscoelastic modulus of the sample to be measured. The measurement conditions can be a heating rate of 5°C / min, a measurement temperature interval of 2.5°C, a frequency of 1 Hz, and a strain of 1 deg. From the measured results, the lowest melt viscosity in the temperature range of 100°C to 140°C, and the temperature at which the lowest melt viscosity value is observed within the measurement temperature range can be determined.

[0139] (a11) The thickness of the prepreg layer is preferably 10 μm or more, more preferably 15 μm or more, even more preferably 20 μm or more, preferably 100 μm or less, more preferably 90 μm or less, even more preferably 80 μm or less, and even more preferably 70 μm or less.

[0140] (a1) The fiber-reinforced sheet may consist only of the (a11) prepreg layer, or it may also consist of a (a12) cured layer formed on one side of the (a11) prepreg layer in combination with the (a11) prepreg layer. Hereinafter, this (a12) cured layer may be referred to as the "(a12) primer cured layer". For example, the (a1) fiber-reinforced sheet may consist only of the (a11) prepreg layer and the (a12) primer cured layer.

[0141] (a12) The primer cured layer contains a cured product obtained by curing a thermosetting resin composition, and may contain only the cured product. Hereinafter, the thermosetting resin composition that serves as the raw material for the cured product contained in the (a12) primer cured layer may be referred to as the "second resin composition". Typically, the (a12) primer cured layer does not contain a fiber substrate. Since the (a12) primer cured layer contains a cured product of the second resin composition, it usually has high hardness. Therefore, when pressure is applied to the (a1) fiber-reinforced sheet during the lamination process, it is possible to suppress the formation of irregularities on the surface of the (a1) fiber-reinforced sheet that reflect the shape of the fiber substrate, or the exposure of the fiber substrate on the surface of the (a1) fiber-reinforced sheet, due to that pressure.

[0142] (a12) In the primer cured layer, the second resin composition may be completely cured, but it is not necessarily required to be completely cured. The second resin composition may be cured to such an extent that, in the process of laminating the (a1) fiber-reinforced sheet, it is possible to suppress the formation of irregularities on the surface of the (a1) fiber-reinforced sheet that reflect the shape of the fiber substrate, or the exposure of the fiber substrate on the surface of the (a1) fiber-reinforced sheet. Specifically, it is preferable that the curing of the second resin composition has progressed to such an extent that the cured product of the second resin composition contained in the (a12) primer cured layer has low fluidity in the process of laminating the (a1) fiber-reinforced sheet. Furthermore, it is even more preferable that the curing of the second resin composition has progressed to such an extent that the cured product of the second resin composition contained in the (a12) primer cured layer has no fluidity in the process of laminating the (a1) fiber-reinforced sheet.

[0143] (a12) The degree of curing of the second resin composition in the primer-cured layer can be expressed, for example, by the maximum seepage length. This maximum seepage length can be measured by a test specimen comprising the (a12) primer-cured layer and a polyethylene terephthalate film (hereinafter sometimes referred to as "PET film") having the same area and planar shape as the (a12) primer-cured layer. Specifically, in the test specimen measurement, a rectangular test specimen is used comprising a PET film with dimensions of 12 cm x 15 cm and a (a12) primer-cured layer with dimensions of 12 cm x 15 cm formed on the entire surface of one side of the PET film. This test specimen is laminated onto a 20 cm square, 0.8 mm thick FR4 substrate. This lamination is performed using a vacuum laminator so that the (a12) primer-cured layer is bonded to the FR4 substrate. More specifically, after vacuum suction at 80°C for 30 seconds, the temperature was set to 80°C and the pressure to 7.0 kgf / cm². 2 Lamination is performed by pressing through heat-resistant rubber for 60 seconds under these conditions. Subsequently, under atmospheric pressure, using a SUS end plate, at a temperature of 80°C and a pressure of 5.5 kgf / cm², the lamination is carried out. 2A smoothing process is performed by pressing the film for 90 seconds under the specified conditions. After this test, the maximum length of the (a12) primer-cured layer that has seeped out from the edge of the PET film is measured as the "maximum seepage length". The maximum seepage length of the (a12) primer-cured layer is preferably 0.3 mm or less, more preferably 0.2 mm or less, even more preferably 0.1 mm or less, and particularly preferably 0 mm.

[0144] Furthermore, the degree of curing of the second resin composition in the (a12) primer cured layer can be expressed, for example, by the glass transition temperature of the cured product of the second resin composition contained in the (a12) primer cured layer. The range of the glass transition temperature of the cured product of the second resin composition is preferably 80°C or higher, more preferably 140°C or higher, even more preferably 150°C or higher, and even more preferably 160°C or higher. A cured product having such a glass transition temperature may not be substantially fluid under the temperature conditions during lamination (e.g., 70°C to 140°C). The upper limit of the glass transition temperature of the cured product of the second resin composition is preferably 300°C or lower, more preferably 250°C or lower, even more preferably 200°C or lower, and even more preferably 180°C or lower. The glass transition temperature of the cured product of the second resin composition can be measured by the same measurement method as the glass transition temperature of the opposite insulating layer containing the fibrous substrate.

[0145] (a12) The thickness of the primer-cured layer is preferably 1 μm or more, more preferably 2 μm, even more preferably 3 μm or more, preferably 30 μm or less, more preferably 20 μm or less, and even more preferably 10 μm or less.

[0146] Typically, when a (a1) fiber-reinforced sheet is cured to obtain a cured sample, the cured sample may have the same composition as the insulating layer containing the fiber substrate. Therefore, when a CTE measurement test is performed to measure the linear thermal expansion coefficient of a cured sample of a (a1) fiber-reinforced sheet, the cured sample may have the same linear thermal expansion coefficient as the insulating layer formed using the (a1) fiber-reinforced sheet. In the following description, unless otherwise specified, "(a1) fiber-reinforced sheet cured sample" refers to a cured sample obtained by curing a (a1) fiber-reinforced sheet under the same curing conditions as the curing conditions for the (a1) fiber-reinforced sheet in the manufacturing method of the structure. In one example, a curing condition of 200°C for 90 minutes may be adopted.

[0147] Therefore, it is preferable that the range of the linear thermal expansion coefficient of the cured sample of the (a1) fiber-reinforced sheet for forming the opposite insulating layer including the fiber substrate is the same as the range of the linear thermal expansion coefficient of the opposite insulating layer including the fiber substrate described above. For example, it is preferable that the range of the linear thermal expansion coefficient in the high-temperature measurement range of the cured sample of the (a1) fiber-reinforced sheet for forming the opposite insulating layer including the fiber substrate is the same as the range of the linear thermal expansion coefficient CTE(FOh) in the high-temperature measurement range of the opposite insulating layer including the fiber substrate described above. Also, for example, it is preferable that the range of the linear thermal expansion coefficient in the low-temperature measurement range of the cured sample of the (a1) fiber-reinforced sheet for forming the opposite insulating layer including the fiber substrate is the same as the range of the linear thermal expansion coefficient CTE(FOl) in the low-temperature measurement range of the opposite insulating layer including the fiber substrate described above. Furthermore, for example, the range of the difference between the linear thermal expansion coefficient in the high-temperature measurement range and the linear thermal expansion coefficient in the low-temperature measurement range of a cured sample of a fiber-reinforced sheet (a1) for forming an insulating layer on the opposite side including a fiber substrate (linear thermal expansion coefficient in the high-temperature measurement range - linear thermal expansion coefficient in the low-temperature measurement range) is preferably the same as the range of the difference between the linear thermal expansion coefficient CTE(FOh) in the high-temperature measurement range and the linear thermal expansion coefficient CTE(FOl) in the low-temperature measurement range of the insulating layer on the opposite side including the fiber substrate, "CTE(FOh)-CTE(FOl)".

[0148] Furthermore, it is preferable that the range of the linear thermal expansion coefficient of the cured sample of the (a1) fiber-reinforced sheet for forming the chip-side insulating layer including the fiber substrate is the same as the range of the linear thermal expansion coefficient of the chip-side insulating layer including the fiber substrate described above. Therefore, for example, it is preferable that the range of the linear thermal expansion coefficient in the high-temperature measurement range of the cured sample of the (a1) fiber-reinforced sheet for forming the chip-side insulating layer including the fiber substrate is the same as the range of the linear thermal expansion coefficient CTE(FCh) in the high-temperature measurement range of the chip-side insulating layer including the fiber substrate described above. Furthermore, for example, it is preferable that the range of the linear thermal expansion coefficient in the low-temperature measurement range of the cured sample of the (a1) fiber-reinforced sheet for forming the chip-side insulating layer including the fiber substrate is the same as the range of the linear thermal expansion coefficient CTE(FCl) in the low-temperature measurement range of the chip-side insulating layer including the fiber substrate described above.

[0149] Furthermore, it is preferable that the range of the difference between the linear thermal expansion coefficient of the cured sample of the (a1) fiber-reinforced sheet for forming the opposite-side insulating layer including the fiber substrate and the linear thermal expansion coefficient of the cured sample of the (a1) fiber-reinforced sheet for forming the chip-side insulating layer including the fiber substrate is the same as the range of the difference between the linear thermal expansion coefficient of the opposite-side insulating layer including the fiber substrate and the linear thermal expansion coefficient of the chip-side insulating layer including the fiber substrate. Therefore, for example, it is preferable that the range of the absolute value of the difference between the linear thermal expansion coefficient in the high-temperature measurement range of the cured sample of the (a1) fiber-reinforced sheet for forming the opposite-side insulating layer including the fiber substrate and the linear thermal expansion coefficient in the high-temperature measurement range of the cured sample of the (a1) fiber-reinforced sheet for forming the chip-side insulating layer including the fiber substrate is the same as the range of the absolute value |CTE(FOh)-CTE(FCh)| of the difference between the linear thermal expansion coefficient CTE(FOh) in the high-temperature measurement range of the opposite-side insulating layer including the fiber substrate and the linear thermal expansion coefficient CTE(FCh) in the high-temperature measurement range of the chip-side insulating layer including the fiber substrate. Furthermore, for example, the range of the absolute value of the difference between the linear thermal expansion coefficient of the cured sample of the (a1) fiber-reinforced sheet for forming the opposite side insulating layer including the fiber substrate in the low temperature measurement range and the linear thermal expansion coefficient of the cured sample of the (a1) fiber-reinforced sheet for forming the chip side insulating layer including the fiber substrate in the low temperature measurement range is preferably the same as the range of the absolute value |CTE(FOl)-CTE(FCl)| of the difference "CTE(FOl)-CTE(FCl)" between the linear thermal expansion coefficient CTE(FOl) of the opposite side insulating layer including the fiber substrate in the low temperature measurement range and the linear thermal expansion coefficient CTE(FCl) of the chip side insulating layer including the fiber substrate in the low temperature measurement range.

[0150] Furthermore, when a cured sample is obtained by curing the (b1) resin composition layer, the cured sample may have the same composition as an insulating layer that does not contain a fibrous substrate. Therefore, when a CTE measurement test is performed to measure the linear thermal expansion coefficient of a cured sample of the (b1) resin composition layer, the cured sample may have the same linear thermal expansion coefficient as an insulating layer that does not contain a fibrous substrate and is formed using the (b1) resin composition layer. In the following description, unless otherwise specified, "(b1) resin composition layer cured sample" refers to a cured sample obtained by curing the (b1) resin composition layer under the same curing conditions as the curing conditions for the (b1) resin composition layer in the manufacturing method of the structure. In one example, a curing condition of 200°C for 90 minutes may be adopted.

[0151] Therefore, it is preferable that the linear thermal expansion coefficient in the high-temperature measurement range of the cured sample of (a1) fiber-reinforced sheet for forming the opposite insulating layer including the fiber substrate is smaller than the linear thermal expansion coefficient in the high-temperature measurement range of the cured sample of (b1) resin composition layer for forming the opposite insulating layer without the fiber substrate. In this case, it is preferable that the range of the difference between the linear thermal expansion coefficient in the high-temperature measurement range of the cured sample of (b1) resin composition layer for forming the opposite insulating layer without the fiber substrate and the linear thermal expansion coefficient in the high-temperature measurement range of the cured sample of (a1) fiber-reinforced sheet for forming the opposite insulating layer including the fiber substrate ((b1) linear thermal expansion coefficient of the cured sample of the resin composition layer - (a1) linear thermal expansion coefficient of the cured sample of the fiber-reinforced sheet) is the same as the range of the difference "CTE(ROh)-CTE(FOh)" between the linear thermal expansion coefficient CTE(ROh) of the opposite insulating layer without the fiber substrate and the linear thermal expansion coefficient CTE(FOh) of the opposite insulating layer including the fiber substrate.

[0152] Furthermore, it is preferable that the linear thermal expansion coefficient in the high-temperature measurement range of the cured sample of (a1) fiber-reinforced sheet for forming the opposite-side insulating layer including the fiber substrate is smaller than the linear thermal expansion coefficient in the high-temperature measurement range of the cured sample of (b1) resin composition layer for forming the chip-side insulating layer without the fiber substrate. In this case, it is preferable that the range of the difference between the linear thermal expansion coefficient in the high-temperature measurement range of the cured sample of (b1) resin composition layer for forming the chip-side insulating layer without the fiber substrate and the linear thermal expansion coefficient in the high-temperature measurement range of the cured sample of (a1) fiber-reinforced sheet for forming the opposite-side insulating layer including the fiber substrate ((b1) linear thermal expansion coefficient of the cured sample of the resin composition layer - (a1) linear thermal expansion coefficient of the cured sample of the fiber-reinforced sheet) is the same as the range of the difference "CTE(RCh)-CTE(FOh)" between the linear thermal expansion coefficient CTE(RCh) of the chip-side insulating layer without the fiber substrate and the linear thermal expansion coefficient CTE(FOh) of the opposite-side insulating layer including the fiber substrate.

[0153] Furthermore, it is preferable that the linear thermal expansion coefficient in the low-temperature measurement range of the cured sample of the (a1) fiber-reinforced sheet for forming the opposite-side insulating layer including the fiber substrate is close to the linear thermal expansion coefficient in the low-temperature measurement range of the cured sample of the (b1) resin composition layer for forming the opposite-side insulating layer without the fiber substrate. In this case, it is preferable that the range of the absolute value of the difference between the linear thermal expansion coefficient in the low-temperature measurement range of the cured sample of the (b1) resin composition layer for forming the opposite-side insulating layer without the fiber substrate and the linear thermal expansion coefficient in the low-temperature measurement range of the cured sample of the (a1) fiber-reinforced sheet for forming the opposite-side insulating layer including the fiber substrate is the same as the range of the absolute value |CTE(ROl)-CTE(FOl)| of the difference "CTE(ROl)-CTE(FOl)" between the linear thermal expansion coefficient CTE(ROl) in the low-temperature measurement range of the opposite-side insulating layer without the fiber substrate and the linear thermal expansion coefficient CTE(FOl) in the low-temperature measurement range of the opposite-side insulating layer including the fiber substrate.

[0154] Furthermore, it is preferable that the linear thermal expansion coefficient in the low-temperature measurement range of the cured sample of the (a1) fiber-reinforced sheet for forming the opposite-side insulating layer including the fiber substrate is close to the linear thermal expansion coefficient in the low-temperature measurement range of the cured sample of the (b1) resin composition layer for forming the chip-side insulating layer without the fiber substrate. In this case, it is preferable that the range of the absolute value of the difference between the linear thermal expansion coefficient in the low-temperature measurement range of the cured sample of the (b1) resin composition layer for forming the chip-side insulating layer without the fiber substrate and the linear thermal expansion coefficient in the low-temperature measurement range of the cured sample of the (a1) fiber-reinforced sheet for forming the opposite-side insulating layer including the fiber substrate is the same as the range of the absolute value |CTE(RCl)-CTE(FOl)| of the difference "CTE(RCl)-CTE(FOl)" between the linear thermal expansion coefficient CTE(RCl) in the low-temperature measurement range of the chip-side insulating layer without the fiber substrate and the linear thermal expansion coefficient CTE(FOl) in the low-temperature measurement range of the opposite-side insulating layer including the fiber substrate.

[0155] Furthermore, it is preferable that the linear thermal expansion coefficient in the high-temperature measurement range of the cured sample of (a1) fiber-reinforced sheet for forming the chip-side insulating layer including the fiber substrate is smaller than the linear thermal expansion coefficient in the high-temperature measurement range of the cured sample of (b1) resin composition layer for forming the chip-side insulating layer without the fiber substrate. In this case, it is preferable that the range of the difference between the linear thermal expansion coefficient of the cured sample of the (b1) resin composition layer for forming the chip-side insulating layer without the fiber substrate and the linear thermal expansion coefficient of the cured sample of (a1) fiber-reinforced sheet for forming the chip-side insulating layer including the fiber substrate ((b1) linear thermal expansion coefficient of resin composition layer - (a1) linear thermal expansion coefficient of fiber-reinforced sheet) is the same as the range of the difference between the linear thermal expansion coefficient CTE(RCh) of the chip-side insulating layer without the fiber substrate in the high-temperature measurement range and the linear thermal expansion coefficient CTE(FCh) of the chip-side insulating layer including the fiber substrate, "CTE(RCh)-CTE(FCh)".

[0156] Furthermore, it is preferable that the linear thermal expansion coefficient in the high-temperature measurement range of the cured sample of (a1) fiber-reinforced sheet for forming the chip-side insulating layer including the fiber substrate is smaller than the linear thermal expansion coefficient in the high-temperature measurement range of the cured sample of (b1) resin composition layer for forming the opposite side insulating layer without the fiber substrate. The range of the difference between the linear thermal expansion coefficient in the high-temperature measurement range of the cured sample of (b1) resin composition layer for forming the opposite side insulating layer without the fiber substrate and the linear thermal expansion coefficient in the high-temperature measurement range of the cured sample of (a1) fiber-reinforced sheet for forming the chip-side insulating layer including the fiber substrate ((b1) linear thermal expansion coefficient of the cured sample of the resin composition layer - (a1) linear thermal expansion coefficient of the cured sample of the fiber-reinforced sheet) is preferably the same as the range of the difference between the linear thermal expansion coefficient CTE(ROh) of the opposite side insulating layer without the fiber substrate and the linear thermal expansion coefficient CTE(FCh) of the chip-side insulating layer including the fiber substrate, "CTE(ROh)-CTE(FCh)".

[0157] Furthermore, it is preferable that the linear thermal expansion coefficient in the low-temperature measurement range of the cured sample of the (a1) fiber-reinforced sheet for forming the chip-side insulating layer including the fiber substrate is close to the linear thermal expansion coefficient in the low-temperature measurement range of the cured sample of the (b1) resin composition layer for forming the chip-side insulating layer without the fiber substrate. In this case, it is preferable that the range of the absolute value of the difference between the linear thermal expansion coefficient in the low-temperature measurement range of the cured sample of the (b1) resin composition layer for forming the chip-side insulating layer without the fiber substrate and the linear thermal expansion coefficient in the low-temperature measurement range of the cured sample of the (a1) fiber-reinforced sheet for forming the chip-side insulating layer including the fiber substrate is the same as the range of the absolute value |CTE(RCl)-CTE(FCl)| of the difference "CTE(RCl)-CTE(FCl)" between the linear thermal expansion coefficient CTE(RCl) of the chip-side insulating layer without the fiber substrate and the linear thermal expansion coefficient CTE(FCl) of the chip-side insulating layer including the fiber substrate.

[0158] Furthermore, it is preferable that the linear thermal expansion coefficient in the low-temperature measurement range of the cured sample of the (a1) fiber-reinforced sheet for forming the chip-side insulating layer including the fiber substrate is close to the linear thermal expansion coefficient in the low-temperature measurement range of the cured sample of the (b1) resin composition layer for forming the opposite side insulating layer without the fiber substrate. In this case, it is preferable that the range of the absolute value of the difference between the linear thermal expansion coefficient in the low-temperature measurement range of the cured sample of the (b1) resin composition layer for forming the opposite side insulating layer without the fiber substrate and the linear thermal expansion coefficient in the low-temperature measurement range of the cured sample of the (a1) fiber-reinforced sheet for forming the chip-side insulating layer including the fiber substrate is the same as the range of the absolute value |CTE(ROl)-CTE(FCl)| of the difference "CTE(ROl)-CTE(FCl)" between the linear thermal expansion coefficient CTE(ROl) in the low-temperature measurement range of the opposite side insulating layer without the fiber substrate and the linear thermal expansion coefficient CTE(FCl) in the low-temperature measurement range of the chip-side insulating layer including the fiber substrate.

[0159] (a1) If the coefficient of linear thermal expansion of the cured sample of the fiber-reinforced sheet satisfies the above-mentioned preferred requirements, warping after mounting of the semiconductor chip can be effectively suppressed.

[0160] (a1) The linear thermal expansion coefficient of a cured sample of a fiber-reinforced sheet can be measured by the same method as the linear thermal expansion coefficient of the insulating layer on the opposite side, which includes the fiber substrate.

[0161] Furthermore, when a Tg measurement test is performed to measure the glass transition temperature of a cured sample of (a1) fiber-reinforced sheet, the cured sample may have the same glass transition temperature as the insulating layer formed using (a1) fiber-reinforced sheet.

[0162] Therefore, it is preferable that the glass transition temperature range of the cured sample of the fiber-reinforced sheet (a1) for forming the opposite insulating layer containing the fiber substrate is the same as the glass transition temperature range of the opposite insulating layer containing the fiber substrate as described above.

[0163] Furthermore, it is preferable that the glass transition temperature range of the cured sample of the (a1) fiber-reinforced sheet for forming the chip-side insulating layer including the fiber substrate is the same as the glass transition temperature range of the chip-side insulating layer including the fiber substrate described above.

[0164] Furthermore, it is preferable that the range of the absolute difference between the glass transition temperature of the cured sample of the (a1) fiber-reinforced sheet for forming the opposite side insulating layer including the fiber substrate and the glass transition temperature of the cured sample of the (a1) fiber-reinforced sheet for forming the chip side insulating layer including the fiber substrate is the same as the range of the absolute difference between the glass transition temperature of the opposite side insulating layer including the fiber substrate and the glass transition temperature of the chip side insulating layer including the fiber substrate.

[0165] Furthermore, when a Tg measurement test is performed to measure the glass transition temperature of a cured sample of the (b1) resin composition layer, the cured sample may have the same glass transition temperature as the insulating layer formed using the (b1) resin composition layer.

[0166] Therefore, the glass transition temperature of the cured sample of the (a1) fiber-reinforced sheet for forming the opposite insulating layer containing the fiber substrate may be higher, lower, or the same as the glass transition temperature of the cured sample of the (b1) resin composition layer for forming the opposite insulating layer without the fiber substrate. In this case, it is preferable that the range of the absolute value of the difference between the glass transition temperature of the cured sample of the (a1) fiber-reinforced sheet for forming the opposite insulating layer containing the fiber substrate and the glass transition temperature of the cured sample of the (b1) resin composition layer for forming the opposite insulating layer without the fiber substrate is the same as the range of the absolute value of the difference between the glass transition temperature of the opposite insulating layer containing the fiber substrate and the glass transition temperature of the opposite insulating layer without the fiber substrate as described above.

[0167] Furthermore, the glass transition temperature of the cured sample of the (a1) fiber-reinforced sheet for forming the opposite-side insulating layer containing the fiber substrate may be higher, lower, or the same as the glass transition temperature of the cured sample of the (b1) resin composition layer for forming the chip-side insulating layer without the fiber substrate. In this case, it is preferable that the range of the absolute value of the difference between the glass transition temperature of the cured sample of the (a1) fiber-reinforced sheet for forming the opposite-side insulating layer containing the fiber substrate and the glass transition temperature of the cured sample of the (b1) resin composition layer for forming the chip-side insulating layer without the fiber substrate is the same as the range of the absolute value of the difference between the glass transition temperature of the opposite-side insulating layer containing the fiber substrate and the glass transition temperature of the chip-side insulating layer without the fiber substrate as described above.

[0168] Furthermore, the glass transition temperature of the cured sample of the (a1) fiber-reinforced sheet for forming the chip-side insulating layer including the fiber substrate may be higher, lower, or the same as the glass transition temperature of the cured sample of the (b1) resin composition layer for forming the chip-side insulating layer without the fiber substrate. In this case, it is preferable that the range of the absolute value of the difference between the glass transition temperature of the cured sample of the (a1) fiber-reinforced sheet for forming the chip-side insulating layer including the fiber substrate and the glass transition temperature of the cured sample of the (b1) resin composition layer for forming the chip-side insulating layer without the fiber substrate is the same as the range of the absolute value of the difference between the glass transition temperature of the chip-side insulating layer including the fiber substrate and the glass transition temperature of the chip-side insulating layer without the fiber substrate.

[0169] Furthermore, the glass transition temperature of the cured sample of the (a1) fiber-reinforced sheet for forming the chip-side insulating layer including the fiber substrate may be higher, lower, or the same as the glass transition temperature of the cured sample of the (b1) resin composition layer for forming the opposite-side insulating layer without the fiber substrate. Preferably, the range of the absolute difference between the glass transition temperature of the cured sample of the (a1) fiber-reinforced sheet for forming the chip-side insulating layer including the fiber substrate and the glass transition temperature of the cured sample of the (b1) resin composition layer for forming the opposite-side insulating layer without the fiber substrate is the same as the range of the absolute difference between the glass transition temperature of the chip-side insulating layer including the fiber substrate and the glass transition temperature of the opposite-side insulating layer without the fiber substrate.

[0170] (a1) If the glass transition temperature of the hardened fiber-reinforced sheet satisfies the above-mentioned preferred requirements, warping after mounting of the semiconductor chip can be effectively suppressed.

[0171] (a1) The glass transition temperature of a cured sample of a fiber-reinforced sheet can be measured by the same method as the glass transition temperature of the insulating layer on the opposite side containing the fiber substrate.

[0172] Furthermore, if an elastic modulus measurement test is performed to measure the tensile modulus of a cured sample of (a1) fiber-reinforced sheet, the cured sample may have the same tensile modulus as the insulating layer formed using (a1) fiber-reinforced sheet.

[0173] Therefore, it is preferable that the range of the tensile modulus of the cured sample of the (a1) fiber-reinforced sheet for forming the opposite insulating layer including the fiber substrate is the same as the range of the tensile modulus of the opposite insulating layer including the fiber substrate described above. For example, it is preferable that the range of the tensile modulus at 260°C of the cured sample of the (a1) fiber-reinforced sheet for forming the opposite insulating layer including the fiber substrate is the same as the range of the tensile modulus E(FOh) at 260°C of the opposite insulating layer including the fiber substrate described above. Also, for example, it is preferable that the range of the tensile modulus at 23°C of the cured sample of the (a1) fiber-reinforced sheet for forming the opposite insulating layer including the fiber substrate is the same as the range of the tensile modulus E(FOl) at 23°C of the opposite insulating layer including the fiber substrate described above. Furthermore, for example, the range of the ratio of the tensile modulus at 260°C to the tensile modulus at 23°C of a cured sample of a fiber-reinforced sheet for forming an opposite insulating layer including a fiber substrate is preferably the same as the range of the ratio "E(FOh) / E(FOl)" of the tensile modulus at 260°C of the opposite insulating layer including a fiber substrate to the tensile modulus E(FOh) at 23°C of the opposite insulating layer including a fiber substrate, as described above.

[0174] Furthermore, it is preferable that the range of the tensile modulus of the cured sample of the (a1) fiber-reinforced sheet for forming the chip-side insulating layer including the fiber substrate is the same as the range of the tensile modulus of the chip-side insulating layer including the fiber substrate described above. Therefore, for example, it is preferable that the range of the tensile modulus at 260°C of the cured sample of the (a1) fiber-reinforced sheet for forming the chip-side insulating layer including the fiber substrate is the same as the range of the tensile modulus E(FCh) at 260°C of the chip-side insulating layer including the fiber substrate described above. Furthermore, for example, it is preferable that the range of the tensile modulus at 23°C of the cured sample of the (a1) fiber-reinforced sheet for forming the chip-side insulating layer including the fiber substrate is the same as the range of the tensile modulus E(FCl) at 23°C of the chip-side insulating layer including the fiber substrate described above.

[0175] Furthermore, it is preferable that the range of the difference between the tensile modulus of the cured sample of the (a1) fiber-reinforced sheet for forming the opposite-side insulating layer including the fiber substrate and the tensile modulus of the cured sample of the (a1) fiber-reinforced sheet for forming the chip-side insulating layer including the fiber substrate is the same as the range of the difference between the tensile modulus of the opposite-side insulating layer including the fiber substrate and the tensile modulus of the chip-side insulating layer including the fiber substrate described above. Therefore, for example, it is preferable that the range of the absolute value of the difference between the tensile modulus at 260°C of the cured sample of the (a1) fiber-reinforced sheet for forming the opposite-side insulating layer including the fiber substrate and the tensile modulus at 260°C of the cured sample of the (a1) fiber-reinforced sheet for forming the chip-side insulating layer including the fiber substrate is the same as the range of the absolute value |E(FOh)-E(FCh)| of the difference "E(FOh)-E(FCh)" between the tensile modulus E(FOh) of the opposite-side insulating layer including the fiber substrate and the tensile modulus E(FCh) of the chip-side insulating layer including the fiber substrate at 260°C described above. Furthermore, for example, the range of the absolute value of the difference between the tensile modulus of the cured sample of the (a1) fiber-reinforced sheet at 23°C for forming the opposite side insulating layer including the fiber substrate and the tensile modulus of the cured sample of the (a1) fiber-reinforced sheet at 23°C for forming the chip side insulating layer including the fiber substrate is preferably the same as the range of the absolute value |E(FOl)-E(FCl)| of the difference "E(FOl)-E(FCl)" between the tensile modulus E(FOl) of the opposite side insulating layer including the fiber substrate at 23°C and the tensile modulus E(FCl) of the chip side insulating layer including the fiber substrate at 23°C.

[0176] Furthermore, if an elastic modulus measurement test is performed to measure the tensile modulus of a cured sample of the (b1) resin composition layer, the cured sample may have the same tensile modulus as the insulating layer formed using the (b1) resin composition layer.

[0177] Therefore, it is preferable that the tensile modulus of the cured sample of the (a1) fiber-reinforced sheet for forming the opposite insulating layer including the fiber substrate is greater than the tensile modulus of the cured sample of the (b1) resin composition layer for forming the opposite insulating layer without the fiber substrate. In this case, it is preferable that the range of the difference between the tensile modulus at 260°C of the cured sample of the (a1) fiber-reinforced sheet for forming the opposite insulating layer including the fiber substrate and the tensile modulus at 260°C of the cured sample of the (b1) resin composition layer for forming the opposite insulating layer without the fiber substrate ((a1) tensile modulus of the cured sample of the fiber-reinforced sheet - (b1) tensile modulus of the cured sample of the resin composition layer) is the same as the range of the difference "E(FOh)-E(ROh)" between the tensile modulus E(FOh) of the opposite insulating layer including the fiber substrate and the tensile modulus E(ROh) of the opposite insulating layer without the fiber substrate at 260°C. Furthermore, it is preferable that the range of the difference between the tensile modulus at 23°C of the cured sample of (a1) fiber-reinforced sheet for forming the opposite insulating layer including the fiber substrate and the tensile modulus at 23°C of the cured sample of (b1) resin composition layer for forming the opposite insulating layer without the fiber substrate ((a1) tensile modulus of fiber-reinforced sheet - (b1) tensile modulus of resin composition layer) is the same as the range of the difference "E(FOl)-E(ROl)" between the tensile modulus E(FOl) at 23°C of the opposite insulating layer including the fiber substrate and the tensile modulus E(ROl) at 23°C of the opposite insulating layer without the fiber substrate.

[0178] Furthermore, it is preferable that the tensile modulus of the cured sample of the (a1) fiber-reinforced sheet for forming the opposite-side insulating layer including the fiber substrate is greater than the tensile modulus of the cured sample of the (b1) resin composition layer for forming the chip-side insulating layer without the fiber substrate. In this case, it is preferable that the range of the difference between the tensile modulus at 260°C of the cured sample of the (a1) fiber-reinforced sheet for forming the opposite-side insulating layer including the fiber substrate and the tensile modulus at 260°C of the cured sample of the (b1) resin composition layer for forming the chip-side insulating layer without the fiber substrate ((a1) tensile modulus of the cured sample of the fiber-reinforced sheet - (b1) tensile modulus of the cured sample of the resin composition layer) is the same as the range of the difference "E(FOh)-E(RCh)" between the tensile modulus E(FOh) of the opposite-side insulating layer including the fiber substrate and the tensile modulus E(RCh) of the chip-side insulating layer without the fiber substrate at 260°C. Furthermore, it is preferable that the range of the difference between the tensile modulus at 23°C of the cured sample of (a1) fiber-reinforced sheet for forming the opposite side insulating layer including the fiber substrate and the tensile modulus at 23°C of the cured sample of (b1) resin composition layer for forming the chip side insulating layer without the fiber substrate ((a1) tensile modulus of fiber-reinforced sheet - (b1) tensile modulus of resin composition layer) is the same as the range of the difference "E(FOl)-E(RCl)" between the tensile modulus at 23°C E(FOl) of the opposite side insulating layer including the fiber substrate and the tensile modulus at 23°C E(RCl) of the chip side insulating layer without the fiber substrate.

[0179] Furthermore, it is preferable that the tensile modulus of the cured sample of the (a1) fiber-reinforced sheet for forming the chip-side insulating layer including the fiber substrate is greater than the tensile modulus of the cured sample of the (b1) resin composition layer for forming the chip-side insulating layer without the fiber substrate. In this case, it is preferable that the range of the difference between the tensile modulus of the cured sample of the (a1) fiber-reinforced sheet for forming the chip-side insulating layer including the fiber substrate at 260°C and the tensile modulus of the cured sample of the (b1) resin composition layer for forming the chip-side insulating layer without the fiber substrate ((a1) tensile modulus of the cured sample of the fiber-reinforced sheet - (b1) tensile modulus of the cured sample of the resin composition layer) at 260°C is the same as the range of the difference between the tensile modulus E(FCh) of the chip-side insulating layer including the fiber substrate at 260°C and the tensile modulus E(RCh) of the chip-side insulating layer without the fiber substrate at 260°C, "E(FCh)-E(RCh)". Furthermore, it is preferable that the range of the difference between the tensile modulus at 23°C of a cured sample of (a1) a fiber-reinforced sheet for forming a chip-side insulating layer including a fiber substrate and the tensile modulus at 23°C of a cured sample of (b1) a resin composition layer for forming a chip-side insulating layer without a fiber substrate ((a1) tensile modulus of the cured sample of the fiber-reinforced sheet - (b1) tensile modulus of the cured sample of the resin composition layer) is the same as the range of the difference between the tensile modulus E(FCl) at 23°C of the chip-side insulating layer including a fiber substrate and the tensile modulus E(RCl) at 23°C of the chip-side insulating layer without a fiber substrate, "E(FCl) - E(RCl)".

[0180] Furthermore, it is preferable that the tensile modulus of the cured sample of the (a1) fiber-reinforced sheet for forming the chip-side insulating layer including the fiber substrate is greater than the tensile modulus of the cured sample of the (b1) resin composition layer for forming the opposite-side insulating layer without the fiber substrate. In this case, it is preferable that the range of the difference between the tensile modulus of the cured sample of the (a1) fiber-reinforced sheet for forming the chip-side insulating layer including the fiber substrate at 260°C and the tensile modulus of the cured sample of the (b1) resin composition layer for forming the opposite-side insulating layer without the fiber substrate at 260°C ((a1) tensile modulus of the cured sample of the fiber-reinforced sheet - (b1) tensile modulus of the cured sample of the resin composition layer) is the same as the range of the difference between the tensile modulus E(FCh) of the chip-side insulating layer including the fiber substrate at 260°C and the tensile modulus E(ROh) of the opposite-side insulating layer without the fiber substrate at 260°C, "E(FCh)-E(ROh)". Furthermore, it is preferable that the range of the difference between the tensile modulus at 23°C of the cured sample of (a1) fiber-reinforced sheet for forming the chip-side insulating layer including the fiber substrate and the tensile modulus at 23°C of the cured sample of (b1) resin composition layer for forming the opposite side insulating layer without the fiber substrate ((a1) tensile modulus of fiber-reinforced sheet - (b1) tensile modulus of resin composition layer) is the same as the range of the difference between the tensile modulus E(FCl) at 23°C of the chip-side insulating layer including the fiber substrate and the tensile modulus E(ROl) at 23°C of the opposite side insulating layer without the fiber substrate, "E(FCl) - E(ROl)".

[0181] (a1) If the tensile modulus of the cured sample of the fiber-reinforced sheet satisfies the above-mentioned preferred requirements, warping after mounting of the semiconductor chip can be effectively suppressed.

[0182] (a1) The tensile modulus of a cured sample of a fiber-reinforced sheet can be measured by the same method as the tensile modulus of the opposite insulating layer containing the fiber substrate.

[0183] (a1) The range of thickness of the fiber-reinforced sheet may be the same as the range of thickness per layer of the insulating layer formed using the (a1) fiber-reinforced sheet.

[0184] From the viewpoint of improving handling, it is preferable that the (a1) fiber-reinforced sheet be provided on the (a) insulating multilayer sheet. In this case, the (a) insulating multilayer sheet comprises a (a2) support and the (a1) fiber-reinforced sheet formed on the (a2) support. (a1) If the fiber-reinforced sheet comprises (a11) a prepreg layer and (a12) a primer-cured layer, (a) the insulating multilayer sheet may comprise (a11) a prepreg layer, (a12) a primer-cured layer and (a2) a support in this order. (a2) Examples of the support include a film of plastic material and metal foil.

[0185] (a2) When using a plastic film as a support, examples of plastic materials include polyesters such as polyethylene terephthalate (hereinafter sometimes abbreviated as "PET") and polyethylene naphthalate (hereinafter sometimes abbreviated as "PEN"), polycarbonate (hereinafter sometimes abbreviated as "PC"), acrylics such as polymethyl methacrylate (PMMA), cyclic polyolefins, triacetylcellulose (TAC), polyether sulfide (PES), polyether ketones, and polyimides. Among these, polyethylene terephthalate and polyethylene naphthalate are preferred, and inexpensive polyethylene terephthalate is particularly preferred.

[0186] (a2) When using a metal foil as a support, examples of metal foils include copper foil and aluminum foil, with copper foil being preferred. As for the copper foil, foil made of a single metal of copper may be used, or foil made of an alloy of copper with another metal (for example, tin, chromium, silver, magnesium, nickel, zirconium, silicon, titanium, etc.) may be used.

[0187] (a2) The support may have surface treatments such as mat treatment, corona treatment, or antistatic treatment applied to the surface of the support that comes into contact with the (a1) fiber-reinforced sheet. Alternatively, a support with a release layer may be used as the (a2) support. The release layer can usually be formed by a release agent. Examples of release agents include one or more release agents selected from the group consisting of alkyd-based release agents, polyolefin-based release agents, urethane-based release agents, and silicone-based release agents. Commercially available support products may be used as the support with a release layer, for example, PET films having a release layer mainly composed of a silicone-based release agent or an alkyd resin-based release agent, such as "PET501010", "SK-1", "AL-5", and "AL-7" from Lintec Corporation; "Lumirror T60" from Toray Industries, Inc.; "Purex" from Teijin Ltd.; and "Unipeel" from Unitika Corporation.

[0188] (a2) The thickness of the support is preferably 1 μm or more, more preferably 5 μm or more, even more preferably 10 μm or more, preferably 75 μm or less, more preferably 60 μm or less, and even more preferably 50 μm or less. When using a support with a release layer, it is preferable that the overall thickness of the support with the release layer is within the above range.

[0189] (a) The insulating multilayer sheet may be combined with (a1) the fiber-reinforced sheet and (a2) the support and further comprise any optional elements. For example, (a) the insulating multilayer sheet may comprise a (a3) ​​protective film layer that protects the (a1) fiber-reinforced sheet. The (a3) ​​protective film layer is usually provided on the side of the (a1) fiber-reinforced sheet that is not bonded to the (a2) support (i.e., the side opposite to the (a2) support). The thickness of the (a3) ​​protective film layer is not particularly limited, but is for example 1 μm to 40 μm. The (a3) ​​protective film can prevent dust from adhering to the surface of the (a1) fiber-reinforced sheet and prevent scratches. Generally, when the (a) insulating multilayer sheet comprises a (a3) ​​protective film layer, the (a) insulating multilayer sheet can be used by peeling off the (a3) ​​protective film layer.

[0190] (a1) Fiber-reinforced sheets can be manufactured by a method that includes a step of forming a prepreg layer. (a11) The prepreg layer can be manufactured by methods such as the hot melt method or the solvent method. (a11) Preferred methods for manufacturing the prepreg layer include the following methods (1) to (4). (1) Without dissolving the first resin composition in a solvent, the first resin composition is coated onto a support substrate to form a layer of the first resin composition. The layer of the first resin composition is laminated with a fiber substrate to form a (a11) prepreg layer on the support substrate. (2) The first resin composition is coated onto a fibrous substrate without being dissolved in a solvent to form a (a11) prepreg layer. (3) Prepare a resin varnish by dissolving the first resin composition in a solvent. Immerse the fiber substrate in the resin varnish to impregnate the fiber substrate with the resin varnish. Then, dry the resin varnish to form a (a11) prepreg layer. (4) A resin varnish is applied to the support substrate and dried as necessary to form a layer of the first resin composition. This layer of the first resin composition is laminated with the fiber substrate to form a (a11) prepreg layer on the support substrate. In the above method, for example, a support (a2) may be used as the support substrate.

[0191] As a solvent for preparing the resin varnish, for example, a solvent similar to solvent (F) that may be included in the resin composition may be used. In one example, the drying temperature is preferably 80°C or higher, more preferably 90°C or higher, preferably 180°C or lower, and more preferably 140°C or lower. The drying time is preferably 3 minutes or more, preferably 13 minutes or less, and more preferably 10 minutes or less.

[0192] (a11) The step of forming the prepreg layer may, if necessary, include laminating the (a2) support and the (a3) ​​protective film layer onto the (a11) prepreg layer.

[0193] (a1) A method for manufacturing a fiber-reinforced sheet may further include (a12) a step of forming a primer-cured layer. (a12) The primer-cured layer can be formed by a method comprising forming a layer of a second resin composition and curing the layer of the second resin composition.

[0194] The layer of the second resin composition may be formed, for example, by coating the (a2) support with a liquid second resin composition. Alternatively, the layer of the second resin composition may be formed by, for example, mixing the second resin composition with a solvent to prepare a liquid resin varnish, coating this with the (a2) support, and then drying it as necessary. As the solvent, for example, one similar to the (F) solvent that may be contained in the resin composition may be used. Furthermore, drying is carried out so that the solvent content in the layer of the second resin composition is usually 10% by mass or less, preferably 5% by mass or less.

[0195] After forming a layer of the second resin composition, the layer is cured to form a (a12) primer-cured layer. Typically, the second resin composition layer is cured by heating. For example, the second resin composition layer may be cured by heating at a temperature of 50°C to 200°C for 10 minutes to 10 hours. Alternatively, the drying and curing of the second resin composition layer may be performed simultaneously.

[0196] By bonding the obtained (a12) primer-cured layer to the (a11) prepreg layer, a (a1) fiber-reinforced sheet comprising the (a11) prepreg layer and the (a12) primer-cured layer is obtained. For example, the (a1) fiber-reinforced sheet may be manufactured by laminating a cured sheet comprising the (a2) support and the (a12) primer-cured layer with the (a11) prepreg layer. Furthermore, the method for manufacturing the (a1) fiber-reinforced sheet may include any additional steps, for example, a step of bonding a (a3) ​​protective film layer.

[0197] (a1) A method for forming an insulating layer using a fiber-reinforced sheet includes laminating the fiber-reinforced sheet. For example, the fiber-reinforced sheet is formed directly on the core substrate by laminating so that the core substrate and the fiber-reinforced sheet are joined together. Here, "directly" forming the fiber-reinforced sheet on the core substrate means that there are no other layers between the core substrate and the fiber-reinforced sheet. Alternatively, for example, the fiber-reinforced sheet is formed on the core substrate via the insulating layer by laminating so that the insulating layer and the fiber-reinforced sheet are joined together. When the fiber-reinforced sheet includes a combination of a prepreg layer and a primer-cured layer, the lamination is usually performed so that the prepreg layer is joined to the core substrate or the insulating layer, so that the primer-cured layer is located further away from the core substrate than the prepreg layer.

[0198] (a1) The lamination of the fiber-reinforced sheet is carried out by pressing the (a1) fiber-reinforced sheet onto the core substrate. This lamination may be carried out using an (a) insulating multilayer sheet equipped with a (a2) support. In this case, it is preferable to perform the lamination by pressing the (a) insulating multilayer sheet from the (a2) support side. Examples of the pressing member (hereinafter also referred to as the "heat-pressing member") include a heated metal plate (such as a SUS end plate) or a metal roll (such as a SUS roll). The heat-pressing member may be pressed directly onto the (a) insulating multilayer sheet, but it is preferable to press via an elastic material such as heat-resistant rubber so that the (a11) prepreg layer can sufficiently follow the surface irregularities of the core substrate or the already formed insulating layer.

[0199] (a1) The lamination of the fiber-reinforced sheets is preferably carried out by lamination. Lamination generally applies lower pressure to the (a1) fiber-reinforced sheets compared to compression molding and vacuum pressing. Therefore, in addition to saving space in the equipment, it is possible to effectively suppress the formation of irregularities on the surface of the (a1) fiber-reinforced sheets that reflect the shape of the fiber substrate, and to effectively suppress the exposure of the fiber substrate on the surface of the (a1) fiber-reinforced sheets.

[0200] In the lamination process, the heating temperature is preferably in the range of 60°C to 160°C, more preferably 80°C to 140°C. The pressing temperature is preferably in the range of 0.098 MPa to 1.77 MPa, more preferably 0.29 MPa to 1.47 MPa. Furthermore, the pressing time is preferably in the range of 10 seconds to 400 seconds, more preferably 30 seconds to 300 seconds. This lamination is preferably carried out under reduced pressure conditions of 26.7 hPa or less.

[0201] Lamination may be performed using a commercially available vacuum laminator. Examples of commercially available vacuum laminators include vacuum pressure laminators manufactured by Meiki Seisakusho Co., Ltd., vacuum applicators manufactured by Nikko Materials Co., Ltd., and batch-type vacuum pressure laminators.

[0202] (a1) A method for forming an insulating layer using a fiber-reinforced sheet may include smoothing the fiber-reinforced sheet (a1) under normal pressure (atmospheric pressure) after lamination of the fiber-reinforced sheets. For example, a method for forming an insulating layer may include smoothing the fiber-reinforced sheet (a1) by pressing it with a heat-sealing member. (a2) When using an insulating multilayer sheet (a) equipped with a support, the fiber-reinforced sheet (a1) can usually be smoothed by pressing the insulating multilayer sheet (a) from the support side. The pressing conditions for the smoothing process may be the same as the lamination conditions for the lamination method described above. The smoothing process can be performed using a commercially available laminator. Lamination and smoothing may be performed continuously using the commercially available vacuum laminator described above.

[0203] (a1) A method for forming an insulating layer using a fiber-reinforced sheet typically involves laminating the (a1) fiber-reinforced sheets and then curing the (a1) fiber-reinforced sheets. By curing the (a1) fiber-reinforced sheets, the (a11) prepreg layer containing the fiber substrate is cured, so that an insulating layer containing the fiber substrate can be formed.

[0204] (a1) The fiber-reinforced sheet is usually cured by thermosetting. (a1) The thermosetting conditions for the fiber-reinforced sheet may vary depending on (a11) the type of primary resin composition contained in the prepreg layer. For example, the curing temperature is preferably 120°C to 240°C, more preferably 150°C to 220°C, and even more preferably 170°C to 210°C. The curing time may be preferably 5 minutes to 120 minutes, more preferably 10 minutes to 100 minutes, and even more preferably 15 minutes to 100 minutes.

[0205] (a1) A method for forming an insulating layer using a fiber-reinforced sheet may include preheating the fiber-reinforced sheet at a temperature lower than the curing temperature before the (a1) fiber-reinforced sheet is heat-cured. For example, prior to heat-curing the (a1) fiber-reinforced sheet, the (a1) fiber-reinforced sheet may be preheated at a temperature of 50°C to 150°C (preferably 60°C to 140°C, more preferably 70°C to 130°C) for 5 minutes or more (preferably 5 minutes to 150 minutes, more preferably 15 minutes to 120 minutes, and even more preferably 15 minutes to 100 minutes). Preheating is usually performed after lamination of the (a1) fiber-reinforced sheet. If a smoothing treatment is performed after lamination, preheating can usually be performed after the smoothing treatment.

[0206] (a2) When using an insulating multilayer sheet (a) equipped with a support, the method for forming the insulating layer may include peeling off the support (a2) after lamination of the fiber-reinforced sheet (a1). The peeling off of the support (a2) may be performed before the hardening of the fiber-reinforced sheet (a1) or after the hardening of the fiber-reinforced sheet (a1).

[0207] (Method for forming an insulating layer without a fibrous substrate) Next, a method for forming an insulating layer that does not contain a fibrous substrate will be described. As described above, it is preferable to form the insulating layer that does not contain a fibrous substrate by a method that includes laminating a resin composition layer (b1) that does not contain a fibrous substrate.

[0208] (b1) The resin composition layer may contain a resin composition, or it may contain only a resin composition. Hereinafter, the resin composition contained in this (b1) resin composition layer may be referred to as the "third resin composition". Since the third resin composition is usually thermosetting, an insulating layer without a fiber substrate can be formed by curing the (b1) resin composition layer containing the third resin composition. For example, an insulating layer without a fiber substrate can be formed on the core substrate 100 by a method that includes laminating the (b1) resin composition layer onto the core substrate 100 and thermosetting the third resin composition contained in the (b1) resin composition layer. Alternatively, for example, an insulating layer without a fiber substrate (the (n+1) insulating layer) can be formed on the insulating layer (the nth insulating layer) by laminating the (b1) resin composition layer onto an insulating layer (the nth insulating layer) and thermosetting the third resin composition contained in the (b1) resin composition layer. The above "n" represents a natural number.

[0209] (b1) The minimum melt viscosity range of the resin composition layer in the temperature range of 100°C to 140°C is preferably 100 poise or more, more preferably 200 poise or more, even more preferably 400 poise or more, preferably 10000 poise or less, more preferably 7000 poise or less, and even more preferably 4000 poise or less. Typically, the minimum melt viscosity of the (b1) resin composition layer in the temperature range of 100°C to 140°C corresponds to the minimum melt viscosity of the third resin composition contained in the (b1) resin composition layer in the temperature range of 100°C to 140°C. When the (b1) resin composition layer has a minimum melt viscosity within the above range in the temperature range of 100°C to 140°C, the conductive layer on the surface that joins with the (b1) resin composition layer can be well embedded.

[0210] (b1) When the temperature of the resin composition layer is increased, the melt viscosity of the (b1) resin composition layer generally decreases gradually with increasing temperature, reaching a lowest value at a certain temperature, and then may increase. In this case, the temperature at which the melt viscosity of the (b1) resin composition layer is lowest is preferably low from the viewpoint of properly embedding conductor layers such as wiring. In one example, the temperature range at which the melt viscosity of the (b1) resin composition layer is lowest is preferably 100°C or higher and 150°C or lower.

[0211] (b1) The melt viscosity of the resin composition layer can be measured by the same method as (a11) the melt viscosity of the prepreg layer. From the measured results, the lowest melt viscosity in the temperature range of 100°C to 140°C, and the temperature at which the lowest melt viscosity value is observed within the measurement temperature range can be determined.

[0212] As described above, when a CTE measurement test is performed to measure the linear thermal expansion coefficient of a cured sample of the (b1) resin composition layer, the cured sample may have the same linear thermal expansion coefficient as the insulating layer formed using the (b1) resin composition layer.

[0213] Therefore, it is preferable that the range of the linear thermal expansion coefficient of the cured sample of the (b1) resin composition layer for forming the opposite insulating layer without a fibrous substrate is the same as the range of the linear thermal expansion coefficient of the opposite insulating layer without a fibrous substrate. For example, it is preferable that the range of the linear thermal expansion coefficient in the high-temperature measurement range of the cured sample of the (b1) resin composition layer for forming the opposite insulating layer without a fibrous substrate is the same as the range of the linear thermal expansion coefficient CTE(ROh) in the high-temperature measurement range of the opposite insulating layer without a fibrous substrate. Also, for example, it is preferable that the range of the linear thermal expansion coefficient in the low-temperature measurement range of the cured sample of the (b1) resin composition layer for forming the opposite insulating layer without a fibrous substrate is the same as the range of the linear thermal expansion coefficient CTE(ROl) in the low-temperature measurement range of the opposite insulating layer without a fibrous substrate.

[0214] Furthermore, it is preferable that the range of the linear thermal expansion coefficient of the cured sample of the (b1) resin composition layer for forming the chip-side insulating layer without a fiber substrate is the same as the range of the linear thermal expansion coefficient of the chip-side insulating layer without a fiber substrate. Therefore, for example, it is preferable that the range of the linear thermal expansion coefficient in the high-temperature measurement range of the cured sample of the (b1) resin composition layer for forming the chip-side insulating layer without a fiber substrate is the same as the range of the linear thermal expansion coefficient CTE(RCh) in the high-temperature measurement range of the chip-side insulating layer without a fiber substrate. Furthermore, for example, it is preferable that the range of the linear thermal expansion coefficient in the low-temperature measurement range of the cured sample of the (b1) resin composition layer for forming the chip-side insulating layer without a fiber substrate is the same as the range of the linear thermal expansion coefficient CTE(RCl) in the low-temperature measurement range of the chip-side insulating layer without a fiber substrate.

[0215] Furthermore, it is preferable that the range of the difference between the linear thermal expansion coefficient of the cured sample of the (b1) resin composition layer for forming the opposite side insulating layer without a fiber substrate and the linear thermal expansion coefficient of the cured sample of the (b1) resin composition layer for forming the chip side insulating layer without a fiber substrate is the same as the range of the difference between the linear thermal expansion coefficient of the opposite side insulating layer without a fiber substrate and the linear thermal expansion coefficient of the chip side insulating layer without a fiber substrate. Therefore, for example, it is preferable that the range of the absolute value of the difference between the linear thermal expansion coefficient in the high-temperature measurement range of the cured sample of the (b1) resin composition layer for forming the opposite side insulating layer without a fiber substrate and the linear thermal expansion coefficient in the high-temperature measurement range of the cured sample of the (b1) resin composition layer for forming the chip side insulating layer without a fiber substrate is the same as the range of the absolute value |CTE(ROh)-CTE(RCh)| of the difference between the linear thermal expansion coefficient CTE(ROh) in the high-temperature measurement range of the opposite side insulating layer without a fiber substrate and the linear thermal expansion coefficient CTE(RCh) in the high-temperature measurement range of the chip side insulating layer without a fiber substrate. Furthermore, for example, the range of the absolute value of the difference between the linear thermal expansion coefficient in the low-temperature measurement range of a cured sample of the (b1) resin composition layer for forming the opposite side insulating layer without a fiber substrate and the linear thermal expansion coefficient in the low-temperature measurement range of a cured sample of the (b1) resin composition layer for forming the chip side insulating layer without a fiber substrate is preferably the same as the range of the absolute value |CTE(ROl)-CTE(RCl)| of the difference "CTE(ROl)-CTE(RCl)" between the linear thermal expansion coefficient CTE(ROl) in the low-temperature measurement range of the opposite side insulating layer without a fiber substrate and the linear thermal expansion coefficient CTE(RCl) in the low-temperature measurement range of the chip side insulating layer without a fiber substrate.

[0216] When a resin composition layer (b1) having such a linear thermal expansion coefficient is used to obtain a cured sample, warping after mounting of the semiconductor chip can be effectively suppressed.

[0217] (b1) The linear thermal expansion coefficient of the cured resin composition layer can be measured by the same method as the method for measuring the linear thermal expansion coefficient of the opposite insulating layer containing the fiber substrate.

[0218] As described above, when a Tg measurement test is performed to measure the glass transition temperature of a cured sample of the (b1) resin composition layer, the cured sample may have the same glass transition temperature as the insulating layer formed using the (b1) resin composition layer. Therefore, it is preferable that the range of glass transition temperatures of a cured sample of the (b1) resin composition layer for forming the opposite insulating layer without a fiber substrate is the same as the range of glass transition temperatures of the opposite insulating layer without a fiber substrate. Furthermore, it is preferable that the range of glass transition temperatures of a cured sample of the (b1) resin composition layer for forming the chip-side insulating layer without a fiber substrate is the same as the range of glass transition temperatures of the chip-side insulating layer without a fiber substrate. Moreover, it is preferable that the range of absolute values ​​of the difference between the glass transition temperature of a cured sample of the (b1) resin composition layer for forming the opposite insulating layer without a fiber substrate and the glass transition temperature of a cured sample of the (b1) resin composition layer for forming the chip-side insulating layer without a fiber substrate is the same as the range of absolute values ​​of the difference between the glass transition temperature of the opposite insulating layer without a fiber substrate and the glass transition temperature of the chip-side insulating layer without a fiber substrate. When a resin composition layer (b1) is used to obtain a cured sample having such a glass transition temperature, warping after mounting of the semiconductor chip can be effectively suppressed.

[0219] (b1) The glass transition temperature of the cured resin composition layer can be measured by the same method as the method for measuring the glass transition temperature of the opposite insulating layer containing the fiber substrate.

[0220] As described above, when an elastic modulus measurement test is performed to measure the tensile modulus of a cured sample of the (b1) resin composition layer, the cured sample may have the same tensile modulus as the insulating layer formed using the (b1) resin composition layer.

[0221] Therefore, it is preferable that the range of the tensile modulus of the cured sample of the (b1) resin composition layer for forming the opposite insulating layer without a fibrous substrate is the same as the range of the tensile modulus of the opposite insulating layer without a fibrous substrate. For example, it is preferable that the range of the tensile modulus at 260°C of the cured sample of the (b1) resin composition layer for forming the opposite insulating layer without a fibrous substrate is the same as the range of the tensile modulus E(ROh) at 260°C of the opposite insulating layer without a fibrous substrate. Also, for example, it is preferable that the range of the tensile modulus at 23°C of the cured sample of the (b1) resin composition layer for forming the opposite insulating layer without a fibrous substrate is the same as the range of the tensile modulus E(ROl) at 23°C of the opposite insulating layer without a fibrous substrate.

[0222] Furthermore, it is preferable that the range of the tensile modulus of the cured sample of the (b1) resin composition layer for forming the chip-side insulating layer without a fiber substrate is the same as the range of the tensile modulus of the chip-side insulating layer without a fiber substrate. Therefore, for example, it is preferable that the range of the tensile modulus at 260°C of the cured sample of the (b1) resin composition layer for forming the chip-side insulating layer without a fiber substrate is the same as the range of the tensile modulus E(RCh) at 260°C of the chip-side insulating layer without a fiber substrate. Also, for example, it is preferable that the range of the tensile modulus at 23°C of the cured sample of the (b1) resin composition layer for forming the chip-side insulating layer without a fiber substrate is the same as the range of the tensile modulus E(RCl) at 23°C of the chip-side insulating layer without a fiber substrate.

[0223] Furthermore, it is preferable that the range of the difference between the tensile modulus of the cured sample of the (b1) resin composition layer for forming the opposite side insulating layer without a fiber substrate and the tensile modulus of the cured sample of the (b1) resin composition layer for forming the chip side insulating layer without a fiber substrate is the same as the range of the difference between the tensile modulus of the opposite side insulating layer without a fiber substrate and the tensile modulus of the chip side insulating layer without a fiber substrate. Therefore, for example, it is preferable that the range of the absolute value of the difference between the tensile modulus at 260°C of the cured sample of the (b1) resin composition layer for forming the opposite side insulating layer without a fiber substrate and the tensile modulus at 260°C of the cured sample of the (b1) resin composition layer for forming the chip side insulating layer without a fiber substrate is the same as the range of the absolute value |E(ROh)-E(RCh)| of the difference "E(ROh)-E(RCh)" between the tensile modulus E(ROh) of the opposite side insulating layer without a fiber substrate and the tensile modulus E(RCh) of the chip side insulating layer without a fiber substrate at 260°C. Furthermore, for example, the range of the absolute value of the difference between the tensile modulus at 23°C of a cured sample of the (b1) resin composition layer for forming the opposite side insulating layer without a fiber substrate and the tensile modulus at 23°C of a cured sample of the (b1) resin composition layer for forming the chip side insulating layer without a fiber substrate is preferably the same as the range of the absolute value |E(ROl)-E(RCl)| of the difference "E(ROl)-E(RCl)" between the tensile modulus E(ROl) at 23°C of the opposite side insulating layer without a fiber substrate and the tensile modulus E(RCl) at 23°C of the chip side insulating layer without a fiber substrate.

[0224] When a resin composition layer (b1) is used to obtain a cured sample having such a tensile modulus, warping after mounting of the semiconductor chip can be effectively suppressed.

[0225] (b1) The tensile modulus of the cured resin composition layer can be measured by the same method as the method for measuring the tensile modulus of the opposite insulating layer containing the fibrous substrate.

[0226] (b1) The range of thickness of the resin composition layer may be the same as the range of thickness per layer of the insulating layer formed using the (b1) resin composition layer.

[0227] From the viewpoint of improving handling, it is preferable that the (b1) resin composition layer be provided on the (b) resin sheet. In this case, the (b) resin sheet comprises a (b2) support and the (b1) resin composition layer formed on the (b2) support. The (b2) support may be the same as the support (a2) of the (a) insulating multilayer sheet.

[0228] (b) The resin sheet may be further provided with any elements in combination with the (b1) resin composition layer and the (b2) support. For example, the (b) resin sheet may be provided with a (b3) protective film layer that protects the (b1) resin composition layer. The (b3) protective film layer is usually provided on the side of the (b1) resin composition layer that is not bonded to the (b2) support (i.e., the side opposite to the (b2) support). The (a3) ​​protective film layer may be the same as the (a3) ​​protective film layer that can be provided by the (a) insulating multilayer sheet. Generally, if the (b) resin sheet is provided with a (b3) protective film layer, the (b) resin sheet becomes usable by peeling off the (b3) protective film layer.

[0229] (b) The resin sheet can be manufactured, for example, by a method that includes forming a layer of the (b1) resin composition on a support (b2). Specifically, the (b1) resin composition layer may be formed by directly applying a liquid third resin composition onto the support (b2). Alternatively, for example, a liquid resin varnish may be prepared by mixing a solvent with the third resin composition, applied to the support (b2), and then dried as necessary to form the (b1) resin composition layer. As the solvent, for example, one similar to the solvent (F) that may be included in the resin composition may be used.

[0230] Coating can be performed using a coating device such as a die coater. Drying can be carried out by drying methods such as heating or hot air blowing. The drying conditions are not particularly limited, but the solvent content in the (b1) resin composition layer is usually 10% by mass or less, preferably 5% by mass or less. This may vary depending on the boiling point of the solvent, but for example, when using a resin varnish containing 30% to 60% by mass of solvent, the (b1) resin composition layer can be formed by drying at 50°C to 150°C for 3 to 10 minutes.

[0231] A method for forming an insulating layer using a (b1) resin composition layer includes laminating the (b1) resin composition layer. For example, the (b1) resin composition layer is formed directly on the core substrate by laminating so that the core substrate and the (b1) resin composition layer are joined together. Here, "directly" forming the (b1) resin composition layer on the core substrate means that there are no other layers between the core substrate and the (b1) resin composition layer. Alternatively, for example, the (b1) resin composition layer is formed on the core substrate via the insulating layer by laminating so that the (b1) resin composition layer is joined to an insulating layer already formed on the core substrate.

[0232] (b1) The lamination of the resin composition layer is carried out by pressing the (b1) resin composition layer onto the core substrate. This lamination may be carried out using a (b) resin sheet equipped with a (b2) support. In this case, it is preferable to perform the lamination by pressing the (b) resin sheet from the (b2) support side. At this time, the heat-pressing member may be pressed directly onto the (b) resin sheet, but it is preferable to press via an elastic material such as heat-resistant rubber so that the (b1) resin composition layer can sufficiently follow the surface irregularities of the core substrate or insulating layer.

[0233] (b1) The lamination of the resin composition layer is preferably carried out by a lamination method. The lamination conditions for (b1) the resin composition layer may be the same as those for (a1) the fiber-reinforced sheet. Alternatively, the lamination of (b1) the resin composition layer may be carried out using a commercially available vacuum laminator.

[0234] (b1) A method for forming an insulating layer using a resin composition layer may include smoothing the (b1) resin composition layer under normal pressure (atmospheric pressure) after lamination of the (b1) resin composition layer. For example, the method for forming an insulating layer may include smoothing the (b1) resin composition layer by pressing it with a heat-sealing member. When using a (b) resin sheet equipped with a (b2) support, the (b1) resin composition layer can usually be smoothed by pressing the (b) resin sheet from the (b2) support side. The pressing conditions for the smoothing process may be the same as the lamination conditions for the lamination method described above. The smoothing process can be performed using a commercially available laminator. Lamination and smoothing may be performed continuously using the commercially available vacuum laminator described above.

[0235] (b1) A method for forming an insulating layer using a resin composition layer typically includes laminating (b) resin sheets and then curing the (b1) resin composition layer. By curing the (b1) resin composition layer, an insulating layer that does not contain a fibrous substrate can be formed.

[0236] (b1) The resin composition layer is usually cured by thermal curing. The thermal curing conditions for the (b1) resin composition layer may vary depending on the type of third resin composition contained in the (b1) resin composition layer. For example, the curing temperature and curing time range for the process of curing the (b1) resin composition layer may be the same as the curing temperature and curing time range for the process of curing the (a1) fiber-reinforced sheet.

[0237] (b1) A method for forming an insulating layer using a resin composition layer may include preheating the (b1) resin composition layer at a temperature lower than the curing temperature before the (b1) resin composition layer is heat-cured. The temperature and time range for preheating the (b1) resin composition layer may be the same as the temperature and time range for preheating the (a1) fiber-reinforced sheet. Preheating is usually performed after lamination of the (b) resin sheet. If a smoothing treatment is performed after lamination, preheating may usually be performed after the smoothing treatment.

[0238] (b2) When using a resin sheet provided with a support, the method for forming the insulating layer may include (b2) peeling the support after laminating the resin composition layer. (b2) The peeling of the support may be performed before curing the resin composition layer in (b1), or may be performed after curing the resin composition layer in (b1).

[0239] (Timing of forming the chip-side insulating layer and the opposite-side insulating layer) The step of forming the chip-side insulating layer and the step of forming the opposite-side insulating layer may be performed at different times, but it is preferable to perform them simultaneously. Specifically, by performing the step of forming the chip-side insulating layer and the step of forming the opposite-side insulating layer simultaneously, it is preferable to form one layer of the opposite-side insulating layer simultaneously with forming one layer of the chip-side insulating layer. In this case, a lamination process such as lamination can be performed once, and a resin composition layer or a fiber-containing sheet can be simultaneously formed on the chip side surface and the opposite side surface of the core substrate. Also, a curing process can be performed once to simultaneously cure those resin composition layers or fiber-containing sheets. Therefore, there is no need to separately perform the lamination process and the curing process for forming the insulating layer included in the chip-side build-up layer and the lamination process and the curing process for forming the insulating layer included in the opposite-side build-up layer, so the number of steps can be reduced and the manufacturing method of the structure can be simplified. Also, since the chip-side insulating layer and the opposite-side insulating layer can be formed simultaneously, the balance between the stress acting on the chip side surface of the core layer and the stress acting on the opposite side surface can be achieved, and thus, the warpage of the intermediate product obtained in the manufacturing process of the structure can be suppressed.

[0240] (Formation of holes) The method for manufacturing a structure according to this embodiment may include a step of forming holes such as via holes and through holes in the insulating layer after forming the insulating layer. Examples of the method for forming holes include, for example, a drilling method, a laser processing method, a plasma processing method, etc. Among them, the laser processing method is preferable. When an insulating multilayer sheet provided with a support (a2) or a resin sheet provided with a support (b2) is used for forming the insulating layer, after peeling the support (a2) or the support (b2), the insulating layer may be irradiated with laser light to form holes, or before peeling, the insulating layer may be irradiated with laser light through the support (a2) or the support (b2) to form holes.

[0241] (Formation of conductor layer) The method for manufacturing a structure according to this embodiment may include a step of forming a conductor layer on the insulating layer after forming the insulating layer. When the method for manufacturing the structure includes a step of forming holes, the step of forming the conductor layer is usually preferably performed after the step of forming holes.

[0242] The conductor layer may be formed by plating. For example, by a conventionally known technique such as a semi-additive method or a full-additive method, plating is performed on the surface of the insulating layer to form a conductor layer having a desired wiring pattern. From the viewpoint of manufacturing simplicity, the semi-additive method is preferable. Hereinafter, an example of forming a conductor layer by the semi-additive method will be shown.

[0243] First, an electroless plating layer (plating seed layer) is formed on the surface of the insulating layer by electroless plating. Next, a mask pattern is formed on the formed electroless plating layer to expose a part of the electroless plating layer corresponding to the desired wiring pattern. After forming an electrolytic plating layer by electrolytic plating on the exposed electroless plating layer, the mask pattern is removed. Thereafter, the unnecessary electroless plating layer is removed by etching to form a conductor layer having a desired wiring pattern.

[0244] Conductor layers are generally formed to have a pattern shape corresponding to the design of the structure. Unless otherwise specified, the term "pattern shape" refers to the shape as viewed from the thickness direction. In this case, the pitch of the conductor layer formed on the outermost chip-side insulating layer (conductor layer 234 in the example shown in Figure 1) and the pitch of the conductor layer formed on the outermost opposite-side insulating layer (conductor layer 334 in the example shown in Figure 1) may be the same, the former may be larger, or the latter may be larger. Conductor layers formed on the outermost chip-side insulating layer are often formed with a relatively narrow pitch in order to connect to the terminals of the tiny semiconductor chip. Conductor layers formed on the outermost opposite-side insulating layer are often formed with a relatively large pitch in order to connect to the terminals of the wiring board on which the semiconductor chip package is mounted. Therefore, the pitch of the conductor layer formed on the outermost opposite-side insulating layer is usually larger than the pitch of the conductor layer formed on the outermost chip-side insulating layer.

[0245] (Other processes) The manufacturing method of the structure according to this embodiment may include any additional steps in combination with the steps described above. For example, the manufacturing method of the structure may include a step of roughening the insulating layer. The roughening treatment roughens the surface of the insulating layer, thereby improving the adhesion of the conductive layer formed on the surface by plating. In addition, smear (resin residue) may form in the holes when holes are formed, but this smear can be removed by the roughening treatment. The roughening treatment may be performed dry or wet. Specifically, the roughening treatment may be carried out by a method that includes applying swelling treatment with a swelling solution, oxidation treatment with an oxidizing agent, and neutralization treatment with a neutralizing solution to the insulating layer in this order. Typically, hole formation, roughening treatment, and conductive layer formation are carried out in this order.

[0246] Furthermore, the manufacturing method of the structure may include annealing the insulating layer after the conductive layer has been formed. Annealing can improve the adhesion between the insulating layer and the conductive layer. Annealing can be performed, for example, by heating at 150°C to 210°C for 20 to 180 minutes.

[0247] (Specific examples of manufacturing methods) A preferred example of a manufacturing method for the structure 10 shown in Figure 1 is described below. Figures 3 to 7 are schematic cross-sectional views illustrating the manufacturing process of one example of the structure 10. In this example of a manufacturing method for the structure 10, resin composition layers 241 and 341 are placed on the chip side surface 100U and the opposite side 100D of the core substrate 100 and laminated to obtain the intermediate product 20 shown in Figure 3. Subsequently, the resin composition layers 241 and 341 are cured to form a chip-side insulating layer 211 and an opposite-side insulating layer 311 that do not contain a fiber base material, as shown in Figure 4. Furthermore, holes 221 and 321 are formed in the chip-side insulating layer 211 and the opposite-side insulating layer 311, as shown in Figure 5, and conductor layers 231 and 331 are formed, as shown in Figure 6.

[0248] Subsequently, in the manufacturing method of the structure 10 according to this example, the lamination of resin composition layers, formation of an insulating layer by curing the resin composition layers, formation of holes, and formation of a conductor layer are repeated to obtain the intermediate product 30 shown in Figure 7. In this intermediate product 30, chip-side insulating layers 212 to 213 are formed on the chip side surface 100U of the core substrate 10 via the previously formed chip-side insulating layer 211. Also, opposite-side insulating layers 312 to 323 are formed on the opposite side 100D of the core substrate 10 via the previously formed opposite-side insulating layer 311. Holes 222 to 223 and 322 to 323 are formed within each insulating layer 212 to 213 and 312 to 313, and conductor layers 232 to 233 and 332 to 333 are formed on each insulating layer 212 to 213 and 312 to 313 and within the holes 222 to 223 and 322 to 323.

[0249] Furthermore, in the manufacturing method of the structure 10 according to this example, a resin composition layer (not shown) is placed on the chip-side insulating layer 213 formed on the chip side surface 100U, and a fiber-reinforced sheet (not shown) is placed on the opposite side insulating layer 313 formed on the opposite side surface 100D. Then, lamination is performed to form the resin composition layer on the chip side surface 100U via the chip-side insulating layers 211-213, and the fiber-reinforced sheet on the opposite side 100D via the opposite side insulating layers 311-313. After that, the resin composition layer and the fiber-reinforced sheet are cured to form the chip-side insulating layer 214 without a fiber base material and the opposite side insulating layer 314 including an insulating layer. Then, holes 224 and 324 are formed, and further conductive layers 234 and 334 are formed to form the chip-side build-up layer 200 and the opposite side build-up layer 300 as shown in Figure 1. Thus, the structure 10 can be obtained.

[0250] As described above, the manufacturing method of the structure according to this embodiment includes a step (ii) of forming an opposite-side insulating layer on the opposite side of the core substrate, which includes a step of forming an opposite-side insulating layer including a fiber substrate. Furthermore, the manufacturing method of the structure according to this embodiment may include a step (i) of forming a chip-side insulating layer on the chip side surface of the core substrate, which includes a step of forming a chip-side insulating layer including a fiber substrate. In this case, the structure of the present invention described above can be manufactured by carrying out the multiple steps (i) and the multiple steps (ii) such that at least one of the following conditions (1) and (2) is satisfied. (1) The number of opposite-side insulating layers containing fiber substrate 400 in the opposite-side build-up layer 300 is greater than the number of chip-side insulating layers containing fiber substrate 400 in the chip-side build-up layer 200, and the "layer-based fiber substrate ratio" in the opposite-side build-up layer 300 is within the above-specified range. (2) The total thickness of the opposite side insulating layer, including the fibrous substrate 400 in the opposite side build-up layer 300, is greater than the total thickness of the chip side insulating layer, including the fibrous substrate 400 in the chip side build-up layer 200, and the "thickness-based fibrous substrate content ratio" in the opposite side build-up layer 300 is within the above-mentioned specific range.

[0251] From the viewpoint of easily satisfying at least one of the above conditions (1) and (2), in one embodiment, the ratio of the number of times the step of forming the opposite insulating layer including the fiber substrate (ii) is performed to the total number of times the step of forming the opposite insulating layer (ii) is performed is usually 5% or more, preferably 8% or more, more preferably 12% or more, preferably 80% or less, more preferably 65% ​​or less, and even more preferably 50% or less. Also, from the viewpoint of easily satisfying at least one of the above conditions (1) and (2), in one embodiment, the number of times the step of forming the opposite insulating layer including the fiber substrate (ii) is performed is greater than the number of times the step of forming the chip-side insulating layer including the fiber substrate (i) is performed.

[0252] <Semiconductor chip mounting> A semiconductor chip can be mounted on the chip-side build-up layer of the structure described above. A semiconductor chip package can be manufactured by a method that includes the step of mounting a semiconductor chip on the chip-side build-up layer of the structure in this way.

[0253] Figure 8 is a schematic cross-sectional view showing a semiconductor chip package 40 according to one embodiment of the present invention. As shown in Figure 8, the semiconductor chip package 40 comprises a structure 10 and a semiconductor chip 500 mounted on the chip side surface 10U, which is the surface of the chip-side build-up layer 200 of the structure 10. The semiconductor chip 500 is generally mounted by a reflow soldering method. Therefore, solder powder 510 may be provided between the semiconductor chip 500 and the structure 10. Typically, an electrical connection is achieved between the conductive layer of the structure 10 (not shown in Figure 8) and the semiconductor chip 500 via this solder powder 510. In addition, an underfill material 520 may be filled between the structure 10 and the semiconductor chip 500 as needed.

[0254] A mounting method for mounting a semiconductor chip 500 on the chip-side build-up layer 200 of a structure 10 typically involves placing the semiconductor chip 500 on the chip side surface 10U of the structure 10. In this case, the semiconductor chip 500 is placed on the chip side surface 10U of the structure 10 via solder powder 510. Hereinafter, the laminate comprising the structure 10 and the semiconductor chip 500 placed on its chip side surface 10U may be referred to as an "intermediate laminate".

[0255] Subsequently, the mounting method includes soldering by reflow soldering. In the reflow soldering process, the solder powder 510 is melted by heating, and the molten solder powder 510 is made to adhere closely to the structure 10 and the semiconductor chip 500. The reflow temperature is generally set to be above the melting point of the solder powder 510 and below the heat resistance temperature of the semiconductor chip 500, and its peak temperature is often set to around 260°C. Generally, the reflow soldering process is carried out in a reflow furnace with the intermediate laminate placed inside the furnace. Therefore, not only the solder powder 510, but also the structure 10 and the semiconductor chip 500 are heated to the aforementioned reflow temperature.

[0256] Subsequently, the mounting method includes cooling the heated structure 10, semiconductor chip 500, and solder powder 510 as described above. This cooling is carried out, for example, by removing the intermediate stack from the reflow oven and allowing it to cool. As the solder powder 510 solidifies due to the cooling, the structure 10 and the semiconductor chip 500 are joined via the solder powder 510. In this way, the semiconductor chip 500 is mounted on the chip side surface 10U of the structure 10, and a semiconductor chip package 40 is obtained.

[0257] In the implementation method described above, heating for reflow processing and subsequent cooling occur, which can cause expansion and contraction within the structure 10. This expansion and contraction will be explained below with reference to the drawings.

[0258] FIG. 9 is a cross-sectional view schematically showing an intermediate laminate 50 obtained in the process of a method for manufacturing a semiconductor chip package 40 according to an embodiment of the present invention. When the intermediate laminate 50 is heated in a reflow furnace, expansion stress occurs in the structure 10. Therefore, the chip-side build-up layer 200 including the chip-side insulating layers 211 to 214 tends to expand in its in-plane direction as indicated by arrow A1. The term "in-plane direction" refers to a direction perpendicular to the thickness direction unless otherwise specified. Also, the opposite-side build-up layer 300 including the opposite-side insulating layers 311 to 314 tends to expand in its in-plane direction as indicated by arrow A2.

[0259] FIG. 10 is a cross-sectional view schematically showing a semiconductor chip package 40 according to an embodiment of the present invention. In the semiconductor chip package 40 obtained by cooling the intermediate laminate 50, contraction stress occurs in the structure 10 due to the cooling. Therefore, the chip-side build-up layer 200 including the chip-side insulating layers 211 to 214 tends to contract in its in-plane direction as indicated by arrow A3. At this time, the semiconductor chip 500 is joined to the chip side surface 10U by solder powder 510. Also, usually, the semiconductor chip 500 has a small linear thermal expansion coefficient. Therefore, the contraction of the portion 250 of the chip-side build-up layer 200 covered by the semiconductor chip 500 is relatively small, and the expansion of the portion 260 of the chip-side build-up layer 200 not covered by the semiconductor chip 500 becomes relatively large. Also, the opposite-side build-up layer 300 including the opposite-side insulating layers 311 to 314 tends to contract in its in-plane direction as indicated by arrow A4. Usually, the entire opposite-side build-up layer 300 tends to contract equally.

[0260] Therefore, conventionally, there has been a tendency for a difference in the degree of contraction to occur between the chip-side build-up layer and the opposite-side build-up layer due to the influence of restraint by the semiconductor chip, and thus warpage of the structure was likely to occur after mounting the semiconductor chip. Also, this warpage tended to become larger when an underfill material 520 was filled between the structure 10 and the semiconductor chip 500.

[0261] In contrast, the structure 10 according to this embodiment, which includes an insulating layer (opposite-side insulating layer) 314 containing a fiber base material 400 as described above, can suppress warping of the structure 10 after mounting the semiconductor chip 500. Furthermore, the structure 10 according to this embodiment can suppress warping not only after mounting the semiconductor chip 500, but also before mounting the semiconductor chip on the structure 10.

[0262] Therefore, according to the structure 10 of this embodiment, warping of the structure 10 can be suppressed after the semiconductor chip 500 is mounted. Such an effect is beneficial in the actual manufacturing process of semiconductor chip packages 40.

[0263] If we assume that it is sufficient to suppress the warping of the structure only after the semiconductor chip has been mounted, then it might be conceivable to pre-warp the structure before mounting the semiconductor chip to a degree that can offset the warping. However, warping the structure before mounting the semiconductor chip in this way may reduce the handling properties of the structure or make precise alignment of the semiconductor chip difficult.

[0264] In contrast, the structure 10, which can suppress warping after mounting the semiconductor chip 500, improves the handling of the structure 10 before mounting the semiconductor chip 500 and facilitates the alignment of the semiconductor chip 500, while suppressing warping of the structure 10 after mounting the semiconductor chip 500. Therefore, it is possible to suppress warping of the semiconductor chip package 40. Consequently, smooth manufacturing of the semiconductor chip package 40 can be achieved.

[0265] From the viewpoint of suppressing warping after reflow processing, it is desirable to use an insulating layer containing a fiber substrate that has a linear thermal expansion coefficient and tensile modulus that satisfy the above-mentioned preferred requirements in the high-temperature environment during reflow processing. If the insulating layer containing a fiber substrate has a small linear thermal expansion coefficient in a high-temperature environment represented by the high-temperature measurement range, the generation of stress due to expansion and contraction can be suppressed. Furthermore, if the insulating layer containing a fiber substrate has a large tensile modulus in a high-temperature environment, such as 260°C, deformation of the structure can be suppressed against stress. Having both a small linear thermal expansion coefficient and a large tensile modulus in a high-temperature environment is generally difficult to achieve with insulating layers that do not contain a fiber substrate. In the above-described embodiment, by appropriately combining an insulating layer without a fiber substrate and an insulating layer containing a fiber substrate having different characteristics (specifically, linear thermal expansion coefficient and tensile modulus in a high-temperature environment) from the insulating layer without a fiber substrate, warping after mounting of the semiconductor chip 500 can be effectively suppressed.

[0266] As mentioned above, the stress during the reflow process affects the occurrence of warping. Therefore, if the insulating layer can absorb and reduce this stress, the warping of the structure 10 can be effectively reduced. Normally, if the insulating layer has a glass transition temperature lower than the reflow temperature, the insulating layer becomes flexible during the reflow process and can absorb stress, thus effectively reducing warping. From this viewpoint, it is preferable that the glass transition temperature of insulating layers, such as the chip-side insulating layer and the opposite-side insulating layer, be lower than the reflow temperature. More specifically, it is preferable that the glass transition temperature of the insulating layer be lower than the peak temperature of the reflow process. In one example, the range of the difference between the peak temperature of the reflow process and the glass transition temperature of the insulating layer (including both insulating layers containing a fiber substrate and insulating layers not containing a fiber substrate) is preferably 10°C or more, more preferably 20°C or more, even more preferably 30°C or more, preferably 160°C or less, more preferably 140°C or less, and even more preferably 120°C or less. Here, the term "glass transition temperature of the insulating layer" encompasses the glass transition temperatures of the chip-side insulating layer containing a fiber substrate, the chip-side insulating layer without a fiber substrate, the opposite-side insulating layer containing a fiber substrate, and the opposite-side insulating layer without a fiber substrate. From a similar viewpoint, it is preferable that the glass transition temperature of the cured sample of (a1) fiber-reinforced sheet for forming an insulating layer containing a fiber substrate, and the glass transition temperature of the cured sample of (b1) resin composition layer for forming an insulating layer without a fiber substrate, are lower than the peak temperature of the reflow process. Furthermore, it is preferable that the range of difference between the peak temperature of the reflow process and the glass transition temperatures of these cured samples is the same as the range of difference between the peak temperature of the reflow process and the glass transition temperature of the insulating layer as described above.

[0267] Furthermore, from the viewpoint of effectively suppressing warping, it is preferable that each insulating layer becomes flexible at a timing close to the heating period during reflow processing, and that each insulating layer hardens at a timing close to the cooling period after reflow processing. Therefore, it is preferable that the glass transition temperatures of each insulating layer are close, as described above.

[0268] As described above, the structure 10 according to this embodiment can suppress warping after mounting the semiconductor chip 500, thereby reducing the amount of warping. In one example, the range of warping of the structure 10 after mounting the semiconductor chip 500 is preferably 500 μm or less, more preferably 400 μm or less, even more preferably 300 μm or less, and particularly preferably 200 μm or less. The lower limit is ideally 0 μm, but may be 10 μm or more or 50 μm or more.

[0269] Furthermore, preferably, the structure 10 according to this embodiment can suppress warping before mounting the semiconductor chip 500, thereby reducing the amount of warping before reflow processing. In one example, the range of warping of the structure 10 at a temperature of 35°C before mounting the semiconductor chip 500 is preferably 1000 μm or less, more preferably 800 μm or less, even more preferably 600 μm or less, and particularly preferably 500 μm or less. The lower limit is ideally 0 μm, but may be 100 μm or more or 200 μm or more.

[0270] Furthermore, preferably, the structure 10 according to this embodiment can reduce the amount of warpage during reflow processing. In one example, the range of warpage of the structure 10 at a temperature of 260°C before mounting the semiconductor chip 500 is preferably 500 μm or less, more preferably 400 μm or less, even more preferably 300 μm or less, and particularly preferably 200 μm or less. The lower limit is ideally 0 μm, but may be 10 μm or more or 50 μm or more.

[0271] The amount of warpage of the structure 10 can be measured using a shadow moiré measuring device in accordance with the Japan Electronics and Information Technology Industries Association (JEITA) standard JEITA EDX-7311-24. The specific measurement method may be the one described in the embodiments below.

[0272] The semiconductor chip package 40 may further include any elements in combination with the structure 10 and the semiconductor chip 500. For example, the semiconductor chip package 40 may include a solder resist layer (not shown) that encapsulates the semiconductor chip 500. Therefore, the manufacturing method of the semiconductor chip package 40 may include a step of forming a solder resist layer in combination with the step of mounting the semiconductor chip 500 on the structure 10. Furthermore, the manufacturing method of the semiconductor chip package 40 may include a step of filling the space between the structure 10 and the semiconductor chip 500 with an underfill material 520.

[0273] Furthermore, although the above-described embodiment shows an example in which holes 221-224 and 321-324 are formed in the insulating layers 211-214 and 311-314, some or all of these holes 221-224 and 321-324 do not need to be formed. Also, although the above-described embodiment shows an example in which conductor layers 231-234 and 331-334 are formed, some or all of these conductor layers 231-234 and 331-334 do not need to be formed.

[0274] <Semiconductor device> The semiconductor chip packages described above can be used in the manufacture of semiconductor devices. A semiconductor device comprises the semiconductor chip packages described above. Typically, a semiconductor device comprises a wiring board and a semiconductor chip package mounted on this wiring board. Examples of semiconductor devices include various types of semiconductor devices used in electrical products (e.g., computers, mobile phones, smartphones, tablet devices, wearable devices, digital cameras, medical equipment, and televisions) and vehicles (e.g., motorcycles, automobiles, trains, ships, and aircraft).

[0275] A semiconductor device may be manufactured, for example, by a manufacturing method that includes the step of mounting the aforementioned semiconductor chip package onto a wiring board. Specifically, a semiconductor device may be manufactured by mounting a semiconductor chip package onto a suitable wiring board to obtain a mounting substrate, and then attaching this mounting substrate to other components constituting the semiconductor device.

[0276] <Resin composition> The following describes the resin composition used to form the insulating layer described above. The resin composition used to form the insulating layer can be one that can form the insulating layer described above upon curing. Generally, a thermosetting resin composition is used as the resin composition. The specific composition of this resin composition may be selected within a range that can form the insulating layer described above after curing. The following describes the composition of a preferred example of a resin composition.

[0277] Since the resin composition is thermosetting, it usually contains (A) a thermosetting resin. Examples of (A) thermosetting resins include epoxy resins, phenolic resins, activated ester resins, benzoxazine resins, cyanate ester resins, carbodiimide resins, acid anhydride resins, amine resins, and radical polymerizable resins. The thermosetting resin may be used alone or in combination of two or more types.

[0278] In particular, (A) the thermosetting resin preferably contains an epoxy resin. The epoxy resin may be a curable resin having epoxy groups. Examples of epoxy resins include bisphenol A type epoxy resin, bisphenol C type epoxy resin, bisphenol F type epoxy resin, bisphenol S type epoxy resin, bisphenol AF type epoxy resin, dicyclopentadiene type epoxy resin, trisphenol type epoxy resin, naphthol novolac type epoxy resin, phenol novolac type epoxy resin, tert-butyl-catechol type epoxy resin, naphthalene type epoxy resin, naphthol type epoxy resin, anthracene type epoxy resin, glycidylamine type epoxy resin, glycidyl ester type epoxy resin, cresol novolac type epoxy resin, phenol aralkyl type epoxy resin, biphenyl type epoxy resin, linear aliphatic epoxy resin, epoxy resin having a butadiene structure, alicyclic epoxy resin, heterocyclic epoxy resin, spiroring-containing epoxy resin, cyclohexane type epoxy resin, cyclohexanedimethanol type epoxy resin, naphthylene ether type epoxy resin, trimethylol type epoxy resin, tetraphenylethane type epoxy resin, isocyanurate type epoxy resin, and imide skeleton-containing bisphenol type epoxy resin. Biphenyl-type epoxy resins refer to epoxy resins having a biphenyl structure, where the biphenyl structure may have substituents such as alkyl groups, alkoxy groups, or aryl groups. Therefore, bixylenol-type epoxy resins and biphenylaralkyl-type epoxy resins can be included in the category of biphenyl-type epoxy resins. Epoxy resins may be used individually or in combination of two or more types.

[0279] From the viewpoint of obtaining a cured product with excellent heat resistance, it is preferable that the epoxy resin contains an aromatic structure. An aromatic structure is a chemical structure generally defined as aromatic, and includes polycyclic aromatics and aromatic heterocyclics. Examples of epoxy resins containing aromatic structures include bisphenol A type epoxy resin, bisphenol C type epoxy resin, bisphenol F type epoxy resin, bisphenol S type epoxy resin, bisphenol AF type epoxy resin, dicyclopentadiene type epoxy resin, trisphenol type epoxy resin, naphthol novolac type epoxy resin, phenol novolac type epoxy resin, tert-butyl-catechol type epoxy resin, naphthalene type epoxy resin, naphthol type epoxy resin, anthracene type epoxy resin, bisquilenol type epoxy resin, and glycidylamine having an aromatic structure. Examples include epoxy resins of the type bisphenol A, glycidyl ester type epoxy resins having an aromatic structure, cresol novolac type epoxy resins, biphenyl type epoxy resins, linear aliphatic epoxy resins having an aromatic structure, epoxy resins having a butadiene structure having an aromatic structure, alicyclic epoxy resins having an aromatic structure, heterocyclic epoxy resins, spiro ring-containing epoxy resins having an aromatic structure, cyclohexanedimethanol type epoxy resins having an aromatic structure, naphthylene ether type epoxy resins, trimethylol type epoxy resins having an aromatic structure, and tetraphenylethane type epoxy resins having an aromatic structure. Among these, bisphenol A type epoxy resins, naphthalene type epoxy resins, and biphenyl type epoxy resins are preferred.

[0280] The epoxy resin preferably contains an epoxy resin having two or more epoxy groups per molecule. The proportion of epoxy resin having two or more epoxy groups per molecule is preferably 50% by mass or more, more preferably 60% by mass or more, and even more preferably 70% by mass or more, relative to 100% by mass of the nonvolatile components of the epoxy resin.

[0281] Epoxy resins can be classified into two types: epoxy resins that are liquid at 20°C (hereinafter sometimes referred to as "liquid epoxy resins") and epoxy resins that are solid at 20°C (hereinafter sometimes referred to as "solid epoxy resins"). Epoxy resins may contain only liquid epoxy resins, only solid epoxy resins, or a combination of liquid and solid epoxy resins.

[0282] As the liquid epoxy resin, a liquid epoxy resin having two or more epoxy groups in one molecule is preferred. Preferred liquid epoxy resins include bisphenol A type epoxy resin, bisphenol C type epoxy resin, bisphenol F type epoxy resin, bisphenol AF type epoxy resin, naphthalene type epoxy resin, glycidyl ester type epoxy resin, glycidylamine type epoxy resin, phenol novolac type epoxy resin, alicyclic epoxy resin having an ester skeleton, cyclohexane type epoxy resin, cyclohexanedimethanol type epoxy resin, and epoxy resin having a butadiene structure; bisphenol A type epoxy resin is even more preferred.

[0283] Specific examples of liquid epoxy resins include DIC's "HP-4032," "HP-4032-D," and "HP-4032-SS" (naphthalene-type epoxy resin); Mitsubishi Chemical's "828US," "828EL," "jER828," "jER828EL," "825," and "Epicote 828EL" (bisphenol A-type epoxy resin); Mitsubishi Chemical's "jER807" and "1750" (bisphenol F-type epoxy resin); Mitsubishi Chemical's "jER152" (phenol novolac-type epoxy resin); Mitsubishi Chemical's "630," "630LSD," and "604" (glycidylamine-type epoxy resin); ADEKA's "ED-523T" (glycyrol-type epoxy resin); ADEKA's "EP-3950L" and "EP-3980S" (glycidylamine-type epoxy resin) Examples include: xylose resins; ADEKA's "EP-4088S" (dicyclopentadiene type epoxy resin); ADEKA's "ED-506" (polypropylene glycol type epoxy resin); Nippon Steel Chemical & Material's "ZX1059" (a mixture of bisphenol A type epoxy resin and bisphenol F type epoxy resin); Nagase ChemteX's "EX-721" (glycidyl ester type epoxy resin); Daicel's "Celoxide 2021P" (alicyclic epoxy resin with an ester skeleton); Daicel's "PB-3600", Nippon Soda's "JP-100" and "JP-200" (epoxy resins with a butadiene structure); and Nippon Steel Chemical & Material's "ZX1658" and "ZX1658GS" (liquid 1,4-glycidylcyclohexane type epoxy resin).

[0284] As the solid epoxy resin, a solid epoxy resin having three or more epoxy groups in one molecule is preferred, and an aromatic solid epoxy resin having three or more epoxy groups in one molecule is more preferred. As the solid epoxy resin, bixylenol type epoxy resin, naphthalene type epoxy resin, naphthalene type tetrafunctional epoxy resin, naphthol novolac type epoxy resin, cresol novolac type epoxy resin, dicyclopentadiene type epoxy resin, trisphenol type epoxy resin, naphthol type epoxy resin, biphenyl type epoxy resin, naphthylene ether type epoxy resin, anthracene type epoxy resin, bisphenol A type epoxy resin, bisphenol AF type epoxy resin, phenol aralkyl type epoxy resin, tetraphenylethane type epoxy resin, and imide skeleton-containing bisphenol type epoxy resin are preferred; biphenyl type epoxy resin and naphthalene type tetrafunctional epoxy resin are even more preferred.

[0285] Specific examples of solid epoxy resins include DIC's "HP4032H" (naphthalene-type epoxy resin); DIC's "HP-4700" and "HP-4710" (naphthalene-type tetrafunctional epoxy resins); DIC's "N-690" (cresol novolac-type epoxy resin); DIC's "N-695" (cresol novolac-type epoxy resin); DIC's "HP-7200", "HP-7200HH", "HP-7200H", and "HP-7200L" (dicyclopentadiene-type epoxy resins); DIC's "EXA-7311" and "EXA-73 11-G3", EXA-7311-G4, EXA-7311-G4S, HP-6000, HP-6000L (naphthylene ether type epoxy resin); Nippon Kayaku Co., Ltd.'s "EPPN-502H" (trisphenol type epoxy resin); Nippon Kayaku Co., Ltd.'s "NC7000L" (naphthol novolac type epoxy resin); Nippon Kayaku Co., Ltd.'s "NC3000H", "NC3000", "NC3000L", "NC3000FH", "NC3100" (biphenyl type epoxy resin); Nippon Steel Chemical & Material Co., Ltd.'s "ESN475V", "ESN4100" V, "ESN-4100VEK75" (naphthalene-type epoxy resin); "ESN485" (naphthol-type epoxy resin) manufactured by Nippon Steel Chemical & Material Co., Ltd.; "ESN375" (dihydroxynaphthalene-type epoxy resin) manufactured by Nippon Steel Chemical & Material Co., Ltd.; "YX4000H", "YX4000", "YX4000HK", "YL7890" (bixylenol-type epoxy resin) manufactured by Mitsubishi Chemical Corporation; "YL6121" (biphenyl-type epoxy resin) manufactured by Mitsubishi Chemical Corporation; "YX8800" (anthracene-type epoxy resin) manufactured by Mitsubishi Chemical Corporation; Mitsubishi Chemical Examples include "YX7700" (phenol aralkyl type epoxy resin) from the company; "PG-100" and "CG-500" from Osaka Gas Chemical Co., Ltd.; "YX7760" (bisphenol AF type epoxy resin) from Mitsubishi Chemical Corporation; "YL7800" (fluorene type epoxy resin) from Mitsubishi Chemical Corporation; "jER1010" (bisphenol A type epoxy resin) from Mitsubishi Chemical Corporation; "jER1031S" (tetraphenylethane type epoxy resin) from Mitsubishi Chemical Corporation; and "WHR991S" (imide skeleton-containing bisphenol type epoxy resin) from Nippon Kayaku Co., Ltd.

[0286] When liquid epoxy resin and solid epoxy resin are used in combination, their mass ratio (liquid epoxy resin:solid epoxy resin) is preferably 20:1 to 1:20, more preferably 10:1 to 1:10, and particularly preferably 7:1 to 1:7.

[0287] The epoxy equivalent range of the epoxy resin is preferably 50 g / eq. to 5,000 g / eq., more preferably 60 g / eq. to 3,000 g / eq., even more preferably 80 g / eq. to 2,000 g / eq., and particularly preferably 110 g / eq. to 1,000 g / eq. Epoxy equivalent represents the mass of resin per equivalent of epoxy groups. This epoxy equivalent can be measured according to JIS K7236.

[0288] The amount of epoxy resin is preferably 10% by mass or more, more preferably 20% by mass or more, even more preferably 30% by mass or more, even more preferably 40% by mass or more, preferably 80% by mass or less, more preferably 70% by mass or less, even more preferably 60% by mass or less, and even more preferably 50% by mass or less, based on 100% by mass of the resin components of the resin composition. Unless otherwise specified, the resin components of the resin composition refer to the components of the resin composition excluding (B) inorganic fillers in the non-volatile components of the resin composition. Also, unless otherwise specified, the non-volatile components of the resin composition refer to the components of the resin composition excluding (F) solvents in the resin composition.

[0289] (A) When the thermosetting resin contains an epoxy resin, it is preferable that the thermosetting resin contains a resin that can react with the epoxy resin to form a bond. The "resin that can react with the epoxy resin to form a bond" may be referred to as the "curing agent" below. Examples of curing agents include phenol resins, benzoxazine resins, cyanate ester resins, carbodiimide resins, acid anhydride resins, and amine resins. The curing agent may be used alone or in combination of two or more types. Among these, phenol resins and activated ester resins are preferred.

[0290] As the phenolic resin, a resin having one or more, preferably two or more, hydroxyl groups (phenolic hydroxyl groups) bonded to aromatic rings such as benzene rings and naphthalene rings per molecule can be used. From the viewpoint of heat resistance and water resistance, a phenolic resin having a novolac structure is preferred. Furthermore, from the viewpoint of adhesion, a nitrogen-containing phenolic resin is preferred, and a triazine skeleton-containing phenolic resin is more preferred. Among these, a triazine skeleton-containing phenol novolac resin is preferred from the viewpoint of highly satisfying heat resistance, water resistance, and adhesion.

[0291] Specific examples of phenolic resins include "MEH-7700", "MEH-7810", "MEH-7851", and "MEH-8000H" from Meiwa Kasei Co., Ltd.; "NHN", "CBN", and "GPH" from Nippon Kayaku Co., Ltd.; and "SN-170", "SN-180", "SN-190", "SN-475", "SN-485", "SN-495", "SN-495V", and "SN-3" from Nippon Steel Chemical & Material Co., Ltd. Examples include "75", "SN-395", "TD-2090", "TD-2090-60M", "LA-7052", "LA-7054", "LA-1356", "LA-3018", "LA-3018-50P", "LA-1356", "TD2090", "TD-2090-60M", and "GDP-6115L", "GDP-6115H", and "ELPC75" from Gun-ei Chemical Co., Ltd.

[0292] As the activated ester resin, a resin containing one or more, preferably two or more, activated ester groups per molecule can be used. The activated ester group refers to a group formed by an ester bond directly bonded to an aromatic ring. Here, the term "ester bond" in a broad sense may also include thioester bonds (-C(=O)-S-). From the viewpoint of improving heat resistance, ester bonds in the narrow sense (-C(=O)-O-) formed by carbonyloxy groups are preferred. Furthermore, this activated ester group includes not only ester bonds contained in the "aromatic carbon-C(=O)-O-aromatic carbon" structure, but also ester bonds contained in the "aliphatic carbon-C(=O)-O-aromatic carbon" structure, insofar as they can react with epoxy groups to form bonds. The term "aromatic carbon" refers to a carbon atom constituting an aromatic ring.

[0293] As the active ester resin, compounds having two or more highly reactive ester groups in one molecule are preferred, such as phenol ester compounds, thiophenol ester compounds, N-hydroxyamine ester compounds, and esters of heterocyclic hydroxy compounds.

[0294] The activated ester resin is preferably obtained by a condensation reaction between a carboxylic acid compound and / or a thiocarboxylic acid compound and a hydroxy compound and / or a thiol compound. Particularly from the viewpoint of improving heat resistance, activated ester resins obtained from a carboxylic acid compound and a hydroxy compound are preferred, and activated ester resins obtained from a carboxylic acid compound and a phenol compound and / or a naphthol compound are more preferred. Examples of carboxylic acid compounds include benzoic acid, acetic acid, succinic acid, maleic acid, itaconic acid, phthalic acid, isophthalic acid, terephthalic acid, and pyromellitic acid. Examples of phenol compounds or naphthol compounds include hydroquinone, resorcinol, bisphenol A, bisphenol F, bisphenol S, phenolphthalein, methylated bisphenol A, methylated bisphenol F, methylated bisphenol S, phenol, o-cresol, m-cresol, p-cresol, catechol, α-naphthol, β-naphthol, 1,5-dihydroxynaphthalene, 1,6-dihydroxynaphthalene, 2,6-dihydroxynaphthalene, dihydroxybenzophenone, trihydroxybenzophenone, tetrahydroxybenzophenone, phloroglucin, benzenetriol, dicyclopentadiene-type diphenol compounds, and phenol novolac. Here, "dicyclopentadiene-type diphenol compounds" refers to diphenol compounds obtained by the condensation of two molecules of phenol with one molecule of dicyclopentadiene.

[0295] Specifically, preferred active ester resins include dicyclopentadiene-type active ester resins, naphthalene-type active ester resins containing a naphthalene structure, active ester resins containing an acetylated phenol novolac, and active ester resins containing a benzoylated phenol novolac. As for dicyclopentadiene-type active ester resins, active ester resins containing a dicyclopentadiene-type diphenol structure are preferred.

[0296] Commercially available active ester resins include, for example, "EXB9451," "EXB9460," "EXB9460S," "HPC-8000L-65TM," "HPC-8000-65T," "EXB-8000H," and "EXB-8000L-65TM" (manufactured by DIC Corporation) as active ester resins containing a naphthalene structure, and "EXB-9416-70BK," "EXB-8100L-65T," "HPC-8150-62T," "EXB-8150L-65T," "EXB-8100L-65T," and "EXB-8" (DI Examples of phosphorus-containing active ester resins include "EXB9401" (manufactured by DIC Corporation), "DC808" (manufactured by Mitsubishi Chemical Corporation), "YLH1026", "YLH1030", "YLH1048" (manufactured by Mitsubishi Chemical Corporation), and "EXB-8500-65T" (manufactured by DIC Corporation), as well as active ester resins containing benzoyl compounds of phenol novolac. Examples of active ester resins containing styryl groups and naphthalene structures include "PC1300-02-65T" and "PC1300-02-65MA" (manufactured by Air Water Corporation).

[0297] The active group equivalent of the curing agent is preferably 50 g / eq. to 3,000 g / eq., more preferably 100 g / eq. to 1,000 g / eq., even more preferably 100 g / eq. to 500 g / eq., and particularly preferably 100 g / eq. to 300 g / eq. The active group equivalent represents the mass of resin per equivalent of active group. The active group of the curing agent refers to a group that can react with the epoxy group of the epoxy resin, such as phenolic hydroxyl groups and active ester groups.

[0298] The amount of curing agent is preferably 10% by mass or more, more preferably 20% by mass or more, even more preferably 30% by mass or more, even more preferably 40% by mass or more, preferably 80% by mass or less, more preferably 70% by mass or less, even more preferably 60% by mass or less, and even more preferably 50% by mass or less, based on 100% by mass of the resin component of the resin composition.

[0299] The number of active groups in the curing agent is preferably 0.01 or more, more preferably 0.1 or more, even more preferably 0.5 or more, preferably 3 or less, more preferably 2 or less, and even more preferably 1 or less, when the number of epoxy groups in the epoxy resin is set to 1. The "number of epoxy groups in the epoxy resin" of the resin composition refers to the sum of all values ​​obtained by dividing the mass of the nonvolatile components of the epoxy resin present in the resin composition by their epoxy equivalents. The "number of active groups in the curing agent" of the resin composition refers to the sum of all values ​​obtained by dividing the mass of the nonvolatile components of the curing agent present in the resin composition by their active group equivalents.

[0300] The weight-average molecular weight (Mw) range of (A) thermosetting resins such as epoxy resins and curing agents is preferably 100 to 5,000, more preferably 250 to 3,000, and even more preferably 400 to 1,500. The weight-average molecular weight can be measured as a polystyrene equivalent value by gel permeation chromatography (GPC).

[0301] (A) The range of the amount of thermosetting resin is preferably 10% by mass or more, preferably 12% by mass or more, more preferably 15% by mass or more, preferably 80% by mass or less, more preferably 70% by mass or less, and even more preferably 60% by mass or less, based on 100% by mass of the nonvolatile components of the resin composition.

[0302] In particular, the first and second resin compositions used to form an insulating layer including a fibrous substrate preferably contain a relatively large amount of (A) thermosetting resin. In one example of the first and second resin compositions, the range of the amount of (A) thermosetting resin per 100% by mass of the resin composition is preferably 15% by mass or more, more preferably 20% by mass or more, even more preferably 25% by mass or more, preferably 80% by mass or less, more preferably 70% by mass or less, and even more preferably 60% by mass or less.

[0303] On the other hand, the third resin composition used to form an insulating layer that does not contain a fibrous substrate preferably contains a relatively small amount of (A) thermosetting resin. In one example of a third resin composition, the range of the amount of (A) thermosetting resin per 100% by mass of the resin composition is preferably 10% by mass or more, preferably 12% by mass or more, more preferably 15% by mass or more, preferably 80% by mass or less, more preferably 70% by mass or less, and even more preferably 60% by mass or less.

[0304] The resin composition preferably contains (A) a thermosetting resin and further (B) an inorganic filler. (B) The inorganic filler is in the form of particles of an inorganic material. Therefore, (B) the inorganic filler is included in the resin composition in the form of particles and is usually included in the cured product of the resin composition while maintaining that particle state.

[0305] (B) Inorganic materials are typically inorganic compounds used to form the inorganic filler. (B) Examples of materials for the inorganic filler include silica, alumina, glass, cordierite, silicon oxide, barium sulfate, barium carbonate, talc, clay, mica powder, zinc oxide, hydrotalcite, boehmite, aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, magnesium oxide, boron nitride, aluminum nitride, manganese nitride, aluminum borate, strontium carbonate, strontium titanate, calcium titanate, magnesium titanate, bismuth titanate, titanium oxide, zirconium oxide, barium titanate, barium zirconate titanate, barium zirconate, calcium zirconate, zirconium phosphate, and zirconium tungstate phosphate. Among these, silica and alumina are preferred, and silica is particularly preferred. Therefore, (B) the inorganic filler preferably contains silica, and may contain only silica. Examples of silica include amorphous silica, fused silica, crystalline silica, synthetic silica, and hollow silica. Furthermore, spherical silica is preferred as the silica. Since the inorganic materials mentioned above generally have insulating properties, the inorganic filler (B) usually also has insulating properties. The inorganic filler (B) may be used alone or in combination of two or more types.

[0306] (B) Examples of commercially available inorganic fillers include "SP60-05" and "SP507-05" from Nippon Steel Chemical & Material Co., Ltd.; "YC100C", "YA050C", "YA050C-MJE", "YA010C", "SC2500SQ", "SO-C4", "SO-C2", and "SO-C1" from Admatex Co., Ltd.; "UFP-30", "DAW-03", and "FB-105FD" from Denka Co., Ltd.; "Silfil NSS-3N", "Silfil NSS-4N", and "Silfil NSS-5N" from Tokuyama Corporation; and "Cellspheres" and "MGH-005" from Taiheiyo Cement Corporation.

[0307] (B) The average particle size of the inorganic filler is preferably 0.01 μm or more, more preferably 0.05 μm or more, even more preferably 0.1 μm or more, preferably 10 μm or less, more preferably 5 μm or less, even more preferably 3 μm or less, and even more preferably 1 μm or less.

[0308] (B) The average particle size of the inorganic filler can be measured by the laser diffraction-scattering method based on Mie scattering theory. Specifically, the particle size distribution of the inorganic filler can be created on a volume basis using a laser diffraction-scattering particle size distribution analyzer, and the median diameter can be used as the average particle size. A sample can be prepared by weighing 100 mg of inorganic filler and 10 g of methyl ethyl ketone into a vial and dispersing them with ultrasound for 10 minutes. The sample can be measured using a laser diffraction-type particle size distribution analyzer with blue and red light source wavelengths, using a flow cell method to measure the volume-based particle size distribution of the inorganic filler, and the average particle size can be calculated as the median diameter from the obtained particle size distribution. An example of a laser diffraction-type particle size distribution analyzer is the "LA-960" manufactured by Horiba, Ltd.

[0309] (B) The specific surface area of ​​the inorganic filler is preferably 0.1 m². 2 / g or more, more preferably 0.5m 2 / g or more, more preferably 1m 2 / g or more, particularly preferably 3m2 It is 100m or more / g, preferably 100m 2 / g or less, more preferably 70m 2 / g or less, more preferably 50m 2 / g or less, particularly preferably 40m 2 (B) The specific surface area of ​​the inorganic filler can be measured by adsorbing nitrogen gas onto the sample surface using a specific surface area measuring device (Macsorb HM-1210, manufactured by Mountec Co., Ltd.) according to the BET method, and calculating the specific surface area using the BET multipoint method.

[0310] (B) The inorganic filler is preferably treated with a surface treatment agent from the viewpoint of improving moisture resistance and dispersibility. Examples of surface treatment agents include fluorine-containing silane coupling agents, aminosilane coupling agents, epoxysilane coupling agents, mercaptosilane coupling agents, silane coupling agents, alkoxysilanes, organosilazane compounds, titanate coupling agents, etc. One type of surface treatment agent may be used alone, or two or more types may be used in any combination.

[0311] Examples of commercially available surface treatment agents include "KBM403" (3-glycidoxypropyltrimethoxysilane), "KBM803" (3-mercaptopropyltrimethoxysilane), "KBE903" (3-aminopropyltriethoxysilane), "KBM573" (N-phenyl-3-aminopropyltrimethoxysilane), "SZ-31" (hexamethyldisilazane), "KBM103" (phenyltrimethoxysilane), "KBM-4803" (long-chain epoxy-type silane coupling agent), and "KBM-7103" (3,3,3-trifluoropropyltrimethoxysilane), all manufactured by Shin-Etsu Chemical Co., Ltd.

[0312] From the viewpoint of improving the dispersibility of the inorganic filler, the degree of surface treatment by the surface treatment agent is preferably within a specific range. Specifically, 100% by mass of the inorganic filler is preferably surface-treated with 0.2% to 5% by mass of the surface treatment agent, more preferably with 0.2% to 3% by mass of the surface treatment agent, and even more preferably with 0.3% to 2% by mass of the surface treatment agent.

[0313] The degree of surface treatment by a surface treatment agent can be evaluated by the amount of carbon per unit surface area of ​​the inorganic filler. From the viewpoint of improving the dispersibility of the inorganic filler, the amount of carbon per unit surface area of ​​the inorganic filler should be 0.02 mg / m². 2 The above is preferred, and 0.1 mg / m² 2 The above is more preferable, 0.2 mg / m² 2 The above is even more preferable. On the other hand, from the viewpoint of suppressing an increase in the melt viscosity of the resin composition, 1.0 mg / m² 2 The following is preferred: 0.8 mg / m² 2 The following is more preferable: 0.5 mg / m² 2 The following are even more preferable.

[0314] (B) The amount of carbon per unit surface area of ​​the inorganic filler can be measured after cleaning the inorganic filler with a solvent (e.g., methyl ethyl ketone (MEK)) following surface treatment. Specifically, a sufficient amount of MEK as the solvent is added to the inorganic filler that has been surface-treated with a surface treatment agent, and ultrasonic cleaning is performed at 25°C for 5 minutes. After removing the supernatant and drying the solids, the amount of carbon per unit surface area of ​​the inorganic filler can be measured using a carbon analyzer. As a carbon analyzer, a Horiba "EMIA-320V" or similar can be used.

[0315] (B) The amount of inorganic filler is preferably 10% by mass or more, preferably 20% by mass or more, more preferably 30% by mass or more, preferably 90% by mass or less, more preferably 80% by mass or less, and even more preferably 70% by mass or less, based on 100% by mass of the nonvolatile components of the resin composition.

[0316] In particular, the first and second resin compositions used to form an insulating layer containing a fibrous substrate preferably contain a relatively small amount of (B) inorganic filler. In one example of the first and second resin compositions, the range of the amount of (B) inorganic filler per 100% by mass of the resin composition is preferably 10% by mass or more, preferably 20% by mass or more, more preferably 30% by mass or more, preferably 80% by mass or less, more preferably 75% by mass or less, and even more preferably 70% by mass or less.

[0317] On the other hand, a third resin composition used to form an insulating layer that does not contain a fibrous substrate preferably contains a relatively large amount of (B) inorganic filler. In one example of a third resin composition, the amount of (B) inorganic filler per 100% by mass of the resin composition is preferably 20% by mass or more, more preferably 30% by mass or more, even more preferably 40% by mass or more, preferably 90% by mass or less, more preferably 85% by mass or less, and even more preferably 80% by mass or less.

[0318] The resin composition may contain (C) a curing accelerator. (C) The curing accelerator can act as a catalyst in the reaction of (A) the thermosetting resin to accelerate the curing of the resin composition. Examples of (C) curing accelerators include phosphorus-based curing accelerators, urea-based curing accelerators, guanidine-based curing accelerators, imidazole-based curing accelerators, metal-based curing accelerators, and amine-based curing accelerators. (C) The curing accelerator may be used alone or in combination of two or more types. Among these, imidazole-based curing accelerators and amine-based curing accelerators are preferred.

[0319] Examples of imidazole-based curing accelerators include 2-methylimidazole, 2-undecylimidazole, 2-heptadecylimidazole, 1,2-dimethylimidazole, 2-ethyl-4-methylimidazole, 1,2-dimethylimidazole, 2-ethyl-4-methylimidazole, 2-phenylimidazole, 2-phenyl-4-methylimidazole, 1-benzyl-2-methylimidazole, 1-benzyl-2- Phenylimidazole, 1-cyanoethyl-2-methylimidazole, 1-cyanoethyl-2-undecylimidazole, 1-cyanoethyl-2-ethyl-4-methylimidazole, 1-cyanoethyl-2-phenylimidazole, 1-cyanoethyl-2-undecylimidazolium trimellitate, 1-cyanoethyl-2-phenylimidazolium trimellitate, 2,4-diamino-6-[2'-methylimidazolyl -(1')]-ethyl-s-triazine, 2,4-diamino-6-[2'-undecylimidazolyl-(1')]-ethyl-s-triazine, 2,4-diamino-6-[2'-ethyl-4'-methylimidazolyl-(1')]-ethyl-s-triazine, 2,4-diamino-6-[2'-methylimidazolyl-(1')]-ethyl-s-triazine isocyanurate adduct, 2-phenylimidazole isocyanurate adduct Examples of imidazole compounds include 2-phenyl-4,5-dihydroxymethylimidazole, 2-phenyl-4-methyl-5-hydroxymethylimidazole, 2,3-dihydro-1H-pyrrolo[1,2-a]benzimidazole, 1-dodecyl-2-methyl-3-benzylimidazolium chloride, 2-methylimidazoline, and 2-phenylimidazoline, as well as adducts of imidazole compounds with epoxy resins. Examples of commercially available imidazole-based curing accelerators include "1B2PZ", "2E4MZ", "2MZA-PW", "2MZ-OK", "2MA-OK", "2MA-OK-PW", "2PHZ", "2PHZ-PW", "Cl1Z", "Cl1Z-CN", "Cl1Z-CNS", and "C11Z-A" from Shikoku Chemicals, Inc., and "P200-H50" from Mitsubishi Chemical Corporation.

[0320] Examples of amine-based curing accelerators include trialkylamines such as triethylamine and tributylamine, 4-dimethylaminopyridine, benzyldimethylamine, 2,4,6-tris(dimethylaminomethyl)phenol, and 1,8-diazabicyclo(5,4,0)-undecene. Commercially available amine-based curing accelerators may also be used, such as "MY-25" manufactured by Ajinomoto Fine Techno Co., Ltd.

[0321] (C) The amount of the curing accelerator is preferably 0.01% by mass or more, more preferably 0.05% by mass or more, preferably 2% by mass or less, more preferably 1% by mass or less, and even more preferably 0.5% by mass or less, based on 100% by mass of the resin component of the resin composition.

[0322] The resin composition may contain (D) polymer resin. (D) polymer resin does not include components (A) to (C) described above. (D) polymer resin is usually thermoplastic. In addition, (D) polymer resin is usually included in the resin composition in a compatible state with (A) thermosetting resin and is included in the cured product in that compatible state. (D) polymer resin may be used alone or in combination of two or more types.

[0323] (D) Polymer resins typically have a large molecular weight. Specifically, the weight-average molecular weight Mw of (D) polymer resins is preferably greater than 5,000, more preferably 8,000 or more, even more preferably 10,000 or more, even more preferably 20,000 or more, preferably 100,000 or less, more preferably 70,000 or less, even more preferably 60,000 or less, and even more preferably 50,000 or less. The weight-average molecular weight Mw of (D) polymer resins can be measured in polystyrene equivalent values ​​by gel permeation chromatography (GPC).

[0324] (D) Examples of polymer resins include phenoxy resin, polyimide resin, polyvinyl acetal resin, polystyrene resin, polyolefin resin, polybutadiene resin, polyamide-imide resin, polyethersulfone resin, polysulfone resin, polyetherimide resin, polyphenylene ether resin, polycarbonate resin, polyetheretherketone resin, polyester resin, etc. Among these, phenoxy resin and polyvinyl acetal resin are preferred.

[0325] Examples of phenoxy resins include phenoxy resins having one or more skeletons selected from the group consisting of bisphenol A skeleton, bisphenol F skeleton, bisphenol S skeleton, bisphenolacetophenone skeleton, novolac skeleton, biphenyl skeleton, fluorene skeleton, dicyclopentadiene skeleton, norbornene skeleton, naphthalene skeleton, anthracene skeleton, adamantane skeleton, terpene skeleton, and trimethylcyclohexane skeleton. The ends of the phenoxy resin may be any functional group such as a phenolic hydroxyl group or an epoxy group. Specific examples of phenoxy resins include "1256" and "4250" (both phenoxy resins containing the bisphenol A skeleton) manufactured by Mitsubishi Chemical Corporation; "YX8100" (phenoxy resin containing the bisphenol S skeleton) manufactured by Mitsubishi Chemical Corporation; "YX7800BH40" (phenoxy resin containing the fluorene skeleton) manufactured by Mitsubishi Chemical Corporation; and "YX6954" (phenoxy resin containing the bisphenolacetophenone skeleton) manufactured by Mitsubishi Chemical Corporation. Examples include: "FX280" and "FX293" manufactured by Nippon Steel Chemical & Material Co., Ltd.; "YL7500BH30", "YX6954BH30", "YX7553", "YX7553BH30", "YL7769BH30", "YL6794", "YL7213", "YL7290", "YL7482", "YL7891BH30", "YL7891T30", and "YL9142T30" manufactured by Mitsubishi Chemical Corporation; and others.

[0326] Examples of polyvinyl acetal resins include polyvinyl formal resin and polyvinyl butyral resin, with polyvinyl butyral resin being preferred. Specific examples of polyvinyl acetal resins include S-Rec BH series, BX series (e.g., BX-5Z), KS series (e.g., KS-1), BL series, BM series, etc., manufactured by Sekisui Chemical Co., Ltd.

[0327] (D) The range of the amount of polymer resin is preferably 0.1% by mass or more, more preferably 0.5% by mass or more, even more preferably 1% by mass or more, preferably 20% by mass or less, preferably 10% by mass or less, and more preferably 5% by mass or less, based on 100% by mass of the resin component of the resin composition.

[0328] The resin composition may further contain (E) any additives as optional components. (E) Any additives do not include those corresponding to components (A) to (D) described above. (E) Any additives include, for example, organometallic compounds such as organocopper compounds, organozinc compounds, and organocalt compounds; colorants such as phthalocyanine blue, phthalocyanine green, iodine green, diazo yellow, crystal violet, titanium dioxide, and carbon black; polymerization inhibitors such as hydroquinone, catechol, pyrogallol, and phenothiazine; leveling agents such as silicone-based leveling agents and acrylic polymer-based leveling agents; thickeners such as bentonite and montmorillonite; defoamers such as silicone-based defoamers, acrylic-based defoamers, fluorine-based defoamers, and vinyl resin-based defoamers; ultraviolet absorbers such as benzotriazole-based ultraviolet absorbers; adhesion improvers such as urea silane; triazole-based adhesion improvers, tetrazole-based adhesion improvers, and triazine-based adhesion improvers Examples of additives include adhesion-improving agents such as additives; antioxidants such as hindered phenol antioxidants; fluorescent whitening agents such as stilbene derivatives; surfactants such as fluorine-based surfactants and silicone-based surfactants; flame retardants such as phosphorus-based flame retardants (e.g., phosphate ester compounds, phosphazene compounds, phosphinic acid compounds, red phosphorus), nitrogen-based flame retardants (e.g., melamine sulfate), halogen-based flame retardants, and inorganic flame retardants (e.g., antimony trioxide); dispersants such as phosphate ester dispersants, polyoxyalkylene dispersants, acetylene dispersants, silicone dispersants, anionic dispersants, and cationic dispersants; and stabilizers such as borate-based stabilizers, titanate-based stabilizers, aluminate-based stabilizers, zirconate-based stabilizers, isocyanate-based stabilizers, carboxylic acid-based stabilizers, and carboxylic acid anhydride-based stabilizers. (E) Any additive may be used individually or in combination of two or more types.

[0329] The resin composition may further contain a solvent (F) as an optional volatile component in combination with the non-volatile components such as components (A) to (E) described above. Typically, an organic solvent is used as the solvent (F). Examples of organic solvents include: ketone solvents such as acetone, methyl ethyl ketone, methyl isobutyl ketone, and cyclohexanone; ester solvents such as methyl acetate, ethyl acetate, butyl acetate, isobutyl acetate, isoamyl acetate, methyl propionate, ethyl propionate, and γ-butyrolactone; ether solvents such as tetrahydropyran, tetrahydrofuran, 1,4-dioxane, diethyl ether, diisopropyl ether, dibutyl ether, diphenyl ether, and anisole; alcohol solvents such as methanol, ethanol, propanol, butanol, and ethylene glycol; and 2-ethoxyethyl acetate, propylene glycol monomethyl ether acetate, diethylene glycol monoethyl ether acetate, ethyl diglycol acetate, γ-butyrolactone, and methyl methoxypropionate. Examples include ether ester solvents such as tyl; ester alcohol solvents such as methyl lactate, ethyl lactate, and methyl 2-hydroxyisobutyrate; ether alcohol solvents such as 2-methoxypropanol, 2-methoxyethanol, 2-ethoxyethanol, propylene glycol monomethyl ether, and diethylene glycol monobutyl ether (butyl carbitol); amide solvents such as N,N-dimethylformamide, N,N-dimethylacetamide, and N-methyl-2-pyrrolidone; sulfoxide solvents such as dimethyl sulfoxide; nitrile solvents such as acetonitrile and propionitrile; aliphatic hydrocarbon solvents such as hexane, cyclopentane, cyclohexane, and methylcyclohexane; and aromatic hydrocarbon solvents such as benzene, toluene, xylene, ethylbenzene, and trimethylbenzene. (F) A single solvent may be used alone, or two or more may be used in combination.

[0330] (F) The amount of solvent may be, for example, 60% by mass or less, 40% by mass or less, 30% by mass or less, 20% by mass or less, 15% by mass or less, 10% by mass or less, or 5% by mass or less, based on 100% by mass of all components of the resin composition, and may also be 0% by mass.

[0331] A resin composition can be manufactured, for example, by mixing components that may be included in the resin composition. The above-mentioned components may be mixed some or all at the same time, or sequentially. The temperature may be set appropriately during the mixing of each component, and thus heating and / or cooling may be performed temporarily or throughout the process. Furthermore, stirring or shaking may be performed during the mixing of each component. [Examples]

[0332] The present invention will be specifically described below with reference to examples. However, the present invention is not limited to these examples. In the following explanation, "parts" and "%" refer to "parts by mass" and "% by mass," respectively, unless otherwise specified. Unless otherwise specified, the temperature and pressure conditions were room temperature (23°C) and atmospheric pressure (1 atm).

[0333] <Manufacturing Example 1: Manufacturing of Insulating Multilayer Sheet 1> (Manufacturing of resin varnish 1) A polyvinyl butyral resin (KS-1, manufactured by Sekisui Chemical Co., Ltd.) was dissolved in a solvent prepared by mixing ethanol and toluene in a 1:1 (mass ratio) ratio at 60°C to obtain a polyvinyl butyral resin solution with a solid content of 15%.

[0334] 28 parts of liquid bisphenol A type epoxy resin (epoxy equivalent 180 g / eq., "Epicote 828EL" manufactured by Japan Epoxy Resin Co., Ltd.) and 28 parts of naphthalene type tetrafunctional epoxy resin (epoxy equivalent 163 g / eq., "HP4700" manufactured by Dainippon Ink and Chemicals, Inc.) were heated and dissolved while stirring in a mixed solvent consisting of 15 parts of methyl ethyl ketone (hereinafter abbreviated as "MEK") and 15 parts of cyclohexanone. To this, 110 parts of phenolic resin (naphthol-based curing agent, phenolic hydroxyl group equivalent 215 g / eq., "SN-485" manufactured by Toto Chemical Co., Ltd., MEK solution with 50% solids), 0.1 parts of curing accelerator ("2E4MZ" manufactured by Shikoku Chemicals Co., Ltd.), 70 parts of spherical silica (average particle size 0.5 μm, "SO-C2" manufactured by Admatex Co., Ltd.), and 30 parts of the aforementioned polyvinyl butyral resin solution were mixed and uniformly dispersed in a high-speed rotary mixer to produce resin varnish 1 as a liquid resin composition.

[0335] (Manufacturing of cured sheets with a primer-cured layer) A PET film (38 μm thick) having a surface treated with an alkyd-based release agent was prepared. The resin varnish 1 was uniformly applied to the release-treated surface of this PET film using a die coater and dried at 80°C to 120°C (average 100°C) for 3 minutes to form a 3 μm thick thermosetting resin composition layer. Subsequently, this thermosetting resin composition layer was heat-cured at 150°C for 15 minutes to obtain a cured sheet comprising a PET film and a primer-cured layer.

[0336] (Manufacturing of prepreg layer) Resin varnish 1 is applied to a fiber base material (Arisawa Seisakusho Co., Ltd.'s glass cloth "1015NS", warp density 95 threads / 25mm, weft density 95 threads / 25mm, fabric weight 17.5g / m). 2 The material was impregnated with a 15 μm thick resin varnish and dried until the residual solvent content in the resin varnish was 0.6%, obtaining a 32 μm thick prepreg layer. A 15 μm thick polypropylene film was laminated to one side of this prepreg layer, and a 38 μm thick PET film was laminated to the other side.

[0337] (Formation of fiber-reinforced sheet 1 containing a fiber base material) The polypropylene film laminated to one side of the prepreg layer was peeled off to expose the prepreg layer. This prepreg layer was placed on the surface of the primer-cured layer of the cured sheet and laminated using a vacuum pressure laminator (manufactured by Meiki Seisakusho Co., Ltd.). This lamination was performed by vacuum suction at 120°C for 30 seconds, followed by lamination at 120°C and a pressure of 7.0 kg / cm². 2 The test was performed by pressing a heat-resistant rubber through a PET film for 30 seconds under the specified conditions. Subsequently, under atmospheric pressure, a SUS end plate was used at a temperature of 120°C and a pressure of 5 kg / cm². 2 The prepreg layer and the primer-cured layer were smoothed by pressing for 60 seconds under the specified conditions. Through these operations, a fiber-reinforced sheet 1 comprising a prepreg layer and a primer-cured layer was formed, and an insulating multilayer sheet 1 having a layer structure of "PET film / fiber-reinforced sheet 1 / PET film" was obtained.

[0338] <Manufacturing Example 2: Manufacturing of Resin Sheet 2> (Manufacturing of resin varnish 2) Fifteen parts of liquid bisphenol A type epoxy resin (epoxy equivalent 180 g / eq., Mitsubishi Chemical Corporation "828US") and fifteen parts of biphenyl type epoxy resin (epoxy equivalent 291 g / eq., Nippon Kayaku Co., Ltd. "NC3000H") were heated and dissolved with stirring in fifteen parts of methyl ethyl ketone (hereinafter abbreviated as "MEK") and fifteen parts of cyclohexanone to obtain a solution. To this solution, forty-three parts of naphthalene type active ester compound (active ester group equivalent 272 g / eq., DIC Corporation "HPC8000-65T", toluene solution with 65% solids), 0.15 parts of curing accelerator (Koei Chemical Industry Co., Ltd., 4-dimethylaminopyridine), and spherical silica (average particle size 0.5 μm, specific surface area 5.8 m²) were added. 2 100 parts of Admatex's "SO-C2" (0.18% carbon content per unit mass), surface-treated with phenylaminosilane, and 15 parts of phenoxy resin (Mitsubishi Chemical's "YL6954BH30", MEK solution with 30% solids content, weight-average molecular weight 40000) were mixed and uniformly dispersed in a high-speed rotary mixer to produce resin varnish 2 as a liquid resin composition.

[0339] (Manufacturing of resin sheet 2) A PET film (38 μm thick) having a surface treated with an alkyd-based release agent was prepared. The resin varnish 2 was uniformly applied to the release-treated surface of this PET film using a die coater and dried at 80°C to 110°C (average 95°C) for 3 minutes to form a resin composition layer 2 with a thickness of 35 μm. Through the above operations, a resin sheet 2 having a layer structure of "PET film / resin composition layer 2" was obtained.

[0340] <Measurement test of the minimum melt viscosity of the prepreg layer of the insulating multilayer sheet 1 and the resin composition layer 2 of the resin sheet 2> The PET films on both sides were peeled off from the insulating multilayer sheet 1 manufactured in Manufacturing Example 1, and the primer-cured layer was further peeled off to obtain a prepreg layer. In addition, the PET film was peeled off from the resin sheet 2 manufactured in Manufacturing Example 2 to obtain a resin composition layer 2. The minimum melt viscosity of the prepreg layer and the resin composition layer 2 were measured using the measurement method described below.

[0341] (Method for measuring minimum melt viscosity) The melt viscosity of the sample (prepreg layer or resin composition layer 2) was measured using a dynamic viscoelasticity analyzer (UBM "Rheosol-G3000"). For 1 g of sample, the temperature was increased from a starting temperature of 60°C to 200°C at a heating rate of 5°C / min using an 18 mm diameter parallel plate. The dynamic viscoelasticity was measured under measurement conditions of a temperature interval of 2.5°C, vibration of 1 Hz, and strain of 1 deg, and the lowest melt viscosity (poise) in the temperature range from 100°C to 140°C was confirmed. In addition, the temperature at which the lowest melt viscosity value was observed within the entire measurement range was identified from the melt viscosity measurement results.

[0342] <Measurement test of the linear thermal expansion coefficient CTE of a cured sample 1 of the fiber-reinforced sheet 1 of the insulating multilayer sheet 1, and a cured sample 2 of the resin composition layer 2 of the resin sheet 2> The insulating multilayer sheet 1 manufactured in Manufacturing Example 1 was heated at 200°C for 90 minutes to cure the fiber-reinforced sheet 1, and the PET films on both sides were peeled off to obtain cured sample 1. Similarly, the resin sheet 2 manufactured in Manufacturing Example 2 was heated at 200°C for 90 minutes to cure the resin composition layer 2, and the PET film was peeled off to obtain cured sample 2. The linear thermal expansion coefficient CTE of cured samples 1 and 2 were measured using the measurement method described below.

[0343] (Method for measuring the coefficient of linear thermal expansion) The sample (hardened sample 1 or 2) was cut into test pieces approximately 5 mm wide and 15 mm long, and measured using a thermomechanical analyzer (TMA, Hitachi High-Tech Science, TMA / SS7100) in "tensile mode" with a load of 1 N. Two measurements were performed. The first measurement was performed in the range of 25°C to 200°C with a heating rate of 5°C / min. The second measurement was performed in the range of 25°C to 260°C with a heating rate of 5°C / min. From the results of the second measurement, the linear thermal expansion coefficient (ppm / °C) in the range of 25°C to 150°C and the linear thermal expansion coefficient (ppm / °C) in the range of 150°C to 240°C were calculated.

[0344] <Measurement test of glass transition temperature Tg of cured sample 1 of the fiber-reinforced sheet 1 of the insulating multilayer sheet 1, and cured sample 2 of the resin composition layer 2 of the resin sheet 2> The glass transition temperature (Tg) of cured samples 1 and 2 was measured using the following method.

[0345] (Method for measuring glass transition temperature Tg) A sample (hardened sample 1 or 2) was cut into pieces 5 mm wide and 15 mm long to obtain test specimens. Thermomechanical analysis was performed on these test specimens using a viscoelasticity analyzer (Hitachi High-Tech Science Corporation's "DMA7100") by the tensile loading method. Specifically, after mounting the test specimens in the thermomechanical analyzer, the storage modulus and loss modulus were measured under measurement conditions of a load of 200 mN and a heating rate of 5 °C / min. The glass transition temperature Tg (°C) was obtained from the peak of the temperature-dependent curve of tanδ (ratio of storage modulus to loss modulus) obtained as a measurement result after heating to 260 °C.

[0346] <Measurement test of tensile modulus of cured sample 1 of the fiber-reinforced sheet 1 of the insulating multilayer sheet 1, and cured sample 2 of the resin composition layer 2 of the resin sheet 2> The tensile modulus of cured samples 1 and 2 was measured using the following method.

[0347] (Method for measuring tensile modulus) Tensile tests were performed on the samples (cured sample 1 or 2) using a Tensilon universal tester (Orientec Co., Ltd. "RTC-1250A") in accordance with the Japanese Industrial Standard JIS K7127, and the tensile modulus was measured. The tensile modulus was measured at room temperature (23°C) and 260°C, respectively.

[0348] <Physical properties of fiber-reinforced sheet 1, resin composition layer 2, and cured samples thereof> The minimum melt viscosity of the prepreg layer and resin composition layer 2 measured by the method described above in the temperature range of 100°C to 140°C, the temperature at which the melt viscosity is lowest throughout the entire measurement range, and the linear thermal expansion coefficient CTE, glass transition temperature Tg, and tensile modulus of the cured sample 1 of the fiber-reinforced sheet 1 and the cured sample 2 of the resin composition layer 2 are shown in Table 1 below. The minimum melt viscosity values ​​of the prepreg layer and resin composition layer 2 measured here were the minimum melt viscosity in the temperature range of 100°C to 140°C, and also the lowest melt viscosity value throughout the entire measurement range. Therefore, the temperature at which this minimum melt viscosity is observed corresponds to the temperature at which the melt viscosity is lowest throughout the entire measurement range.

[0349] [Table 1]

[0350] <Example 1> (1-1. Preparation of the core board) A glass cloth substrate epoxy resin double-sided copper-clad laminate (copper layer thickness 18 μm, substrate thickness 0.2 mm, manufactured by Resonaq Corporation, "MCL-E-705G") with copper layers on both surfaces was prepared as the core substrate. The surface of the copper layer of this core substrate was roughened by immersing both sides in an etching agent (manufactured by MEC Corporation, "CZ8100").

[0351] (1-2. Formation of the first insulating layer) A resin sheet 2 was placed on the chip side of the core substrate so that the resin composition layer 2 was bonded to the core substrate. Another resin sheet 2 was also placed on the opposite side of the core substrate so that the resin composition layer 2 was bonded to the core substrate. Lamination was then performed using a vacuum pressure laminator (MVLP-500, manufactured by Meiki Seisakusho Co., Ltd.). This lamination was performed by vacuum suction at 120°C for 30 seconds, followed by pressing from above the PET film through heat-resistant rubber for 60 seconds at 120°C and a pressure of 0.7 MPa. Next, the resin composition layer 2 was smoothed by pressing with a SUS end plate at atmospheric pressure for 90 seconds at 120°C and a pressure of 0.54 MPa.

[0352] The PET film was peeled off from the laminated resin composition layer 2. Then, the resin composition layer 2 was heat-cured at 200°C for 90 minutes to form the first insulating layer on the chip side and the opposite side of the core substrate. Through the above operations, an intermediate product (I) having a layer structure of "insulating layer / core substrate / insulating layer" was obtained.

[0353] (1-3. Formation of the second insulating layer) A resin sheet 2 was placed on the insulating layer on the chip side of the intermediate product (I) so that the resin composition layer 2 was bonded to the intermediate product (I). A resin sheet 2 was also placed on the insulating layer on the opposite side of the intermediate product (I) so that the resin composition layer 2 was bonded to the intermediate product (I). Then, lamination, smoothing, PET film peeling, and heat curing were performed under the same conditions as in the step (1-2) for forming the first insulating layer, to form a second insulating layer on the chip side and the opposite side of the core substrate, via the first insulating layer. Through these operations, an intermediate product (II) having a layer structure of "insulating layer (second layer) / insulating layer (first layer) / core substrate / insulating layer (first layer) / insulating layer (second layer)" was obtained.

[0354] (1-4. Formation of the third insulating layer) A resin sheet 2 was placed on the insulating layer on the chip side of the intermediate product (II) so that the resin composition layer 2 was bonded to the intermediate product (II). A resin sheet 2 was also placed on the insulating layer on the opposite side of the intermediate product (II) so that the resin composition layer 2 was bonded to the intermediate product (II). Then, lamination, smoothing, PET film peeling, and heat curing were performed under the same conditions as in the step of forming the first insulating layer (1-2) to form a third insulating layer on the chip side and the opposite side of the core substrate, via the first and second insulating layers. Through the above operations, an intermediate product (III) having a layer structure of "insulating layer (third layer) / insulating layer (second layer) / insulating layer (first layer) / core substrate / insulating layer (first layer) / insulating layer (second layer) / insulating layer (third layer)" was obtained.

[0355] (1-5. Formation of the fourth insulating layer) A resin sheet 2 was placed on the insulating layer on the chip side of the aforementioned intermediate product (III) such that the resin composition layer 2 was bonded to the intermediate product (III). Furthermore, one PET film of the insulating multilayer sheet 1 was peeled off to expose the prepreg layer. The insulating multilayer sheet 1 was placed on the insulating layer on the opposite side of the intermediate product (III) so that the prepreg layer was bonded to the intermediate product (III). Subsequently, lamination, smoothing, PET film peeling, and heat curing were performed under the same conditions as in the step of forming the first insulating layer (1-2) to form a fourth insulating layer on the chip side and the opposite side of the core substrate, respectively, via the first, second, and third insulating layers. Through these operations, an evaluation structure having the layer configuration of "insulating layer (fourth layer) / insulating layer (third layer) / insulating layer (second layer) / insulating layer (first layer) / core substrate / insulating layer (first layer) / insulating layer (second layer) / insulating layer (third layer) / insulating layer (fourth layer)" was obtained. In this evaluation structure, the fourth insulating layer formed on the opposite side of the core substrate contained a fiber substrate, while the other insulating layers did not contain a fiber substrate.

[0356] <Example 2> In the process of forming the third insulating layer (1-4), an insulating multilayer sheet 1, obtained by peeling off a PET film, was placed on the insulating layer opposite the intermediate product (II) instead of the resin sheet 2. This insulating multilayer sheet 1 had one PET film peeled off to expose the prepreg layer, and was positioned so that the prepreg layer was bonded to the intermediate product (II). Except for the matters described above, the evaluation structure was manufactured using the same method as in Example 1. In this evaluation structure, the third and fourth insulating layers formed on the opposite side of the core substrate contained a fibrous substrate, while the other insulating layers did not contain a fibrous substrate.

[0357] <Example 3> In the process of forming the second insulating layer (1-3), an insulating multilayer sheet 1, obtained by peeling off a PET film, was placed on the insulating layer opposite the intermediate product (I) instead of the resin sheet 2. This insulating multilayer sheet 1 had one PET film peeled off to expose the prepreg layer, and was positioned so that the prepreg layer was bonded to the intermediate product (I). Furthermore, in the process of forming the third insulating layer (1-4), an insulating multilayer sheet 1, obtained by peeling off a PET film, was placed on the insulating layer opposite the intermediate product (II) instead of the resin sheet 2. This insulating multilayer sheet 1 had one PET film peeled off to expose the prepreg layer, and was positioned so that the prepreg layer was bonded to the intermediate product (II). Except for the matters described above, the evaluation structure was manufactured using the same method as in Example 1. In this evaluation structure, the second, third, and fourth insulating layers formed on the opposite side of the core substrate contained a fibrous substrate, while the other insulating layers did not contain a fibrous substrate.

[0358] <Example 4> In the step of forming the first insulating layer (1-2), an insulating multilayer sheet 1, obtained by peeling off the PET film, was placed on the chip side and the opposite side of the core substrate instead of the resin sheet 2. This insulating multilayer sheet 1 had one of the PET films peeled off to expose the prepreg layer, and was positioned so that the prepreg layer was bonded to the core substrate. Except for the matters described above, the evaluation structure was manufactured using the same method as in Example 1. In this evaluation structure, the first insulating layer formed on the chip side of the core substrate, and the first and fourth insulating layers formed on the opposite side of the core substrate, contained a fibrous substrate, while the other insulating layers did not contain a fibrous substrate.

[0359] <Example 5> In the step of forming the first insulating layer (1-2), an insulating multilayer sheet 1, obtained by peeling off the PET film, was placed on the opposite side of the core substrate instead of the resin sheet 2. This insulating multilayer sheet 1 had one of the PET films peeled off to expose the prepreg layer, and was positioned so that the prepreg layer was bonded to the core substrate. Furthermore, in the process of forming the fourth insulating layer (1-5), a resin sheet 2 was placed on the insulating layer opposite the intermediate product (III) instead of the insulating multilayer sheet 1. The resin sheet 2 was positioned so that its resin composition layer 2 was bonded to the intermediate product (III). Except for the matters described above, the evaluation structure was manufactured using the same method as in Example 1. In this evaluation structure, the first insulating layer formed on the opposite side of the core substrate contained a fibrous substrate, while the other insulating layers did not contain a fibrous substrate.

[0360] <Comparative Example 1> In the process of forming the fourth insulating layer (1-5), a resin sheet 2 was placed on the insulating layer opposite the intermediate product (III) in place of the insulating multilayer sheet 1. The resin sheet 2 was positioned so that its resin composition layer 2 was bonded to the intermediate product (III). Except for the matters mentioned above, the evaluation structure was manufactured using the same method as in Example 1. In this evaluation structure, none of the insulating layers contained a fibrous substrate.

[0361] <Comparative Example 2> In the step of forming the first insulating layer (1-2), an insulating multilayer sheet 1, obtained by peeling off the PET film, was placed on the opposite side of the core substrate instead of the resin sheet 2. This insulating multilayer sheet 1 had one of the PET films peeled off to expose the prepreg layer, and was positioned so that the prepreg layer was bonded to the core substrate. Furthermore, in the process of forming the second insulating layer (1-3), an insulating multilayer sheet 1, obtained by peeling off a PET film, was placed on the insulating layer on the opposite side of the intermediate product (I) instead of the resin sheet 2. This insulating multilayer sheet 1 had one PET film peeled off to expose the prepreg layer, and was positioned so that the prepreg layer was bonded to the intermediate product (I). Furthermore, in the process of forming the third insulating layer (1-4), an insulating multilayer sheet 1, obtained by peeling off a PET film, was placed on the insulating layer on the opposite side of the intermediate product (II) instead of the resin sheet 2. This insulating multilayer sheet 1 had one PET film peeled off to expose the prepreg layer, and was positioned so that the prepreg layer was bonded to the intermediate product (II). Except for the matters described above, the evaluation structure was manufactured using the same method as in Example 1. In this evaluation structure, all insulating layers formed on the opposite side of the core substrate contained a fibrous substrate, while the other insulating layers did not contain a fibrous substrate.

[0362] <Comparative Example 3> In the step of forming the first insulating layer (1-2), an insulating multilayer sheet 1, obtained by peeling off the PET film, was placed on the chip side and the opposite side of the core substrate instead of the resin sheet 2. This insulating multilayer sheet 1 had one of the PET films peeled off to expose the prepreg layer, and was positioned so that the prepreg layer was bonded to the core substrate. Furthermore, in the process of forming the fourth insulating layer (1-5), an insulating multilayer sheet 1, obtained by peeling off a PET film, was placed on the insulating layer on the chip side of the intermediate product (III) instead of the resin sheet 2. This insulating multilayer sheet 1 had one PET film peeled off to expose the prepreg layer, and was positioned so that the prepreg layer was bonded to the intermediate product (III). Also, a resin sheet 2 was placed on the insulating layer on the opposite side of the intermediate product (III) instead of the insulating multilayer sheet 1. The resin sheet 2 was positioned so that its resin composition layer 2 was bonded to the intermediate product (III). Except for the matters described above, the evaluation structure was manufactured using the same method as in Example 1. In this evaluation structure, the first and fourth insulating layers formed on the chip side surface of the core substrate, and the first insulating layer formed on the opposite side, contained a fibrous substrate, while the other insulating layers did not contain a fibrous substrate.

[0363] <Method for measuring warp amount> A model experiment was conducted in which a dummy chip, equivalent to a semiconductor chip, was mounted on the evaluation structure described above using an adhesive layer, and the amount of warpage was measured. In both the example and comparative example, the model experiment was performed four times, and four values ​​each of the warpage W(A) before reflow, W(B) during reflow, and W(C) after reflow were obtained. Table 2, described later, shows the average values ​​of these warpage amounts W(A), W(B), and W(C). The specific procedure for the model experiment was carried out as follows.

[0364] (1) Preparing the dummy chip: An adhesive sheet (ABF: Ajinomoto Build-up Film, 20 μm thick) comprising a support and an adhesive layer was prepared. This adhesive sheet was laminated to one side of a 20 mm x 20 mm silicon wafer using a vacuum pressure laminator (Meiki Seisakusho Co., Ltd. "MVLP-500"). This lamination was performed by vacuum suction at 80°C for 30 seconds, followed by pressing from above the support via heat-resistant rubber for 60 seconds under conditions of 80°C and a pressure of 0.7 MPa. After that, the support was peeled off to obtain a dummy chip as a semiconductor chip comprising the silicon wafer and adhesive layer.

[0365] (2) Laminating the dummy chip: The evaluation structure was cut to 50 mm vertically and 50 mm horizontally using a cutting machine. A dummy chip was placed on the evaluation structure so that the adhesive layer was bonded to the evaluation structure, and it was laminated using a vacuum pressure laminator (MVLP-500, manufactured by Meiki Seisakusho Co., Ltd.). This lamination was performed by vacuum suction at 100°C for 30 seconds, followed by pressing at 100°C and a pressure of 0.7 MPa for 30 seconds via heat-resistant rubber. Next, under atmospheric pressure, a SUS end plate was used to perform a heat press at 100°C and a pressure of 0.54 MPa for 60 seconds. Then, the adhesive layer was cured at 190°C for 60 minutes to obtain an evaluation intermediate having a layer structure of "evaluation structure / adhesive layer / dummy chip".

[0366] (3) Reflow process: Subsequently, a reflow process was performed using a reflow apparatus (ANTOM, HAS-6116) to heat the evaluation intermediate under thermal history conditions of 260°C or higher for 1 minute or more, thereby obtaining an evaluation package.

[0367] (4) Test 1. Measurement test of warpage W(A) before reflow treatment: The warpage W(A) of the evaluation intermediate was measured at 25°C. The warpage was measured using a shadow moiré measuring device (Akorometrix "ThermoireAXP") in accordance with the Japan Electronics and Information Technology Industries Association standard JEITA EDX-7311-24. Specifically, all data was acquired from the surface of the evaluation structure of the evaluation intermediate in the measurement area (the surface opposite to the dummy chip), and a virtual plane as a reference plane was calculated from this data us...

Claims

1. A method for manufacturing a structure for mounting semiconductor chips; The structure is core substrate and A chip-side build-up layer formed on the first side surface of the core substrate, The core substrate comprises a second side surface formed on the opposite side to the first side surface, and a reverse build-up layer formed on the second side surface opposite to the first side surface; The chip-side build-up layer comprises multiple insulating layers; Either all of the multiple insulating layers of the chip-side build-up layer do not contain a fibrous substrate, or some of the multiple insulating layers of the chip-side build-up layer contain a fibrous substrate; The opposite build-up layer comprises multiple insulating layers; Some of the multiple insulating layers of the opposite build-up layer include a fibrous substrate; The method for manufacturing the structure is Multiple steps (i) to form an insulating layer on the first side surface of the core substrate and Multiple steps (ii) to form an insulating layer on the second side surface of the core substrate, Including; The number of insulating layers containing fibrous substrates in the opposite build-up layer is 5% or more and 80% or less of the total number of insulating layers in the opposite build-up layer (100%); A method for manufacturing a structure, wherein the number of insulating layers containing fibrous substrates in the opposite build-up layer is greater than the number of insulating layers containing fibrous substrates in the chip-side build-up layer.

2. A method for manufacturing a structure for mounting semiconductor chips; The structure is core substrate and A chip-side build-up layer formed on the first side surface of the core substrate, The core substrate comprises a second side surface formed on the opposite side to the first side surface, and a reverse build-up layer formed on the second side surface opposite to the first side surface; The chip-side build-up layer comprises multiple insulating layers; Either all of the multiple insulating layers of the chip-side build-up layer do not contain a fibrous substrate, or some of the multiple insulating layers of the chip-side build-up layer contain a fibrous substrate; The opposite build-up layer comprises multiple insulating layers; Some of the multiple insulating layers of the opposite build-up layer include a fibrous substrate; The method for manufacturing the structure is Multiple steps (i) to form an insulating layer on the first side surface of the core substrate and Multiple steps (ii) to form an insulating layer on the second side surface of the core substrate, Including; The total thickness of the insulating layers, including the fibrous substrate, in the opposite build-up layer is between 5% and 80% of the total thickness of the multiple insulating layers in the opposite build-up layer, with the total thickness being 100%; A method for manufacturing a structure, wherein the total thickness of the insulating layer containing the fibrous substrate in the opposite build-up layer is greater than the total thickness of the insulating layer containing the fibrous substrate in the chip-side build-up layer.

3. Multiple steps (ii) for forming an insulating layer on the second side surface of the core substrate include a step for forming an insulating layer including a fibrous substrate; The step of forming an insulating layer including a fibrous substrate includes laminating a fibrous sheet having a prepreg layer; A method for producing the structure according to claim 1 or 2, wherein the prepreg layer comprises a fibrous substrate and a resin composition impregnated into the fibrous substrate.

4. A method for manufacturing the structure according to claim 3, wherein the lamination of fiber-reinforced sheets is performed by a lamination method.

5. The fiber-reinforced sheet comprises a prepreg layer and a cured layer formed on one side of the prepreg layer. A method for producing the structure according to claim 3, wherein the cured layer includes a cured product of a thermosetting resin composition.

6. A method for manufacturing the structure according to claim 3, wherein the minimum melt viscosity of the prepreg layer in the temperature range of 100°C to 140°C is 10,000 poise or less.

7. A method for manufacturing a structure according to claim 3, wherein the glass transition temperature of the cured sample obtained by curing a fiber-reinforced sheet is 250°C or lower.

8. Multiple steps (ii) for forming an insulating layer on the second side surface of the core substrate include a step for forming an insulating layer that does not contain a fiber substrate; The step of forming an insulating layer that does not contain a fibrous substrate includes laminating a resin composition layer that does not contain a fibrous substrate; The method for manufacturing a structure according to claim 3, wherein the absolute value of the difference between the glass transition temperature of a cured sample obtained by curing a fiber-reinforced sheet and the glass transition temperature of a cured sample obtained by curing a resin composition layer is 80°C or less.

9. A method for manufacturing the structure according to claim 1 or 2, wherein the core substrate has a thickness of 0.1 mm or more and 2 mm or less.

10. A method for manufacturing the structure according to claim 1 or 2, wherein the opposite build-up layer comprises four or more insulating layers.

11. A method for manufacturing the structure according to claim 1 or 2, wherein the opposite build-up layer has a thickness of 60 μm or more and 700 μm or less.

12. A method for manufacturing the structure according to claim 1 or 2, wherein the number of insulating layers provided in the chip-side build-up layer is the same as the number of insulating layers provided in the opposite-side build-up layer.

13. A structure for mounting semiconductor chips; The structure is core substrate and A chip-side build-up layer formed on the first side surface of the core substrate, The core substrate comprises a second side surface formed on the opposite side to the first side surface, and a reverse build-up layer formed on the second side surface opposite to the first side surface; The chip-side build-up layer comprises multiple insulating layers; Either all of the multiple insulating layers of the chip-side build-up layer do not contain a fibrous substrate, or some of the multiple insulating layers of the chip-side build-up layer contain a fibrous substrate; The opposite build-up layer comprises multiple insulating layers; Some of the multiple insulating layers of the opposite build-up layer include a fibrous substrate; The number of insulating layers containing fibrous substrates in the opposite build-up layer is 5% or more and 80% or less of the total number of insulating layers in the opposite build-up layer (100%); A structure in which the number of insulating layers containing fibrous substrates in the opposite build-up layer is greater than the number of insulating layers containing fibrous substrates in the chip-side build-up layer.

14. A structure for mounting semiconductor chips; The structure is core substrate and A chip-side build-up layer formed on the first side surface of the core substrate, The core substrate comprises a second side surface formed on the opposite side to the first side surface, and a reverse build-up layer formed on the second side surface opposite to the first side surface; The chip-side build-up layer comprises multiple insulating layers; Either all of the multiple insulating layers of the chip-side build-up layer do not contain a fibrous substrate, or some of the multiple insulating layers of the chip-side build-up layer contain a fibrous substrate; The opposite build-up layer comprises multiple insulating layers; Some of the multiple insulating layers of the opposite build-up layer include a fibrous substrate; The total thickness of the insulating layers, including the fibrous substrate, in the opposite build-up layer is between 5% and 80% of the total thickness of the multiple insulating layers in the opposite build-up layer, with the total thickness being 100%; A structure in which the total thickness of the insulating layer, including the fibrous substrate, in the opposite build-up layer is greater than the total thickness of the insulating layer, including the fibrous substrate, in the chip-side build-up layer.

15. A method for manufacturing a semiconductor chip package, comprising the step of mounting a semiconductor chip on the chip-side build-up layer of the structure described in claim 13 or 14.

16. A semiconductor chip package comprising a structure according to claim 13 or 14, and a semiconductor chip mounted on the chip-side build-up layer of the structure.

17. A semiconductor device comprising the semiconductor chip package described in claim 16.

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