Control circuit, semiconductor memory device, and method for controlling a semiconductor memory device

Abstract

The present invention provides a control circuit, a semiconductor memory device, and a control method thereof that can efficiently estimate the delay amount between a first signal and a second signal, and generate an output signal corresponding to that delay amount. [Solution] The control circuit 30 includes a delay line section 31 to which a start signal start_tdc is input, which includes a plurality of delay units U1 to U8 connected in series; a detection section 32 to which an end signal end_tdc is input, which detects the number of delay units that the start signal has passed through among the plurality of delay units before the end signal is input when the end signal is input after the start signal has been input to the delay line section; and a control unit 33 that controls the transmission path of the start signal in the delay line section so that the number of delay units that the start signal has passed through before the start signal is output from the delay line section is equal to the number of delay units detected by the detection unit.

Description

[[Technical Field]]

[0001] The present invention relates to a control circuit, a semiconductor memory device, and a method for controlling a semiconductor memory device. [[Background Art]]

[0002] A TDC (Time to Digital Converter) circuit configured to detect a delay amount (phase difference) between a first signal and a second signal and generate a digital value corresponding to the delay amount is known (for example, Patent Document 1). [[Prior Art Documents]] [[Patent Documents]]

[0003] [[Patent Document 1]] Japanese Unexamined Patent Application Publication No. 2019-87797 [[Summary of the Invention]] [[Problem to be Solved by the Invention]]

[0004] Such a circuit has a plurality of delay units, and can generate a digital value corresponding to a predetermined delay amount by using some of the plurality of delay units. Here, it is desired to efficiently perform estimation of the delay amount between the first signal and the second signal (that is, estimation of the number of delay units corresponding to the predetermined delay amount) and generation of an output signal according to the delay amount.

[0005] The present invention has been made in view of the above problem, and an object thereof is to provide a control circuit, a semiconductor memory device, and a control method therefor capable of efficiently performing estimation of a delay amount between a first signal and a second signal and generation of an output signal according to the delay amount. [[Means for Solving the Problem]]

[0006] To solve the above problems, the present invention provides a control circuit comprising: a delay line section to which a first signal is input, the delay line section including a plurality of delay units connected in series, each of the plurality of delay units delaying the input first signal; a detection section to which a second signal, which is a delayed signal of the first signal, is input, the detection section detecting the number of delay units that the first signal has passed through among the plurality of delay units before the second signal is input when the second signal is input after the first signal has been input to the delay line section; and a control section that controls the transmission path of the first signal in the delay line section so that the number of delay units that the first signal passes through before it is output from the delay line section is equal to the number of delay units detected by the detection section.

[0007] According to this invention, the number of delay units that the first signal passes through before the second signal is input is detected as the delay amount between the first signal and the second signal. Therefore, the delay amount can be easily detected by inputting each of the first and second signals. Furthermore, according to this invention, the transmission path of the first signal in the delay line section is controlled so that the number of delay units that the first signal passes through is equal to the number of delay units detected by the detection unit (i.e., the delay amount between the first signal and the second signal). Therefore, it becomes possible to easily generate an output signal delayed by the said delay amount from the input signal using this delay line section. This makes it possible to efficiently estimate the delay amount between the first signal and the second signal and generate an output signal corresponding to that delay amount.

[0008] Furthermore, the present invention provides a semiconductor memory device equipped with the above-described control circuit.

[0009] Furthermore, the present invention provides a control method for a semiconductor memory device, which is performed by a control circuit provided in the semiconductor memory device, and includes a delay line section to which a first signal is input, comprising a plurality of delay units connected in series, each of the plurality of delay units delaying the input first signal, and when a second signal, which is a delayed signal of the first signal, is input to the control circuit after the first signal has been input to the delay line section, the step of detecting the number of delay units that the first signal has passed through among the plurality of delay units before the second signal is input, and the step of controlling the transmission path of the first signal in the delay line section so that the number of delay units that the first signal passes through before it is output from the delay line section is equal to the number of detected delay units. [Effects of the Invention]

[0010] According to the control circuit, semiconductor memory device, and control method of the present invention, it is possible to efficiently estimate the delay amount between a first signal and a second signal, and to generate an output signal corresponding to the said delay amount. [Brief explanation of the drawing]

[0011] [Figure 1] This figure shows an example configuration of a semiconductor memory device according to one embodiment of the present invention. [Figure 2] This figure shows an example of the configuration of a control circuit according to one embodiment of the present invention. [Figure 3] This is a time chart showing an example of the voltage progression of a signal in a control circuit. [Figure 4] This figure shows an example of the signal state within the control circuit during delay estimation processing. [Figure 5] This figure shows an example of the signal state within the control circuit during delay estimation processing. [Figure 6] This figure shows an example of the signal state within the control circuit during output signal generation processing. [Figure 7] This figure shows an example of a part of the control circuit configuration in a modified example. [Figure 8] This figure shows an example of a part of the control circuit configuration in a modified example. [Modes for carrying out the invention]

[0012] Figure 1 shows an example configuration of a semiconductor memory device according to one embodiment of the present invention. As shown in Figure 1, the semiconductor memory device includes an input buffer 10, a delay circuit 20, a control circuit 30, a replica unit 40, and an output buffer 50. In this embodiment, the case where the semiconductor memory device is DRAM (Dynamic Random Access Memory) is described as an example. Also, in this embodiment, in order to simplify the explanation, well-known configurations provided in the semiconductor memory device (e.g., memory cell array, power supply circuit, clock generator, etc.) are not shown.

[0013] The input buffer 10 buffers the external clock signal input to the input buffer 10 and generates a reference clock signal clk_ref. The generated reference clock signal clk_ref is output to the delay circuit 20 and the control circuit 30.

[0014] The delay circuit 20 is a delay-locked loop (DLL) circuit that generates an output clock signal (delayed signal) dll_clk by delaying the input reference clock signal clk_ref. The delay circuit 20 outputs the generated output clock signal dll_clk to the replica unit 40 and the output buffer 50. The delay circuit 20 also has a delay line unit 31 and a detection unit 32, which are included in the control circuit 30 described later.

[0015] The replica unit 40 outputs the output clock signal dll_clk generated by the delay circuit 20 as a feedback signal clk_fb to the control circuit 30.

[0016] The output buffer 50 outputs the output clock signal dll_clk generated by the delay circuit 20 as an internal clock signal to other circuits (not shown) in the semiconductor memory device.

[0017] Referring to Fig. 2, the control circuit 30 according to the present embodiment will be described. The control circuit 30 includes a delay line unit 31, a detection unit 32, and a control unit 33.

[0018] The delay line unit 31 is configured to receive a reference clock signal clk_ref or a start signal start_tdc described later, and includes a plurality of (eight in the present embodiment) delay units U1 to U8 connected in series. Here, each of the reference clock signal clk_ref and the start signal start_tdc is an example of the "first signal" in the present invention.

[0019] Each of the plurality of delay units U1 to U8 is configured to delay an input signal by a predetermined amount and output the delayed signal. Further, in the example shown in Fig. 2, a signal (the reference clock signal clk_ref or the start signal start_tdc) is input to the most upstream delay unit U1 in the delay line unit 31 among the plurality of delay units U1 to U8, and the signals output from the immediately preceding delay units U1 to U7 are input to the subsequent delay units U2 to U8.

[0020] Furthermore, each of the multiple delay units U1 to U8 includes one or more delay elements that delay the input signal. Here, each of the multiple delay units U1 to U8 may include an even number (two in this embodiment) of NAND circuits N1 to N16 as one or more delay elements. This makes it possible to match the logic level of the signal input to the delay line section 31 with the logic level of the signals output from each delay unit U1 to U8. In the example shown in Figure 2, delay unit U1 includes two NAND circuits N1 and N2, delay unit U2 includes two NAND circuits N3 and N4, delay unit U3 includes two NAND circuits N5 and N6, delay unit U4 includes two NAND circuits N7 and N8, delay unit U5 includes two NAND circuits N9 and N10, delay unit U6 includes two NAND circuits N11 and N12, delay unit U7 includes two NAND circuits N13 and N14, and delay unit U8 includes two NAND circuits N15 and N16.

[0021] In the delay line section 31, one input terminal of the upstream NAND circuit N1 of the multiple NAND circuits N1 to N16 receives a signal (reference clock signal clk_ref or start signal start_tdc), and one input terminal of the subsequent NAND circuits N2 to N16 receives the signal output from the output terminal of the preceding NAND circuit N1 to N15. In addition, the other input terminal of each of the NAND circuits N1 to N10, N12, N14, and N16 receives activation signals AS[1] to AS

[10] , AS

[12] , AS

[14] , and AS

[16] to activate the corresponding NAND circuits N1 to N10, N12, N14, and N16. For example, if the logical value of the activation signal AS[i] (in this embodiment, i is an integer between 1 and 16, excluding 11, 13, and 15) is "1", the NAND circuit Ni is activated, and if the logical value of the activation signal AS[i] is "0", the NAND circuit Ni is deactivated. In this embodiment, the logical value of the activation signal AS[i] is set by the control unit 33.

[0022] Furthermore, the delay line section 31 has multiple bypass paths BR1 to BR3, each with a different number of delay units that the input signal (reference clock signal clk_ref or start signal start_tdc) passes through before being output from the delay line section 31 (three in this embodiment). In the example shown in Figure 2, bypass path BR1 is configured to provide a shortcut connection between delay unit U1 and delay unit U8. As a result, the signal passes through two delay units (delay units U1 and U8) before being output from the delay line section 31 after passing through bypass path BR1. Bypass path BR2 is configured to provide a shortcut connection between delay unit U2 and delay unit U7. As a result, the signal passes through four delay units (delay units U1, U2, U7, and U8) before being output from the delay line section 31 after passing through bypass path BR2. Furthermore, bypass path BR3 is configured to provide a shortcut connection between delay unit U3 and delay unit U6. As a result, the number of delay units that the signal passes through from the bypass path BR3 to the output from the delay line section 31 is six (delay units U1, U2, U3, U6, U7, U8).

[0023] Furthermore, in this embodiment, each of the multiple bypass paths BR1 to BR3 is configured to include at least one delay unit. This makes it possible to delay the signal in each of the bypass paths BR1 to BR3.

[0024] In the example shown in Figure 2, bypass path BR1 includes one NAND circuit BN1 as a delay unit, bypass path BR2 includes one NAND circuit BN2 as a delay unit, and bypass path BR3 includes one NAND circuit BN3 as a delay unit. One input terminal of NAND circuit BN1 of bypass path BR1 is connected to the output terminal of NAND circuit N1 of delay unit U1, and the output terminal of NAND circuit BN1 is connected to the other input terminal of NAND circuit N15 of delay unit U8. Also, one input terminal of NAND circuit BN2 of bypass path BR2 is connected to the output terminal of NAND circuit N3 of delay unit U2, and the output terminal of NAND circuit BN2 is connected to the other input terminal of NAND circuit N13 of delay unit U7. Furthermore, one input terminal of the NAND circuit BN3 of the bypass path BR3 is connected to the output terminal of the NAND circuit N5 of the delay unit U3, and the output terminal of the NAND circuit BN3 is connected to the other input terminal of the NAND circuit N11 of the delay unit U6. In addition, activation signals AS[B1] to AS[B3] for activating the corresponding NAND circuits BN1 to BN3 are input to the other input terminal of each of the NAND circuits BN1 to BN3. For example, if the logical value of the activation signal AS[Bj] (in this embodiment, j is an integer between 1 and 3) is "1", the NAND circuit BNj is activated, and if the logical value of the activation signal AS[Bj] is "0", the NAND circuit BNj is deactivated. In this embodiment, the logical values ​​of each of the activation signals AS[B1] to AS[B3] are set by the control unit 33.

[0025] In this embodiment, the delay line section 31 is formed in a U-shape in plan view (i.e., multiple delay units U1 to U8 (more specifically, multiple NAND circuits N1 to N16) are arranged in a U-shape in plan view). This makes it possible to compactly arrange the region in which the delay line section 31 is formed. Furthermore, the length of each bypass path BR1 to BR3 can be shortened, for example, by forming each bypass path BR1 to BR3 to provide a shortcut connection between delay units arranged opposite each other in the U-shaped path.

[0026] The detection unit 32 is configured to receive the end signal end_tdc, which is a delayed signal of the start signal start_tdc. Furthermore, when the end signal end_tdc is received after the start signal start_tdc has been received by the delay line unit 31, the detection unit 32 is configured to detect the number of delay units U1 to U8 that the start signal start_tdc has passed through before the end signal end_tdc is received. Here, the end signal end_tdc is an example of the "second signal" of the present invention.

[0027] Furthermore, in this embodiment, the detection unit 32 includes latch units corresponding to each of the plurality of delay units U1 to U8, which latch the signals output from the corresponding delay units U1 to U8 when the end signal end_tdc is input. Here, the detection unit 32 is configured to detect, when the end signal end_tdc is input, the number of delay units among the plurality of delay units U1 to U8 for which a signal with the same value as the start signal start_tdc has been latched by the corresponding latch unit, as the number of delay units that the start signal start_tdc has passed through before the end signal end_tdc is input. This makes it possible to easily detect the number of delay units that the start signal start_tdc has passed through before the end signal end_tdc is input (i.e., the amount of delay between the start signal start_tdc and the end signal end_tdc) when the start signal start_tdc and the end signal end_tdc are each input.

[0028] Here, the latching section may include a flip-flop circuit. Furthermore, the flip-flop circuit may include a D flip-flop circuit. This makes it possible to easily latch the signals output from delay units U1 to U8.

[0029] As shown in Figure 2, the detection unit 32 is equipped with a plurality of D flip-flop circuits FF1 to FF8, each corresponding to a plurality of delay units U1 to U8 (eight in this embodiment). Here, the D terminal of D flip-flop circuit FF1 is connected to the output terminal of NAND circuit N2 of delay unit U1, and the D terminal of D flip-flop circuit FF2 is connected to the output terminal of NAND circuit N4 of delay unit U2. Furthermore, the D terminal of D flip-flop circuit FF3 is connected to the output terminal of NAND circuit N6 of delay unit U3, and the D terminal of D flip-flop circuit FF4 is connected to the output terminal of NAND circuit N8 of delay unit U4. In addition, the D terminal of D flip-flop circuit FF5 is connected to the output terminal of NAND circuit N10 of delay unit U5, and the D terminal of D flip-flop circuit FF6 is connected to the output terminal of NAND circuit N12 of delay unit U6. Furthermore, the D terminal of the D flip-flop circuit FF7 is connected to the output terminal of the NAND circuit N14 of the delay unit U7, and the D terminal of the D flip-flop circuit FF8 is connected to the output terminal of the NAND circuit N16 of the delay unit U8. In addition, the end signal end_tdc is input to the clock terminal of each of the multiple D flip-flop circuits FF1 to FF8. Furthermore, the output of each of the multiple D flip-flop circuits FF1 to FF8 is sent to the control unit 33.

[0030] The control unit 33 is configured to control the transmission path of the reference clock signal clk_ref in the delay line section 31 such that the number of delay units that the reference clock signal clk_ref passes through before it is output from the delay line section 31 is equal to the number of delay units detected by the detection unit 32.

[0031] Furthermore, the control unit 33 may control the transmission of the reference clock signal clk_ref via a bypass path (any of the bypass paths BR1 to BR3) formed in the delay line section 31 such that the number of delay units that the reference clock signal clk_ref passes through before being output from the delay line section 31 is equal to the number of delay units detected by the detection unit 32. This makes it possible to easily output an output signal from the delay line section 31 that is delayed by the number of delay units detected by the detection unit 32 (i.e., the delay amount between the start signal start_tdc and the end signal end_tdc) by the reference clock signal clk_ref being output from the delay line section 31 via the bypass path.

[0032] Furthermore, the control unit 33 may select a bypass path from among the multiple bypass paths BR1 to BR3 such that the number of delay units through which the reference clock signal clk_ref passes before it is output from the delay line section 31 is equal to the number of delay units detected by the detection unit 32, and control the system so that the reference clock signal clk_ref is transmitted through the selected bypass path. This makes it possible to delay the input reference clock signal clk_ref through the optimal bypass path selected from among the multiple bypass paths BR1 to BR3.

[0033] The control unit 33 is configured to receive the reference clock signal clk_ref output from the input buffer 10 and the feedback signal clk_fb output from the replica unit 40. In this embodiment, the control unit 33 asserts the start signal start_tdc (sets its logical value to "1") at the rising edge of the feedback signal clk_fb and outputs it to the delay line unit 31. Furthermore, in this embodiment, the control unit 33 asserts the end signal end_tdc (sets its logical value to "1") at the rising edge of the reference clock signal clk_ref immediately following the rising edge of the feedback signal clk_fb and outputs it to the detection unit 32.

[0034] Furthermore, the control unit 33 controls the transmission path of the reference clock signal clk_ref in the delay line section 31 by setting the logical values ​​of activation signals AS[1]~AS

[10] , AS

[12] , AS

[14] , AS

[16] and activation signals AS[B1]~AS[B3] to "1" or "0" according to the number of delay units detected by the detection unit 32 (i.e., the amount of delay between the start signal start_tdc and the end signal end_tdc).

[0035] Referring to Figure 3, an example of the relationship between the signal and the delay amount in the control circuit 30 will be explained. First, when the reference clock signal clk_ref output from the input buffer 10 is input to the delay circuit 20, the delay circuit 20 generates the output clock signal dll_clk by delaying the input reference clock signal clk_ref. In this embodiment, it is assumed that the delay circuit 20 generates the output clock signal dll_clk without using the delay line section 31 when the control circuit 30 has not detected the delay amount. The replica section 40 then outputs the output clock signal dll_clk generated by the delay circuit 20 to the control circuit 30 as a feedback signal clk_fb.

[0036] If the delay of the output clock signal dll_clk is adjusted using a DLL circuit, a sequence is executed that includes the delay (locking) operation of the DLL circuit (for example, an operation that synchronizes the reference clock signal clk_ref and the output clock signal dll_clk while activating delay lines one by one).

[0037] The lock time tDLL due to the delayed operation of the DLL circuit can be expressed by the following equation (1). tINT + tDLL = N × tCK (1) In equation (1) above, tINT represents the intrinsic delay time in the DLL circuit, N represents the number of delayed clock cycles between the reference clock signal clk_ref and the output clock signal dll_clk (feedback signal clk_fb), and tCK represents the clock cycle.

[0038] Furthermore, the lock time tDLL can be expressed by the following equation (2). tDLL = X × CDL + Y × FDL (2) In equation (2) above, CDL (coarse delay line) represents the signal delay per delay unit within the CDL, where the adjustment pitch for the delay amount is relatively large, and FDL (fine delay line) represents the signal delay per delay unit within the FDL, where the adjustment pitch for the delay amount is relatively small. Furthermore, X and Y each represent the number of delay units used for signal delay.

[0039] In this embodiment, as shown in Figure 3, it is assumed that the period from the rising edge of the feedback signal clk_fb (and its corresponding start signal start_tdc) at time t1 to the rising edge of the reference clock signal clk_ref (and its corresponding end signal end_tdc) at time t2 is approximately equal to X × CDL in equation (2) above. The detection unit 32 then detects this value of X (i.e., the number of delay units used to delay the signal in the CDL (delay line section 31)).

[0040] An example of the operation of the control circuit 30 in this embodiment will be described with reference to Figures 4 to 6. Figure 4 shows an example of the signal state within the control circuit 30 during the delay amount estimation process, and more specifically, an example of the logical value of the signal within the control circuit 30 at time t1 in Figure 3. At time t1, when the rising edge of the feedback signal clk_fb is input to the control unit 33, the control unit 33 asserts the start signal start_tdc (sets its logical value to "1") and outputs it to the delay line section 31. The control unit 33 also sets the logical values ​​of each of the activation signals AS[1] to AS

[10] , AS

[12] , AS

[14] , and AS

[16] to "1", and sets the logical values ​​of each of the activation signals AS[B1] to AS[B3] to "0". As a result, the start signal start_tdc is transmitted in the delay line section 31 via each of the delay units U1 to U8.

[0041] Figure 5 shows an example of the signal state within the control circuit 30 during the delay amount estimation process, and more specifically, an example of the logical value of the signal within the control circuit 30 at time t2 in Figure 3. At time t2, when the rising edge of the reference clock signal clk_ref immediately following the rising edge of the feedback signal clk_fb is input to the control unit 33, the control unit 33 asserts the end signal end_tdc (sets its logical value to "1") and outputs it to the detection unit 32. At this time, each of the multiple D flip-flop circuits FF1 to FF8 of the detection unit 32 latches the signal output from the corresponding delay units U1 to U8 and outputs the latched signal to the control unit 33. Here, as shown in Figure 5, if the asserted start signal start_tdc has been transmitted to the delay unit U6 at time t2, the logical value of the signal latched by the D flip-flop circuits FF1 to FF6 corresponding to each of the delay units U1 to U6 will be "1". On the other hand, the logic value of the signals latched by the D flip-flop circuits FF7 to FF8, which correspond to each of the delay units U7 to U8, where the asserted start signal start_tdc has not been transmitted, becomes "0". As a result, the detection unit 32 can detect (estimate) the number of D flip-flop circuits FF1 to FF8 that latch a signal with a logic value of "1" when the asserted end signal end_tdc is input (6 in the example shown in Figure 5) as the number of delay units through which the start signal start_tdc has passed before the end signal end_tdc is input.

[0042] Figure 6 shows an example of the signal state within the control circuit 30 during the output signal generation process. Here, the control unit 33 may use, for example, a switch circuit (not shown) to control the input of the reference clock signal clk_ref to the delay line section 31. The control unit 33 also controls the transmission path of the reference clock signal clk_ref in the delay line section 31 so that the number of delay units that the reference clock signal clk_ref passes through before being output from the delay line section 31 is equal to the number of delay units detected by the detection unit 32.

[0043] Specifically, the control unit 33 controls the transmission path of the reference clock signal clk_ref in the delay line section 31 so that the reference clock signal clk_ref is transmitted through one of the multiple bypass paths BR1 to BR3. The control unit 33 may also negate (set the logical value to "0") the start signal start_tdc and the end signal end_tdc. For example, as shown in Figure 5, if the number of delay units detected by the detection unit 32 is 6 (the number of NAND circuits is 12), the control unit 33 controls the transmission of the reference clock signal clk_ref through bypass path BR3, which is one of the multiple bypass paths BR1 to BR3, as the number of delay units that the reference clock signal clk_ref passes through before being output from the delay line section 31 is 6 (the number of NAND circuits is 12). In this case, the control unit 33 sets the logical values ​​of each of the activation signals AS[1]~AS[5], AS

[12] , AS

[14] , AS

[16] , and AS[B3] to "1", and sets the logical values ​​of each of the activation signals AS[6]~AS

[10] , AS[B1]~AS[B2] to "0". As a result, the reference clock signal clk_ref is transmitted in the delay line section 31 via each delay unit U1~U3, the bypass path BR3, and each delay unit U6~U8. That is, the reference clock signal clk_ref is transmitted via the NAND circuits N1, N2, N3, N4, N5, BN3, N11, N12, N13, N14, N15, and N16.

[0044] In this way, the delay line section 31 makes it easy to generate an output signal that is delayed by the amount detected by the detection section 32 from the input signal (reference clock signal clk_ref).

[0045] As described above, according to the control circuit 30, semiconductor memory device, and control method of this embodiment, the number of delay units that the start signal start_tdc (first signal) passes through before the end signal end_tdc (second signal) is input is detected as the delay amount between the start signal start_tdc and the end signal end_tdc. Therefore, the delay amount can be easily detected by inputting each of the start signal start_tdc and the end signal end_tdc. Furthermore, according to the control circuit 30, semiconductor memory device, and control method of this embodiment, the transmission path of the reference clock signal clk_ref (first signal) in the delay line section 31 is controlled so that the number of delay units that the reference clock signal clk_ref (first signal) passes through is equal to the number of delay units detected by the detection unit 32 (i.e., the delay amount between the start signal start_tdc and the end signal end_tdc). Therefore, using this delay line section 31, it is possible to easily generate an output signal delayed by the said delay amount from the input signal (reference clock signal clk_ref). This allows for efficient estimation of the delay between the start signal (start_tdc) and the end signal (end_tdc), and the generation of an output signal corresponding to that delay.

[0046] In the embodiments described above, an example was described in which the delay unit Uk (where k is an integer between 1 and 8) comprises a NAND circuit N(2k-1) that delays the start signal start_tdc or the reference clock signal clk_ref (first signal), and a NAND circuit N(2k) connected to the output of the NAND circuit N(2k-1). However, the present invention is not limited to this case. For example, as shown in Figure 7, the delay unit Uk may comprise a NAND circuit N(2k-1), a NAND circuit N(2k), and a NAND circuit CNk connected between the NAND circuit N(2k-1) and a corresponding D flip-flop circuit FFk (latch section). Here, the NAND circuit N(2k-1) is an example of the "first delay element" of the present invention, the NAND circuit N(2k) is an example of the "second delay element" of the present invention, and the NAND circuit CNk is an example of the "third delay element" of the present invention. This makes it possible to delay a signal using three NAND circuits (delay elements).

[0047] In the example shown in Figure 7, one NAND circuit CN1 is provided between NAND circuit N1 and the corresponding D flip-flop circuit FF1, and one NAND circuit CN2 is provided between NAND circuit N3 and the corresponding D flip-flop circuit FF2. Furthermore, one NAND circuit CN3 is provided between NAND circuit N5 and the corresponding D flip-flop circuit FF3, and one NAND circuit CN4 is provided between NAND circuit N7 and the corresponding D flip-flop circuit FF4. In addition, one NAND circuit CN5 is provided between NAND circuit N9 and the corresponding D flip-flop circuit FF5, and one NAND circuit CN6 is provided between NAND circuit N11 and the corresponding D flip-flop circuit FF6. Furthermore, one NAND circuit CN7 is provided between NAND circuit N13 and the corresponding D flip-flop circuit FF7, and one NAND circuit CN8 is provided between NAND circuit N15 and the corresponding D flip-flop circuit FF8.

[0048] Furthermore, in the example shown in Figure 7, one input terminal of NAND circuit CN1 is connected to the output terminal of NAND circuit N1, and the output terminal of NAND circuit CN1 is connected to the D terminal of D flip-flop circuit FF1. Also, one input terminal of NAND circuit CN2 is connected to the output terminal of NAND circuit N3, and the output terminal of NAND circuit CN2 is connected to the D terminal of D flip-flop circuit FF2. In addition, one input terminal of NAND circuit CN3 is connected to the output terminal of NAND circuit N5, and the output terminal of NAND circuit CN3 is connected to the D terminal of D flip-flop circuit FF3. Furthermore, one input terminal of NAND circuit CN4 is connected to the output terminal of NAND circuit N7, and the output terminal of NAND circuit CN4 is connected to the D terminal of D flip-flop circuit FF4. Also, one input terminal of NAND circuit CN5 is connected to the output terminal of NAND circuit N9, and the output terminal of NAND circuit CN5 is connected to the D terminal of D flip-flop circuit FF5. Furthermore, one input terminal of NAND circuit CN6 is connected to the output terminal of NAND circuit N11, and the output terminal of NAND circuit CN6 is connected to the D terminal of D flip-flop circuit FF6. In addition, one input terminal of NAND circuit CN7 is connected to the output terminal of NAND circuit N13, and the output terminal of NAND circuit CN7 is connected to the D terminal of D flip-flop circuit FF7. Also, one input terminal of NAND circuit CN8 is connected to the output terminal of NAND circuit N15, and the output terminal of NAND circuit CN8 is connected to the D terminal of D flip-flop circuit FF8.

[0049] Each of the other input terminals of each NAND circuit CN1 to CN8 receives activation signals AS[C1] to AS[C8] to activate the corresponding NAND circuits CN1 to CN8. Here, the logical values ​​of each activation signal AS[C1] to AS[C8] may be set by the control unit 33. For example, in the delay amount estimation process described with reference to Figures 4 and 5, the control unit 33 may set the logical values ​​of each activation signal AS[C1] to AS[C8] to "1" (i.e., activate each of the NAND circuits CN1 to CN8). Alternatively, in the output signal generation process described with reference to Figure 6, the control unit 33 may set the logical values ​​of each activation signal AS[C1] to AS[C8] to "0" (i.e., deactivate each of the NAND circuits CN1 to CN8).

[0050] Furthermore, although the above-described embodiments and modifications explained as an example in which the delay line portion 31 is formed in a U-shape in plan view, the present invention is not limited to this case. The delay line portion 31 may be formed in a straight line, for example, as shown in Figure 8, or it may have a shape different from a U-shape or a straight line in plan view.

[0051] Furthermore, while the embodiments and modifications described above illustrate the case where one delay unit is provided in each bypass path BR1 to BR3, the present invention is not limited to this case. For example, at least one of the multiple bypass paths BR1 to BR3 may be provided with two or more delay units (delay elements).

[0052] Furthermore, although the above-described embodiments and modifications explained as an example where three bypass paths BR1 to BR3 are provided, the present invention is not limited to this case. The number of bypass paths may be arbitrarily set according to, for example, the number of delay units (delay elements) through which the input signal passes.

[0053] Furthermore, while the above-described embodiments and modifications mention the use of a NAND circuit as a delay element as an example, the present invention is not limited to this case. For example, other circuits such as inverter circuits or buffer circuits may be used as delay elements.

[0054] Furthermore, although the embodiments and modifications described above illustrate the case where the semiconductor memory device is DRAM as an example, the present invention is not limited to this case. For example, the semiconductor memory device may be SRAM (Static Random Access Memory), pSRAM (pseudo-Static Random Access Memory), flash memory, or other semiconductor memory devices. [Explanation of Symbols]

[0055] 30...Control circuit 31... Delay line section 32...Detection unit 33…Control Unit BR1, BR2, BR3... Bypass routes FF1, FF2, FF3, FF4, FF5, FF6, FF7, FF8... Flip-flop circuits N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,BN1,BN2,BN3,CN1,CN2,CN3,CN4,CN5,CN6,CN7,CN8...NAND circuit U1, U2, U3, U4, U5, U6, U7, U8… Delay Units clk_ref…Reference clock signal clk_fb... Feedback signal end_tdc...end signal start_tdc…start signal

Claims

1. A delay line section into which a first signal is input, wherein the delay line section includes a plurality of delay units connected in series, and each of the plurality of delay units delays the input first signal. A detection unit to which a second signal, which is a delayed signal of the first signal, is input, and when the second signal is input after the first signal has been input to the delay line section, the detection unit detects the number of delay units that the first signal has passed through before the second signal was input, among the plurality of delay units. The system includes a control unit that controls the transmission path of the first signal in the delay line section so that the number of delay units the first signal passes through before it is output from the delay line section is equal to the number of delay units detected by the detection unit, Control circuit.

2. The control unit controls the transmission of the first signal through a bypass path formed in the delay line section such that the number of delay units the first signal passes through before it is output from the delay line section is equal to the number of delay units detected by the detection unit. The control circuit according to claim 1.

3. The delay line section has multiple bypass paths formed therein, each with a different number of delay units through which the first signal passes before being output from the delay line section. The control unit selects a bypass path from among the plurality of bypass paths such that the number of delay units the first signal passes through before being output from the delay line section is equal to the number of delay units detected by the detection unit, and controls the transmission of the first signal through the selected bypass path. The control circuit according to claim 2.

4. The bypass path includes at least one delay unit, The control circuit according to claim 2.

5. The detection unit is Each of the plurality of delay units has a latching section that latches the signal output from the corresponding delay unit when the second signal is input. When the second signal is input, the number of delay units among the plurality of delay units for which a signal with the same value as the first signal is latched by the corresponding latch unit is detected as the number of delay units through which the first signal has passed before the second signal is input. The control circuit according to claim 1.

6. At least one of the plurality of delay units comprises a first delay element for delaying the first signal, a second delay element connected to the output of the first delay element, and a third delay element connected between the first delay element and a corresponding latching unit. The control circuit according to claim 5.

7. The latch section includes a flip-flop circuit, The control circuit according to claim 5.

8. The aforementioned flip-flop circuit includes a D flip-flop circuit. The control circuit according to claim 7.

9. The aforementioned delay line section is formed in a U-shape in plan view. The control circuit according to claim 1.

10. Each of the plurality of delay units includes one or more delay elements that delay the first signal. The control circuit according to claim 1.

11. Each of the plurality of delay units includes an even number of NAND circuits as one or more delay elements. The control circuit according to claim 10.

12. Each of the plurality of delay units includes two NAND circuits as one or more delay elements. The control circuit according to claim 11.

13. A control circuit according to any one of claims 1 to 12, Semiconductor memory device.

14. A control method executed by a control circuit provided in a semiconductor memory device, A delay line section into which a first signal is input, comprising a plurality of delay units connected in series, each of the plurality of delay units delaying the input first signal; a step of detecting the number of delay units through which the first signal has passed before the input of the second signal when a second signal, which is a delayed signal of the first signal, is input to the control circuit after the first signal has been input to the delay line section; The process includes the step of controlling the transmission path of the first signal in the delay line section such that the number of delay units the first signal passes through before it is output from the delay line section is equal to the number of detected delay units. A method for controlling semiconductor memory devices.

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