Control chip and switching power supply

Abstract

Perform proper testing of the power supply circuit. [Solution] A control chip is provided that controls the switching elements of a switching power supply, which is supplied with input power from a power supply circuit and supplies output power to a load, and has at least two operating modes: a power supply test mode for testing the power supply circuit and a normal operating mode, and includes a feedback terminal to which a feedback signal corresponding to the output voltage applied to the load is input, and a power supply test mode switching unit that switches between the power supply test mode and the normal operating mode according to a switching signal input to the feedback terminal.

Description

Technical Field

[0001] The present invention relates to a control chip and a switching power supply.

Background Art

[0002] Patent Document 1 describes that a power supply control IC has "a test mode different from a normal operation mode (paragraph 0002)" and performs "an IC test (paragraph 0007)" in the test mode. Patent Document 2 describes "a method of using a fast clock instead of an actual machine clock to reduce test time (paragraph 0002)". Patent Document 3 describes that "when a setting circuit generates a test mode setting output, the output clock of a clock generation circuit is output to an internal circuit in place of the external input clock (claim 1)". [Patent Document 1] Japanese Patent Laid-Open No. 2007-258294 [Patent Document 2] Japanese Patent Laid-Open No. 5-11025 [Patent Document 3] Japanese Patent Laid-Open No. 3-204951

Summary of the Invention

Problem to be Solved by the Invention

[0003] In the test mode for testing the power supply control IC itself, testing of the power supply circuit used in the switching power supply is not taken into consideration, so the test of the power supply circuit cannot be appropriately performed.

Means for Solving the Problem

[0004] To solve the above problems, a first embodiment of the present invention provides a control chip that controls the switching elements of a switching power supply, which receives input power from a power supply circuit and supplies output power to a load. The control chip may have at least two operating modes: a power supply test mode for testing the power supply circuit and a normal operation mode. Any of the control chips may have a feedback terminal to which a feedback signal corresponding to the output voltage applied to the load is input. Any of the control chips may have a power supply test mode switching unit that switches between the power supply test mode and the normal operation mode in response to a switching signal input to the feedback terminal.

[0005] Any of the above control chips may have power terminals to which a power supply voltage for driving the control chip is applied. In any of the above control chips, the power test mode switching unit may switch between the power test mode and the normal operation mode in accordance with the power supply voltage applied to the power terminals and the switching signal.

[0006] Any of the above control chips may include a low-voltage detection unit that stops the switching operation of the switching element when the power supply voltage is lower than the set release voltage. In any of the above control chips, the power test mode switching unit may operate the control chip in the power test mode when the switching signal is input while the power supply voltage is lower than the release voltage.

[0007] Any of the control chips described above may shorten the overload protection detection delay time in the power test mode compared to the normal operation mode.

[0008] Any of the above control chips may have a time detection unit that detects when the overload protection detection delay time has elapsed based on the input clock signal. Any of the above control chips may have a time reduction unit that shortens the overload protection detection delay time by making the period of the clock signal input to the time detection unit in the power test mode shorter than the period of the clock signal input to the time detection unit in the normal operation mode.

[0009] Any of the above control chips may have a circuit test mode for testing the control chip as one of its operating modes. Any of the above control chips may operate in a way that is closer to the normal operating mode than to the circuit test mode in the power supply test mode.

[0010] Any of the control chips described above may shorten the overload protection detection delay time and the initial setup period in the circuit test mode compared to the normal operation mode.

[0011] The power supply circuit may include an AC power supply and a smoothing capacitor provided between the positive and negative output terminals of the AC power supply. Any of the control chips may have a power supply detection terminal connected to the power supply circuit. Any of the control chips may have a discharge unit that discharges the smoothing capacitor when the voltage input to the power supply detection terminal is a DC voltage. Any of the control chips may stop the discharge unit in the circuit test mode and operate the discharge unit in the normal operation mode and the power supply test mode.

[0012] Any of the above control chips may have a frequency spreading unit that varies the switching frequency of the switching element. Any of the above control chips may stop the frequency spreading unit in the circuit test mode and operate the frequency spreading unit in the normal operation mode and the power supply test mode.

[0013] In a second aspect of the present invention, a control chip is provided that controls the switching elements of a switching power supply, which receives input power from a power supply circuit and supplies output power to a load. The control chip may have at least three operating modes: a circuit test mode for testing the control chip, a power supply test mode for testing the power supply circuit, and a normal operation mode.

[0014] In a third embodiment of the present invention, a switching power supply is provided that supplies output power to a load based on input power. The switching power supply may include a power supply circuit that generates the input power. Any of the above switching power supplies may include switching elements. Any of the above switching power supplies may include a control chip of the first or second embodiment that controls the switching elements.

[0015] Any of the above-described switching power supplies may include a switching signal generation unit that inputs a switching signal having a set voltage to the feedback terminal when the output voltage is lower than a predetermined threshold voltage, and stops inputting the switching signal to the feedback terminal when the output voltage is equal to or greater than the threshold voltage.

[0016] A fourth embodiment of the present invention provides a switching power supply that supplies output power to a load based on input power. The switching power supply may include a power supply circuit that generates the input power. Any of the above switching power supplies may include a switching element. Any of the above switching power supplies may include a control chip that controls the switching element. In any of the above switching power supplies, the control chip may have a feedback terminal to which a feedback signal corresponding to the output voltage applied to the load is input. Any of the above switching power supplies may include a switching signal generation unit that inputs a switching signal having a set voltage to the feedback terminal when the output voltage is lower than a predetermined threshold voltage, and stops inputting the switching signal to the feedback terminal when the output voltage is equal to or greater than the threshold voltage.

[0017] In any of the above-described switching power supplies, the control chip may have at least two operating modes: a power test mode for testing the power supply circuit and a normal operating mode. In any of the above-described switching power supplies, the control chip may switch between the power test mode and the normal operating mode in response to a switching signal input to the feedback terminal.

[0018] In any of the above-described switching power supplies, the control chip may have power terminals to which a power supply voltage for driving the control chip is applied. In any of the above-described switching power supplies, the control chip may switch between the power test mode and the normal operation mode in response to the power supply voltage applied to the power terminals and the switching signal.

[0019] In any of the above switching power supplies, the control chip may have a low-voltage detection unit that stops the switching operation of the switching element when the power supply voltage is lower than a set release voltage. In any of the above switching power supplies, the control chip may switch to the power supply test mode when the switching signal is input while the power supply voltage is lower than the release voltage. [Brief explanation of the drawing]

[0020] [Figure 1] This figure shows an example of a switching power supply 300. [Figure 2] This figure shows an example configuration of the control chip 100. [Figure 3] This figure shows an example of the time waveforms of each voltage and clock signal in normal operating mode. [Figure 4] This figure shows an example of the time waveforms of each voltage and clock signal when transitioning to power test mode. [Figure 5] This figure shows an example of the time waveforms of each voltage and clock signal when transitioning to circuit test mode. [Figure 6] This diagram illustrates an example of operation during the initial setup period. [Figure 7] It is a diagram schematically illustrating a normal operation mode, a circuit test mode, and a power supply test mode. [Figure 8] It is a diagram showing a configuration example of a power supply test mode switching unit 34 and a time shortening unit 46. [Figure 9] It is a diagram showing a configuration example of a clock generation unit 60.

Mode for Carrying Out the Invention

[0021] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention claimed in the scope of patent claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention. In the present specification and the drawings, elements having substantially the same function and configuration are denoted by the same reference numerals to omit repeated description, and illustration of elements not directly related to the present invention is omitted. Furthermore, in one drawing, elements having the same function and configuration may be representatively denoted by reference numerals, and reference numerals for other elements may be omitted. In the present specification, when the terms "identical" or "equal" are used, they may also include cases where an error caused by manufacturing variation or the like is included. Such error is, for example, within 10%.

[0022] In the description of a circuit, when it is described that an element C is provided "between" an element A and an element B, this means that the element C is provided between the element A and the element B in an electrical path. The above description does not limit the spatial position of the element C.

[0023] In the present specification, when two elements are described as being "electrically connected", this refers to a state where electrical signals, voltage, or current can be transmitted between the two elements. The two elements may be directly connected to each other via wiring or the like, and another electrical element may be interposed between the two elements.

[0024] Figure 1 shows an example of a switching power supply 300. The switching power supply 300 receives input power from the power supply circuit 230 and supplies output power to the load. The switching power supply 300 generates a predetermined voltage or current in the secondary winding 112 of the main transformer 110 by repeatedly controlling the switching element 120 connected to the primary winding 111 of the main transformer 110 to an on state and an off state. The switching power supply 300 in this example comprises a power supply circuit 230, a primary circuit 210, a secondary circuit 220, a switching signal generation unit 180, and a main transformer 110.

[0025] The primary circuit 210 may include a power supply circuit 230. The power supply circuit 230 supplies power to the primary circuit 210. In this example, the power supply circuit 230 includes an AC power supply 142, a coil 144, a smoothing capacitor 146, a diode bridge section 148, a diode 150, a diode 152, and a capacitor 154. The AC power supply 142 may be an external power supply such as a commercial power supply.

[0026] Coil 144 is connected to the AC power supply 142. Coil 144 may be provided for both the positive and negative output terminals of the AC power supply 142. Coil 144 may also be a transformer connected to the positive and negative output terminals of the AC power supply 142. Smoothing capacitor 146 is provided between the positive and negative output terminals of the AC power supply 142. Coil 144 and smoothing capacitor 146 remove noise from the AC power output by the AC power supply 142.

[0027] The diode bridge section 148 full-wave rectifies the AC power output by the AC power supply 142. The capacitor 154 smooths the power rectified by the diode bridge section 148. As a result, the power supply circuit 230 rectifies and smooths the voltage and current from the AC power supply 142 and outputs them.

[0028] The primary side circuit 210 in this example includes a control chip 100, a primary side winding 111, a switching element 120, a resistor 130, an auxiliary winding 113, a diode 128, a resistive element 122, a capacitor 131, a capacitor 134, a capacitor 136, a resistor 132, a resistor 138, a capacitor 139, and a resistor 140. Power is supplied to the primary side winding 111 in this example from the power supply circuit 230.

[0029] The secondary circuit 220 in this example includes a secondary winding 112, a diode 160, a capacitor 162, a light-emitting element 164, a resistor 166, and a diode 168. The secondary winding 112 is magnetically coupled to the primary winding 111. The light-receiving element 170 shown in Figure 1 may be provided in the primary circuit 210.

[0030] The switching element 120 controls the main current flowing through the main transformer 110. In this example, the switching element 120 is connected in series with the primary winding 111 and controls whether or not to allow the main current to flow through the primary winding 111. The switching element 120 is, for example, a power MOSFET. A resistor 130 is provided between the switching element 120 and the reference potential. The resistor 130 is a resistor for detecting the magnitude of the main current.

[0031] The control chip 100 controls the on and off states of the switching element 120. The control chip 100 may output a control signal to be input to the gate terminal of the switching element 120. The control chip 100 is, for example, a semiconductor integrated circuit chip. In this example, the control chip 100 has a LAT terminal, an FB terminal (feedback terminal), a CS terminal, a GND terminal, a VH terminal (power supply detection terminal), a VCC terminal (power supply terminal), and an OUT terminal.

[0032] When the switching element 120 is turned on and an excitation current flows through the primary winding 111, a load current corresponding to the turns ratio flows through the secondary winding 112. The load current flowing through the secondary winding 112 is rectified by the diode 160. The output of the diode 160 charges the capacitor 162. An output voltage Vout is applied to the load according to the amount of charge stored in the capacitor 162.

[0033] The auxiliary winding 113 supplies power to the VCC terminal. The VCC terminal is a power supply terminal to which the power supply voltage that drives the control chip 100 is applied. In this example, the auxiliary winding 113 is positioned between the VCC terminal of the control chip 100 and a reference potential. The auxiliary winding 113 is magnetically coupled to the secondary winding 112. That is, a current flows through the auxiliary winding 113 corresponding to the current in the secondary winding 112. A resistor 122 and a diode 128 may be placed between the auxiliary winding 113 and the VCC terminal. The diode 128 rectifies the current flowing through the auxiliary winding 113. The resistor 122 is positioned between the diode 128 and the VCC terminal. The capacitor 131 is charged by the current that passes through the diode 128.

[0034] Capacitor 131 is electrically connected to the VCC terminal of the control chip 100. The power stored in capacitor 131 is supplied as the power supply power for the control chip 100. In this example, capacitor 131 is an electrolytic capacitor. The capacitance of capacitor 131 may be larger than that of capacitors 134 and 136.

[0035] The control chip 100 may have a CS terminal for detecting the magnitude of the main current (in this example, the drain current) flowing through the switching element 120. The CS terminal captures a potential that indicates the magnitude of the voltage drop across the resistor 130. Since a voltage drop occurs across the resistor 130 corresponding to the magnitude of the main current, the magnitude of the main current can be detected from this potential. In this example, the CS terminal captures the potential at the end of the resistor 130 connected to the switching element 120. A filter consisting of a resistor 132 and a capacitor 134 may be provided between the CS terminal and the resistor 130. If an overcurrent is flowing through the switching element 120, the control chip 100 may control the switching element 120 to an off state.

[0036] A feedback signal corresponding to the output voltage Vout applied to the load from the secondary circuit 220 is input to the FB terminal. The light-emitting element 164, resistor 166, and diode 168 in the secondary circuit 220 are arranged in series between the terminal that outputs the output voltage Vout and the reference potential. A current corresponding to the magnitude of the output voltage Vout flows through the light-emitting element 164, and it outputs light of an intensity corresponding to the magnitude of the current. The light-emitting element 164 is, for example, a light-emitting diode.

[0037] The light-receiving element 170 receives the light output by the light-emitting element 164. The light-receiving element 170 is, for example, a phototransistor. The light-receiving element 170 inputs a current to the FB terminal corresponding to the intensity of the received light. As a result, a current corresponding to the output voltage Vout flows through the FB terminal. This generates a voltage at the FB terminal corresponding to the output voltage Vout, which becomes the output voltage detection signal (feedback signal). The current flowing through the FB terminal increases as the output voltage Vout increases, and decreases as the output voltage Vout decreases. The primary circuit 210 may have a capacitor 136 connected in parallel with the light-receiving element 170. This allows for the removal of high-frequency components from the current flowing through the FB terminal.

[0038] The voltage at the FB terminal changes according to the output voltage Vout. The control chip 100 controls the on and off periods of the switching element 120 according to the voltage at the FB terminal. For example, the higher the output voltage Vout is above the target voltage, the shorter the on period of the switching element 120 in each switching cycle.

[0039] In this example, the VH terminal is connected to the power supply circuit 230 via diode 150, diode 152, and resistor 140. When the switching power supply 300 is started up, the VH terminal supplies a charging current to the VCC terminal based on the power from the power supply circuit 230. This charges the capacitor 131 connected to the VCC terminal. When the voltage across capacitor 131 rises and the control chip 100 starts switching control, the supply of charging current from the VH terminal stops. This allows for faster startup of the control chip 100 while reducing power consumption.

[0040] In this example, the LAT terminal is used to perform the initial setup of the control chip 100. By adjusting the voltage of the LAT terminal during the initial setup period of the control chip 100, the functions of the control chip 100 are set. The functions of the control chip 100 include, for example, the X-CAP discharge function and the frequency spreading function. Details of these functions will be described later. In this example, the control chip 100 can enable or disable these functions by adjusting the voltage of the LAT terminal to a predetermined range at a predetermined timing during the initial setup period.

[0041] In this example, a resistor 138 and a capacitor 139 are connected in parallel between the LAT terminal and the reference potential. During the initial setup period, the control chip 100 outputs a constant current from the LAT terminal. Therefore, the voltage waveform at the LAT terminal is determined by the resistance value of resistor 138 and the capacitance of capacitor 139. By adjusting the resistance value of resistor 138 and the capacitance of capacitor 139, the voltage waveform at the LAT terminal can be adjusted, and the control chip 100 can be initially set up. During the initial setup period, the resistance value of resistor 138 and the capacitance of capacitor 139 may be varied.

[0042] The control chip 100 in this example has at least two operating modes: a power test mode for testing the power supply circuit 230 and a normal operation mode. In normal operation mode, the control chip 100 supplies output power to the load based on the input power from the power supply circuit 230. The power test mode may be, for example, a test of the switching power supply 300 performed by the user of the switching power supply 300.

[0043] In power test mode, some parameters within the control chip 100 are set to a different state than in normal operation mode. In this example, the control chip 100 shortens the overload protection detection delay time in power test mode compared to normal operation mode.

[0044] The overload protection detection delay time is the time from the detection of an overload until the start of the protection operation. For example, the control chip 100 determines that an overload condition exists when the output power to the load exceeds a threshold. The control chip 100 performs a protection operation if the overload condition persists for the overload protection detection delay time. The protection operation may be, for example, stopping the switching operation of the switching element 120 and fixing it in the off state. By providing an overload protection detection delay time, it is possible to suppress the switching element 120 from stopping due to false detection of an overload condition caused by noise, etc. The overload protection detection delay time may be set to, for example, a few seconds.

[0045] Even in power supply test mode, the switching power supply 300 may be tested under an overload condition. However, if the overload protection detection delay time is left unchanged, the test will take a long time. As mentioned above, in power supply test mode, the power supply circuit 230 can be tested efficiently by shortening the overload protection detection delay time. For example, in power supply test mode, the overload protection detection delay time may be reduced to half or less, to one-quarter or less, or to one-tenth or less, compared to normal operation mode.

[0046] On the other hand, in power test mode, it is preferable to operate the control chip 100 in a state close to that of normal operation mode. This allows the power supply circuit 230 and the control chip 100 to be tested in an environment close to that of normal operation mode. For example, among the parameters that can be set in the control chip 100, parameters other than the length of the overload protection detection delay time do not need to be changed between power test mode and normal operation mode.

[0047] For example, the delay time settings other than the overload protection detection delay time do not need to be changed between power test mode and normal operation mode. Also, the control chip 100 does not need to shorten its initial setup period in power test mode compared to normal operation mode. The initial setup period will be described later. Furthermore, the settings for enabling or disabling functions of the control chip 100, such as the X-CAP discharge function and the frequency spreading function, do not need to be changed between power test mode and normal operation mode.

[0048] The control chip 100 may further have a circuit test mode as an operating mode for testing the control chip 100. In the circuit test mode, the control chip 100 may be tested with the AC power supply 142 or power supply circuit 230 not connected. The control chip 100 operates closer to its normal operating mode in the power supply test mode than in the circuit test mode. For example, in the circuit test mode, the control chip 100 shortens the overload protection detection delay time and the initial setup period compared to the normal operating mode.

[0049] For example, in circuit test mode, delay times other than the overload protection detection delay time may be set shorter than in normal operation mode. This allows the control chip 100 to be tested in a shorter time. Also, in circuit test mode, the X-CAP discharge function and the frequency spreading function may be disabled. This also allows the control chip 100 to be tested in a shorter time, excluding those functions.

[0050] The control chip 100 may switch between a power test mode and a normal operation mode in response to a switching signal input to the FB terminal. The switching signal is a different signal from the feedback signal corresponding to the output voltage Vout. In other words, both the switching signal and the feedback signal corresponding to the output voltage Vout are input to the FB terminal. By switching the operation mode using the FB terminal, the operation mode can be switched without increasing the number of terminals on the control chip 100.

[0051] In this example, the switching signal is generated by the switching signal generation unit 180. The switching signal generation unit 180 inputs a switching signal of a predetermined voltage to the FB terminal when the output voltage Vout is lower than a predetermined threshold voltage. The switching signal generation unit 180 also stops inputting the switching signal to the FB terminal when the output voltage Vout is equal to or greater than the threshold voltage. When the input of the switching signal is stopped, a feedback signal indicating the magnitude of the output voltage Vout is input to the FB terminal. In this example, the switching signal is input to the FB terminal when the output voltage Vout is low, such as when the switching power supply 300 is started up.

[0052] The switching signal generation unit 180 in this example includes a light-emitting element 182, a diode 184, a light-receiving element 186, a power supply 188, a resistor 190, and a transistor 192. The light-emitting element 182 and the diode 184 are provided in series between the terminal that outputs the output voltage Vout and the reference potential. A current corresponding to the magnitude of the output voltage Vout flows through the light-emitting element 182, and it outputs light of an intensity corresponding to the magnitude of the current. The light-emitting element 182 is, for example, a light-emitting diode.

[0053] The light-receiving element 186 receives light output from the light-emitting element 182. The light-receiving element 186 is, for example, a phototransistor. The light-receiving element 186 causes a current corresponding to the intensity of the received light to flow through the resistor 190. The resistor 190 is located between the power supply 188 and the light-receiving element 186. The voltage at the connection node between the resistor 190 and the light-receiving element 186 is determined by the current flowing through the resistor 190.

[0054] Transistor 192 has control terminals, such as its base or gate terminal, connected to the connection node. Transistor 192 switches whether or not to connect power supply 188 to the FB terminal. When the output voltage Vout is lower than the threshold voltage and the current flowing through resistor 190 is small, the voltage drop across resistor 190 is small, and the voltage at the connection node is maintained at a high level. In this case, transistor 192 in this example is ON, and the voltage Vps of power supply 188 is input to the FB terminal as a switching signal. When the output voltage Vout is above the threshold voltage and the current flowing through resistor 190 increases, the voltage drop across resistor 190 increases. In this case, transistor 192 in this example is OFF, and power supply 188 is disconnected from the FB terminal. As a result, a voltage corresponding to the output voltage Vout is input to the FB terminal.

[0055] The power supply 188 may be provided by the user of the switching power supply 300 when testing the power supply circuit 230. The user may connect the power supply 188 for generating the switching signal to the switching power supply 300 when testing the power supply circuit 230. The configuration of the switching signal generation unit 180 other than the power supply 188 may be pre-built into the switching power supply 300 or prepared by the user.

[0056] Figure 2 shows an example configuration of the control chip 100. The configuration of each terminal of the control chip 100 is the same as in the example shown in Figure 1. However, the GND terminal is omitted in Figure 2. The reference potential applied to the GND terminal may be used as the reference potential of the internal circuit of the control chip 100.

[0057] The control chip 100 in this example includes a startup voltage generation unit 10, a low voltage detection unit 12, a discharge unit 14, and a startup control unit 16. These components are connected directly or indirectly to the VH terminal or VCC terminal.

[0058] The startup voltage generation unit 10 charges the capacitor 131 (see Figure 1) based on the voltage Vvh at the VH terminal when the switching power supply 300 is started. The startup voltage generation unit 10 may charge the capacitor 131 in response to the startup signal startup. This makes it possible to increase the power supply voltage Vvcc of the control chip 100 during the period when the current flowing through the auxiliary winding 113 is small when the switching power supply 300 is started.

[0059] The low voltage detection unit 12 detects whether the power supply voltage Vvc has become equal to or greater than a predetermined release voltage vref_uvlo. If the power supply voltage Vvc is less than the release voltage vref_uvlo, the low voltage detection unit 12 outputs a reset signal rst to stop the operation of at least some of the circuits of the control chip 100 or to return to the initial state. For example, if the power supply voltage Vvc is less than the set release voltage vref_uvlo, the low voltage detection unit 12 stops the switching operation of the switching element 120.

[0060] The startup control unit 16 outputs a startup signal startup in response to the reset signal rst. The startup control unit 16 may output a startup signal startup when the power supply voltage VVCC is less than the release voltage vref_uvlo. As a result, when the power supply voltage VVCC is less than the release voltage vref_uvlo, the startup voltage generation unit 10 generates the power supply voltage VVCC, and when the power supply voltage VVCC is equal to or greater than the release voltage vref_uvlo, the power supply voltage VVCC can be generated by the current flowing through the auxiliary winding 113. The startup control unit 16 may also generate a startup signal startup using the latch signal latch and the discharge signal xcapdis, which will be described later.

[0061] The discharge unit 14 discharges the smoothing capacitor 146 (see Figure 1) when the voltage Vvh input to the VH terminal is a DC voltage (X-CAP discharge function). The discharge unit 14 may determine that the voltage Vvh is a DC voltage if the fluctuation (amplitude) of the voltage Vvh remains below a reference value for a reference time or longer.

[0062] When the AC power supply 142 is disconnected, the smoothing capacitor 146 retains charge from the AC power supply 142. If charge remains in the smoothing capacitor 146, there is a risk of electric shock. Therefore, it is preferable to discharge the smoothing capacitor 146 when the voltage Vvh becomes a DC voltage.

[0063] The discharge unit 14 may discharge the smoothing capacitor 146 by extracting charge through diodes 150 and 152. This eliminates the need to provide a discharge resistor in parallel with the smoothing capacitor 146 to discharge it. As a result, losses due to the discharge resistor in normal operating modes can be eliminated.

[0064] The discharge unit 14 may input a discharge signal xcapdis to the startup control unit 16 when it discharges the smoothing capacitor 146. The startup control unit 16 outputs a startup signal startup when the smoothing capacitor 146 is discharged. As a result, the startup voltage generation unit 10 generates the power supply voltage Vvcc.

[0065] In this example, the discharge unit 14 may be stopped by the circuit test mode signal test_ic, which indicates that the control chip 100 is in circuit test mode. This allows the X-CAP discharge function to be disabled in circuit test mode. The X-CAP discharge function may be enabled in normal operation mode and power supply test mode.

[0066] In circuit test mode, a voltage is input to the VH terminal of the control chip 100 from the test equipment. Even if the test equipment cannot apply an AC voltage to the VH terminal, the control chip 100 can be tested by disabling the X-CAP discharge function. On the other hand, by enabling the X-CAP discharge function in power supply test mode, the power supply circuit 230 can be tested in an environment similar to the normal operating mode.

[0067] The discharge unit 14 may operate according to the operating clock clk_xcap. The operating clock clk_xcap is generated by the clock generation unit 60, which will be described later. The period of the operating clock clk_xcap may be constant in both the normal operation mode and the power supply test mode. The period of the operating clock clk_xcap in the circuit test mode may be shorter than the period of the operating clock clk_xcap in the other operation modes.

[0068] The discharge unit 14 may be configured to enable or disable the X-CAP discharge function according to the initial setting signal ini_sel2. The initial setting signal ini_sel2 is generated by the initial setting unit 50.

[0069] The control chip 100 in this example includes an initial setting unit 50 and a circuit test mode switching unit 52. These components are connected directly or indirectly to the LAT terminal.

[0070] The initial setting unit 50 sets each parameter of the control chip 100 according to the voltage Vlat at the LAT terminal. The user can adjust the voltage Vlat using the resistor 138 and capacitor 139 (see Figure 1) to set each parameter of the control chip 100.

[0071] In this example, the initial setup unit 50 receives the voltage Vlat, the reference voltage vref_ini, the operation clock clk_ini, and the reset signal rst as inputs. The voltage value of the reference voltage vref_ini is set in advance. The control chip 100 may have a voltage generation circuit that generates the reference voltage vref_ini. Based on the comparison result between the voltage Vlat and the reference voltage vref_ini, the initial setup unit 50 generates one or more initial setup signals ini_sel1, ini_sel2, and ini_end.

[0072] As described above, the initial setup signal ini_sel2 is a signal that disables the X-CAP discharge function. In other words, the X-CAP discharge function can be disabled by user settings. The initial setup signal ini_sel1 is a signal that sets the magnitude of the reference value for determining whether or not an overload state is present in the overload detection unit 40, which will be described later. The initial setup signal ini_end is a signal that indicates whether or not the initial setup period has ended. The initial setup unit 50 may output the initial setup signal ini_end when a predetermined period has elapsed since the reset signal rst was released. This period may be measured by counting the pulses of the operating clock clk_ini.

[0073] The circuit test mode switching unit 52 outputs a circuit test mode signal test_ic that transitions to circuit test mode based on the voltage Vlat at the LAT terminal. In this example, the circuit test mode switching unit 52 receives the voltage Vlat, the reference voltage vref_test_ic, and the reset signal rst as inputs.

[0074] In this example, the circuit test mode switching unit 52 generates a circuit test mode signal test_ic based on the comparison result between the voltage Vlat and the reference voltage vref_test_ic. For example, the circuit test mode switching unit 52 generates the circuit test mode signal test_ic when the voltage Vlat at the time the reset signal rst is released (i.e., when the power supply voltage Vvcc becomes equal to or greater than the release voltage vref_uvlo) is equal to or greater than the reference voltage vref_test_ic. Through this operation, the control chip 100 can be switched to circuit test mode.

[0075] The control chip 100 in this example includes a transistor 36, a resistor 37, a frequency spreader 20, an oscillator circuit 22, a one-shot circuit 24, a comparator circuit 26, a flip-flop 28, a logical OR circuit 30, a driver circuit 32, and a power supply test mode switching unit 34. These components are connected directly or indirectly to the FB terminal or the OUT terminal.

[0076] Transistor 36 switches whether or not to connect the voltage line Vdd to the FB terminal according to the initial setup signal ini_end. The voltage of the voltage line Vdd may be generated internally by the control chip 100. A resistor 37 is connected in series between transistor 36 and the FB terminal. In this example, transistor 36 connects the voltage line Vdd to the FB terminal when the initial setup period is over. In this case, the voltage Vfb at the FB terminal is determined by the current flowing through the photodetector 170 according to the output voltage Vout. As a result, after the initial setup period ends, the control chip 100 operates according to the output voltage Vout.

[0077] Before the initial setup period ends, transistor 36 disconnects the voltage line Vdd from the FB terminal. In this case, the switching signal generated by the switching signal generation unit 180 is input to the FB terminal as the voltage Vfb.

[0078] The oscillation circuit 22 generates an oscillation signal with a period corresponding to the voltage Vfb. The oscillation circuit 22 may have a voltage-controlled oscillator (VCO).

[0079] The one-shot circuit 24 outputs a pulse of a predetermined width according to the period of the oscillation signal from the oscillation circuit 22. For example, the one-shot circuit 24 outputs the pulse at each rising edge of the oscillation signal.

[0080] The comparison circuit 26 outputs the result of comparing the voltage Vfb with the voltage Vcs at the CS terminal. In this example, the comparison circuit 26 outputs an L logic when the voltage Vfb is lower than the voltage Vcs, and an H logic when it is higher.

[0081] The flip-flop 28 receives the pulse from the one-shot circuit 24 as input to its set terminal, and the output of the comparator circuit 26 as input to its reset terminal. In this example, the flip-flop 28 outputs high logic from the time the pulse from the one-shot circuit 24 is input until the voltage Vfb becomes higher than the voltage Vcs.

[0082] The OR circuit 30 outputs the OR of the pulse output by the one-shot circuit 24 and the pulse output by the flip-flop 28. The driver circuit 32 outputs a control voltage Vg to the OUT terminal corresponding to the output of the OR circuit 30. The switching element 120 is controlled by the control voltage Vg. The driver circuit 32 controls the switching element 120 to the ON state in response to the pulse of the one-shot circuit 24, and may control the switching element 120 to the OFF state when the voltage Vfb becomes higher than the voltage Vcs.

[0083] The driver circuit 32 may receive a latch signal and a reset signal rst. When at least one of the reset signal rst and the latch signal latct is input to the driver circuit 32, it may output a control voltage Vg at an L level to control the switching element 120 to the OFF state.

[0084] The frequency spreading unit 20 varies the switching frequency of the switching element 120. For example, the frequency spreading unit 20 periodically varies the switching frequency of the switching element 120. The variation range of the switching frequency is, for example, within ±10%, but is not limited thereto. The frequency spreading unit 20 may vary the switching frequency by superimposing periodic jitter on the control signal that controls the switching element 120. The control signal may be an oscillation signal output by the oscillation circuit 22, a pulse output by the one-shot circuit 24, or a control voltage Vg output by the driver circuit 32. In this example, the frequency spreading unit 20 superimposes jitter on the oscillation signal. The frequency spreading unit 20 may superimpose jitter on the oscillation signal by periodically varying the oscillation frequency of the oscillation circuit 22. By varying the switching frequency, the energy of noise due to switching can be dispersed along the frequency axis. This reduces conducted EMI.

[0085] In circuit test mode, the frequency spreading unit 20 may be stopped, while in normal operation mode and power supply test mode, the frequency spreading unit 20 may be operated. In this example, the frequency spreading unit 20 receives the circuit test mode signal test_ic. The frequency spreading unit 20 may determine whether or not to superimpose jitter on the oscillation signal according to the circuit test mode signal test_ic.

[0086] By disabling the frequency spreading function in circuit test mode, the switching frequency generated by the control chip 100 can be measured with high accuracy. On the other hand, by enabling the frequency spreading function in power supply test mode, the power supply circuit 230 and the control chip 100 can be tested in an environment close to the normal operating mode.

[0087] The power test mode switching unit 34 switches between power test mode and normal operation mode according to the switching signal (voltage Vfb in this example) input to the FB terminal. In this example, the power test mode switching unit 34 receives the voltage Vfb, the reference voltage vref_test_ps, and the reset signal rst.

[0088] The power test mode switching unit 34 may switch the operating mode according to the comparison result between the voltage Vfb and the reference voltage vref_test_ps. In this example, the power test mode switching unit 34 outputs a power test mode signal test_ps that transitions to the power test mode, provided that the voltage Vfb is greater than the reference voltage vref_test_ps. The power supply 188 shown in Figure 1 outputs a voltage Vps that is greater than the reference voltage vref_test_ps. Therefore, the power test mode switching unit 34 outputs the power test mode signal test_ps, provided that the voltage Vps is input as the voltage Vfb.

[0089] The power test mode switching unit 34 may switch between power test mode and normal operation mode depending on the power supply voltage Vvcc applied to the VCC terminal and the switching signal (or voltage Vfb). For example, the power test mode switching unit 34 operates the control chip 100 in power test mode when the power supply voltage Vvcc is less than the release voltage vref_uvlo and the switching signal (voltage Vps of power supply 188) is input as voltage Vfb. In this example, the power test mode switching unit 34 operates the control chip 100 in power test mode when the switching signal is input before the reset signal rst is input. The power test mode switching unit 34 may also output a power test mode signal test_ps when the voltage Vfb (e.g., voltage Vps) at the time the reset signal rst is input is greater than the reference voltage vref_test_ps.

[0090] The control chip 100 in this example includes an overload detection unit 40, a time detection unit 42, a latch unit 44, and a time reduction unit 46. These components are connected directly or indirectly to the CS terminal.

[0091] The overload detection unit 40 detects an overload condition by comparing the voltage Vcs of the CS terminal with a set reference value vref_olp. The overload detection unit 40 may determine that an overload condition exists if the voltage Vcs is greater than the reference value vref_olp. In this example, the overload detection unit 40 receives the voltage Vcs, a first reference value vref_olp1, a second reference value vref_olp2, and an initial setting signal ini_sel1 as inputs. The first reference value vref_olp1 may be greater than or less than the second reference value vref_olp2. Based on the initial setting signal ini_sel1, the overload detection unit 40 selects either the first reference value vref_olp1 or the second reference value vref_olp2 and compares it with the voltage Vcs. In other words, the reference value vref_olp for determining an overload condition can be selected during the initial setting period.

[0092] The time detection unit 42 detects whether the period during which the overload detection unit 40 has determined to be an overload state has exceeded the overload protection detection delay time. The time detection unit 42 may detect that the overload protection detection delay time has elapsed based on the input clock signal clk_olp. In this example, the time detection unit 42 determines that the period of the overload state has exceeded the overload protection detection delay time when the number of pulses of the clock signal clk_olp during the period in which the overload state continues exceeds a preset value.

[0093] The latch unit 44 outputs a latch signal "latch" if the overload condition lasts longer than the overload protection detection delay time. The latch unit 44 may continue to output the latch signal "latch" until the overload condition is resolved. The latch signal "latch" is input to the driver circuit 32 and the startup control unit 16. The driver circuit 32 controls the switching element 120 to the off state while the latch signal "latch" is input. The startup control unit 16 does not output a startup signal "startup" while the latch signal "latch" is input. This control allows the switching operation in an overload condition to be stopped.

[0094] The time reduction unit 46 shortens the period of the clock signal clk_olp input to the time detection unit 42 in power test mode compared to the period of the clock signal clk_olp input to the time detection unit 42 in normal operation mode, thereby reducing the overload protection detection delay time. In this example, the time reduction unit 46 receives the clock signal clk_olp_nor, the clock signal clk_olp_test, and the power test mode signal test_ps.

[0095] The clock signal clk_olp_test has a shorter period than the clock signal clk_olp_nor. When the time reduction unit 46 transitions to power test mode by the power test mode signal test_ps, it outputs the clock signal clk_olp_test as the clock signal clk_olp. When the time reduction unit 46 operates in normal operation mode or circuit test mode, it outputs the clock signal clk_olp_nor as the clock signal clk_olp. By shortening the period of the clock signal clk_olp input to the time detection unit 42 in power test mode, the overload protection detection delay time measured by the time detection unit 42 can be shortened.

[0096] In this example, the power test mode signal test_ps is not input to any configuration other than the time reduction unit 46. Therefore, even when switching to power test mode, it does not affect any parameters or functions other than the overload protection detection delay time. This allows the environment in power test mode to be set to an environment similar to that of normal operation mode.

[0097] The clock generation unit 60 generates the clock signals to be supplied to the internal circuits of the control chip 100. In this example, the clock generation unit 60 may generate the clock signals clk_ini, clk_xcap, clk_olp_nor, and clk_olp_test according to the circuit test mode signal test_ic.

[0098] The clock generation unit 60 may generate a clock signal clk_olp_test with a fixed period, regardless of the circuit test mode signal test_ic. The clock generation unit 60 may make the periods of the clock signals clk_ini, clk_xcap, and clk_olp_nor in circuit test mode shorter than the periods of each clock in normal operation mode. For example, the period of the clock signal clk_olp_nor in circuit test mode is shorter than the period of the clock signal clk_olp_nor in normal operation mode. This shortens the period of the clock signal clk_olp input to the time detection unit 42 in circuit test mode, thereby shortening the overload protection detection delay time in circuit test mode. The period of the clock signal clk_olp in circuit test mode may be set to be the same as the period of the clock signal clk_olp in power supply test mode, or it may be set to be different.

[0099] The clock signal clk_ini is input to the initial setting unit 50. The initial setting unit 50 determines whether the initial setting period has elapsed by counting the number of pulses of the clock signal clk_ini. By making the period of the clock signal clk_ini in circuit test mode shorter than the period of the clock signal clk_ini in normal operation mode, the initial setting period in circuit test mode can be shortened. On the other hand, the period of the clock signal clk_ini in power supply test mode is the same as the period of the clock signal clk_ini in normal operation mode. Therefore, the initial setting period in power supply test mode is not shortened.

[0100] The clock signal clk_xcap is input to the discharge unit 14. The discharge unit 14 determines whether the period for discharging the smoothing capacitor 146 has elapsed by counting the number of pulses of the clock signal clk_xcap. By making the period of the clock signal clk_xcap in circuit test mode shorter than the period of the clock signal clk_xcap in normal operation mode, the discharge period in circuit test mode can be shortened. On the other hand, the period of the clock signal clk_xcap in power supply test mode is the same as the period of the clock signal clk_xcap in normal operation mode. Therefore, the discharge period in power supply test mode is not shortened. As mentioned above, the discharge unit 14 may be stopped in circuit test mode and operated in normal operation mode and power supply test mode.

[0101] Figure 3 shows an example of the time waveforms of each voltage and clock signal in normal operation mode. Figure 3 shows the time waveform when the switching power supply 300 is started up. When the power supply voltage Vvcc becomes equal to or greater than the release voltage vref_uvlo, the reset signal rst in the low voltage detection unit 12 is released. At the moment the reset signal rst is released, the circuit test mode switching unit 52 determines whether the voltage Vlat is equal to or greater than the reference voltage vref_test_ic and determines whether to switch to circuit test mode. Similarly, at the moment the reset signal rst is released, the power supply test mode switching unit 34 determines whether the voltage Vfb is equal to or greater than the reference voltage vref_test_ps and determines whether to switch to power supply test mode. In the example in Figure 3, since the voltage Vlat is less than the reference voltage vref_test_ic and the voltage Vfb is less than the reference voltage vref_test_ps, the control chip 100 operates in normal operation mode.

[0102] Initialization is performed by the initial setting unit 50 when the reset signal rst is released. Details of the initial setting will be described later. Once the initial setting is complete and the voltage Vfb becomes equal to or greater than the switching start voltage, the switching operation of the switching element 120 begins. In this example, the period of the clock signal clk_olp does not change before and after the release of the reset signal rst.

[0103] Figure 4 shows an example of the time waveforms of each voltage and clock signal when transitioning to power test mode. In this example, the voltage Vps of power supply 188 is applied to the FB terminal before the power supply voltage Vvcc becomes equal to or greater than the release voltage vref_uvlo. In this example, at the timing when the reset signal rst is released, the voltage Vlat is less than the reference voltage vref_test_ic and the voltage Vfb is equal to or greater than the reference voltage vref_test_ps, so the system transitions to power test mode.

[0104] In power test mode, the initial setup period is not shortened. Additionally, the period of the clock clk_olp is shortened upon transitioning to power test mode. This reduces the overload protection detection delay time. If an overload protection detection test is performed after switching begins in power test mode, the operating time of the power test mode itself can be shortened by utilizing this faster clock clk_olp.

[0105] Figure 5 shows an example of the time waveforms of each voltage and clock signal when transitioning to circuit test mode. In this example, a voltage greater than the reference voltage vref_test_ic is applied to the LAT terminal from the test equipment, etc., before the power supply voltage Vvcc becomes greater than or equal to the release voltage vref_uvlo. In this example, at the timing when the reset signal rst is released, the voltage Vlat is greater than the reference voltage vref_test_ic and the voltage Vfb is less than the reference voltage vref_test_ps, so the system transitions to circuit test mode.

[0106] In circuit test mode, the period of the clock signal clk_ini, used to measure the initial setup period, is shortened. As a result, the initial setup period is shortened or becomes almost zero. In Figure 5, the initial setup period is omitted. In addition, the period of the clock clk_olp is shortened when transitioning to circuit test mode. This shortens the overload protection detection delay time. Thus, when an overload protection detection test is performed after switching starts in circuit test mode, this shortened clock clk_olp is used. Furthermore, the initial setup period is also shortened. Therefore, the operating time of circuit test mode itself can be shortened compared to power supply test mode.

[0107] Figure 6 illustrates an example of operation during the initial setup period. During the initial setup period, the control chip 100 outputs a constant current from the LAT terminal. The constant current charges the capacitor 139, and the voltage Vlat gradually increases.

[0108] The initial setup unit 50 compares the voltage Vlat with the reference voltage vref_ini at timing T1, after a predetermined time has elapsed since the start of the initial setup period, and outputs an initial setup signal ini_sel1 according to the comparison result. The initial setup signal ini_sel1 is a signal that selects the reference value vref_olp for overload detection in the overload detection unit 40. For example, the initial setup unit 50 selects reference value vref_olp1 when the voltage Vlat is greater than or equal to the reference voltage vref_ini, and selects reference value vref_olp2 when the voltage Vlat is less than the reference voltage vref_ini. The voltage Vlat at timing T1 can be set by the resistance value of resistor 138 and the capacitance of capacitor 139, and the reference value vref_olp can be set. At timing T1, the initial setup unit 50 discharges capacitor 139 to make the voltage Vlat the reference potential.

[0109] In this example, the initial setting unit 50 compares the voltage Vlat with the reference voltage vref_ini even at timing T2, which is after timing T1, and outputs an initial setting signal ini_sel2 according to the comparison result. The initial setting signal ini_sel2 is a signal that selects whether to enable or disable the X-CAP discharge function in the discharge unit 14. For example, the initial setting unit 50 enables the X-CAP discharge function when the voltage Vlat is greater than or equal to the reference voltage vref_ini, and disables the X-CAP discharge function when the voltage Vlat is less than the reference voltage vref_ini. The voltage Vlat at timing T2 can be set by the resistance value of resistor 138 and the capacitance of capacitor 139, and the enabling or disabling of the X-CAP discharge function can be set.

[0110] As mentioned above, in circuit test mode, the initial setup period is shortened or omitted, making it impossible to perform initial setup. Therefore, attempting to test the power supply circuit 230 in circuit test mode results in testing the power supply circuit 230 in an environment that differs significantly from the normal operating mode. Consequently, the power supply circuit 230 cannot be tested accurately in circuit test mode. In contrast, by providing a power supply test mode, the power supply circuit 230 can be tested in an environment closer to the normal operating mode.

[0111] Figure 7 is a diagram illustrating the general operation mode, circuit test mode, and power supply test mode. As described above, the control chip 100 switches to circuit test mode depending on whether the voltage Vlat at the LAT terminal is equal to or greater than the reference voltage vref_test_ic. The control chip 100 also switches to power supply test mode depending on whether the voltage Vfb at the FB terminal is equal to or greater than the reference voltage vref_test_ps.

[0112] In normal operation mode, the overload detection delay time and initial setup time are not shortened, and the X-CAP discharge function and frequency spreading function are set to enabled. In circuit test mode, the overload detection delay time and initial setup time are shortened, and the X-CAP discharge function and frequency spreading function are set to disabled. In power supply test mode, the overload detection delay time and initial setup time are shortened, and the X-CAP discharge function and frequency spreading function are set to enabled.

[0113] The control chip 100 in this example has at least three operating modes: a circuit test mode for testing the control chip 100, a power supply test mode for testing the power supply circuit 230, and a normal operation mode. As shown in Figure 7, the control chip 100 operates more like the normal operation mode in power supply test mode than in circuit test mode. For example, in the settings for each time and the settings for enabling and disabling each function shown in Figure 7, the power supply test mode has more items that are the same as the normal operation mode than the circuit test mode. By providing these operating modes, the control chip 100 and the power supply circuit 230 can be tested with high accuracy.

[0114] Figure 8 shows an example configuration of the power test mode switching unit 34 and the time reduction unit 46. In this example, the power test mode switching unit 34 has a comparison circuit 71, a flip-flop 72, and a plurality of inverters 73, 74, and 75. The comparison circuit 71 outputs a comparison signal fv_o which compares the voltage Vfb with the reference voltage vref_test_ps. For example, the comparison signal fb_o is a signal that is H logic when the voltage Vfb is greater than or equal to the reference voltage vref_test_ps, and L logic when the voltage Vfb is less than the reference voltage vref_test_ps.

[0115] Multiple inverters 73, 74, and 75 are connected in series. The first stage inverter 73 is input with a reset signal rst. For example, the reset signal rst is a signal that is high logic when the power supply voltage Vvcc is less than the release voltage vref_uvlo, and low logic when the release voltage is greater than or equal to vref_uvlo.

[0116] The comparison signal fb_o is input to input terminal D of flip-flop 72. The reset signal rst is delayed by inverters 73, 74, and 75, and the inverted signal rst_b is input to the inverting clock terminal of flip-flop 72. Flip-flop 72 takes in the comparison signal fb_o according to the signal rst_b and outputs it. The reset terminal R of flip-flop 72 is input to signal rst_a, which is the inverted reset signal rst. The power test mode signal test_ps is output from the inverting output terminal QB of flip-flop 72. For example, the power test mode signal test_ps indicates L logic when transitioning to power test mode and H logic when not transitioning.

[0117] The time reduction unit 46 selects either the clock signal clk_olp_nor or the clock signal clk_olp_ps according to the power test mode signal test_ps and outputs it as the clock signal clk_olp. In this example, the time reduction unit 46 has multiple AND circuits 81, 84, multiple inverters 82, 83, 85, 87, and an OR circuit 86.

[0118] The AND gate 81 outputs the inverted AND of the power test mode signal test_ps and the clock signal clk_olp_nor. In other words, the AND gate 81 outputs a signal masked to high logic when in power test mode (when the power test mode signal test_ps is low logic), and passes the clock signal clk_olp_nor when not in power test mode.

[0119] The AND circuit 84 outputs an inverted AND of the power test mode signal test_ps, which has been inverted by the inverter 83, and the clock signal clk_olp_test. In other words, the AND circuit 81 outputs a signal masked to high logic when in power test mode, and passes the clock signal clk_olp_nor when not in power test mode.

[0120] Inverter 82 inverts the output of AND circuit 81. Inverter 85 inverts the output of AND circuit 84. OR circuit 86 inverts the OR of the output of inverter 82 and the output of inverter 85 and outputs it. As a result, OR circuit 86 passes either the clock signal clk_olp_nor or the clock signal clk_olp_test through. Inverter 87 inverts the output of OR circuit 86 and outputs it as the clock signal clk_olp.

[0121] Figure 9 shows an example configuration of the clock generation unit 60. The clock generation unit 60 in this example includes a reference clock generation circuit 91, inverters 92 and 93, a period switching unit 97, a plurality of flip-flops 94, a plurality of flip-flops 95, and a plurality of inverters 96. The reference clock generation circuit 91 generates a reference clock with a predetermined period. The period of the reference clock in this example is 2 μs, but is not limited to this. The plurality of inverters 96 invert the outputs of their respective flip-flops 94 and 95.

[0122] In the multiple flip-flops 94, the output of the preceding flip-flop 94 is input as the clock for the next flip-flop 94. Furthermore, the inverted output of each flip-flop 94 is connected to its own input terminal. This connection allows each flip-flop 94 to output a signal with twice the period of the input clock signal. The first flip-flop 94 is input to a reference clock. This connection allows the multiple flip-flops 94 to generate multiple clock signals with periods that double each time, such as 4μs, 8μs, ..., 64μs.

[0123] Inverter 92 inverts and outputs the circuit test mode signal test_ic. Inverter 93 further inverts and outputs the output of inverter 92. Period switching unit 97 receives the high-speed clock signal (period 4μs in this example) output by the first-stage flip-flop 94 and the low-speed clock signal (period 64μs in this example) output by the later-stage (e.g., final-stage) flip-flop 94. Depending on the circuit test mode signal test_ic, the period switching unit 97 selects either the high-speed clock signal or the low-speed clock signal and inputs it to the first-stage flip-flop 95 in the multiple flip-flops 95. In this example, the period switching unit 97 selects the high-speed clock signal when in circuit test mode and the low-speed clock signal when not in circuit test mode.

[0124] Multiple flip-flops 95 are connected in the same way as multiple flip-flops 94. That is, each flip-flop 95 outputs a clock signal with twice the period of the preceding flip-flop 95. As shown in Figure 9, when not in circuit test mode, multiple flip-flops 95 output clock signals with periods of 128 μs, 256 μs, ..., and 16 ms. On the other hand, in circuit test mode, multiple flip-flops 95 generate clock signals with shorter periods, such as 8 μs, 16 μs, ...

[0125] In this example, the clock generation unit 60 selects a signal output by any of the flip-flops 94 and outputs it as the clock signal clk_olp_test for measuring the overload protection detection delay time in power supply test mode. The clock generation unit 60 also selects the signals to be used as the clock signals clk_ini, clk_olp_nor, and clk_xcap from the outputs of multiple flip-flops 95, respectively. Since the period of the signals output by the flip-flops 95 varies according to the circuit test mode signal test_ic, the periods of the clock signals clk_ini, clk_olp_nor, and clk_xcap can be changed depending on whether or not circuit test mode is active.

[0126] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention. [Explanation of Symbols]

[0127] 10...Startup voltage generation unit, 12...Low voltage detection unit, 14...Discharge unit, 16...Startup control unit, 20...Frequency spreading unit, 22...Oscillation circuit, 24...One-shot circuit, 26...Comparison circuit, 28...Flip-flop, 30...OR circuit, 32...Driver circuit, 34...Power supply test mode switching unit, 36...Transistor, 37...Resistor, 40...Overload detection unit, 42...Time detection unit, 44...Latch unit, 46...Time reduction unit, 50...Initial setting unit, 52... Circuit test mode switching section, 60... Clock generation section, 71... Comparison circuit, 72... Flip-flop, 73, 74, 75... Inverter, 81... AND circuit, 82, 83... Inverter, 84... AND circuit, 85... Inverter, 86... OR circuit, 87... Inverter, 91... Reference clock generation circuit, 92, 93... Inverter, 94... Flip-flop, 95... Flip-flop, 96... Inverter, 97... Period switching section, 100... Control chip 110...Main transformer, 111...Primary winding, 112...Secondary winding, 113...Auxiliary winding, 120...Switching element, 122...Resistor element, 128...Diode, 130...Resistor, 131...Capacitor, 132...Resistor, 134...Capacitor, 136...Capacitor, 138...Resistor, 139...Capacitor, 140...Resistor, 142...AC power supply, 144...Coil, 146...Smoothing capacitor, 148...Diode bridge section, 150... ...diode, 152...diode, 154...capacitor, 160...diode, 162...capacitor, 164...light-emitting element, 166...resistor, 168...diode, 170...photodetector, 180...switching signal generation unit, 182...light-emitting element, 184...diode, 186...photodetector, 188...power supply, 190...resistor, 192...transistor, 210...primary circuit, 220...secondary circuit, 230...power supply circuit, 300...switching power supply

Claims

1. A control chip that controls the switching elements of a switching power supply, which receives input power from a power supply circuit and supplies output power to a load, The system has at least two operating modes: a power test mode for testing the power supply circuit and a normal operation mode. A feedback terminal to which a feedback signal corresponding to the output voltage applied to the load is input, A power test mode switching unit that switches between the power test mode and the normal operation mode according to a switching signal input to the feedback terminal. A control chip equipped with this feature.

2. The control chip has a power supply terminal to which a power supply voltage for driving the control chip is applied. The power test mode switching unit switches between the power test mode and the normal operation mode according to the power supply voltage applied to the power supply terminals and the switching signal. The control chip according to claim 1.

3. The system further includes a low-voltage detection unit that stops the switching operation of the switching element when the power supply voltage is lower than a set release voltage. The power test mode switching unit operates the control chip in the power test mode when the switching signal is input while the power supply voltage is lower than the release voltage. The control chip according to claim 2.

4. The control chip reduces the overload protection detection delay time in the power test mode compared to the normal operation mode. The control chip according to claim 1.

5. The control chip is A time detection unit that detects when the overload protection detection delay time has elapsed based on the input clock signal, A time reduction unit shortens the period of the clock signal input to the time detection unit in the power test mode to a shorter period than the period of the clock signal input to the time detection unit in the normal operation mode, thereby shortening the overload protection detection delay time. A control chip according to claim 4, having the following features.

6. The aforementioned operating modes further include a circuit test mode for testing the control chip, The control chip operates in a manner closer to the normal operation mode than to the circuit test mode when using the power supply test mode. The control chip according to claim 4.

7. The control chip shortens the overload protection detection delay time and the initial setup period in the circuit test mode compared to the normal operation mode. The control chip according to claim 6.

8. The aforementioned power supply circuit is AC power supply and A smoothing capacitor is provided between the positive output terminal and the negative output terminal of the AC power supply. It has, The control chip is A power detection terminal connected to the aforementioned power supply circuit, When the voltage input to the power supply detection terminal is a DC voltage, a discharge unit discharges the smoothing capacitor. It has, In the circuit test mode, the discharge unit is stopped, and in the normal operation mode and the power supply test mode, the discharge unit is operated. The control chip according to claim 6.

9. The system further includes a frequency spreading unit that varies the switching frequency of the switching element, In the circuit test mode, the frequency spreading unit is stopped, and in the normal operation mode and the power supply test mode, the frequency spreading unit is operated. The control chip according to claim 6.

10. A control chip that controls the switching elements of a switching power supply, which receives input power from a power supply circuit and supplies output power to a load, The system has at least three operating modes: a circuit test mode for testing the control chip, a power supply test mode for testing the power supply circuit, and a normal operation mode. Control chip.

11. A switching power supply that supplies output power to a load based on input power, A power supply circuit that generates the aforementioned input power, Switching element and A control chip according to any one of claims 1 to 10 for controlling the switching element, A switching power supply equipped with the following features.

12. A switching power supply that supplies output power to a load based on input power, A power supply circuit that generates the aforementioned input power, Switching element and A control chip that controls the switching element and Equipped with, The control chip includes a feedback terminal to which a feedback signal corresponding to the output voltage applied to the load is input. The switching power supply includes a switching signal generation unit that inputs a switching signal having a set voltage to the feedback terminal when the output voltage is lower than a predetermined threshold voltage, and stops inputting the switching signal to the feedback terminal when the output voltage is equal to or greater than the threshold voltage. Switching power supply.

13. The control chip is The system has at least two operating modes: a power test mode for testing the power supply circuit and a normal operation mode. The power test mode and the normal operation mode are switched according to the switching signal input to the feedback terminal. The switching power supply according to claim 12.

14. The control chip is It includes a power supply terminal to which a power supply voltage for driving the control chip is applied, The power supply test mode and the normal operation mode are switched according to the power supply voltage applied to the power supply terminal and the switching signal. The switching power supply according to claim 13.

15. The control chip is The system includes a low-voltage detection unit that stops the switching operation of the switching element when the power supply voltage is lower than the set release voltage. When the power supply voltage is lower than the release voltage and the switching signal is input, the system switches to the power supply test mode. The switching power supply according to claim 14.

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