Semiconductor wafers

Abstract

This invention provides a semiconductor wafer that suppresses probe damage during semiconductor testing and allows for accurate measurement of the current flowing between wiring after testing. [Solution] The semiconductor wafer according to this embodiment includes a pattern wiring under test, which comprises a first insulating film under test and a first wiring under test and a second wiring under test, which are arranged on either side of the first insulating film under test and electrically insulated from each other. The first lead wiring is electrically connected to the first wiring under test and is wider than the first and second wiring under test. The second lead wiring is electrically connected to the second wiring under test and is wider than the first and second wiring under test. The third lead wiring is electrically connected to the second lead wiring and is wider than the first and second wiring under test. The fourth lead wiring is provided in the middle of the third lead wiring and is narrower than the third lead wiring.

Description

[[Technical Field]]

[0001] The present embodiment relates to a semiconductor wafer. [[Background Art]]

[0002] In semiconductor tests such as TDDB (Time Dependent Dielectric Breakdown), when a high voltage is applied between wirings of a device under test, a short circuit may occur between the wirings, causing a large current to flow. In this case, the probes of the probe card may be melted by the current, and it may be necessary to repair the probe card. In addition, damage to the lead-out wiring of the device under test may make it impossible to accurately measure the current value flowing between the wirings after the test. [[Prior Art Literature]] [[Patent Literature]]

[0003] [[Patent Document 1]] US Patent Publication No. 2015 / 0077150 [[Patent Document 2]] US Patent Publication No. 2008 / 0122476 [[Patent Document 3]] US Patent Publication No. 2008 / 0038851 [[Summary of the Invention]] [[Problem to be Solved by the Invention]]

[0004] Provided is a semiconductor wafer that can suppress probe damage in semiconductor tests and accurately measure the current value flowing between wirings after the test. [[Means for Solving the Problem]]

[0005] The semiconductor wafer according to this embodiment includes a pattern wiring under test, which comprises a first insulating film under test and a first wiring under test and a second wiring under test, which are arranged on either side of the first insulating film under test and electrically insulated from each other. The first lead wiring is electrically connected to the first wiring under test and is wider than the first and second wiring under test. The second lead wiring is electrically connected to the second wiring under test and is wider than the first and second wiring under test. The third lead wiring is electrically connected to the second lead wiring and is wider than the first and second wiring under test. The fourth lead wiring is provided in the middle of the third lead wiring and is narrower than the third lead wiring. [Brief explanation of the drawing]

[0006] [Figure 1] This is a plan view showing an example of the configuration of a semiconductor wafer according to the first embodiment. [Figure 2] This is a plan view showing an example of the configuration of the test pattern wiring and its surroundings according to the first embodiment. [Figure 3] This is a plan view showing an example of a wiring configuration for the lead-out cable. [Figure 4] This is a plan view showing an example of the configuration of the test pattern wiring and its surroundings according to the second embodiment. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will be described below with reference to the drawings. These embodiments are not limiting to the present invention. The drawings are schematic or conceptual. The same elements are denoted by the same reference numerals in the specification and the drawings.

[0008] (First Embodiment) Figure 1 is a plan view showing an example of a semiconductor wafer configuration according to the first embodiment.

[0009] The semiconductor wafer 1 includes a plurality of semiconductor chips CH and scribe lines SL located between adjacent semiconductor chips CH. Semiconductor elements such as transistors (not shown) are formed on the semiconductor chips CH. The scribe lines SL are regions that are cut when the plurality of semiconductor chips CH are separated into individual pieces during the dicing process. The test pattern wiring 2, lead wirings 31-35, and pads Pin and Pout in Figure 2 are located on the scribe lines SL in Figure 1. Therefore, when the semiconductor wafer 1 is diced during the dicing process, the test pattern wiring 2, etc., are cut away. Note that the test pattern wiring 2, lead wirings 31-35, and pads Pin and Pout in Figure 2 may be located in the space within each semiconductor chip CH in Figure 1. In this case, the test pattern wiring 2, etc., remain within each semiconductor chip CH.

[0010] Figure 2 is a plan view showing an example of the configuration of the test pattern wiring and its surroundings according to the first embodiment.

[0011] The semiconductor wafer 1 according to this embodiment comprises a test pattern wiring 2, lead wirings 31 to 35, contacts C1 to C3, and pads Pin, Pout, and Pe.

[0012] The pattern wiring under test 2 is a test wiring provided for testing and measuring the withstand voltage between wirings, and is provided separately from the wiring provided on the semiconductor chip CH as a product. The pattern wiring under test 2 comprises a plurality of wirings under test 10, a plurality of wirings under test 20, and a test insulating film 15. The plurality of wirings under test 10 and the plurality of wirings under test 20 are each arranged with the test insulating film 15 in between, and are electrically insulated from each other by the test insulating film 15. The wirings under test 10 and 20 are embedded in the test insulating film 15. Conductive materials such as copper, tungsten, and aluminum are used for the wirings under test 10 and 20. Insulating materials such as silicon oxide and silicon nitride are used for the test insulating film 15.

[0013] Multiple wirings under test 10 are commonly connected to a single lead wire 31. The multiple wirings under test 10 extend in the +Y direction from lead wire 31 to lead wire 32 and are arranged in parallel in the X direction, intersecting (e.g., orthogonal to) the Y direction. The multiple wirings under test 10 do not reach lead wire 32 and are electrically isolated from lead wire 32 and the wirings under test 20.

[0014] Multiple wirings under test 20 are commonly connected to a single lead wire 32. The multiple wirings under test 20 extend in the -Y direction from lead wire 32 to lead wire 31 and are arranged in parallel in the X direction. The multiple wirings under test 20 do not reach lead wire 31 and are electrically isolated from lead wire 31 and the wiring under test 10.

[0015] Thus, the wirings under test 10 and 20 are arranged alternately in an alternating pattern in the X direction. Due to this planar layout of the wirings under test 10 and 20, the insulating film under test 15 is provided in a zigzag pattern between the wirings under test 10 and 20 in a planar view from the Z direction.

[0016] The lead wire 31 extends in the X direction and is electrically connected to multiple wires 10 under test. At one end, the lead wire 31 is connected to contact C1. The lead wire 31 is electrically connected via contact C1 to a pad Pout located above it (in the +Z direction). The width of the lead wire 31 is wider than the width of the wires 10 and 20 under test.

[0017] Here, the width of the wiring refers to the length in the direction perpendicular to the direction of extension (longitudinal direction) of the wiring. For example, the widths of the lead wires 31 to 34 are the lengths in the Y direction. The widths of the wires under test 10, 20 and lead wire 35 are the lengths in the X direction.

[0018] The lead-out wiring 32 extends in the X direction and is electrically connected to the plurality of wirings under test 20. At one end, the lead-out wiring 32 is connected to the contact C2. The lead-out wiring 32 is electrically connected to the pad Pe located thereabove (+Z direction) via the contact C2. The width of the lead-out wiring 32 is larger than the widths of the wirings under test 10 and 20. The width of the lead-out wiring 32 may be equal to the width of the lead-out wiring 31.

[0019] The lead-out wiring 33 extends in the X direction and is electrically connected to the lead-out wiring 32 via the lead-out wiring 35. Accordingly, the lead-out wiring 33 is commonly electrically connected to the plurality of wirings under test 20 via the lead-out wirings 32 and 35. At one end, the lead-out wiring 33 is connected to the contact C3. The lead-out wiring 33 is electrically connected to the pad Pin located thereabove (+Z direction) via the contact C3. The width of the lead-out wiring 33 is larger than the widths of the wirings under test 10 and 20. The width of the lead-out wiring 33 may be equal to the widths of the lead-out wirings 31 and 32.

[0020] The lead-out wiring 34 is provided in the middle of the lead-out wiring 33. The lead-out wiring 34 has a smaller (narrower) width than the lead-out wiring 33 and is constricted. Similarly to the lead-out wiring 33, the lead-out wiring 34 is commonly electrically connected to the plurality of wirings under test 20 via the lead-out wirings 32 and 35. The lead-out wiring 34 is also connected to the contact C3. Therefore, the lead-out wiring 34 may be regarded as a part of the lead-out wiring 33.

[0021] The width of the lead-out wiring 34 is not more than one third of the width of the lead-out wiring 33. Furthermore, the width of the lead-out wiring 34 is narrower than the width of the wirings under test 10 and 20. Thereby, the lead-out wiring 34 functions as a fuse when a short circuit occurs between the wiring under test 10 and the wiring under test 20 due to breakdown between the wiring under test 10 and the wiring under test 20 in a pressure resistance test process (e.g., a TDDB test). That is, when a short circuit occurs between the wiring under test 10 and the wiring under test 20 and a relatively large current flows, the lead-out wiring 34 is melted and cut off in the middle of the lead-out wiring 33 by the current, electrically isolating between the pad Pin and the patterned wiring under test 2. Thereby, the patterned wiring under test 2 is protected, and damage to the probe that contacts the pad Pin can be suppressed.

[0022] The plurality of lead-out wirings 35 extend in the Y direction and are provided between the lead-out wiring 32 and the lead-out wiring 33. The plurality of lead-out wirings 35 electrically connect the lead-out wiring 32 and the lead-out wiring 33. The width of the lead-out wiring 35 is wider than the width of the wirings under test 10 and 20. The width of the lead-out wiring 35 may be equal to the width of the lead-out wirings 31 to 33.

[0023] The length of the lead-out wiring 35 in the Y direction, that is, the distance between the lead-out wiring 34 and the lead-out wiring 32, is preferably spaced apart by about 10 µm to 20 µm. The reason for this is to prevent the influence of the breakage from affecting the lead-out wiring 32 when a high current flows through the lead-out wiring 34 serving as a fuse and breaks it.

[0024] For the lead-out wirings 31 to 35, for example, conductive materials such as copper, tungsten, and aluminum are used. The wirings under test 10 and 20, as well as the lead-out wirings 31 to 35, may be provided by processing a conductive layer (e.g., a metal layer) of the same layer. Thereby, the wirings under test 10 and 20, as well as the lead-out wirings 31 to 35, can be formed with one conductive layer only by changing the mask pattern in the lithography technique, no additional process is required.

[0025] Pad Pout is electrically connected to lead wire 31 via contact C1. Pad Pe is electrically connected to lead wire 32 via contact C2. Pad Pin is electrically connected to lead wires 33 and 34 via contact C3. Conductive materials such as copper, tungsten, and aluminum are used for pads Pin, Pout, and Pe.

[0026] Pads Pin, Pout, and Pe are provided in a conductive layer located above the wiring under test 10, 20 and the lead wirings 31-35. An insulating layer (not shown) is provided between the conductive layers of the wiring under test 10, 20 and the lead wirings 31-35 and the conductive layers of pads Pin, Pout, and Pe. Contacts C1-C3 penetrate this insulating layer. Contact C1 is provided between lead wiring 31 and pad Pout, electrically connecting lead wiring 31 and pad Pout. Contact C2 is provided between lead wiring 32 and pad Pe, electrically connecting lead wiring 32 and pad Pe. Contact C3 is provided between lead wiring 33 and pad Pin, electrically connecting lead wiring 33 and pad Pin. Pads Pin, Pout, and Pe may overlap with the wiring under test 10, 20, or the lead wirings 31-35 in a plan view from the Z direction. This reduces the area of ​​the pattern required for the withstand voltage test.

[0027] Figure 3 is a plan view showing an example configuration of the lead wiring 34. The width W34 of the lead wiring 34, which functions as a fuse, is less than or equal to the width of the wirings under test 10 and 20, and less than or equal to one-third of the width W33 of the lead wiring 33. Furthermore, the lower limit of the width W34 of the lead wiring 34 may be the minimum width that can be formed by lithography and etching techniques. The length of the lead wiring 34 is the length that can be formed by lithography and etching techniques.

[0028] To form such a thin lead wire 34, a dummy wire D34 is provided. The dummy wire D34 extends in the X direction, approximately parallel to the lead wire 34. The widths Wd34_1 and Wd34_2 of the dummy wire D34 are progressively wider than the width W34 of the lead wire 34 as they move away from the lead wire 34. That is, width Wd34_1 is somewhat wider than width W34, and width Wd34_2 is somewhat wider than width Wd34_1. By arranging such a dummy wire D34 around the lead wire 34, the width of the lead wire 34 can be stably formed to the desired width W34 using lithography and etching techniques or the CMP (Chemical Mechanical Polishing) method. For example, when forming a damascene lead wire 34 in an insulating layer (not shown), the material for the lead wire 34 is embedded in the grooves of the insulating layer, and then the material for the lead wire 34 is polished using the CMP method.

[0029] In this case, if dummy wiring D34 is not provided around the thin lead wire 34, the difference in hardness between the lead wire 34 and the insulating layer may cause the insulating layer around the lead wire 34 to be excessively polished. Alternatively, the lead wire 34 may be excessively polished and not formed to the thickness as designed.

[0030] In contrast, this embodiment provides dummy wiring D34 around the lead wiring 34, which suppresses excessive polishing of the insulating layer around the lead wiring 34 when polished by the CMP method. As a result, the lead wiring 34 can be formed to the thickness specified in the design.

[0031] Next, we will explain the pressure resistance test process.

[0032] The semiconductor wafer 1 according to this embodiment is mounted on a semiconductor test apparatus (not shown). The probes of the probe card make contact with pads Pout and Pin in Figure 2. A reference voltage, for example, the ground voltage, is applied to pad Pout. A high-level voltage, for example, higher than the reference voltage, is applied to pad Pin. The high-level voltage is swept or stepped up so that it gradually increases from the reference voltage. As a result, the voltage of the wiring under test 20 increases while the wiring under test 10 remains at the reference voltage. Since the wiring under test 10 and the wiring under test 20 are electrically isolated by the insulating film 15 under test, the electric field applied to the insulating film 15 increases as the voltage of the wiring under test 20 increases.

[0033] When the voltage difference between the wiring under test 10 and the wiring under test 20 exceeds the withstand voltage of the insulating film under test 15, the insulating film under test 15 breaks down, and a relatively large current flows between the wiring under test 10 and the wiring under test 20.

[0034] At this time, because the width of the lead wire 34 is narrower than the other lead wires 31-33, 35 and the wires under test 10, 20, lead wire 34 acts as a fuse, melting and cutting. This electrically isolates the contact C3 side of lead wire 33 from lead wire 31. In other words, it electrically isolates pad Pin from pad Pout. Therefore, after the insulating film under test 15 breaks down and lead wire 34 is cut, almost no current flows between the wires under test 10 and 20. This suppresses further damage to the pattern wiring 2 under test. It also suppresses damage to the probes that contact pads Pin and Pout.

[0035] Next, we will explain the evaluation process after the pressure resistance test.

[0036] After the withstand voltage test, the lead wire 34 is cut, so the pad pin is not electrically connected to the test pattern wire 2 and cannot be used for evaluation.

[0037] Therefore, in this embodiment, pad Pe is used in the evaluation process. Pad Pe is electrically connected to the wiring under test 20 via contact C2 and lead wiring 32. Thus, the wiring pattern 2 under test after the withstand voltage test can be evaluated using pad Pe.

[0038] For example, while maintaining pad Pout at the reference voltage, the voltage of pad Pe is increased from the reference voltage. This allows for the measurement of the current flowing between the tested wiring 10 and the tested wiring 20 after the withstand voltage test, and for identifying breakdown points in the tested pattern wiring 2. In this way, the tested pattern wiring 2 can be evaluated using pad Pe, which is different from pad Pin used in the test process.

[0039] As described above, the semiconductor wafer 1 according to this embodiment has a lead wire 34 that is narrower than the lead wires 31-33, 35 and the test wires 10, 20, provided on a portion of the lead wire 33. This allows the lead wire 34 to function as a fuse during the testing process, protecting the test pattern wire 2 after the test insulating film 15 has broken down. It also protects the probes that come into contact with the pads Pin and Pout.

[0040] Furthermore, in the semiconductor wafer 1 according to this embodiment, multiple lead wires 32 and 33 to which a high-level voltage is applied are connected to the wiring under test 20. Accordingly, multiple pads Pin and Pe are provided on the wiring under test 20 side. Therefore, even if the lead wire 34 is cut during the withstand voltage test and the pad Pin is electrically isolated from the wiring under test 20, the wiring pattern 2 under test can be evaluated after the withstand voltage test using the pad Pe.

[0041] Thus, according to this embodiment, damage to the probe and the pattern wiring 2 under test can be suppressed during the testing process, and the pattern wiring 2 under test can be accurately evaluated after the testing process.

[0042] In the above embodiment, a high-level voltage is applied to pad Pin during the withstand voltage test. However, a low-level voltage may be applied to pad Pin. In this case, the low-level voltage applied to pad Pin is swept or stepped down so that it gradually decreases from the reference voltage. This allows the voltage of the wiring under test 20 to decrease while the wiring under test 10 remains at the reference voltage. Thus, in the withstand voltage test, an electric field opposite to that in the first embodiment may be applied to the insulating film 15 under test. In this case, during the evaluation step, the voltage of pad Pe is reduced from the reference voltage. This makes it possible to measure the current flowing between the wiring under test 10 and the wiring under test 20 after the withstand voltage test, or to identify breakdown points in the pattern wiring 2 under test. Thus, the voltages applied to pad Pin and Pe may be negative voltages relative to the reference voltage.

[0043] (Second Embodiment) Figure 4 is a plan view showing an example of the configuration of the test pattern wiring and its surroundings according to the second embodiment. In the second embodiment, the lead wires 33 to 35 are provided on the side of lead wire 31 to which the reference voltage is applied.

[0044] The lead wire 33 extends in the X direction and is electrically connected to the lead wire 31 via the lead wire 35. Thus, the lead wire 33 is electrically connected in common to multiple wires under test 10 via the lead wires 31 and 35. At one end, the lead wire 33 is connected to contact C3. The lead wire 33 is electrically connected via contact C3 to a pad Pout located above it (in the +Z direction). The width of the lead wire 33 may be the same as that of the first embodiment.

[0045] The configuration of the lead wiring 34 may be the same as that of the first embodiment.

[0046] Multiple lead wires 35 extend in the Y direction and are provided between lead wire 31 and lead wire 33. Multiple lead wires 35 electrically connect lead wire 31 and lead wire 33. The width of the lead wires 35 may be the same as that of the first embodiment.

[0047] Pad Pout is electrically connected to lead wires 33 and 34 via contact C3. Pad Pe is electrically connected to lead wire 31 via contact C1. Pad Pin is electrically connected to lead wire 32 via contact C2.

[0048] Other configurations of the second embodiment may be the same as those of the first embodiment.

[0049] Next, the pressure resistance test process according to the second embodiment will be described.

[0050] The probes of the probe card make contact with pads Pout and Pin in Figure 2. A reference voltage, such as the ground voltage, is applied to pad Pout. A high-level voltage, such as one higher than the reference voltage, is applied to pad Pin. The high-level voltage is swept or stepped up so that it gradually increases from the reference voltage. This causes the voltage of the wiring under test 20 to increase while the wiring under test 10 remains at the reference voltage.

[0051] When the voltage difference between the wiring under test 10 and the wiring under test 20 exceeds the withstand voltage of the insulating film under test 15, the insulating film under test 15 breaks down, and a relatively large current flows between the wiring under test 10 and the wiring under test 20.

[0052] At this time, the lead wire 34 acts as a fuse, melting and cutting the circuit. This electrically isolates the contact C3 side of the lead wire 33 from the lead wire 31. This prevents further damage to the pattern wiring 2 under test. It also prevents damage to the probe that contacts the pads Pin and Pout.

[0053] Next, we will explain the evaluation process after the pressure resistance test.

[0054] After the pressure test, the lead wire 34 is cut, so pad Pout is not electrically connected to the test pattern wire 2 and cannot be used for evaluation.

[0055] Therefore, pad Pe is used in the evaluation process. Pad Pe is electrically connected to the wiring under test 20 via contact C1 and lead wiring 31. Thus, pad Pe can be used to evaluate the pattern wiring 2 under test after the withstand voltage test.

[0056] For example, while maintaining pad Pe at the reference voltage, the voltage of pad Pin is increased from the reference voltage. This allows for the measurement of the current flowing between the tested wiring 10 and the tested wiring 20 after the withstand voltage test, and for identifying breakdown points in the tested pattern wiring 2. In this way, the tested pattern wiring 2 can be evaluated using a different pad Pe than the pad Pin used in the test process.

[0057] Thus, even if the lead wires 33-35 are provided on the lead wire 31 side, the effects of this embodiment can still be obtained.

[0058] In addition, in the second embodiment, as in the first embodiment, a low-level voltage may be applied to the pad pin during the withstand voltage test process.

[0059] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0060] 1. Semiconductor wafer CH semiconductor chip SL Scribeline 2. Wiring pattern under test 31-35 Pull-out wiring C1-C3 Contact Lenses Pin, Pout, Pe Pad 10 Wiring under test 15. Insulating film under test 20 Wiring under test

Claims

1. A test pattern wiring including a first insulating film under test, and a first wiring under test and a second wiring under test arranged on either side of the first insulating film under test and electrically insulated from each other, A first lead wire is electrically connected to the first wiring under test and is wider than the first and second wirings under test, A second lead wire is electrically connected to the second wiring under test and is wider than the first and second wiring under test, A third lead wire is electrically connected to the second lead wire and is wider than the first and second wires under test, A semiconductor wafer comprising a fourth lead wiring provided in the middle of the third lead wiring and having a narrower width than the third lead wiring.

2. The semiconductor wafer according to claim 1, wherein the width of the fourth lead wiring is one-third or less of the width of the third lead wiring.

3. The semiconductor wafer according to claim 1, wherein the width of the fourth lead wire is narrower than the width of the first wire under test or the width of the second wire under test.

4. The first pad connected to the first lead wiring, The second pad connected to the second lead wiring, The semiconductor wafer according to claim 1, further comprising a third pad connected to the third and fourth lead wirings.

5. In the testing process of the aforementioned pattern wiring, A reference voltage is applied to the first pad. The semiconductor wafer according to claim 4, wherein a voltage higher or lower than the reference voltage is applied to the third pad.

6. The semiconductor wafer according to claim 5, wherein the test step is a withstand voltage test between the first wiring under test and the second wiring under test.

7. In the evaluation step of the test pattern wiring after the test step, A reference voltage is applied to the first pad. The semiconductor wafer according to claim 5 or claim 6, wherein a voltage higher or lower than the reference voltage is applied to the second pad.

8. The semiconductor wafer according to claim 7, wherein the evaluation step involves measuring the current between the first wiring under test and the second wiring under test.

9. The semiconductor wafer according to claim 5 or 6, wherein the fourth lead wire is disconnected by the current flowing between the first wire under test and the second wire under test during the test process.

Images