Memory system and its test method

Abstract

This invention provides a memory system and a method for testing a memory system that can rapidly test non-volatile memory using a bypass interface, in a memory system composed of a controller and non-volatile memory. [Solution] The memory system 1 according to the embodiment includes a non-volatile memory 20 and a controller 10 capable of controlling the non-volatile memory 20. The controller 10 includes a first input / output circuit 17 that inputs an access control signal and a data control signal CTRL_IN[6:0] for accessing the non-volatile memory 20 and outputs an output signal CTRL_OUT[8:0] based on the data read from the non-volatile memory 20. The controller 10 further includes a data control circuit 18 that controls the data to be input to the non-volatile memory 20 and the data output from the non-volatile memory 20 based on the data control signal CTRL_IN[6:0] input from the first input / output circuit 17.

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory system and a test method therefor. Background Art

[0002] There are memory systems configured of a non-volatile memory and a controller. An example of the memory system is a Multi Chip Package (MCP) in which one or more NAND flash memories and a controller chip used for controlling the NAND flash memories are housed in a single package.

[0003] Some memory systems are equipped with an interface used for normal operation and an interface used for testing (see, for example, Patent Document 1). Examples of interfaces used for normal operation include high-speed interfaces conforming to standards such as UFS (Universal Flash Storage) and PCIe (PCI Express). Further, the interface used for testing includes an interface that enables access to the non-volatile memory from an external terminal without passing through a non-volatile memory control circuit included in the controller, which is hereinafter referred to as "BypassI / F (Bypass Interface)". In a memory system having BypassI / F, during testing or failure analysis, a control signal is input to the memory system via BypassI / F from a test device such as a tester provided outside the memory system (hereinafter referred to as "Bypass operation host"). Prior Art Literature Patent Literature

[0004] Patent Document 1 United States Patent Application Publication No. 2010-0195396 Specification Summary of the Invention Problem to be Solved by the Invention

[0005] Conventionally, command, address, and data signals input from a bypass-operating host via a bypass interface are latched internally by the controller before being output to non-volatile memory. Due to a skew between these signals, inputting signals at high frequencies prevents them from being correctly transmitted to non-volatile memory. Tests or failure analyses using a bypass interface (hereinafter collectively referred to as "tests") require inputting signals to the memory system at low frequencies, resulting in slow tests that cannot detect defects that occur only during high-speed operation of non-volatile memory.

[0006] Embodiments of the present invention aim to provide a memory system and a method for testing a memory system, which are configured with non-volatile memory and a controller, and which can rapidly test non-volatile memory using a bypass interface. [Means for solving the problem]

[0007] The memory system according to the embodiment comprises a non-volatile memory and a controller capable of controlling the non-volatile memory. The controller includes a first input / output circuit that can input an access control signal and a data control signal for accessing the non-volatile memory and output an output signal based on the data read from the non-volatile memory. The controller further includes a data control circuit that controls the data to be input to the non-volatile memory and the data output from the non-volatile memory based on the data control signal input from the first input / output circuit. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a block diagram of the memory system according to the embodiment. [Figure 2A] Figure 2A shows an example of the configuration of input / output signals for the non-volatile memory of the memory system according to the embodiment. [Figure 2B]Figure 2B shows an example of the configuration of a data control signal for a memory system according to the embodiment. [Figure 2C] Figure 2C shows an example of the configuration of the controller output signals of the memory system according to the embodiment. [Figure 3] Figure 3 is a block diagram of the main components of the memory system according to the embodiment. [Figure 4] Figure 4 shows an example of the operation of the memory system according to the embodiment. [Figure 5A] Figure 5A is a timing chart diagram illustrating the operation of the memory system according to the embodiment. [Figure 5B] Figure 5B is a timing chart diagram illustrating the operation of the memory system according to the embodiment. [Figure 6A] Figure 6A is a timing chart diagram illustrating the operation of the memory system according to the embodiment. [Figure 6B] Figure 6B is a timing chart diagram illustrating the operation of the memory system according to the embodiment. [Figure 7A] Figure 7A is a timing chart diagram illustrating the operation of the memory system according to the embodiment. [Figure 7B] Figure 7B is a timing chart diagram illustrating the operation of the memory system according to the embodiment. [Figure 8A] Figure 8A is a timing chart diagram illustrating the operation of the memory system according to the embodiment. [Figure 8B] Figure 8B is a timing chart diagram illustrating the operation of the memory system according to the embodiment. [Figure 9] Figure 9 is a block diagram of the comparative memory system. [Figure 10] Figure 10 is a block diagram of the main components of the comparative memory system. [Modes for carrying out the invention]

[0009] Embodiments will be described with reference to the drawings. In the description of the drawings set forth below, the same or similar reference numerals are assigned to the same or similar parts, and the description thereof will be omitted. The drawings are schematic.

[0010] In addition, the embodiments shown below are examples of apparatuses and methods for embodying the technical idea, and do not specify the material, shape, structure, arrangement, etc. of each component. Various modifications can be made to this embodiment within the scope of the claims.

[0011] [Embodiment] (Configuration of Memory System) First, a memory system according to an embodiment will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of a memory system 1 according to an embodiment. The memory system 1 includes a memory controller 10 and a non-volatile memory 20. The memory system 1 may be a storage device such as Storage Class Memory (SCM), an SSD (Solid State Drive), or a USB (Universal Serial Bus) memory. The memory system 1 may be an MCP in which the non-volatile memory 20 including one or more non-volatile memory chips and the chip of the memory controller 10 are housed in a single package.

[0012] The memory system 1 can be connected to a host 30 via a high-speed interface conforming to standards such as UFS and PCIe. During normal operation of the memory system 1, the memory system 1 is connected to the host 30 as shown in FIG. 1. The host 30 may be, for example, an electronic device such as a personal computer or a mobile terminal. Unlike the configuration shown in FIG. 1, the memory system 1 does not need to be connected to the host 30 when the memory system 1 is tested.

[0013] Further, the memory system 1 is connectable to a bypass operation host 40. When testing the memory system 1, the memory system 1 is connected to the bypass operation host 40 as shown in FIG. 1. The bypass operation host 40 may be, for example, a testing device such as a tester. Unlike during testing, during normal operation of the memory system 1, the memory system 1 does not need to be connected to the bypass operation host 40.

[0014] The memory system 1 can switch the interface and operation mode used between normal operation and testing. Although not illustrated in the drawings, the switching of the interface and the operation mode can be performed by setting a register provided inside the memory controller 10, or by setting via voltage application to a dedicated terminal of the memory system 1 during power activation, or the like.

[0015] The non-volatile memory 20 is a memory that retains data even when power is not supplied. In the following description, a case where a NAND flash memory is used is exemplified as an example of the non-volatile memory 20. However, as the non-volatile memory 20, storage devices such as MRAM (Magnetoresistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory), and ReRAM (Resistive Random Access Memory) may also be used, for example.

[0016] The memory controller 10 is a semiconductor integrated circuit configured as, for example, an SoC (System On a Chip). The memory controller 10 includes a normal operation path section 11, a bypass operation path section 12, a memory I / F circuit 13, and an internal memory 14. The memory controller 10 can control the non-volatile memory 20 as follows. The memory controller 10 can control writing to the non-volatile memory 20 in accordance with a write request from the host 30 or the bypass operation host 40. Further, the memory controller 10 can control reading from the non-volatile memory 20 in accordance with a read request from the host 30 or the bypass operation host 40.

[0017] The normal operation path section 11 includes a high-speed I / F circuit 15 and a controller circuit 16. The high-speed I / F circuit 15 is connectable to the host 30 and is connected to the controller circuit 16. The controller circuit 16 is connected to the high-speed I / F circuit 15, the memory I / F circuit 13, and the internal memory 14.

[0018] During normal operation of the memory system 1, the high-speed I / F circuit 15 performs processing according to the interface standard with the host 30 and outputs commands received from the host 30, data to be written, etc., to the controller circuit 16. The high-speed I / F circuit 15 also transmits data read from the non-volatile memory 20, responses from the controller circuit 16, etc., to the host 30.

[0019] The controller circuit 16 comprehensively controls each component of the memory system 1 during its normal operation. When the controller circuit 16 receives an instruction from the host 30 via the high-speed I / F circuit 15, it performs control according to that instruction. For example, the controller circuit 16 instructs the memory I / F circuit 13 to write data to the non-volatile memory 20 according to an instruction from the host 30. The controller circuit 16 also instructs the memory I / F circuit 13 to read data from the non-volatile memory 20 according to an instruction from the host 30. Furthermore, when the controller circuit 16 receives a write request or read request from the host 30, it converts the logical address received from the host 30 into a physical address indicating a storage area on the non-volatile memory 20 and instructs the memory I / F circuit 13 to do so. Here, the controller circuit 16 will also be referred to as the first control circuit 16.

[0020] The Bypass operation path unit 12 includes a Bypass I / F circuit 17 and a data control circuit 18. The Bypass I / F circuit 17 is connectable to the Bypass operation host 40 and is connected to the data control circuit 18. The data control circuit 18 is connected to the Bypass I / F circuit 17, the memory I / F circuit 13, and the internal memory 14. Signals, which will be described later, are input and output between the Bypass operation host 40 and the Bypass I / F circuit 17, and between the Bypass I / F circuit 17 and the data control circuit 18, with reference to Figures 2A to 2C.

[0021] Hereinafter, the operation using the Bypass I / F circuit 17 in the testing of memory system 1 will be referred to as "Bypass operation". During Bypass operation, the Bypass I / F circuit 17 performs processing in accordance with the interface standard with the Bypass operation host 40. It then outputs the instructions received from the Bypass operation host 40, the data to be written, etc. to the data control circuit 18. The Bypass I / F circuit 17 also transmits the data read from the non-volatile memory 20, the response from the data control circuit 18, etc. to the Bypass operation host 40. Detailed operation of the Bypass I / F circuit 17 will be described later with reference to Figures 2A to 8B.

[0022] As explained above, the memory system 1 can perform signal input and output with the outside world through two types of interfaces: the Bypass I / F circuit 17 and the High-Speed ​​I / F circuit 15. The High-Speed ​​I / F circuit 15 can operate at a higher speed than the Bypass I / F circuit 17. Here, the Bypass I / F circuit 17 will also be referred to as the first input / output circuit 17, and the High-Speed ​​I / F circuit 15 will also be referred to as the second input / output circuit 15. Switching from normal operation to Bypass operation can be done, as mentioned above, by setting a register internally provided by the memory controller 10, or by applying a voltage to a dedicated terminal of the memory system 1 when the power is turned on.

[0023] The data control circuit 18 controls the input and output of data between the Bypass operation host 40, the Bypass operation path 12, the memory I / F circuit 13, the internal memory 14, and the non-volatile memory 20 during Bypass operation of the memory system 1. The detailed operation of the data control circuit 18 will be described later with reference to Figures 2A to 8B.

[0024] The memory interface circuit 13 is connected to the controller circuit 16, the data control circuit 18, and the non-volatile memory 20. Based on instructions from the controller circuit 16 or the data control circuit 18, it performs write operations to the non-volatile memory 20 and read operations from the non-volatile memory 20. Signals, as described later with reference to Figure 2A, are input and output between the data control circuit 18 and the memory interface circuit 13, and between the memory interface circuit 13 and the non-volatile memory 20.

[0025] The internal memory 14 temporarily stores data received by the memory controller 10 from the host 30 or the bypass-operating host 40, or data read from the non-volatile memory 20. The detailed operation of the internal memory 14 during bypass operation will be described later with reference to Figures 2A to 8B.

[0026] During normal operation of memory system 1, data is written to non-volatile memory 20 as follows:

[0027] The host 30 inputs signals to the memory system 1 for a write command to the non-volatile memory 20, along with an address and data. The high-speed I / F circuit 15 of the memory system 1 receives the input signals and outputs them to the controller circuit 16. The controller circuit 16 instructs the memory I / F circuit 13 to write to the non-volatile memory 20. The input data may be temporarily stored in the internal memory 14. The memory I / F circuit 13 controls the writing of the input data to the storage location on the non-volatile memory 20 instructed by the controller circuit 16.

[0028] Furthermore, during normal operation of the memory system 1, data is read from the non-volatile memory 20 as follows.

[0029] The host 30 inputs a read command and address signal to the memory system 1 for the non-volatile memory 20. The high-speed I / F circuit 15 of the memory system 1 receives the input signal and outputs it to the controller circuit 16. The controller circuit 16 instructs the memory I / F circuit 13 to read the data. The memory I / F circuit 13 reads the data from the specified address in the non-volatile memory 20 according to the instructions of the controller circuit 16 and outputs the read data to the controller circuit 16. The read data may be temporarily stored in the internal memory 14. The controller circuit 16 outputs the read data to the host 30 via the high-speed I / F circuit 15.

[0030] Figure 2A is a diagram showing an example of the configuration of input / output signals for the non-volatile memory of the memory system 1 according to the embodiment. The signals shown in Figure 2A are signals used to access the non-volatile memory 20 and will be referred to as access control signals. In Figure 1, the access control signals in Figure 2A are input from the Bypass operating host 40 to the memory system 1. Then, within the memory system 1, they are received by the Bypass I / F circuit 17, transmitted to the memory I / F circuit 13 via the data control circuit 18, and input to the non-volatile memory 20. In addition, the signals output from the non-volatile memory 20 are output to the Bypass operating host 40 via the memory I / F circuit 13, the data control circuit 18, and the Bypass I / F circuit 17. The operation of the access control signals in Figure 2A will be described later with reference to Figures 5A to 8B.

[0031] Note that among the access control signals shown in Figure 2A, signals whose code begins with "N" are negative logic signals, meaning their active level is L. In some cases, " / " is used as the first character of the code for negative logic signals instead of "N". For example, the chip enable signal "NCE" may be written as " / CE". The timing charts shown in Figures 5A to 8B, described later, use " / " but represent the same signals as those using "N" in Figure 2A.

[0032] Figure 2B shows an example of the configuration of data control signals for the memory system 1 according to the embodiment. The data control signal CTRL_IN[6:0] according to the embodiment includes a data instruction enable signal CTRL_IN[6], a data pattern instruction signal CTRL_IN[5:3], and a status instruction signal CTRL_IN[2:0]. Figure 2C shows an example of the configuration of controller output signals for the memory system 1 according to the embodiment. The controller output signal CTRL_OUT[8:0] according to the embodiment includes a completion signal CTRL_OUT[8] and a comparison result signal CTRL_OUT[7:0].

[0033] The data control signal CTRL_IN[6:0] and the controller output signal CTRL_OUT[8:0] are input and output between the Bypass operation host 40 and the data control circuit 18 via the Bypass I / F circuit 17 in Figure 1. The data control signal CTRL_IN[6:0] and the controller output signal CTRL_OUT[8:0] are used to control the data input and output to the non-volatile memory 20 during Bypass operation, and to output the results read from the non-volatile memory 20 to the Bypass operation host 40. The operation of the signals shown in Figures 2B and 2C will be described later with reference to Figures 5A to 8B.

[0034] As explained above, in Figure 1, the signals handled by the Bypass I / F circuit 17 are the access control signal for the non-volatile memory 20, with the data control signal CTRL_IN[6:0] and the controller output signal CTRL_OUT[8:0] added.

[0035] Figure 3 is a block diagram of the main components 50 usable during bypass operation of the memory system 1 according to the embodiment. The data control circuit 18 includes a data generation / comparison circuit 181 and a selector 182. The data generation / comparison circuit 181 is connected to the selector 182. The selector 182 is connected to the memory I / F circuit 13, the internal memory 14, and the data generation / comparison circuit 181.

[0036] The data generation / comparison circuit 181 includes, in detail, a data generation circuit 181a that generates data and an expected value comparison circuit 181b that performs an expected value comparison. The data generation / comparison circuit 181 generates data to be written to the non-volatile memory 20. The data generation / comparison circuit 181 also compares the data read from the non-volatile memory 20 with the expected value. The selector 182 selects either the data stored in the internal memory 14 or the data generated by the data generation / comparison circuit 181 and outputs it to the memory interface circuit 13. The selector 182 also outputs the data output from the non-volatile memory 20 via the memory interface circuit 13 to the selected one of the internal memory 14 or the data generation / comparison circuit 181.

[0037] In Figure 3, solid arrows represent signal paths capable of operating at high operating frequencies, while dashed arrows represent signal paths operating at low operating frequencies. The Bypass operation host 40, the Bypass I / F circuit 17, and the parts of the data control circuit 18 and internal memory 14 that input and output signals to and from the Bypass I / F circuit 17 (hereinafter referred to as the "first part" of each) operate at low speed. The parts of the data control circuit 18 and internal memory 14 other than the first part (hereinafter referred to as the "second part" of each), the memory I / F circuit 13, and the non-volatile memory 20 can operate at high speed.

[0038] During testing of the non-volatile memory 20, the operating frequencies of the Bypass I / F circuit 17, the data control circuit 18, and the first part of the internal memory 14 can be lower than the maximum operating frequencies of the second part of the data control circuit 18 and the internal memory 14, the high-speed I / F circuit 15, and the controller circuit 16. The signals input from the Bypass operating host 40 via the Bypass I / F circuit 17 can be correctly captured internally by the memory controller 10 by latching them at an appropriate timing for the skew between those signals.

[0039] Figure 4 shows an example of an operation that can be performed during Bypass operation of the memory system 1 according to the embodiment. The memory system 1 according to the embodiment can perform two types of operations, for example, operation Op1 and operation Op2, during Bypass operation.

[0040] In operation Op1, the data to be written to the non-volatile memory 20 (hereinafter referred to as "written data") is generated within the data control circuit 18. The data generated within the data control circuit 18 is selected from a preset data pattern according to the data pattern instruction signal CTRL_IN[5:3], as shown in Figure 2B. In operation Op1, the data output from the memory system 1 to the outside (hereinafter referred to as "output data") is data showing the comparison result obtained by comparing the data read from the non-volatile memory 20 with the expected value. In operation Op1, the internal memory 14 does not need to be used.

[0041] In operation Op2, the data to be written is input from outside the memory system 1 and temporarily stored in internal memory 14. Any data can be input as the data to be written. Also, in operation Op2, the output data is arbitrary data read from non-volatile memory 20. In operation Op2, no comparison is made between the data read from non-volatile memory 20 and the expected value. The data read from non-volatile memory 20 is temporarily stored in internal memory 14 and output externally. As described above, internal memory 14 is used in operation Op2.

[0042] The operations Op1 and Op2 described above are selected by the status indicator signal CTRL_IN[2:0]. The combination of write and read operations in Op1 and Op2 is not limited to Figure 4. For example, it is possible to change the write and read combination of operations Op1 and Op2, such as performing a write to the non-volatile memory 20 with operation Op1 and reading from the non-volatile memory 20 with operation Op2.

[0043] In the memory system 1 according to this embodiment, during bypass operation, signals are not directly transmitted or received between the bypass operation host 40 and the non-volatile memory 20 for both writing to and reading from the non-volatile memory 20. By using the data control circuit 18 and internal memory 14 within the memory controller 10, signals can be transmitted and received at high speed between the memory controller 10 and the non-volatile memory 20. This enables high-speed testing of the non-volatile memory 20 and allows detection of defects that occur only during high-speed operation of the non-volatile memory 20.

[0044] Next, the operation of the memory system 1 according to the embodiment will be described in detail with reference to the timing chart. Figures 5A and 5B are timing charts illustrating the write operation in operation Op1 during bypass operation of the memory system 1. The timing charts shown hereafter are examples of a test method for the memory system 1. Due to space limitations, Figure 5A and Figure 5B are shown separately, but both show the signal behavior in the same operation, and the time axis is common to both Figure 5A and Figure 5B.

[0045] In Figures 5A and 5B, "S11" to "S15" represent steps in the write operation of operation Op1. "Data control circuit state" represents the state of the data control circuit 18, and "state (n) (n is a natural number from 1 to 7)" corresponds to the state (n) of the state instruction signal CTRL_IN[2:0] shown in Figure 2B. "Non-volatile memory state" represents the state of the non-volatile memory 20.

[0046] In Figure 5A, "CTRL_IN[6:0]" and "CTRL_OUT[8:0]" correspond to the status indicator signal CTRL_IN[6:0] shown in Figure 2B and the controller output signal CTRL_OUT[8:0] shown in Figure 2C, respectively. Here, the number written in the row for status indicator signal CTRL_IN[2:0] represents the state (n) of the status indicator signal CTRL_IN[2:0] in Figure 2B. For example, in step S12, "1" is written in the row for status indicator signal CTRL_IN[2:0]. Note that the "1" written here represents the state (1) of the status indicator signal CTRL_IN[2:0] shown in Figure 2B, that is, the state set by status indicator signal CTRL_IN[2:0]=000b, and does not represent the state indicator signal CTRL_IN[2:0]=001b.

[0047] Furthermore, in Figure 5A, the signals denoted with the symbol "(A)" are the signals at the location of (A) in Figure 1, excluding the status indicator signal CTRL_IN[6:0] and the controller output signal CTRL_OUT[8:0]. These signals correspond to the access control signals for the non-volatile memory 20 input from the Bypass operation host 40. In Figure 5B, the signals denoted with the symbol "(B)" are the signals at the location of (B) in Figure 1. These signals correspond to the access control signals input to the non-volatile memory 20 from the memory I / F circuit 13.

[0048] The following describes the operations in each step shown in Figures 5A and 5B.

[0049] Initially, the data control circuit 18 is in the "Ready" state and is capable of receiving input signals from the Bypass operation host 40.

[0050] In step S11, a write command 61a, indicated by the signal shown in Figure 5A(A), is input to the memory controller 10 from the Bypass operating host 40 via the Bypass I / F circuit 17. The write command 61a is output directly to the non-volatile memory 20 via the memory I / F circuit 13 as a write command 61b, indicated in Figure 5B(B).

[0051] The write command 61a will be explained below. From this point forward, a state where the signal is at an H level will be denoted as "1", and a state where it is at an L level will be denoted as "0".

[0052] First, the command latch enable CLE is set to 1, and while inputting 80h (=1000_0000b) indicating a write command from the data input / output terminal DQ[7:0] (hereinafter referred to as "DQ"), the write enable NWE (indicated as " / WE" in Figure 5A) is set to 1 to begin inputting the write command. Next, the command latch enable CLE is set to 0, and the address latch enable ALE is set to 1. Then, the column addresses C1 and C2, and the row addresses R1, R2, and R3, also called page addresses, are input sequentially from the data input / output terminal DQ, while setting the write enable NWE from 0 to 1 to input the addresses. Next, the address latch enable ALE is set to 0, the command latch enable CLE is set to 1, and while inputting E0h indicating the end of command input from the data input / output terminal DQ, the write enable NWE is set to 1 to complete the input of the write command 61a.

[0053] Once the input of the write command 61a is complete, the system transitions to step S12, in which the non-volatile memory 20 is in a state waiting for data input. In step S12, the data control signal CTRL_IN[6:0] is input to the memory controller 10 from the Bypass operating host 40 via the Bypass I / F circuit 17. By setting the state indicator signal CTRL_IN[2:0] to 000b, the state indicator is set to "State (1): Data generation for non-volatile memory output" in Figure 2B. Then, by setting the data pattern indicator signal CTRL_IN[5:3] for period 62 to 001b, the data pattern is set to "Random data (seed2)" in Figure 2B. Here, the value of the data pattern indicator signal CTRL_IN[5:3] is just an example, and other data patterns may be used.

[0054] Then, by setting the data instruction enable signal CTRL_IN[6] to 1b and enabling the data instruction, the values ​​of the data pattern instruction signal CTRL_IN[5:3] and the status instruction signal CTRL_IN[2:0] are input to the data control circuit 18. At this time, the data control signal CTRL_IN[6:0] becomes 100_1000b.

[0055] In step S13, write data is input to the non-volatile memory 20. As shown in Figure 5A, when the data control circuit 18 receives the state instruction signal CTRL_IN[2:0]=000b, it transitions to the "State (1): Data generation for non-volatile memory output" state and generates 4KB (4K Byte) of write data. The Bypass operating host 40 is prohibited from inputting commands to the memory controller 10 via signal (A) during the period 70 shown in Figure 5A, until it receives the completion signal CTRL_OUT[8]=1 from the memory controller 10.

[0056] As shown in Figure 5B, the memory controller 10 inputs the generated write data WDATA 81 to the non-volatile memory 20 via the memory I / F circuit 13, synchronized with the data strobe DQS from the data input / output terminal DQ. WDATA 81 and the data strobe DQS are input to the non-volatile memory 20 via the high-speed I / F circuit 15 at the same transmission speed as during normal operation.

[0057] The interval between inputting a write command to the non-volatile memory 20 and starting to input the data to be written is determined by the interval between inputting the write command 61a in step S11 and inputting the data control signal CTRL_IN[6:0] in step S12.

[0058] Once the transmission of WDATA81 to the non-volatile memory 20 is complete, the process proceeds to step S14. In step S14, the memory controller 10 outputs a completion signal CTRL_OUT[8]=1 to the Bypass operation host 40. The data control circuit 18 also transitions to the Ready state.

[0059] In step S14, when the Bypass-operating host 40 receives the completion signal CTRL_OUT[8]=1 from the memory controller 10, it becomes possible to output the following command. In step S15, the write execution command 63a shown in Figure 5A(A) is input from the Bypass-operating host 40 to the memory controller 10 via the Bypass I / F circuit 17. The write execution command 63a is output directly to the non-volatile memory 20 as the write execution command 63b shown in Figure 5B(B) via the memory I / F circuit 13.

[0060] The write execution commands 63a and 63b are explained below. First, the write execution command is entered by setting the command latch enable CLE to 1, inputting 10h (indicating the write execution command) from the data input / output terminal DQ, and setting the write enable NWE to 1. When the non-volatile memory 20 receives the write execution command 63b, it writes WDATA81. During the write execution, the ready busy signal RnB transitions to 0. When the write is complete, the ready busy signal RnB transitions to 1.

[0061] In Figures 5A and 5B, after executing the write execution command 63a, the data input / output terminal DQ is set to 70h and the status read commands 64a and 64b for the non-volatile memory 20 are executed to determine if the write operation was completed successfully. However, the status read commands 64a and 64b are just examples, and other commands may be used, or no commands may be entered at all.

[0062] The writing of 4KB of data to the non-volatile memory 20 is completed by steps S11 to S15 described above. Note that some non-volatile memory 20s have a page size of 16KB. If the page size is 16KB, it is possible to write one page's worth of data by repeating the operations shown in Figures 5A and 5B four times (=16KB / 4KB) while switching column addresses C1 and C2 within the page.

[0063] Next, the details of the read operation in operation Op1 of the memory system 1 according to this embodiment will be described. Figures 6A and 6B are timing charts illustrating the read operation in operation Op1 of the memory system 1. Both Figures 6A and 6B show the signal behavior in the same operation, and the time axis is common to both Figures 6A and 6B. The same reference numerals are used for parts that are the same as those in Figures 5A and 5B, and their explanations are omitted.

[0064] In Figures 6A and 6B, "S21" through "S24" represent the steps in the read operation of operation Op1. The operations in each step of Figures 6A and 6B will be described below.

[0065] In step S21, the Bypass operation host 40 inputs a read command 65a, shown in Figure 6A(A), to the memory controller 10 via the Bypass I / F circuit 17. The read command 65a is output directly to the non-volatile memory 20 as a read command 65b, shown in Figure 6B(B), via the memory I / F circuit 13.

[0066] The read command 65a is explained below. First, the command latch enable CLE is set to 1, and the read command input is started by inputting 05h (=0000_0101b) from the data input / output terminal DQ, while the write enable NWE ( / WE) is set to 1. Next, as explained with reference to Figures 5A and 5B, the address is entered, and then E0h, which indicates the end of command input, is entered to complete the input of the read command 65a.

[0067] Once the input of the read command 65a is complete, the process proceeds to step S22. In step S22, the data control signal CTRL_IN[6:0] is input to the memory controller 10 from the Bypass operating host 40 via the Bypass I / F circuit 17. By setting the status indicator signal CTRL_IN[2:0] to 100b, the status indicator is set to "Status (5): Non-volatile memory data input and data generation for expected value comparison and result output" in Figure 2B. Then, by setting the data pattern indicator signal CTRL_IN[5:3] for period 66 to 001b, the data pattern is set to "Random data (seed2)" in Figure 2B. The data pattern set in Figure 6A is just an example, but in order to compare the data read from the non-volatile memory 20 with the expected value, it is set to the same data pattern as the data pattern previously written to the non-volatile memory 20.

[0068] Then, by setting the data instruction enable signal CTRL_IN[6] to 1 and enabling the data instruction, the values ​​of the data pattern instruction signal CTRL_IN[5:3] and the status instruction signal CTRL_IN[2:0] are input to the data control circuit 18. At this time, the data control signal CTRL_IN[6:0] becomes 100_1100b.

[0069] In step S23, data is read from the non-volatile memory 20. As shown in Figure 6A, when the data control circuit 18 receives the status instruction signal CTRL_IN[2:0]=100b, it transitions to the "Wait" state, waiting for data to be read from the non-volatile memory 20, as a preparation state for "State (5): Input of non-volatile memory data and generation of data for expected value comparison and result output". The Bypass operation host 40 is prohibited from inputting commands to the memory controller 10 via signal (A) until it receives the completion signal CTRL_OUT[8]=1 from the memory controller 10, which is shown as a period 70 in Figure 6A.

[0070] The non-volatile memory 20 performs data readout and, as shown in Figure 6B, outputs the read data, RDATA82, to the memory controller 10 via the memory I / F circuit 13 from the data input / output terminal DQ in synchronization with the data strobe DQS. RDATA82 and the data strobe DQS are output from the non-volatile memory 20 via the high-speed I / F circuit 15 at the same transmission speed as during normal operation.

[0071] When data is read from the non-volatile memory 20, the data control circuit 18 transitions to the state "State (5): Input of non-volatile memory data and generation of data for expected value comparison and result output". The data control circuit 18 generates a 4KB expected value and compares it with the RDATA 82 read from the non-volatile memory 20.

[0072] Once all 4KB of read data, RDATA82, has been read from the non-volatile memory 20 and the comparison between RDATA82 and the expected value is complete, the process proceeds to step S24. In step S24, the memory controller 10 outputs a completion signal CTRL_OUT[8]=1 to the Bypass operating host 40 and outputs a comparison result signal CTRL_OUT[7:0] during period 67. Accordingly, the data control circuit 18 transitions to the Ready state.

[0073] The comparison result signal CTRL_OUT[7:0] represents the number of bits (hereinafter referred to as the "bit flip number") in which the read data does not match the expected value. When the comparison result signal CTRL_OUT[7:0] is FFh (1111_1111b), it indicates that the bit flip number is 255 bits or more. In this embodiment, the comparison result signal CTRL_OUT[7:0] is set to 8 bits, but it is possible to indicate a bit flip number of 256 bits or more by increasing the bit width.

[0074] In step S24, when the Bypass-operating host 40 receives the completion signal CTRL_OUT[8]=1 from the memory controller 10, it becomes possible to output the following commands. In Figures 6A and 6B, after executing the read commands 65a and 65b, the data input / output terminal DQ is set to 70h and the status read commands 64a and 64b for the non-volatile memory 20 are executed to determine if the read operation was completed successfully. However, the status read commands 64a and 64b are just examples, and other commands may be used, or no commands may be entered at all.

[0075] Steps S21 to S24 described above complete the reading of 4KB of data from the non-volatile memory 20. If the page size of the non-volatile memory 20 is 16KB, one page's worth of data can be read by repeating the operations shown in Figures 6A and 6B four times while switching column addresses C1 and C2 within the page.

[0076] The write and read operations in operation Op1 of the memory system 1 according to this embodiment have been described above. Next, the details of the write operation in operation Op2 of the memory system 1 will be described.

[0077] Figures 7A and 7B are timing charts illustrating the write operation in operation Op2 of memory system 1. Both Figures 7A and 7B show the signal behavior in the same operation, and the time axis is common to both Figures 7A and 7B. The same reference numerals are used for parts identical to those in Figures 5A and 5B, and their explanations are omitted.

[0078] In Figures 7A and 7B, "S31" to "S38" represent the steps in the write operation of operation Op2. Compared with Figures 5A and 5B, Figures 7A and 7B differ in the following respects. In Figure 7A, data input 83, which inputs write data, is performed in steps S31 to S33. Also, in Figure 5A, in step S12, which is before step S13, which inputs data to the non-volatile memory 20, the state indicator signal CTRL_IN[2:0] is set to state (1), whereas in Figure 7A, in step S35, the state indicator signal CTRL_IN[2:0] is set to state (4). The operation in each step of Figures 7A and 7B will be described below.

[0079] In step S31, the data control signal CTRL_IN[6:0] is input from the Bypass operating host 40 to the memory controller 10 via the Bypass I / F circuit 17. By setting the status instruction signal CTRL_IN[2:0]=001b, the status instruction is set to "Status (2): Host data input for internal memory writing". As will be described later, in operation Op2, the data pattern instruction signal CTRL_IN[5:3] becomes "Don't care". As an example, the data pattern instruction signal CTRL_IN[5:3]=000b. Then, the data instruction enable signal CTRL_IN[6]=1 causes the memory controller 10 to take in the value of the status instruction signal CTRL_IN[2:0]. At this time, the data control signal CTRL_IN[6:0] becomes 100_0001b.

[0080] When the data control circuit 18 receives the state instruction signal CTRL_IN[2:0]=001b, it transitions to state (2). This makes it possible to input data to write to the internal memory 14.

[0081] In step S32, data input 83 for write data is sent from the Bypass operating host 40 through the data input / output terminal DQ in synchronization with the toggle of the write enable NWE ( / WE). As a result, the write data is input to the memory controller 10. The input write data is written to the internal memory 14 via the data control circuit 18 and temporarily stored.

[0082] Once the writing of the data to be written to the internal memory 14 is complete, in step S33, the data control signal CTRL_IN[6:0] is input from the Bypass operating host 40 to the memory controller 10 via the Bypass I / F circuit 17. By setting the status instruction signal CTRL_IN[2:0]=010b, the status instruction is set to "Status (3): Host data input complete" in Figure 2B. Then, the data instruction enable signal CTRL_IN[6]=1 causes the memory controller 10 to take in the value of the status instruction signal CTRL_IN[2:0]. At this time, the data control signal CTRL_IN[6:0]=100_0010b. When the data control circuit 18 receives the status instruction signal CTRL_IN[2:0]=010b, it finishes writing the data to the internal memory 14 and transitions to the Ready state.

[0083] In step S34, the write command 61a shown in Figure 7A(A) is input to the memory controller 10 from the Bypass operating host 40 via the Bypass I / F circuit 17. The write command 61a is output directly to the non-volatile memory 20 as the write command 61b shown in Figure 7B(B) via the memory I / F circuit 13. The write commands 61a and 61b are the same as those described with reference to Figures 5A and 5B, so their explanation is omitted.

[0084] Once the input of the write command 61a is complete, the system transitions to step S35, where the non-volatile memory 20 is in a state waiting for data input. In step S35, the data control signal CTRL_IN[6:0] is input to the memory controller 10 from the Bypass operating host 40 via the Bypass I / F circuit 17. By setting the state instruction signal CTRL_IN[2:0] to 011b, the state instruction is set to "State (4): Internal memory read for non-volatile memory output" in Figure 2B. Selecting state (4) instructs the system to handle arbitrary data, so the data pattern instruction signal CTRL_IN[5:3] becomes "Don't care". Then, the data instruction enable signal CTRL_IN[6]=1 causes the memory controller 10 to take in the value of the state instruction signal CTRL_IN[2:0]. At this time, the data control signal CTRL_IN[6:0] becomes 100_0011b.

[0085] In step S36, when the data control circuit 18 receives the status indicator signal CTRL_IN[2:0]=011b, it transitions to the state "State (4): Internal memory read for non-volatile memory output". As shown in Figure 7B, the memory controller 10 inputs WDATA81, which is the write data read from the internal memory 14, to the non-volatile memory 20 via the memory I / F circuit 13, synchronized with the data strobe DQS from the data input / output terminal DQ. WDATA81 and the data strobe DQS are input to the non-volatile memory 20 via the high-speed I / F circuit 15 at the same transmission speed as during normal operation.

[0086] The interval between inputting a write command to the non-volatile memory 20 and starting to input the write data is determined by the interval between inputting the write command 61a in step S34 and inputting the data control signal CTRL_IN[6:0] in step S35. The Bypass operation host 40 is prohibited from inputting commands to the memory controller 10 via signal (A) during the period 70 shown in Figure 7A, until it receives the completion signal CTRL_OUT[8]=1 from the memory controller 10.

[0087] Once the transmission of the WDATA81 data to the non-volatile memory 20 is complete, the process proceeds to step S37. In step S37, the memory controller 10 outputs a completion signal CTRL_OUT[8]=1 to the Bypass operation host 40. The data control circuit 18 also transitions to the Ready state.

[0088] In step S37, when the Bypass-operating host 40 receives the completion signal CTRL_OUT[8]=1 from the memory controller 10, it becomes possible to output the following command. In step S38, the write execution command 63a shown in Figure 7A(A) is input from the Bypass-operating host 40 to the memory controller 10 via the Bypass I / F circuit 17. The write execution command 63a is output directly to the non-volatile memory 20 as the write execution command 63b shown in Figure 7B(B) via the memory I / F circuit 13. The write execution commands 63a and 63b are the same as those described with reference to Figures 5A and 5B, so their explanation is omitted.

[0089] In Figures 7A and 7B, after executing the write execution command 63a, status read commands 64a and 64b for the non-volatile memory 20 are executed to determine if the write operation was completed successfully. However, status read commands 64a and 64b are just examples; other commands may be used, or no commands may be entered at all.

[0090] The writing of 4KB of data to the non-volatile memory 20 is completed by steps S31 to S38 described above. In the write operation of operation Op2 described above, arbitrary data to be written is temporarily stored at low speed in the internal memory 14 from the Bypass operation host 40, and then written at high speed to the non-volatile memory 20. According to the write operation of operation Op2, it is possible to write arbitrary data to the non-volatile memory 20 at high speed. If the page size of the non-volatile memory 20 is 16KB, it is possible to write one page's worth of data by repeating the operations shown in Figures 7A and 7B four times while switching column addresses C1 and C2 within the page.

[0091] Figures 8A and 8B are timing charts illustrating the read operation in operation Op2 of the memory system 1. Both Figures 8A and 8B show the signal behavior in the same operation, and the time axis is common to both Figures 8A and 8B. The same reference numerals are used for parts identical to those in Figures 6A and 6B, and their explanations are omitted.

[0092] In Figures 8A and 8B, "S41" to "S47" represent the steps in the read operation of operation Op2. Compared with Figures 6A and 6B, Figures 8A and 8B differ in the following points. In Figure 6A, in step S22, which precedes step S23, the step in which data is read from the non-volatile memory 20, the state indicator signal CTRL_IN[2:0] is set to state (5). In contrast, in Figure 8A, in step S42, the state indicator signal CTRL_IN[2:0] is set to state (6). Also, in Figure 8A, in steps S45 to S47, data output 84 is performed to output the read data. The operation in each step of Figures 8A and 8B will be described below.

[0093] In step S41, the read command 65a shown in Figure 8A(A) is input to the memory controller 10 from the Bypass operating host 40 via the Bypass I / F circuit 17. The read command 65a is output directly to the non-volatile memory 20 as the read command 65b shown in Figure 8B(B) via the memory I / F circuit 13. The read command 65a is the same as described with reference to Figure 6A, so its explanation is omitted.

[0094] Once the input of the read command 65a is complete, the process proceeds to step S42. In step S42, the data control signal CTRL_IN[6:0] is input to the memory controller 10 from the Bypass operating host 40 via the Bypass I / F circuit 17. By setting the status instruction signal CTRL_IN[2:0] to 101b, the status instruction is set to "Status (6): Input of non-volatile memory data for internal memory writing" in Figure 2B. By selecting status (6), it is instructed to handle arbitrary data, so the data pattern instruction signal CTRL_IN[5:3] becomes "Don't care".

[0095] Then, by setting the data instruction enable signal CTRL_IN[6] to 1 and enabling the data instruction, the value of the status instruction signal CTRL_IN[2:0] is input to the data control circuit 18. At this time, the data control signal CTRL_IN[6:0] becomes 100_0101b.

[0096] In step S43, data is read from the non-volatile memory 20. As shown in Figure 8A, when the data control circuit 18 receives the status instruction signal CTRL_IN[2:0]=101b, it transitions to a Wait state, waiting for data to be read from the non-volatile memory 20, as a preparation state for "State (6): Input of non-volatile memory data for internal memory writing". The Bypass operation host 40 is prohibited from inputting commands to the memory controller 10 via signal (A) until it receives the completion signal CTRL_OUT[8]=1 from the memory controller 10, which is shown as a period 70 in Figure 8A.

[0097] The non-volatile memory 20 performs data readout and, as shown in Figure 8B, outputs the read data, RDATA82, to the memory controller 10 via the memory I / F circuit 13 from the data input / output terminal DQ in synchronization with the data strobe DQS. RDATA82 and the data strobe DQS are output from the non-volatile memory 20 via the high-speed I / F circuit 15 at the same transmission speed as during normal operation.

[0098] When data is read from the non-volatile memory 20, the data control circuit 18 transitions to the state "State (6): Non-volatile memory data input for internal memory writing". The data control circuit 18 writes the RDATA82, which is the data read from the non-volatile memory 20, to the internal memory 14 for temporary storage.

[0099] Once all 4KB of RDATA82 has been read from the non-volatile memory 20, the process proceeds to step S44. In step S44, the memory controller 10 outputs a completion signal CTRL_OUT[8]=1 to the Bypass operating host 40. Consequently, the data control circuit 18 transitions to the Ready state.

[0100] In step S44, when the Bypass-operating host 40 receives the completion signal CTRL_OUT[8]=1 from the memory controller 10, it becomes possible to output the following commands. In Figures 8A and 8B, after executing the read commands 65a and 65b, status read commands 64a and 64b for the non-volatile memory 20 are executed to determine whether the read was completed successfully. However, status read commands 64a and 64b are just examples, and commands do not necessarily have to be entered.

[0101] In step S45, the Bypass-operating host 40 inputs the data control signal CTRL_IN[6:0] to the memory controller 10 via the Bypass I / F circuit 17. By setting the status instruction signal CTRL_IN[2:0] to 110b, the status instruction is set to "Status (7): Read from internal memory for host output". Then, the data instruction enable signal CTRL_IN[6]=1 causes the memory controller 10 to receive the status instruction signal CTRL_IN[2:0]=110b, which specifies status (7). At this time, the data control signal CTRL_IN[6:0] becomes 100_0110b. When the data control circuit 18 receives the status instruction signal CTRL_IN[2:0]=110b, it transitions to the "Status (7): Read from internal memory for host output" state. This makes it possible to output read data from the internal memory 14.

[0102] In step S46, synchronized with the toggle of the read-enable NRE (indicated as " / RE" in Figure 8A), the read data from the internal memory 14 is output to the bypass-operating host 40 through the data input / output terminal DQ.

[0103] When the reading of data from the internal memory 14 is complete, in step S47, the memory controller 10 outputs a completion signal CTRL_OUT[8]=1 to the Bypass operating host 40. Accordingly, the data control circuit 18 transitions to the Ready state. In step S47, when the Bypass operating host 40 receives the completion signal CTRL_OUT[8]=1 from the memory controller 10, it becomes possible to output the following command.

[0104] The reading of 4KB of data from the non-volatile memory 20 is completed by steps S41 to S47 described above. In the reading operation of operation Op2 described above, arbitrary data read from the non-volatile memory 20 is temporarily stored at high speed in the internal memory 14, and then output to the Bypass operation host 40 at low speed. According to the reading operation of operation Op2, it is possible to read arbitrary data from the non-volatile memory 20 at high speed. If the page size of the non-volatile memory 20 is 16KB, it is possible to read one page's worth of data by repeating the operations shown in Figures 8A and 8B four times while switching column addresses C1 and C2 within the page.

[0105] Furthermore, the non-volatile memory 20 of the memory system 1 may be capable of performing erase operations in addition to data write and read operations. If the non-volatile memory 20 is capable of performing erase operations, during bypass operation, the bypass operation host 40 can input an erase command to the memory system 1 using the access control signal shown in Figure 2A, thereby causing the non-volatile memory 20 to perform an erase operation.

[0106] To facilitate understanding of the features of the embodiments of the present invention, a comparative memory system will now be described. Figure 9 is a block diagram of the comparative memory system 91. The same reference numerals are used for parts identical to those in Figure 1, and their descriptions are omitted.

[0107] The comparative example memory system 91 in Figure 9 includes a high-speed I / F circuit 915, a controller circuit 916, a bypass I / F circuit 917, a memory I / F circuit 913, and internal memory 914. During normal operation, the memory system 91 is connected to the host 30 via the high-speed I / F circuit 915. During testing, the memory system 91 is connected to the bypass-operating host 940 via the bypass I / F circuit 917. The memory system 91 can switch between normal operation using the high-speed I / F circuit 915 and bypass operation using the bypass I / F circuit 917 by setting a register internally provided in the memory controller 910, or by applying a voltage to a dedicated terminal when the power is turned on.

[0108] Compared to Figure 1, Figure 9 differs in the following respects. In Figure 1, the memory controller 10 is equipped with a data control circuit 18. Also in Figure 1, the data control signal CTRL_IN[6:0] and the controller output signal CTRL_OUT[8:0] are input and output between the Bypass operation host 40, the Bypass I / F circuit 17, and the data control circuit 18. In contrast, in Figure 9, the memory controller 910 is not equipped with a data control circuit 18. Also, in Figure 9, the data control signal CTRL_IN[6:0] and the controller output signal CTRL_OUT[8:0] are not input and output between the Bypass operation host 940 and the Bypass I / F circuit 917.

[0109] Figure 10 is a block diagram of the main components 950 usable during bypass operation of the comparative example memory system 91. The same reference numerals are used for parts identical to those in Figure 3, and their explanations are omitted. In Figure 10, the dashed arrows represent signal paths operating at low operating frequencies. The parts that input and output signals between the bypass operation host 940, the bypass I / F circuit 917, and the memory I / F circuit 13 operate at a low speed.

[0110] The Bypass I / F circuit 917 is connected to the non-volatile memory 20 via the memory I / F circuit 913, without going through the controller circuit 916. Therefore, it is possible to directly output and execute any command to control the non-volatile memory 20 from the Bypass operating host 940 to the non-volatile memory 20. However, as mentioned above, there is a skew between the signals input from the Bypass operating host 940 via the Bypass I / F circuit 917. Therefore, in order for the signal to be properly latched inside the memory controller 910, the signal must be input at a low frequency, resulting in a slow test of the non-volatile memory 20. In the comparative example memory system 91, because the test is slow, it is not possible to detect defects that occur only during high-speed operation of the non-volatile memory 20.

[0111] In comparison with the comparative example shown in Figure 9, the memory system 1 according to the embodiment shown in Figure 1 includes a data control circuit 18, and data control is possible using the data control signal CTRL_IN[6:0] and the controller output signal CTRL_OUT[8:0]. The data control circuit 18 and the internal memory 14 of the memory system 1, excluding the parts that input and output signals to and from the Bypass I / F circuit 17, are capable of high-speed operation. In the memory system 1, by using the data control circuit 18 and the internal memory 14 during Bypass operation, signals can be sent and received at high speed between the memory controller 10 and the non-volatile memory 20. This enables high-speed testing of the non-volatile memory 20 and allows detection of defects that occur only during high-speed operation of the non-volatile memory 20.

[0112] (Effects of the embodiment) According to the memory system 1 of this embodiment, during bypass operation, signals can be sent and received at high speed between the memory controller 10 and the non-volatile memory 20 by using the data control circuit 18 and the internal memory 14. This enables high-speed testing of the non-volatile memory 20 and allows detection of defects that occur only during high-speed operation of the non-volatile memory 20.

[0113] According to the memory system 1 of this embodiment, during bypass operation, it is possible to select and execute a desired operation from, for example, operation Op1 and operation Op2. In operation Op1, data to be written to the non-volatile memory 20 can be generated within the data control circuit 18, and the comparison result obtained by comparing the data read from the non-volatile memory 20 with the expected value can be output externally. In operation Op2, arbitrary data to be written to the non-volatile memory 20 can be input from outside the memory system 1, and arbitrary data read from the non-volatile memory 20 can be output externally. As described above, high-speed testing can be performed according to the purpose of the test and the test environment.

[0114] [Other embodiments] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents.

[0115] For example, in the memory system 1 according to the embodiment, an example was shown in which two types of operations, operation Op1 and operation Op2, can be executed. However, the memory system 1 is not limited to this, and for example, it may be possible to make either operation Op1 or operation Op2 executable, and not include the other operation specification. By not including one of the operation specifications, the circuit size of the data control circuit 18 or the internal memory 14 can be reduced, and the chip size of the memory controller 10 can be reduced. For example, if the operation specification for operation Op2 is not included, the internal memory 14 may not be used, and the circuit size of the internal memory 14 may be reduced.

[0116] Furthermore, in the description of the memory system 1 according to the above embodiment, an example was shown of using bypass operation with the data control circuit 18 in testing or failure analysis of the memory system 1. However, the example of using bypass operation with the data control circuit 18 is not limited to this. For example, if a failure occurs in the controller circuit 16 or the like after the memory system 1 has been shipped, and some of the functions of the memory system 1 do not work, the user's system developer may use bypass operation to directly access the non-volatile memory 20.

[0117] Furthermore, in the memory system 1 according to the embodiment, a case was shown where NAND flash memory was used as the non-volatile memory 20. However, the non-volatile memory 20 is not limited to semiconductor memory, but may be various storage media other than semiconductor memory. [Explanation of Symbols]

[0118] 1. Memory System 10 Memory Controllers 11 Normal operation path section 12 Bypass operation path section 13. Memory I / F Circuit 14 Internal Memory 15 High-speed I / F circuit (second input / output circuit) 16. Controller Circuit (First Control Circuit) 17 Bypass I / F circuit (1st input / output circuit) 18. Data control circuit 20 Non-volatile memory 30 hosts 40 Bypass-operating hosts 181 Data generation / comparison circuit 181a Data generation circuit 181b Expected Value Comparison Circuit 182 Selector CTRL_IN[2:0] Status indicator signal CTRL_IN[5:3] Data pattern instruction signal CTRL_IN[6] Data instruction enable signal CTRL_IN[6:0] Data control signal CTRL_OUT[7:0] Comparison result signal CTRL_OUT[8] Completion signal CTRL_OUT[8:0] Controller output signal Steps S11-S15, S21-S24, S31-S38, S41-S47

Claims

1. Non-volatile memory and A controller capable of controlling the aforementioned non-volatile memory, Equipped with, The aforementioned controller, A first input / output circuit capable of receiving an access control signal and a data control signal for accessing the non-volatile memory and outputting a signal based on the data read from the non-volatile memory, A data control circuit that controls the data to be input to the non-volatile memory and the data output from the non-volatile memory based on the data control signal input from the first input / output circuit, Equipped with, Memory system.

2. The aforementioned data control signal is A data pattern instruction signal that instructs the data pattern to be input / output to the non-volatile memory, A status indicator signal that indicates the state of input / output to the non-volatile memory, including, The memory system according to claim 1.

3. The memory system according to claim 1, wherein the data control circuit includes a data generation circuit that generates write data to be input to the non-volatile memory based on the data control signal.

4. The memory system according to claim 3, wherein the controller is capable of inputting into the non-volatile memory a combination of the access control signal input from the first input / output circuit and the write data generated by the data generation circuit, based on the data control signal.

5. The memory system according to claim 4, wherein the controller is capable of inputting the written data to the non-volatile memory at an operating frequency higher than the operating frequency of the first input / output circuit.

6. The memory system according to claim 1, wherein the data control circuit includes an expected value comparison circuit that compares the read data output from the non-volatile memory with an expected value based on the data control signal.

7. The memory system according to claim 6, wherein the controller is capable of outputting the output of the expected value comparison circuit from the first input / output circuit based on the data control signal.

8. The memory system according to claim 7, wherein the controller is capable of causing the non-volatile memory to perform a read operation at an operating frequency higher than the operating frequency of the first input / output circuit.

9. The controller further comprises an internal memory located inside the controller, The internal memory is capable of storing the write data input to the non-volatile memory from the first input / output circuit. The memory system according to claim 1.

10. The memory system according to claim 9, wherein the controller is capable of inputting the access control signal input from the first input / output circuit and the write data stored in the internal memory into the non-volatile memory based on the data control signal.

11. The controller further comprises an internal memory located inside the controller, The aforementioned internal memory is capable of storing the data read from the aforementioned non-volatile memory. The memory system according to claim 1.

12. The memory system according to claim 11, wherein the controller is capable of outputting the read data stored in the internal memory from the first input / output circuit based on the data control signal.

13. The aforementioned controller, A second input / output circuit that inputs and outputs signals for controlling the normal operation of the non-volatile memory, A first control circuit capable of controlling the normal operation of the non-volatile memory based on signals input from the second input / output circuit, Furthermore, The first input / output circuit and the data control circuit are operational during testing of the non-volatile memory. The second input / output circuit and the first control circuit are operable during the normal operation of the non-volatile memory. The memory system according to claim 1.

14. The data control circuit includes a first part that inputs and outputs signals to the first input / output circuit, and a second part other than the first part. The memory system according to claim 13, wherein the operating frequency of the non-volatile memory of the first input / output circuit and the first portion of the data control circuit during testing can be made lower than the maximum operating frequency of the second portion of the data control circuit, the second input / output circuit, and the first control circuit.

15. The memory system according to any one of claims 1 to 14, wherein the non-volatile memory is a NAND flash memory.

16. The memory system according to claim 15, wherein the NAND flash memory and the controller are housed in the same package to constitute an MCP.

17. A method for testing a memory system according to claim 1, The steps include: inputting a write command to the memory system using the access control signal; The steps include: inputting the data control signal to the memory system and setting the controller to input data to the non-volatile memory; The steps include: the controller generating the data and inputting it into the non-volatile memory; The steps include causing the data to be written to the non-volatile memory, including, Testing methods for memory systems.

18. A method for testing a memory system according to claim 1, The steps include: inputting a read command to the memory system using the access control signal; The steps include: inputting the data control signal to the memory system and setting an expected value in the controller; The controller performs the steps of comparing the data read from the non-volatile memory with the expected value and generating a comparison result, The steps include outputting the comparison result from the memory system, including, Testing methods for memory systems.

19. A method for testing a memory system according to claim 9, The steps include: inputting the data control signal to the memory system to set the internal memory in a state where data can be input; The steps include inputting data into the internal memory, The steps include: inputting the data control signal to the memory system and ending the state in which the data can be input; The steps include: inputting a write command to the memory system using the access control signal; The steps include: setting the memory system to input the data control signal and read data from the internal memory to be input to the non-volatile memory; The steps include reading data from the internal memory to be input to the non-volatile memory and inputting it into the non-volatile memory, The steps include causing the data to be written to the non-volatile memory, including, Testing methods for memory systems.

20. A method for testing a memory system according to claim 11, The steps include: inputting a read command to the memory system using the access control signal; The steps include: setting the memory system to input the data control signal and input the data read from the non-volatile memory into the internal memory; The steps include inputting the data read from the non-volatile memory into the internal memory, The steps include: inputting the data control signal to the memory system and setting the internal memory to a state where it can output the data input to the internal memory; The memory system outputs the data input to the internal memory, The steps include: inputting the data control signal to the memory system and ending the state in which the data can be outputted; including, Testing methods for memory systems.

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