Electronic components and equipment equipped with electronic components

Abstract

To provide an electronic component with a structure that can suppress temperature rise. [Solution] The electronic component comprises a semiconductor substrate, a base, a cooling member, and a plate member. The plate member is positioned between the heat-absorbing side of the cooling member and the semiconductor substrate, the base is positioned on the heat-generating side of the cooling member, a first electrode is positioned on the semiconductor substrate, a second electrode and a third electrode are positioned on the plate member, and a fourth electrode is positioned on the base. The second electrode and the third electrode are connected by wiring in the plate member, the first electrode and the second electrode are connected by a first conductive wire, and the third electrode and the fourth electrode are connected by a second conductive wire.

Description

[Technical Field]

[0001] The present invention relates to an electronic component and an apparatus including the electronic component. [Background Art]

[0002] Patent Document 1 discloses an electronic apparatus having a Peltier element and an image pickup element. [Prior Art Documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2006-191465 [Summary of the Invention] [Problem to be Solved by the Invention]

[0004] In an electronic component obtained by wire-bonding a semiconductor substrate placed on a cooling member such as a Peltier element and a package on which the semiconductor substrate is placed, a heat flow may occur in which heat on the heat generation side of the cooling member returns from the package to the substrate via the wires. This may cause a temperature rise of the electronic component. An object of the present invention is to provide an electronic component having a structure capable of suppressing a temperature rise. [Means for Solving the Problem]

[0005] In view of the above problem, an electronic component according to an embodiment of the present invention includes a semiconductor substrate, a base body, a cooling member, and a plate member. The plate member is disposed between the heat absorption side of the cooling member and the semiconductor substrate, the base body is disposed on the heat generation side of the cooling member, a first electrode is disposed on the semiconductor substrate, a second electrode and a third electrode are disposed on the plate member, a fourth electrode is disposed on the base body, the second electrode and the third electrode are connected by a wiring of the plate member, the first electrode and the second electrode are connected by a first conductive wire, and the third electrode and the fourth electrode are connected by a second conductive wire. [Effects of the Invention]

[0006] According to the present invention, it is possible to provide an electronic component with a structure that can suppress temperature rise. [Brief explanation of the drawing]

[0007] [Figure 1] A schematic cross-sectional view of an electronic component according to the first embodiment. [Figure 2] A schematic top view of an electronic component according to the first embodiment. [Figure 3] A schematic view of the bottom of an electronic component according to the first embodiment. [Figure 4] A schematic diagram of an electronic component according to the first embodiment. [Figure 5] A schematic diagram of a plate member according to the first embodiment. [Figure 6] A schematic cross-sectional view of an electronic component according to the second embodiment. [Figure 7] A schematic top view of an electronic component according to the second embodiment. [Figure 8] A diagram illustrating a method for forming conductive wires for electronic components according to the second embodiment. [Figure 9] A diagram illustrating a method for forming conductive wires for electronic components according to the second embodiment. [Figure 10] A schematic cross-sectional view of an electronic component according to the third embodiment. [Figure 11] A schematic top view of an electronic component according to the third embodiment. [Figure 12] A schematic diagram of an electronic component according to the third embodiment. [Figure 13] A schematic diagram of a plate member according to the third embodiment. [Figure 14] A schematic cross-sectional view of an electronic component according to the fourth embodiment. [Figure 15] A schematic top view of an electronic component according to the fourth embodiment. [Figure 16] A diagram illustrating an example of applying the electronic component according to the present invention to a device. [Modes for carrying out the invention]

[0008] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The following embodiments do not limit the invention according to the claims. Although a plurality of features are described in the embodiments, not all of the plurality of features are essential to the invention, and the plurality of features may be arbitrarily combined. Furthermore, in the accompanying drawings, the same or similar configurations are denoted by the same reference numerals, and duplicate explanations are omitted.

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, terms indicating specific directions and positions (for example, "up", "down", "right", "left", and other terms including these terms) are used as necessary. The use of these terms is for facilitating the understanding of the embodiments with reference to the drawings, and the technical scope of the present invention is not limited by the meanings of these terms.

[0010] In this specification, plan view refers to viewing from a direction perpendicular to the light incident surface of the semiconductor layer. When an optical member is disposed on the light incident side, viewing may be performed from the optical member or from the opposite side. In addition, cross-sectional view refers to a plane in a direction perpendicular to the light incident surface of the semiconductor layer. When the light incident surface of the semiconductor layer is rough when viewed microscopically, the plan view is defined based on the light incident surface of the semiconductor layer when viewed macroscopically.

[0011] The semiconductor layer has a first surface on which light is incident, and a second surface on a side opposite to the first surface. In the present specification, when a PD (photodiode) is disposed in the semiconductor layer, the depth direction refers to a direction from the first surface toward the second surface of the semiconductor layer. The "depth" of a certain point or a certain region in the semiconductor layer means a distance from the first surface to the point or the region. When there are a point (or region) Z1 at which a distance (depth) from the first surface is d1, and a point (or region) Z2 at which a distance (depth) from the first surface is d2, and d1>d2, this may also be expressed as "Z1 is deeper than Z2" or "Z2 is shallower than Z1". Further, when there is a point (or region) Z3 at which a distance (depth) from the first surface is d3, and d1>d3>d2 holds, this may also be expressed as "Z3 is at a depth between Z1 and Z2" or "Z3 is between Z1 and Z2 in the depth direction".

[0012] In the present specification, unless explicitly defined, expressions such as "A or B", "at least one of A and B", "at least one of A and / or B", and "one or more of A and / or B" may include all possible combinations of the listed items. That is, the above expressions are understood to disclose all cases: a case including at least one A, a case including at least one B, and a case including both at least one A and at least one B. This also applies similarly to combinations of three or more elements.

[0013] The disclosure of the present specification includes complements of the concepts described in the present specification. That is, if the present specification describes, for example, that "A is larger than B", it can be said that the present specification discloses "A is not larger than B" even if the description of "A is not larger than B" is omitted. This is because when a statement that "A is larger than B" is described, the statement is based on the premise that the case where "A is not larger than B" is taken into consideration.

[0014] (First Embodiment) Electronic components according to embodiments of this disclosure will be described with reference to Figures 1 to 5. Semiconductor chips housed in a package may change their characteristics due to heat generation. In the case of electronic components equipped with a photoelectric conversion element as an image sensor, noise may be generated in the output signal of the photoelectric conversion element due to temperature changes. To reduce noise, a cooling member for cooling the semiconductor chip may be placed on the package on which the semiconductor chip with the photoelectric conversion element is mounted. One example of a member used for cooling a semiconductor chip is a Peltier element. In the following embodiments, an electronic component having a photoelectric conversion element and a Peltier element as a cooling member will be described, but the element mounted on the semiconductor chip is not limited to a photoelectric conversion element. Furthermore, the cooling member is not limited to a Peltier element, but may be a cooling fin, heat pipe, etc.

[0015] This embodiment will be explained with reference to a cross-sectional view showing an example of the configuration of the electronic component shown in Figure 1. The electronic component may include a package 100 having a substrate 101 and an optical member 102 bonded to the frame of the substrate 101 by an optical member adhesive 107. Alternatively, the electronic component may include a substrate 101, a semiconductor substrate 103, a cooling member 200, and a plate member 301.

[0016] In this embodiment, the cooling member 200 is bonded to the bottom of the base body 101 by a cooling adhesive 105, and the semiconductor substrate 103 is bonded to it by a semiconductor substrate adhesive 106. The semiconductor substrate 103 is electrically connected to the base body 101 via a heat-absorbing plate member 301 of the cooling member 200 by a first conductive wire 108 and a second conductive wire 110. The base body 101 is formed mainly from ceramics such as alumina or aluminum nitride. Since these materials have high thermal conductivity, the heat generated by the cooling member 200 is easily dissipated to the outside of the package.

[0017] The optical component 102 is made of glass, quartz, sapphire, etc. Quartz and sapphire can also function as low-pass filters (LPFs). Sapphire has higher strength than quartz and can be made thinner. That is, it is advantageous for miniaturizing the entire package 100. In addition, since the coefficient of thermal expansion of sapphire is about the same as that of alumina, if the substrate 101 is alumina and the optical component 102 is sapphire, the reliability of adhesion can be increased.

[0018] The semiconductor substrate 103 is, for example, a silicon substrate, and is provided with a pixel region 104 in which a plurality of photoelectric conversion elements are arranged in an array. The photoelectric conversion elements may be, for example, CMOS image sensors or avalanche diodes. If the photoelectric conversion elements are avalanche diodes, the photoelectric conversion elements may also be SPADs (Single Photon Avalanche Diodes).

[0019] For the cooling section adhesive 105 and the semiconductor substrate adhesive 106, it is preferable to use materials with high thermal conductivity, such as silver paste. Since gaps in the bonding surface hinder heat conduction, the adhesive should be applied to as wide a surface as possible, or even to the entire surface. The thickness of the adhesives for the cooling section adhesive 105 and the semiconductor substrate adhesive 106 should be approximately 100 μm or less, and preferably around 20-30 μm.

[0020] The optical component adhesive 107 can be an epoxy-based adhesive. It may be an UV-curing adhesive or a thermosetting adhesive. Since the inside of the package 100 may be kept in an atmosphere of N2, Ar, Xe, etc. or under vacuum for insulation purposes, it is preferable to use an adhesive with low moisture permeability that can maintain airtightness.

[0021] To maintain low moisture permeability, the adhesive thickness of the optical component adhesive 107 should be thin and the adhesive width wide. For example, the thickness of the optical component adhesive 107 should be 20-30 μm or less. The adhesive width can be determined from the standpoint of miniaturizing the package 100, ensuring adhesive reliability, and maintaining moisture permeability.

[0022] The cooling member 200 consists of a cooling section 201 in which metal electrodes, P-type semiconductors, and N-type semiconductors are alternately connected, a plate member 301 positioned above the area where the cooling section 201 is located, and a lower flat plate 203 positioned below the area where the cooling section 201 is located. The plate member 301 is positioned between the cooling section 201 and the semiconductor substrate 103, and the lower flat plate 203 is positioned between the cooling section 201 and the bottom of the base body 101.

[0023] In this embodiment, multiple wirings can be stacked on the plate member 301. The plate member 301 is positioned on the heat-absorbing side of the cooling section 201 (hereinafter referred to as the "heat-absorbing surface"), and the lower flat plate 203 is positioned on the heat-generating side of the cooling section 201 (hereinafter referred to as the "heat-generating surface"). In the electronic component according to this embodiment, the plate member 301 positioned on the heat-absorbing side faces the semiconductor substrate 103, and the lower flat plate 203 positioned on the heat-generating side faces the base body 101. The plate member 301 and the lower flat plate 203 are mainly made of alumina or aluminum nitride. The surfaces of the plate member 301 and the lower flat plate 203 may be treated with gold plating or the like to improve heat conductivity. The cooling member 200 has a conductive space including electrodes (not shown) for conductivity with the outside. The electrodes may be electrodes connected to a power supply and electrodes connected to ground.

[0024] Heat absorption will be explained using an example where a Peltier element is used as the cooling element 200. When a voltage V is applied to the Peltier element, a current I flows. The heat absorption surface temperature is T. c , the heating surface temperature is T h Let's assume the Seebeck coefficient is α, the internal resistance is R, the thermal conductivity is λ, and the temperature of the heat-absorbing surface is T. c and the temperature T of the heat dissipation surface h When the temperature difference between the two is ΔT, the endothermic Qc is expressed by the following equation.

[0025]

number

[0026] In other words, to increase the heat absorption Qc of a Peltier element, it is desirable to have a small thermal conductivity λ and internal resistance R. In a standard Peltier element, a smaller area of ​​the plate member 301 can reduce the thermal conductivity λ. However, this also reduces Qc, so it is important to select a Peltier element that has an appropriate number of P-type and N-type semiconductors.

[0027] This embodiment will be explained with reference to Figure 2, which shows a plan view of the electronic component from the optical member 102 side according to this embodiment. A rectangular semiconductor substrate 103 is placed in the center of the electronic component, and a pixel area 104 is placed on the semiconductor substrate 103. Multiple first conductive wires 108 are provided on each side of the semiconductor substrate 103, connecting the electrodes of the semiconductor substrate 103 to the electrodes on the plate member 301 of the cooling member 200. Furthermore, the electrodes of the plate member 301 and the electrodes provided on the base 101 are connected by multiple second conductive wires 110. Here, we assume an electronic component in which the length in the longitudinal direction of the electronic component is x and the length in the short direction is y, and both x and y are approximately 20 mm, but the size of the electronic component is not limited to this.

[0028] Figures 3(a) and 3(b) both show a plan view of the electronic component according to this embodiment, from the side opposite to the optical member 102. Two types of packages are shown here as examples. Figure 3(a) is a schematic diagram of the case where the package 100 is a so-called LGA (Land Grid Array), and Figure 3(b) is a schematic diagram of the case where it is a so-called LCC (Leadless Ceramic Chip Carrier).

[0029] The electrode configuration for connecting package 100 to the outside may be LGA, LCC, or PGA (Pin Grid Array). In the case of LGA, a lower profile is possible compared to other configurations, so LGA is preferred from the viewpoint of miniaturization. Alternatively, a configuration combining LGA and LCC may be used.

[0030] If the package 100 is configured as LGA, it can be manufactured using a reflow oven, and improved productivity can be expected compared to other methods. However, in order to prevent damage to the cooling element 200 due to the solder contained within the cooling element 200 melting in the reflow oven, it is preferable to use a low-temperature reflow oven for manufacturing the electronic components according to this embodiment. The temperature of the reflow oven should be lower than 200°C, which is lower than the solder melting temperature of the cooling element 200. Therefore, the bonding between the Peltier element and the outside can be achieved using a low-melting-point material such as resin-reinforced solder.

[0031] When the package configuration is LGA, it is preferable to have a terminal-free section in the central part of the package, as shown in Figure 3(a). By joining a material with high thermal conductivity to this terminal-free section, the heat from the substrate 101 can be released to the outside, thereby increasing the cooling efficiency of the cooling element 200. Examples of materials with high thermal conductivity include carbon graphite sheets, alloy plates for heat spreaders, and heat pipes.

[0032] Figure 4 is a schematic diagram showing an enlarged view of the area near the junction of the base body 101, cooling member 200, first conductive wire 108, and second conductive wire 110 of the electronic component according to this embodiment. The semiconductor substrate 103 is provided with a first electrode 109. The plate member 301 is provided with a second electrode 204 and a third electrode 205. The base body 101 is provided with a fourth electrode 111. The second electrode 204 and the third electrode 205 are located outside the outer edge of the semiconductor substrate 103 when viewed from the optical member 102 side. The first electrode 109 provided on the semiconductor substrate 103 and the second electrode 204 provided on the plate member 301 are connected by the first conductive wire 108. The plate member 301 is provided with a third electrode 205, and the third electrode 205 and the fourth electrode 111 provided on the base body 101 are connected by the second conductive wire 110.

[0033] The second electrode 204 and the third electrode 205 are connected by wiring 206 arranged on the plate member 301, and the semiconductor substrate 103 and the base body 101 are electrically connected via the plate member 301. The plate member 301, which is part of the cooling member 200, acts as a relay point for the wiring. The heat flow transmitted from the lower flat plate 203, which is the heat-generating surface, through the base body 101 to the second conductive wire 110 is cooled by the plate member 301, which is cooled by the cooling unit 201. Therefore, compared to a configuration in which the electrodes of the semiconductor substrate 103 and the electrodes of the base body 101 are directly connected by conductive wires, the heat flow returning to the semiconductor substrate 103 can be suppressed.

[0034] The second conductive wire 110 is preferably high in thermal resistance. This suppresses the heat flow transmitted to the plate member 301, thereby reducing the power consumption of the cooling member 200. Methods for increasing the thermal resistance of the second conductive wire 110 include, for example, reducing the wire diameter, increasing the wire length, or using a material with low thermal conductivity. As for the wire material, Cu, Ag, Au, Al, and alloys mainly composed of these materials can be selected, but to reduce thermal conductivity, it is better to select Au alloy rather than Au, and Al rather than Au alloy. The wire diameters of the first conductive wire 108 and the second conductive wire 110 are determined by balancing the allowable current, electrical resistance, inductance, etc., in order to prevent wire breakage.

[0035] On the other hand, the wiring length between the semiconductor substrate 103 and the base 101 is the sum of the length of the first conductive wire 108, the length of the wiring 206, and the length of the second conductive wire 110. Therefore, compared to a configuration in which the electrodes of the semiconductor substrate 103 and the electrodes of the base 101 are directly connected by conductive wires, the wiring may be longer, which may increase electrical resistance and inductance. Increased electrical resistance and other factors may increase voltage drop, potentially causing malfunctions in the operation of the semiconductor substrate 103. Therefore, from the standpoint of electrical wiring, it is preferable that the length of the first conductive wire 108, the wiring 206 between the second electrode 204 and the third electrode 205, and the second conductive wire 110 be shorter, and that they be thicker. Since there is a trade-off between the power consumption of the cooling member 200, and consequently the heat flow suppression effect, and the challenges in electrical wiring, the length and thickness of the electrical wiring can be appropriately set according to the type of wiring (power wiring, ground wiring, signal lines, control lines, etc.).

[0036] Figure 5 is a schematic diagram illustrating the configuration of the plate member 301 according to this embodiment. Figure 5(a) is a schematic cross-sectional view of the plate member 301, and Figures 5(b) to 5(d) are schematic plan views illustrating the laminated structure of the plate member 301. The plate member 301 includes a first layer 207 and a second layer 208, which form the surface layer. Figure 5(b) is a schematic plan view of the first layer 207. A second electrode 204 and a third electrode 205 are formed, and the second electrode 204 and the third electrode 205 are connected by wiring 206. Furthermore, a portion of the second electrode 204 has wiring 206 formed toward the center of the interior of the plate member 301 and is connected to the wiring region of a solid pattern, which is a planar conductive layer. The second electrode 204, electrode 205, wiring 206, and the wiring region of the solid pattern are electrodes at the same potential and can be, for example, a power source or ground.

[0037] Figure 5(c) is a schematic plan view of the intermediate layer between the first layer 207 and the second layer 208. Vias 209 are formed in the intermediate layer for connecting the wiring 206 of the first layer 207 and the second layer 208. Figure 5(d) is a schematic plan view of the second layer 208. Wiring 206 of electrodes connected by vias 209 is formed therein. For example, if the electrode with a solid pattern wiring 206 formed in the first layer 207 is a power supply, then the wiring 206 formed in the second layer 208 may be a ground. By devising the routing of wiring such as power and ground in the wiring 206 of the plate member 301, electrical resistance and inductance can be reduced and voltage drop can be suppressed.

[0038] Furthermore, at least a portion of the wiring 206 arranged on the plate member 301 is positioned to overlap with the cooling section 201 in a plan view, allowing for efficient cooling of the wiring 206. Figure 5 shows an example in which a solid pattern of wiring 206 of one type of electrode with the same potential is formed on the first layer 207 and the second layer 208, but multiple wirings of electrodes with the same potential may be formed on the same layer, and the wiring 206 does not have to be a solid pattern. Also, the laminated structure of the plate member 301 may be a structure of three or more layers.

[0039] Furthermore, among the first conductive wire 108 and the second conductive wire 110, the conductive wires arranged at the power supply and ground electrodes may be thicker or shorter than the conductive wires arranged at electrodes other than the power supply and ground. Thicker and shorter conductive wires can increase the effect of suppressing voltage drop. However, since making the second conductive wire 110 thicker and shorter will lower its thermal resistance, the effect of suppressing heat flow may decrease compared to the case where all second conductive wires 110 are thin and long. Therefore, in order to improve the effect of suppressing heat flow, measures such as making the conductive wires arranged at electrodes other than the power supply and ground thinner or longer may be taken.

[0040] As described above, by electrically connecting the wiring from the semiconductor substrate 103 to the base body 101 via the plate member 301 placed on the heat-absorbing surface of the cooling member 200, the heat flow returning from the base body 101 to the semiconductor substrate 103 can be suppressed. Furthermore, by using a laminated wiring plate for the plate member 301, the electrical resistance and inductance of the wiring can be reduced, thereby suppressing voltage drop due to the wiring.

[0041] (Second embodiment) The electronic components according to the second embodiment will be described using Figures 6 to 9. Parts that overlap with the description of the electronic components according to the first embodiment will be omitted, and the differences from the first embodiment will be the main focus.

[0042] Figure 6 is a cross-sectional view showing an example of the configuration of the electronic component in this embodiment, and Figure 7 is a plan view from the optical member 102 side. Figure 6(a) is a cross-sectional view of the electronic component as seen from the X direction in Figure 2, and Figure 6(b) is a cross-sectional view of the electronic component as seen from the Y direction in Figure 2. The difference from the first embodiment is that, as shown in Figure 6(a), the conductive wires arranged along the Y direction of the electronic component are not connected to the plate member 301 of the cooling member 200, but are directly connected to the substrate 101. Regarding the connection of the conductive wires arranged along the X direction of the electronic component, as shown in Figure 6(b), the first electrode is connected to the fourth electrode 111 via the second electrode 204 and third electrode 205 of the plate member 301, similar to the first embodiment.

[0043] The arrangement shown in Figure 6(a) will be explained. The first electrode 109 formed on the semiconductor substrate 103 and the fourth electrode 111 formed on the base 101 are directly connected by a third conductive wire 112. Since the conductive wire is not connected to the plate member 301, the dimensions of the plate member 301 in the X direction can be reduced. In other words, the electronic components can be miniaturized. It is preferable that the first conductive wire 108 and the second conductive wire 110 include, for example, power supply and ground wiring. By devising the routing of power supply and ground wiring in the wiring 206 of the plate member 301, electrical resistance and inductance can be reduced, and voltage drop can be suppressed. In addition, the third conductive wire 112 may be used for wiring other than power supply and ground. By routing wiring that has little effect on voltage drop without connecting it to the plate member 301, the number of wires can be reduced, thereby suppressing the heat flow transmitted to the cooling member 200, and thus the power consumption of the cooling member 200 can be suppressed.

[0044] In this embodiment as well, among the first conductive wire 108, second conductive wire 110, and third conductive wire 112, the conductive wires arranged for the power supply and ground electrodes may be thicker or shorter than the conductive wires arranged for electrodes other than the power supply and ground. This is to improve the effect of suppressing voltage drop. Since the third conductive wire 112 directly connects the substrate 101 and the semiconductor substrate 103, it may be thinner or longer than the first conductive wire 108 and the second conductive wire 110 in order to improve the effect of suppressing heat flow. The length of the third conductive wire 112 can also be adjusted by changing the height from the bottom surface of the fourth electrode 111 to which the third conductive wire is connected, which is provided on the substrate 101.

[0045] Figure 7 is a plan view of the electronic component according to this embodiment from the optical member 102 side, showing an example of the arrangement of the first conductive wire 108, the second conductive wire 110, and the third conductive wire 112. As shown in Figure 7(a), all electrodes aligned in the Y direction of the semiconductor substrate 103 may be connected to the base body 101 by the third conductive wire 112. Alternatively, as shown in Figure 7(b), the conductive wires connected to the electrodes aligned in the Y direction of the semiconductor substrate 103 may be arranged in a mixed manner, with the first conductive wire 108, the second conductive wire 110, and the third conductive wire 112. From the viewpoint of miniaturizing the electronic component, the arrangement in Figure 7(a), which allows for a smaller dimension in the X direction than in Figure 7(b), is preferable, but an appropriate configuration can be selected among the first electrodes 109 of the semiconductor substrate 103 depending on the arrangement of power supplies, grounds, etc. In addition to the arrangement examples in Figures 7(a) and 7(b), there may be arrangements in which the XY direction arrangement shown in Figure 2 is reversed. Various combinations can be selected for mixing the first conductive wire 108, the second conductive wire 110, and the third conductive wire 112.

[0046] On the other hand, since the third conductive wire 112 is connected directly from the semiconductor substrate 103 to the fourth electrode 111 of the base body 101 without going through the plate member 301, it may be necessary to form a conductive wire with a high step height for the connection. In order to form a conductive wire with a high step height, it becomes increasingly necessary to consider interference between the capillary, a tool used during wire bonding, and the conductive wire and base body 101.

[0047] Figure 8 is a diagram illustrating the relationship between the wire angle and the capillary angle during the downward driving of a typical wire bond. When θ is the angle between the perpendicular line to the surface on which the fourth electrode 111 is formed and the third conductive wire 112, Figure 8(a) shows the case when θ is greater than 10-15°, and Figure 8(b) shows the case when θ is less than 10-15°.

[0048] As shown in Figure 8(a), in typical wire bonding, a wire loop is formed after joining the first electrode 109 of the semiconductor substrate 103 to the third conductive wire 112, and then the fourth electrode 111 of the substrate 101 to the third conductive wire 112 is joined with a stitch bond. At this time, the tip of the capillary used for bonding usually has an angle of about 20 to 30° in cross-section. As shown in Figure 8(b), if bonding is attempted when the wire angle θ is steeper than the angle of the capillary, the capillary and wire may interfere with each other. This has sometimes prevented bonding. When the wire angle θ is large, it is necessary to leave a horizontal space to avoid interference between the fourth electrode 111 and the end of the substrate 101. This space can hinder the miniaturization of electronic components.

[0049] Figure 9 is a diagram illustrating the relationship between the wire angle and the capillary angle during wire bonding using the ball stitch-on bonding (BSOB) method. In the BSOB method, a ball is first formed on the first electrode 109. Then, the fourth electrode 111 and the third conductive wire 112 are joined, and the capillary is raised almost vertically to join the first electrode 109 and the third conductive wire 112. That is, balls are formed and joined at both the joint between the first electrode 109 and the third conductive wire 112, and at the joint between the fourth electrode 111 and the third conductive wire 112. At the joint between the fourth electrode 111 and the third conductive wire 112, a stitch is formed on the ball to complete the bond.

[0050] In the BSOB method, it is sufficient to ensure horizontal space when joining the third conductive wire 112 and the fourth electrode 111. According to the BSOB method, interference between the capillary and the third conductive wire 112 when joining the third conductive wire 112 to the semiconductor substrate 103 does not occur even without ensuring an extra distance between the fourth electrode 111 and the end of the substrate 101. Therefore, it is possible to reduce the horizontal space required compared to when the third conductive wire 112 is joined using a normal bonding method, and consequently, the miniaturization of electronic components becomes possible. For this reason, the BSOB method is preferable when forming a conductive wire that connects high steps using the third conductive wire 112.

[0051] (Third embodiment) The electronic component according to the third embodiment will be described using Figures 10 to 13. Parts that overlap with the descriptions of the electronic components according to the first and second embodiments will be omitted, and the differences from the first and second embodiments will be mainly described. Figure 10 is a cross-sectional view showing an example of the configuration of the electronic component according to this embodiment, and Figure 11 is a plan view from the optical member 102 side. Figure 12 is a schematic diagram showing an enlarged view of the area near the joint between the base 101, cooling member 200, plate member 301, and first conductive wire 108 and second conductive wire 110 of the electronic component according to this embodiment. The difference from the first embodiment is that the upper flat plate 202 is placed between the cooling member 200 and the plate member 301. The plate member 301 is placed on the upper flat plate 202 of the cooling member 200 via a plate adhesive 113. The semiconductor substrate 103 is placed on the plate member 301 via a semiconductor substrate adhesive 106. Here, the upper flat plate 202 of the cooling member 200 is a single-layer flat plate and does not need to have wiring. Multiple wirings can be stacked on the plate member 301.

[0052] The plate member 301 and the upper flat plate 202 are mainly made of alumina or aluminum nitride. The surface may be treated with gold plating or other methods to enhance thermal conductivity. As shown in Figure 12, the plate member 301 has a fifth electrode 302 and a sixth electrode 303, and the first electrode 109 of the semiconductor substrate 103 and the fifth electrode 302 are connected by a first conductive wire 108. The sixth electrode 303 and the fourth electrode 111 formed on the base body 101 are connected by a second conductive wire 110. The fifth electrode 302 and the sixth electrode 303 are connected by wiring 304, and the semiconductor substrate 103 and the base body 101 are electrically connected via the plate member 301. The heat flow transmitted from the lower flat plate 203, which is the heat-generating surface, through the base body 101 to the second conductive wire 110 is cooled by the plate member 301 which is joined to the upper flat plate 202, which is cooled by the cooling section 201. Therefore, compared to a configuration in which the electrodes of the semiconductor substrate 103 and the electrodes of the base body 101 are directly connected by conductive wires, the heat flow returning to the semiconductor substrate 103 can be suppressed.

[0053] In this embodiment, compared to the configuration of the first embodiment, the thermal resistance may be somewhat weaker because the adhesive 113 and plate member 301 between the cooling member 200 and the semiconductor substrate 103 may act as thermal resistance. This may lead to an increase in power consumption. However, as in the first embodiment, the increase in power consumption and the decrease in the heat flow suppression effect can be suppressed by considering the length and thickness of the conductive wire.

[0054] In the first embodiment, wiring had to be formed on the plate member 301, which corresponds to the upper flat plate of the cooling member 200. Therefore, when using a Peltier element as the cooling member 200, the plate member 301 had to be custom designed. In this embodiment, since wiring is not formed on the upper flat plate 202, which is part of the Peltier element, a general-purpose Peltier element can be used as the cooling member 200. Designing and using only the plate member 301 to match the semiconductor substrate 103 offers advantages in terms of cost and versatility.

[0055] Figure 13 is a schematic diagram of the plate member 301 according to this embodiment. Figure 13(a) is a schematic cross-sectional view of the plate member 301, and Figures 13(b) to 13(d) are schematic plan views of each layer of the laminated wiring of the plate member 301. The configuration of each layer is basically the same as that of the plate member 301 described in Figure 5. As shown in Figure 13(a), the plate member 301 includes a first layer 305 and a second layer 306, which are surface layers. Figure 13(b) is a schematic plan view of the first layer 305. A fifth electrode 302 and a sixth electrode 303 are formed, and the fifth electrode 302 and the sixth electrode 303 are connected by wiring 304. Furthermore, wiring 304 is formed on a part of the fifth electrode 302 toward the center of the plate member 301 and is connected to the wiring area of ​​the solid pattern. These are electrodes at the same potential, such as power and ground. Figure 13(c) is a schematic plan view of the intermediate layer between the first layer 305 and the second layer 306, where vias 307 are formed to connect the wiring 304 of the first layer 305 and the second layer 306.

[0056] Figure 13(d) is a schematic plan view of the second layer 306. Wiring 304 of electrodes connected by vias 307 is formed therein. For example, if the electrode with a solid pattern wiring 304 formed in the first layer 305 is a power supply, then the wiring 304 formed in the second layer 306 may be a ground, etc. By devising the wiring route of power supplies, grounds, etc. in the wiring 304 of the plate member 301, electrical resistance and inductance can be reduced and voltage drops can be suppressed. In Figure 13, an example is shown in which one type of solid pattern wiring 304 of the same potential electrode is formed in both the first layer 305 and the second layer 306, but multiple types of wiring of the same potential electrode may be formed in the same layer, or the wiring may not be a solid pattern. The number of layers may also be three or more. (Fourth embodiment) The electronic components according to the fourth embodiment will be described using Figures 14 and 15. Sections that overlap with the descriptions of the electronic components according to the first to third embodiments will be omitted, and the differences from the first to third embodiments will be the main focus.

[0057] Figure 14 is a cross-sectional view showing an example of the configuration of an electronic component in the fourth embodiment, and Figure 15 is a plan view from the optical member 102 side. Figure 14(a) is a cross-sectional view of the electronic component when viewed from the X direction, and Figure 14(b) is a cross-sectional view of the electronic component when viewed from the Y direction. The difference from the third embodiment is that, as shown in Figure 14(a), the conductive wire along the Y direction is not connected to the plate member 301, but is directly connected to the substrate 101. Regarding the connection of the conductive wire along the X direction shown in Figure 14(b), the connection is made via the plate member 301, similar to the third embodiment. According to the configuration of this embodiment, the dimensions of the plate member 301 in the X direction can be reduced, similar to the example of the second embodiment, which is advantageous for miniaturizing the electronic component.

[0058] <Examples of application of electronic components to equipment> An example of applying the electronic components according to the above embodiment to the device 1000 will be explained with reference to Figure 16. The semiconductor chip 1110, comprising the electronic component 1100 including a package 1020 on which the semiconductor chip 1110 is mounted, is housed in the package 1020 and mounted on the device 1000. A cooling member (not shown) is placed between the substrate 1010 of the package 1020 and the semiconductor chip 1110. The semiconductor device 1100 may include a package 1020 that includes a substrate 1010 on which the semiconductor chip 1110 is fixed, and a light-transmitting member 1030 such as glass facing the semiconductor chip 1110. The package 1020 may include connecting members such as wires and bumps that connect inner leads provided on the substrate 1010 and terminals such as pad electrodes provided on the semiconductor chip 1110.

[0059] The device 1000 may include at least one of the following: an optical device 1040, a control device 1050, a processing device 1060, a display device 1070, a storage device 1080, and a mechanical device 1090. The optical device 1040 is, for example, a lens, a shutter, or a mirror. The control device 1050 controls the semiconductor chip 1110. The control device 1050 is, for example, a semiconductor device such as an ASIC.

[0060] The processing unit 1060 processes the output signals from the semiconductor integrated circuit contained in the semiconductor chip 1110. The processing unit 1060 is a semiconductor device such as a CPU or ASIC for configuring the AFE analog front end or DFE digital front end. For example, it may generate an image based on the imaging signal when an event is detected. The display device 1070 is an EL display device or liquid crystal display device that displays the information image obtained from the semiconductor chip 1110. The storage device 1080 is a magnetic device or semiconductor device that stores the information image obtained from the semiconductor chip 1110. The storage device 1080 is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as flash memory or a hard disk drive.

[0061] The mechanical device 1090 has movable parts or propulsion parts such as a motor or engine. In the device 1000, signals output from the semiconductor chip 1110 are displayed on the display device 1070 or transmitted to the outside by a communication device (not shown) provided in the device 1000. For this purpose, the device 1000 may further include a storage device 1080 and a processing device 1060, separate from the memory circuits and arithmetic circuits of the semiconductor chip 1110. The mechanical device 1090 may be controlled based on signals output from the semiconductor chip 1110.

[0062] The device 1000 is suitable for electronic devices such as information terminals with shooting capabilities, such as smartphones and wearable devices, and cameras, such as interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras. In a camera, the mechanical device 1090 may be a device that can drive components of the optical device 1040 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 1090 in a camera may be a device that can move the optical device 1040 for vibration damping.

[0063] Furthermore, the device 1000 may be a transport device such as a vehicle or a ship. The mechanical device 1090 in the transport device may be used as a mobile device. The device 1000 as a transport device is suitable for transporting semiconductor chips 1110 or for assisting and / or automating driving operations through its imaging function. The processing device 1060 for assisting and / or automating driving operations can perform processing to operate the mechanical device 1090 as a mobile device based on information obtained from the semiconductor chip 1110. Alternatively, the device 1000 may be a medical device such as an endoscope, a measuring instrument such as a distance sensor, an analytical instrument such as an electron microscope, office equipment such as a copier, or industrial equipment such as a robot.

[0064] (Other embodiments) The disclosures herein include the following electronic components and devices to which these electronic components are applied. (Item 1) It comprises a semiconductor substrate, a base, a cooling member, and a plate member, The plate member is placed between the heat-absorbing side of the cooling member and the semiconductor substrate. The base is positioned on the heat-generating side of the cooling member. A first electrode is arranged on the semiconductor substrate, a second electrode and a third electrode are arranged on the plate member, and a fourth electrode is arranged on the base body. The second electrode and the third electrode are connected by wiring of the plate member, the first electrode and the second electrode are connected by a first conductive wire, and the third electrode and the fourth electrode are connected by a second conductive wire. An electronic component characterized by the following features. (Item 2) The electronic component according to item 1, characterized in that the second electrode and the third electrode are positioned outside the outer edge of the semiconductor substrate in a plan view. (Item 3) The electronic component according to item 1 or 2, characterized in that at least a portion of the wiring of the plate member is arranged to overlap with the area where the cooling member is located in a plan view. (Item 4) The electronic component according to any one of items 1 to 3, characterized in that a plurality of pixels are arranged on the semiconductor substrate. (Item 5) The electronic component according to item 4, characterized in that each of the plurality of pixels has a photoelectric conversion element. (Item 6) The electronic component according to item 5, characterized in that the photoelectric conversion element includes an avalanche diode. (Item 7) An electronic component according to any one of items 1 to 6, characterized in that an optical member is mounted on the substrate. (Item 8) The electronic component according to item 1, characterized in that a first flat plate is disposed between the plate member and the cooling member, and a second flat plate is disposed between the heat-generating side of the cooling member and the base body. (Item 9) The electronic component according to any one of items 1 to 8, characterized in that the cooling member is a Peltier element. (Item 10) The electronic component according to any one of items 1 to 9, characterized in that at least one of the plate member and the substrate contains at least one of alumina and aluminum nitride. (Item 11) The electronic component according to any one of items 1 to 10, characterized in that the wiring of the plate member has a solid pattern region. (Item 12) The electronic component according to item 11, characterized in that the aforementioned solid pattern is connected to at least the power supply or ground electrodes. (Item 13) The electronic component according to any one of items 1 to 12, characterized in that, among the first conductive wire and the second conductive wire, the conductive wires arranged at the power supply and ground electrodes are thicker than the conductive wires arranged at electrodes other than the power supply and ground. (Item 14) The electronic component according to any one of items 1 to 13, characterized in that, of the first conductive wire and the second conductive wire, the conductive wires arranged at the power supply and ground electrodes are shorter than the conductive wires arranged at electrodes other than the power supply and ground. (Item 15) The electronic component according to any one of items 1 to 14, characterized in that, in addition to the first conductive wire and the second conductive wire, the first electrode and the fourth electrode are connected by a third conductive wire. (Item 16) The electronic component according to item 15, characterized in that the third conductive wire is connected to at least electrodes other than the power supply and ground. (Item 17) The electronic component according to item 15 or 16, characterized in that the third conductive wire has a higher thermal resistance than the first conductive wire and the second conductive wire. (Item 18) The electronic component according to any one of items 15 to 17, characterized in that the joint between the first electrode and the third conductive wire and the joint between the fourth electrode and the third conductive wire are constructed by ball stitch-on bonding. (Item 19) The electronic component according to any one of items 1 to 18, characterized in that the first conductive wire and the second conductive wire include at least one of gold and aluminum. (Item 20) An electronic component listed in any one of items 1 through 19, The apparatus is characterized by comprising a processing device for processing the output signal from the aforementioned electronic component.

[0065] The disclosures herein include not only what is described herein, but also all matters that can be understood from this specification and the drawings attached herein. The invention is not limited to the embodiments described above, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, claims are attached to make the scope of the invention public. [Explanation of Symbols]

[0066] 100 Package, 101 Substrate, 102 Optical component, 103 Semiconductor substrate, 104 Pixel area, 105 Cooling section adhesive, 106 Semiconductor substrate adhesive, 107 Optical component adhesive, 108 First conductive wire, 109 First electrode, 110 Second conductive wire, 111 Fourth electrode, 200 Cooling component, 201 Cooling section, 203 Lower plate, 204 Second electrode, 205 Third electrode, 301 Plate component

Claims

1. It comprises a semiconductor substrate, a base, a cooling member, and a plate member, The plate member is placed between the heat-absorbing side of the cooling member and the semiconductor substrate. The base is positioned on the heat-generating side of the cooling member. A first electrode is arranged on the semiconductor substrate, a second electrode and a third electrode are arranged on the plate member, and a fourth electrode is arranged on the base body. The second electrode and the third electrode are connected by wiring of the plate member, the first electrode and the second electrode are connected by a first conductive wire, and the third electrode and the fourth electrode are connected by a second conductive wire. An electronic component characterized by the following features.

2. The electronic component according to claim 1, characterized in that the second electrode and the third electrode are arranged outside the outer edge of the semiconductor substrate in a plan view.

3. The electronic component according to claim 1, characterized in that at least a portion of the wiring of the plate member is arranged to overlap with the area where the cooling member is located in a plan view.

4. The electronic component according to claim 1, characterized in that a plurality of pixels are arranged on the semiconductor substrate.

5. The electronic component according to claim 4, characterized in that each of the plurality of pixels has a photoelectric conversion element.

6. The electronic component according to claim 5, characterized in that the photoelectric conversion element includes an avalanche diode.

7. The electronic component according to claim 1, characterized in that an optical member is mounted on the substrate.

8. The electronic component according to claim 1, characterized in that a first flat plate is disposed between the plate member and the cooling member, and a second flat plate is disposed between the heat-generating side of the cooling member and the base body.

9. The electronic component according to claim 1, characterized in that the cooling member is a Peltier element.

10. The electronic component according to claim 1, characterized in that at least one of the plate member and the substrate contains at least one of alumina and aluminum nitride.

11. The electronic component according to claim 1, characterized in that the wiring of the plate member has a solid pattern region.

12. The electronic component according to claim 11, characterized in that the solid plane is connected to at least the power supply or ground electrodes.

13. The electronic component according to claim 1, characterized in that, of the first conductive wire and the second conductive wire, the conductive wires arranged at the power supply and ground electrodes are thicker than the conductive wires arranged at electrodes other than the power supply and ground electrodes.

14. The electronic component according to claim 1, characterized in that, of the first conductive wire and the second conductive wire, the conductive wires arranged at the power supply and ground electrodes are shorter than the conductive wires arranged at electrodes other than the power supply and ground electrodes.

15. The electronic component according to claim 1, characterized in that, in addition to the first conductive wire and the second conductive wire, the first electrode and the fourth electrode are connected by a third conductive wire.

16. The electronic component according to claim 15, characterized in that the third conductive wire is connected to at least electrodes other than the power supply and ground.

17. The electronic component according to claim 15, characterized in that the third conductive wire has a higher thermal resistance than the first conductive wire and the second conductive wire.

18. The electronic component according to claim 15, characterized in that the joint between the first electrode and the third conductive wire, and the joint between the fourth electrode and the third conductive wire, are constructed using ball stitch-on bonding.

19. The electronic component according to claim 1, characterized in that the first conductive wire and the second conductive wire include at least one of gold and aluminum.

20. An electronic component according to any one of claims 1 to 19, The apparatus is characterized by comprising a processing device for processing the output signal from the aforementioned electronic component.

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