Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same that can reduce the number of manufacturing steps. [Solution] The semiconductor device according to this embodiment comprises a first laminate and a plurality of first columnar bodies. The first laminate has a first insulating film and a first conductive film alternately laminated in a first direction. The plurality of first columnar bodies extend in a first direction so as to penetrate the first laminate and include conductors that are electrically connected to any of the first conductive films. The first laminate has a plurality of protruding structures that project in the first direction according to the shape of a plurality of trenches, either at the bottom of the first laminate, in the middle of the first laminate, or both. The first columnar bodies penetrate the joints of the first conductive films inside the trench structures and are electrically connected to the first conductive films.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] A semiconductor memory device such as a NAND flash memory may have a three-dimensional memory cell array in which a plurality of memory cells are arranged three-dimensionally. A contact connected to a word line is formed in a lead-out region of the three-dimensional memory cell array. It is desired to reduce the number of processes for forming the contact.

Prior Art Literature

Patent Literature

[0003]

Patent Literature 1

Patent Literature 2

Summary of the Invention

Problem to be Solved by the Invention

[0004] To provide a semiconductor device capable of reducing the number of processes and a method for manufacturing the same.

Means for Solving the Problem

[0005] The semiconductor device according to the present embodiment includes a first stacked body and a plurality of first columnar bodies. In the first stacked body, first insulating films and first conductive films are alternately stacked in a first direction. The plurality of first columnar bodies extend in the first direction so as to penetrate the first stacked body, and each include a conductor electrically connected to any one of the first conductive films. The first stacked body has, in a lower portion of the first stacked body, inside the first stacked body, or both, a plurality of protruding portions that protrude in the first direction in accordance with the shapes of a plurality of trenches. The first columnar body penetrates a butted portion of the first conductive film inside the trench structure and is electrically connected to the first conductive film.

Brief Description of Drawings

[0006] [Figure 1] A block diagram showing an example configuration of a semiconductor memory device according to the first embodiment. [Figure 2] A circuit diagram showing an example of the circuit configuration of a memory cell array of a semiconductor memory device according to the first embodiment. [Figure 3] A plan view showing an example of a planar layout of a part of the memory cell array of a semiconductor memory device according to the first embodiment. [Figure 4] A plan view showing an example of a partial planar layout of the memory area of ​​a semiconductor storage device according to the first embodiment. [Figure 5] A cross-sectional view showing the structure of a part of the memory area of ​​a semiconductor memory device according to the first embodiment. [Figure 6] A cross-sectional view showing the cross-sectional structure of a memory pillar of a semiconductor memory device according to the first embodiment. [Figure 7] A plan view showing the positional relationship between the support pillar, trench, and contact plug of a semiconductor memory device according to the first embodiment. [Figure 8A] A cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 8B] A cross-sectional view illustrating the manufacturing method of a semiconductor memory device, following Figure 8A. [Figure 8C] Figure 8B is followed by a cross-sectional view illustrating the manufacturing method of a semiconductor memory device. [Figure 8D] Figure 8C is followed by a cross-sectional view illustrating the manufacturing method of a semiconductor memory device. [Figure 8E] Figure 8D is followed by a cross-sectional view illustrating the manufacturing method of a semiconductor memory device. [Figure 9] This is a cross-sectional view showing the structure of a portion of the draw-out area of ​​a semiconductor memory device according to a comparative example. [Figure 10A] A cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the second embodiment. [Figure 10B] A cross-sectional view illustrating the manufacturing method of a semiconductor memory device, following Figure 10A. [Figure 10C] Figure 10B is followed by a cross-sectional view illustrating the manufacturing method of a semiconductor memory device. [Figure 10D] Figure 10C is followed by a cross-sectional view illustrating the manufacturing method of a semiconductor memory device. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will be described below with reference to the drawings. These embodiments are not limiting to the present invention. The drawings are schematic or conceptual, and the proportions of each part may not necessarily be the same as those of actual objects. In the specification and drawings, elements similar to those described above with respect to previously shown drawings are denoted by the same reference numerals, and detailed explanations are omitted as appropriate.

[0008] (First Embodiment) (Configuration of semiconductor memory device 100) Figure 1 is a block diagram showing an example configuration of a semiconductor memory device 100 according to the first embodiment. The semiconductor memory device 100 is, for example, a NAND flash memory capable of storing data non-volatilely, and is controlled by an external memory controller 1002. Communication between the semiconductor memory device 100 and the memory controller 1002 supports, for example, the NAND interface standard.

[0009] As shown in Figure 1, the semiconductor memory device 100 includes, for example, a memory cell array 10, a command register 1011, an address register 1012, a sequencer 1013, a driver module 1014, a row decoder module 1015, and a sense amplifier module 1016.

[0010] The memory cell array 10 includes multiple blocks BLK(0) to BLK(n) (where n is an integer greater than or equal to 1). A block BLK is a collection of multiple memory cells that can store data non-volatilely, and is used, for example, as a data erasure unit. The memory cell array 10 is also provided with multiple bit lines and multiple word lines. Each memory cell is associated with, for example, one bit line and one word line. The detailed structure of the memory cell array 10 will be described later.

[0011] The command register 1011 holds a command CMD received by the semiconductor memory device 100 from the memory controller 1002. The command CMD includes, for example, instructions for causing the sequencer 1013 to perform a read operation, a write operation, an erase operation, and the like.

[0012] The address register 1012 holds address information ADD received by the semiconductor memory device 100 from the memory controller 1002. The address information ADD includes, for example, a block address BA, a page address PA, and a column address CA. For example, the block address BA, the page address PA, and the column address CA are respectively used for selecting a block BLK, a word line, and a bit line.

[0013] The sequencer 1013 controls the operation of the entire semiconductor memory device 100. For example, the sequencer 1013 controls the driver module 1014, the row decoder module 1015, the sense amplifier module 1016, and the like based on the command CMD held in the command register 1011, to execute a read operation, a write operation, an erase operation, and the like.

[0014] The driver module 1014 generates voltages used in a read operation, a write operation, an erase operation, and the like. Then, the driver module 1014 applies the generated voltage to a signal line corresponding to a selected word line based on, for example, the page address PA held in the address register 1012.

[0015] The row decoder module 1015 includes a plurality of row decoders. A row decoder selects one block BLK in the corresponding memory cell array 10 based on the block address BA held in the address register 1012. Then, the row decoder transfers, for example, the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0016] During a write operation, the sense amplifier module 1016 applies a desired voltage to each bit line according to the write data DAT received from the memory controller 1002. During a read operation, the sense amplifier module 1016 determines the data stored in the memory cell based on the voltage of the bit line and transfers the determination result as read data DAT to the memory controller 1002.

[0017] The semiconductor memory device 100 and memory controller 1002 described above may be combined to form a single semiconductor device. Examples of such semiconductor devices include memory cards such as SD™ cards and SSDs (Solid State Drives).

[0018] Figure 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array 10. One block BLK is extracted from among the multiple block BLKs included in the memory cell array 10. As shown in Figure 2, the block BLK contains multiple string units SU(0) to SU(k) (where k is an integer of 1 or greater).

[0019] Each string unit SU contains multiple NAND strings NS, each associated with a bit line BL(0) to BL(m) (where m is an integer greater than or equal to 1). Each NAND string NS contains, for example, memory cell transistors MT(0) to MT(15), as well as selection transistors ST(1) and ST(2). The memory cell transistor MT includes a control gate and a charge storage layer that holds data non-volatile. The selection transistors ST(1) and ST(2) are used to select the string unit SU during various operations.

[0020] In each NAND string NS, the memory cell transistors MT(0) to MT(15) are connected in series. The drain of the selection transistor ST(1) is connected to the associated bit line BL, and the source of the selection transistor ST(1) is connected to one end of the series-connected memory cell transistors MT(0) to MT(15). The drain of the selection transistor ST(2) is connected to the other end of the series-connected memory cell transistors MT(0) to MT(15). The source of the selection transistor ST(2) is connected to the source line SL.

[0021] In the same block BLK, the control gates of memory cell transistors MT(0) to MT(15) are commonly connected to word lines WL(0) to WL(7), respectively. The gates of each selection transistor ST(1) in string units SU(0) to SU(k) are commonly connected to selection gates SGD(0) to SGD(k), respectively. The gate of selection transistor ST(2) is commonly connected to the selection gate line SGS.

[0022] In the circuit configuration of the memory cell array 10 described above, the bit line BL is shared by NAND strings NS, each of which string units SU is assigned the same column address. The source line SL is shared, for example, between multiple blocks BLK.

[0023] A collection of multiple memory cell transistors MT connected to a common word line WL within a single string unit SU is referred to, for example, as a cell unit CU. For instance, the storage capacity of a cell unit CU containing memory cell transistors MT, each storing 1 bit of data, is defined as "1 page of data." A cell unit CU may have a storage capacity of 2 pages of data or more, depending on the number of bits of data stored by the memory cell transistors MT.

[0024] The memory cell array 10 of the semiconductor memory device 100 according to this embodiment is not limited to the circuit configuration described above. For example, the number of memory cell transistors MT and selection transistors ST(1) and ST(2) included in each NAND string NS can be designed to any number. The number of string units SU included in each block BLK can be designed to any number.

[0025] Figure 3 is a plan view showing an example of a partial planar layout of the memory cell array 10 of the semiconductor memory device 100 according to the first embodiment. Figure 3 shows the region where four blocks BLK_0 to BLK_3 are formed, along the xy plane. The structure shown in Figure 3 is repeatedly provided along the y axis.

[0026] As shown in Figure 3, the memory cell array 10 includes a memory area MA, an extraction area HA1, and an extraction area HA2. The extraction area HA1, memory area MA, and extraction area HA2 are arranged along the x-axis in this order. The memory cell array 10 is provided with multiple slits SLT and SHE.

[0027] Memory region MA is a region containing multiple NAND strings NS. Extraction regions HA1 and HA2 are regions where contact plugs are provided that connect to a stacked structure in which memory cell transistors are formed.

[0028] Multiple slits (SLTs) extend along the x-axis and are aligned along the y-axis. Each slit (SLT) is located at the boundary between adjacent blocks (BLK). The slits (SLTs) traverse the memory area (MA), the extraction area (HA1), and the extraction area (HA2). The slits (SLTs) have a structure in which, for example, an insulator and / or plate-like contacts are embedded. Each slit (SLT) separates adjacent stacked structures through itself.

[0029] Multiple slits SHE extend along the x-axis and are aligned along the y-axis. Each slit SHE is located between every two adjacent slits SLT. Figure 4 shows an example of four slits SHE. Each slit SHE traverses the memory region MA along the x-axis. Both ends of each slit SHE are located within the draw-out regions HA1 and HA2, respectively. Each slit SHE contains, for example, an insulator. Each slit SHE separates adjacent selected gate lines SGDL through itself. Each region separated by slits SLT and slit SHE is a region where one string unit SU is formed.

[0030] Figure 4 is a plan view showing an example of a planar layout of a portion of the memory area MA of the semiconductor memory device 100 according to the first embodiment. Figure 4 shows one block BLK, i.e., a region containing string units SU0 to SU4, and two slits SLT flanking this block BLK. As shown in Figure 4, the memory cell array 10 includes a plurality of memory pillars MP, a plurality of contact plugs CV, and a plurality of conductors 25 in the memory area MA. Each slit SLT includes a contact LI and a spacer SP.

[0031] A memory pillar MP is a structure in which memory cell transistors MT are formed inside. A memory pillar MP is an example of a second columnar body. A memory pillar MP contains one or more semiconductors, conductors, and insulators. A memory pillar MP functions as one NAND string NS. Multiple memory pillar MPs are distributed in a staggered arrangement in the region between two slits SLT. That is, multiple memory pillar MPs are arranged in columns along multiple y-axes, and each column of memory pillar MPs is arranged in a zigzag pattern along the y-axis. In other words, each column contains two sub-columns. The y-axis coordinate of each memory pillar MP in one sub-column corresponds to the y-axis coordinate between two adjacent memory pillar MPs in the other sub-column. Each column contains, for example, 24 memory pillar MPs.

[0032] Slit SHE overlaps with, for example, the 5th, 10th, 15th, and 20th memory pillars MP, starting from the top in Figure 4.

[0033] Each conductor 25 functions as a single bit line BL. The conductors 25 extend along the y-axis and are aligned along the x-axis. Each conductor 25 is positioned to overlap with at least one memory pillar MP for each string unit SU. Figure 4 shows an example where two conductors 25 are positioned to overlap with one memory pillar MP. Each memory pillar MP is electrically connected to one of the multiple conductors 25 that overlap with this memory pillar MP via a contact plug CV.

[0034] The contact LI contains a conductor. The contact LI extends along the xz plane and has a plate-like shape. The spacer SP is an insulator and is located on the side surface of the contact LI, for example, covering the side surface of the contact LI.

[0035] Figure 5 is a cross-sectional view showing the structure of a portion of the memory area MA of the semiconductor memory device 100 according to the first embodiment. Figure 5 is a cross-sectional view along the CC line in Figure 4.

[0036] As shown in Figure 5, the memory cell array 10 includes a substrate 20, conductors 21 and 22, a plurality of conductors 23, conductors 24 and 25, and insulators 30-37. Figure 5 shows eight examples of conductors 23. The insulators 30-37, with the exception of insulator 31, include, for example, silicon oxide.

[0037] The substrate 20 is, for example, a p-type semiconductor substrate. An insulator 30 is located on the upper surface of the substrate 20. Circuits (not shown) are formed in the substrate 20 and the insulator 30. The circuits include, for example, a command register 1011, an address register 1012, a sequencer 1013, a driver module 1014, a row decoder module 1015, and a sense amplifier module 1016, and further include transistors (not shown).

[0038] The insulator 31 is located on the upper surface of the insulator 30. The insulator 31 prevents hydrogen from entering the substrate 20 and the transistors contained in the insulator 30, for example, from the structure above the insulator 31. The insulator 31 includes, for example, silicon nitride (SiN).

[0039] The insulator 32 is located on the upper surface of the insulator 31.

[0040] The conductor 21 is located on the upper surface of the insulator 32. The conductor 21 extends along the xy plane and has a plate-like shape. The conductor 21 functions as at least part of the source wire SL. The conductor 21 includes, for example, phosphorus (P)-doped silicon.

[0041] The insulator 33 is located on the upper surface of the conductor 21.

[0042] The conductor 22 is located on the upper surface of the insulator 33. The conductor 22 extends along the xy plane and has a plate-like shape. The conductor 22 functions as at least part of the selected gate line SGSL. The conductor 22 includes, for example, tungsten (W).

[0043] Multiple insulators 34 and multiple conductors 23 are positioned alternately one by one along the z-axis on the upper surface of the conductor 22. The insulators 34 are examples of first insulating films, and the conductors 23 are examples of first conductive films. The z-axis is an example of a first direction. The multiple insulators 34 and multiple conductors 23 are stacked alternately along the z-axis to form a laminate S1. Laminate S1 is an example of a first laminate. In laminate S1, the conductors 23 are arranged along the z-axis, separated from each other or with spacing between them. The insulators 34 and conductors 23 extend along the xy-plane and have a plate-like shape. The multiple conductors 23 function as word lines WL0 to WL7, respectively, in order from the side of the substrate 20. The conductors 23 include, for example, tungsten.

[0044] The insulator 35 is located on the upper surface of the top conductor 23.

[0045] The conductor 24 is located on the upper surface of the insulator 35. The conductor 24 extends along the xy plane and has a plate-like shape. The conductor 24 functions as at least part of the selected gate line SGDL. The conductor 24 contains tungsten.

[0046] The insulator 36 is located on the upper surface of the conductor 24.

[0047] The conductor 25 is located on the upper surface of the insulator 36. The conductor 25 has a linear shape and extends along the y-axis. The conductor 25 functions as at least part of one bit line BL. The conductor 25 is also provided in a yz-plane different from the yz-plane shown in Figure 5, so that the conductors 25 are spaced apart along the x-axis. The conductor 25 includes, for example, copper.

[0048] The insulator 37 is located on the upper surface of the conductor 25.

[0049] The memory pillar MP extends along the z-axis and has a columnar shape. The memory pillar MP is an example of a second columnar body. The memory pillar MP extends in the z-axis direction within the laminate S1. The upper surface of the memory pillar MP is located above the conductor 24. The lower surface of the memory pillar MP is located within the conductor 21. The portion where the memory pillar MP contacts the conductor 22 functions as a selection gate transistor ST. The portion where the memory pillar MP contacts one conductor 23 functions as one memory cell transistor MT. The portion where the memory pillar MP contacts the conductor 24 functions as a selection transistor DT.

[0050] The memory pillar MP includes, for example, a core 50, a semiconductor 51, and a laminate 52. The core 50 is made of an insulator, for example, silicon oxide. The core 50 extends along the z-axis and has a columnar shape. The semiconductor 51 includes, for example, silicon. The semiconductor 51 is an example of a first semiconductor portion. The semiconductor 51 covers the surface of the core 50. The laminate 52 covers the side and bottom surfaces of the semiconductor 51. The laminate 52 is an example of a first insulator portion. The laminate 52 is open in the conductor 21, which is partially located within the opening. Within the opening, the conductor 21 and the semiconductor 51 are in contact.

[0051] As described above, one memory pillar MP and one conductor 25 are connected by a contact plug CV.

[0052] The slit SLT divides the conductors 22-24. The upper surface of the slit SLT is located above the upper surface of the memory pillar MP. The lower surface of contact LI is in contact with conductor 21. The spacer SP is located between contact LI and conductors 22-24, insulating contact LI from conductors 22-24. Contact LI functions as part of the source wire SL.

[0053] The slit SHE divides the conductor 24. The lower surface of the slit SHE is located within the insulator 35. The slit SHE contains an insulator such as silicon oxide.

[0054] Figure 6 shows the cross-sectional structure of the memory pillar MP of the semiconductor memory device 100 according to the first embodiment. Figure 6 shows a cross-section along the DD line in Figure 5. As shown in Figure 6, the laminate 52 includes, for example, a tunnel insulating film 53, a charge storage film 54, and a block insulating film 55.

[0055] The tunnel insulating film 53 covers the outer periphery of the semiconductor 51. The charge storage film 54 covers the outer periphery of the tunnel insulating film 53. The block insulating film 55 covers the outer periphery of the charge storage film 54. The conductor 23 covers the outer periphery of the block insulating film 55.

[0056] The semiconductor 51 functions as a channel (current path) for memory cell transistors MT0 to MT7 and selection transistors DT and ST. Each of the tunnel insulating film 53 and block insulating film 55 contains, for example, silicon oxide. The charge storage film 54 stores charge. The charge storage film 54 contains, for example, silicon nitride.

[0057] (Description of support pillar HR and contact plug CC) Here, the support pillar HR and contact plug CC will be described in detail with reference to Figure 7.

[0058] Figure 7 is a plan view showing the positional relationship between the support pillar HR, the trench TR, and the contact plug CC. Figure 7 is a plan view showing an enlarged view of area B in Figure 3.

[0059] In Figure 7, trenches TR1 and TR2, and contact plugs CC1 and CC2 each have different sizes. Hereafter, trenches TR1 and TR2 may be collectively referred to as trench TR, and contact plugs CC1 and CC2 may be collectively referred to as contact plug CC.

[0060] The contact plugs CC are provided so as to extend the laminate S1 along the z-axis. The contact plugs CC are an example of a first columnar body. The contact plugs CC are provided, for example, between adjacent support pillars HR. The contact plugs CC and the support pillars HR may be in contact with each other or separated. The number of contact plugs CC provided in the withdrawal region HA1 is arbitrary.

[0061] In a plan view from the z-direction, the shape of the contact plug CC is, for example, approximately rectangular. However, the shape of the contact plug CC as viewed from the z-direction is not limited to approximately rectangular, and may be approximately circular or approximately elliptical, etc.

[0062] The support pillars HR are provided so as to extend the laminate S1 along the z-axis direction. The support pillars HR function as pillars to suppress the collapse of the laminate S1 (memory cell array 10) in the replacement process described later. Therefore, the support pillars HR need to be provided at intervals of a predetermined value or less (an interval that can suppress collapse). The support pillars HR have a column shape and extend along the z-axis from the insulator 36 to the conductor 21. The support pillars HR include an insulator such as silicon oxide. The number of support pillars HR provided in the extraction region HA1 is arbitrary.

[0063] As shown in Figure 7, the support pillars HR are provided at intervals of less than a predetermined value throughout the entire extension area HA1. Each support pillar HR has a substantially circular planar shape.

[0064] The trench TR is a groove extending in the z-axis direction from the bottom surface of the laminate S1. The trench TR is provided so as to overlap with the contact plug CC in a plan view from the z direction.

[0065] In a plan view from the z-direction, the shape of the trench TR is, for example, roughly rectangular. However, the shape of the contact plug as viewed from the z-direction is not limited to roughly rectangular.

[0066] Figure 7 illustrates the support pillar HR, trench TR, and contact plug CC in the extension region HA1 of Figure 3, but the support pillar HR, trench TR, and contact plug CC may be similarly configured in the extension region HA2 as well.

[0067] (Method for manufacturing semiconductor memory device 100) Next, a method for manufacturing the semiconductor memory device 100 will be described.

[0068] Figures 8A to 8E are cross-sectional views illustrating each step of the manufacturing method of the semiconductor memory device 100 according to the first embodiment. The upper part of Figures 8A to 8E shows a cross-section along the EE line (short side of the trench TR) in Figures 8A to 8E, and the lower part of Figure 8B shows a cross-section along the FF line (long side of the trench TR) in Figure 7.

[0069] First, as shown in Figure 8A, an insulator 30 is formed on the substrate 20. The insulator 30 is an example of a third insulating film. Then, trenches TR are formed in the insulator 30. The substrate 20 is a semiconductor substrate such as a silicon substrate.

[0070] Next, as shown in Figure 8B, a laminate S1a is formed by alternately stacking sacrificial films 23a and insulators 34 in the z-axis direction on an insulator 30 and a trench TR. Then, an insulator 36 is formed on the laminate S1a. For example, silicon oxide films are used for insulators 34 and 36, and for example, silicon nitride films are used for sacrificial films 23a.

[0071] An insulator 34 and a sacrificial film 23a are alternately stacked inside the trench TR, and a portion of the sacrificial film 23a closes the trench TR at the rafter surface. The portion of the sacrificial film 23a that closes the trench TR is called the rafter portion 231a. Depending on the shape of the trench TR, a protrusion Pa is formed at the bottom of the laminate S1a.

[0072] Next, as shown in Figure 8C, contact holes CH for contact plugs CC are formed. The contact holes CH penetrate a portion of the apex 231a of the sacrificial film 23a inside the trench TR1 and the laminate S1a. More specifically, a hard mask 70 is formed on the insulator 36. The hard mask 70 may be, for example, silicon nitride. Then, using the hard mask 70 as a mask, contact holes CH penetrating the laminate S1a in the z direction are formed by anisotropic etching using lithography and RIE (Reactive Ion Etching) methods.

[0073] As shown in the upper part of Figure 8C, the width of the contact hole CH in the x-direction is greater than the width of the trench TR in the x-direction (width of the shorter side). As shown in the lower part of Figure 8C, the width of the contact hole CH in the y-direction is smaller than the width of the trench TR in the y-direction (width of the longer side).

[0074] Next, as shown in Figure 8D, a portion of the sacrificial film 23a is removed (recessed) from the inner surface of the contact hole CH. This creates a recess where a portion of the sacrificial film 23a has been removed.

[0075] In the example shown in the lower part of Figure 8D, the width in the z-direction of the recess in the bottommost sacrificial film 23a is greater than the width in the z-direction of the recesses in the sacrificial films 23a other than the bottommost layer.

[0076] Subsequently, an insulator 80 (spacer) is formed on the inner surface of the contact hole CH. The insulator 80 is an example of a second insulating film. For example, silicon oxide is used for the insulator 80. The recesses of the sacrificial film 23a other than the bottom layer are filled and closed by the insulator 80. On the other hand, the recesses of the bottom layer of the sacrificial film 23a are not closed, although an insulator 80 is formed on the surface.

[0077] Subsequently, a portion of the insulator 80 is removed by etch-back. The portion of the insulator 80 is removed, for example, by wet etching. More specifically, the insulator 80 is removed until the rafter portion 231a is exposed. The insulator 80 embedded in the recesses of the sacrificial film 23a other than the bottom layer is not removed and remains. On the other hand, all of the insulator 80 in the recesses of the bottom layer of the sacrificial film 23a is removed. Therefore, the rafter portion 231a is not covered by the insulator 80 and is exposed on the side of the contact hole CH.

[0078] Subsequently, a sacrificial film 72 is embedded in the contact hole CH and etched back. For example, amorphous silicon is used for the sacrificial film 72.

[0079] Next, as shown in Figure 8E, a slit SLT is formed. Then, the sacrificial film 23a is replaced with the conductor 23 (word line WL) through the slit SLT. The apex portion 231a of the sacrificial film 23a becomes the apex portion 231 of the conductor 23 after replacement. Subsequently, a contact plug CC is formed by replacing the sacrificial film 72 with the conductor. The contact plug CC is in contact with the apex portion 231 and is electrically connected to the apex portion 231. Then, it is planarized. The slit SLT is embedded after the replacement of the conductor 23. After that, the semiconductor memory device 100 is completed by a process not shown.

[0080] The steps shown in Figures 8A to 8E are not limited to trench TR1, but are performed on multiple trenches TR. In the step shown in Figure 8A, multiple trenches TR (for example, trenches TR1 and TR2 shown in Figure 7) having different widths in a direction intersecting the z direction are formed so that the central part of each trench TR is closed by different sacrificial films 23a. As shown in Figure 7, the multiple contact plugs CC1 and CC2 may also have different widths in a direction intersecting the z direction. In the step shown in Figure 8C, multiple contact holes CH are formed such that, when viewed from the z direction, at least a portion of the outer edge of the rafter 231a extends beyond the outer edge of the contact hole CH.

[0081] Although Figure 7 shows two trenches TR1 and TR2, three or more trenches may be formed. By forming trenches TR with varying widths, such as trenches TR1 and TR2, it is possible to form contact plugs CC that electrically connect to multiple conductors 23 in a single photolithography process (PEP (Photo Engraving Process)).

[0082] The semiconductor memory device 100 comprises a stack S1 and a plurality of contact plugs CC. The plurality of contact plugs CC extend in the z direction so as to penetrate the stack S1. The plurality of contact plugs CC include a conductor that is electrically connected to any one of the conductors 23. The stack S1 has a plurality of protrusions P at its lower part that project in the z direction according to the shape of a plurality of trenches TR. The contact plugs CC penetrate the joint portions 231 of the conductors 23 inside the trenches TR and are electrically connected to the conductors 23.

[0083] Furthermore, around one contact plug CC, the thickness (thickness in the z-direction) of the gusset portion 231 of the conductor 23 that is electrically connected to one contact plug CC is greater than the thickness of the other conductors 23. Also, the gusset portion 231 is part of the conductor that closes the trench TR, among the insulator 34 and conductor 23 that are laminated along the inner surface of the trench TR. In addition, the gusset portion 231 is provided in the central part of the trench TR.

[0084] Furthermore, the multiple trenches TR have different widths in directions intersecting the z-direction, such that the central portion of each trench TR is blocked by a different conductor 23.

[0085] Furthermore, the contact plug CC may have a substantially elliptical or substantially rectangular shape when viewed from the z direction. Also, the contact plug CC and trench TR may have a substantially rectangular shape when viewed from the z direction. In this case, when viewed from the z direction, the longer side of the contact plug CC may be longer than the shorter side of the rafter 231. Furthermore, when viewed from the z direction, it is preferable that at least a portion of the outer edge of the rafter 231 extends beyond the outer edge of the contact plug CC.

[0086] The first embodiment is not limited to the semiconductor memory device 100, but may also be applied to semiconductor devices such as those in which contacts are formed on stacked electrodes.

[0087] As described above, according to the first embodiment, the laminate S1 has a plurality of protrusions P projecting in the z direction according to the shape of the plurality of trenches TR, either at the bottom of the laminate S1, in the middle of the laminate S1, or both. The contact plug CC penetrates the joint portion 231 of the conductor 23 inside the trench TR and electrically connects with the conductor 23. This reduces the number of steps required to form the contact plug CC.

[0088] Furthermore, in the process shown in Figure 8C, the contact hole CH is formed so as to penetrate a portion of the rafter portion 231a of the sacrificial film 23a. Also, in the process shown in Figure 8C, the contact hole CH is formed so that, in a plan view from the z direction, at least a portion of the outer edge of the rafter portion 231a extends beyond the outer edge of the contact hole CH. As a result, the replaced rafter portion 231 and the contact plug CC come into contact with each other. Consequently, the rafter portion 231 and the contact plug CC are electrically connected to each other.

[0089] Furthermore, in the process shown in Figure 8B, the width of the short side of the trench TR (width in the x-direction) is adjusted so that the trench TR is closed by the sacrificial film 23a and the rafter portion 231a is formed. In the example shown in Figure 8B, the rafter portion 231a is formed by the bottommost layer of sacrificial film 23a. By changing the width of the short side of the trench TR, it is possible to adjust, for example, the target word line WL on which the rafter portion 231 is formed from the word lines WL0 to WL7 that are later formed when the sacrificial film 23a is replaced. Trench TR2 shown in Figure 7 has a different width from trench TR1. Trench TR2 is closed by, for example, the sacrificial film 23a one layer above the bottom layer.

[0090] Furthermore, by forming multiple trenches TR with different widths in a single photolithography process, multiple contact plugs CC connected to each of the multiple conductors 24 can be formed more easily.

[0091] Figure 9 is a cross-sectional view showing the structure of a portion of the drawout region HA1 of a semiconductor memory device according to a comparative example. The comparative example differs from the first embodiment in that a stepped structure is formed in the laminate S1 and a contact plug CC is formed that penetrates the laminate S1.

[0092] In the comparative example, a step structure is formed on the laminate S1a, a sacrificial film 23a is added to connect the conductor 23 and the contact plug CC, the step structure is embedded, and the process of flattening is required. In this case, the number of steps is large, making cost reduction difficult.

[0093] In contrast, in the first embodiment, the steps corresponding to forming the stepped structure and the steps corresponding to increasing the thickness of the sacrificial film 23a that replaces the conductor 23 are eliminated. As a result, the number of steps can be reduced. In addition, the density of the contact plug CC can be increased. As a result, the lead-out regions HA1 and HA2 can be reduced.

[0094] (Second Embodiment) Figures 10A to 10D are cross-sectional views illustrating each step of the manufacturing method of the semiconductor memory device 100 according to the second embodiment. The second embodiment differs from the first embodiment in that the trench TR is provided in the laminate S1 (laminated laminate S1a). In addition, in Figures 10B and 10C, the portion beyond the cross-section of the contact hole CH is also shown with a dashed line.

[0095] In the examples shown in Figures 10A to 10D, the laminate S1a is divided into two laminates S11a and S12a. Laminate S12a is located above laminate S11a. Laminate S11a is an example of the first or second laminate. Laminate S12a is an example of the third laminate.

[0096] First, as shown in Figure 10A, an insulator 30 is formed on the substrate 20. Then, trenches TR1 and TR2 are formed in the insulator 30. Next, a laminate S11a is formed on the insulator 30 and trenches TR1 and TR2 by alternately stacking sacrificial films 23a and insulators 34 in the z-axis direction. Then, an insulator 38 is formed on the laminate S11a. The material of the insulator 38 is, for example, the same material as the insulator 36. Next, trenches TR3 and TR4 are formed on the insulator 38 and the laminate S11a. Trenches TR3 and TR4 are formed in positions different from the positions of trenches TR1 and TR2 on the xy plane. Then, a laminate S12a is formed on the insulator 38 and trenches TR3 and TR4 by alternately stacking sacrificial films 23a and insulators 34 in the z-axis direction. Trenches TR3 and TR4 are grooves extending in the z-axis direction from the bottom surface of the laminate S12a. Note that the insulator 38 may not be formed. In this case, a laminate S12a is formed on top of a laminate S11a.

[0097] In the example shown in Figure 10A, the apex 231a of the bottommost sacrificial film 23a of the laminate S11a is formed inside trench TR1. The apex 231a of the third sacrificial film 23a from the bottom of the laminate S11a is formed inside trench TR2. The apex 231a of the second sacrificial film 23a from the bottom of the laminate S12a is formed inside trench TR3. The apex 231a of the fourth sacrificial film 23a from the bottom of the laminate S12a is formed inside trench TR4.

[0098] Next, as shown in Figure 10B, contact holes CH for the contact plug CC are formed. Multiple contact holes CH are formed that penetrate a portion of the joint portion 231a inside trenches TR1, TR2 and trenches TR3, TR4. The method for forming the contact holes CH is the same as the process shown in Figure 8C in the first embodiment.

[0099] Next, as shown in Figure 10C, a portion of the sacrificial film 23a is removed (recessed) from the inner surface of the contact hole CH. Then, an insulator 80 (spacer) is formed on the inner surface of the contact hole CH. After that, a portion of the insulator 80 is removed by etch-back.

[0100] As shown in Figure 10C, the joint portion 231a is not covered by the insulator 80 and is exposed on the side of the contact hole CH.

[0101] Next, as shown in Figure 10D, a sacrificial film 72 is embedded in the contact hole CH and etched back. Then, a slit SLT is formed. Subsequently, the sacrificial film 23a is replaced with the conductor 23 (word wire WL) through the slit SLT. The apex 231a of the sacrificial film 23a becomes the apex 231 of the conductor 23 after replacement. Then, a contact plug CC is formed by replacing the sacrificial film 72 with the conductor. The contact plug CC is electrically connected to the apex 231. Finally, the hard mask 70 is planarized so that it is exposed.

[0102] As the number of layers of conductive material 23 increases, the width of the short side of the trench TR to be formed also needs to be gradually increased. By dividing the laminate S1 into multiple laminates S11 and S12 and forming trench TRs corresponding to each laminate S11 and S12, the width of the short side of the trench TR corresponding to the upper layer of laminate S1 can be reduced. For example, the width in the x-direction of trench TR3 shown in Figure 10A is smaller than the width in the x-direction of trench TR2. This makes it possible to reduce the size of the extraction regions HA1 and HA2.

[0103] Note that the number of divisions in the laminate S1 is not limited to 2. Increasing the number of divisions in the laminate S1 can reduce the width of the trench TR. However, increasing the number of divisions increases the number of photolithography steps (PEPs) required to form the trench TR. Therefore, the number of divisions in the laminate S1 is determined by considering both the area and the number of steps.

[0104] Note that the trench TR at the bottom of the laminate S1 (laminated S1a) does not necessarily have to be provided. However, the trench TR at the bottom of the laminate S1 (laminated S1a) may be provided for contact with the lower layer portion of the laminate S1.

[0105] As in the second embodiment, the trench TR may be provided in the laminate S1 (laminated laminate S1a). The semiconductor memory device 100 according to the second embodiment can obtain the same effects as in the first embodiment.

[0106] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0107] 100 Semiconductor memory device, 10 Memory cell array, 23 Conductor, 23a Sacrificial film, 231, 231a Joint portion, 30-37 Insulator, 50 Core, 51 Semiconductor, 52 Stack, 61 Conductor, 72 Sacrificial film, 80 Insulator, CC Contact plug, CH Contact hole, HA1, HA2 Lead-out region, P, Pa Protrusion, S1, S1a, S11, S11a, S12, S12a Stack, TR Trench, WL Word line

Claims

1. A first laminate in which a first insulating film and a first conductive film are alternately stacked in a first direction, A plurality of first columnar bodies, each including a conductor that extends in the first direction so as to penetrate the first laminate and is electrically connected to any of the first conductive films, Equipped with, The first laminate has a plurality of protrusions projecting in a first direction according to the shape of the plurality of trenches, in the lower part of the first laminate, in the middle of the first laminate, or both. The first columnar body penetrates the apex of the first conductive film inside the trench and is electrically connected to the first conductive film, forming a semiconductor device.

2. The semiconductor device according to claim 1, wherein, around one of the first columnar bodies, the thickness of the joint portion of the first conductive film electrically connected to the one first columnar body is greater than the thickness of the other first conductive films.

3. The semiconductor device according to claim 1, wherein the mortise portion is a part of the first conductive film that closes the trench, among the first insulating film and the first conductive film that are laminated along the inner surface of the trench.

4. The semiconductor device according to claim 1, wherein the aforementioned joint portion is provided in the central part of the trench.

5. The semiconductor device according to claim 1, wherein the plurality of trenches have different widths in a direction intersecting the first direction such that the central portion of each trench is closed by a different first conductive film.

6. The semiconductor device according to claim 1, wherein the first columnar body has a substantially elliptical or substantially rectangular shape when viewed from the first direction.

7. The first columnar body and the trench have a substantially rectangular shape when viewed from the first direction. The semiconductor device according to claim 1, wherein, when viewed from the first direction, the long side of the first columnar body is longer than the short side of the gable portion.

8. The semiconductor device according to claim 1, wherein, when viewed from the first direction, at least a portion of the outer edge of the rafter extends beyond the outer edge of the first columnar body.

9. The semiconductor device according to claim 1, further comprising a first semiconductor portion extending in a first direction within the first laminate, and a second columnar body including a first insulating portion provided on the outer circumferential surface of the first semiconductor portion.

10. Multiple first trenches are formed in the material film. A second laminate is formed by alternately stacking a first insulating film and a first sacrificial film in a first direction on the material film and a plurality of first trenches. Extending in the first direction, it forms a plurality of holes that penetrate a portion of the apex of the first sacrificial film inside the plurality of first trenches and the second laminate, A portion of the first sacrificial film is removed from the inner surface of the hole. A second insulating film is formed on the inner surface of the aforementioned hole. Remove the second insulating film until the aforementioned joint portion is exposed. A second sacrificial membrane is embedded in the aforementioned hole. The first sacrificial film is replaced with the first conductive film. By replacing the second sacrificial film with a conductor, a plurality of first columnar bodies are formed. A method for manufacturing a semiconductor device, comprising the following:

11. The method for manufacturing a semiconductor device according to claim 10, wherein the material film is a third insulating film.

12. The method for manufacturing a semiconductor device according to claim 10, wherein forming a plurality of first trenches includes forming a plurality of first trenches having different widths in directions intersecting the first direction such that the central portions of the first trenches are closed by different first sacrificial films.

13. The method for manufacturing a semiconductor device according to claim 10, wherein forming the plurality of holes includes forming the plurality of holes such that, when viewed from the first direction, at least a portion of the outer edge of the girdle portion extends beyond the outer edge of the hole.

14. After forming the second laminate, A plurality of second trenches are formed in the second laminate, A third laminate is formed by alternately stacking the first insulating film and the first sacrificial film in a first direction on the material film and a plurality of second trenches. It further possesses the following: The method for manufacturing a semiconductor device according to claim 10, wherein forming the plurality of holes includes forming the plurality of holes that penetrate a portion of the girdle inside the plurality of first trenches and the plurality of second trenches.

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