Semiconductor devices and methods for forming the same

Abstract

This invention provides a method for forming semiconductor devices that eliminates problems arising from the die fragmentation process. [Solution] The semiconductor device is manufactured on a wafer to include one or more buffer regions that can be used to dice or cut the semiconductor device from the wafer in a die-partitioning process. The buffer regions of the semiconductor device may be located between the scribe line region of the wafer and the seal ring region of the semiconductor device. A laser beam may be used to cut grooves in the buffer regions of the semiconductor device, rather than in the scribe line region of the wafer. Another laser beam and / or a wafer saw may be used to completely cut the scribe line region and dice or cut the wafer into individual semiconductor devices.

Description

[[Background Art]]

[0001] A plurality of semiconductor devices are often manufactured on a single wafer such as a silicon (Si) wafer. Manufacturing a plurality of semiconductor devices on the same wafer allows manufacturing processes such as deposition, patterning by lithography, and / or etching to be shared among the plurality of semiconductor devices, which reduces processing time, cost, and complexity in mass production of semiconductor device manufacturing. [[Summary of the Invention]] [[Problem to be Solved by the Invention]]

[0002] However, the process of dicing a wafer into individual semiconductor devices may cause manufacturing defects in the semiconductor devices. [[Means for Solving the Problem]]

[0003] According to an embodiment of the present invention, a method comprises: forming a first semiconductor device including a first device region, a first seal ring region laterally surrounding the first device region, and a first buffer region laterally surrounding the first seal ring region; forming a second semiconductor device including a second device region, a second seal ring region laterally surrounding the second device region, and a second buffer region laterally surrounding the second seal ring region; laterally forming a scribe line region between the first buffer region and the second buffer region; forming a first trench in the first buffer region and forming a second trench in the second buffer region; and cutting the scribe line region between the first trench and the second trench.

[0004] According to embodiments of the present invention, the semiconductor device includes a device region. A seal ring region surrounds the device region laterally, and the seal ring region includes a plurality of metallized structures. The semiconductor device includes buffer regions laterally adjacent to one or more sides of the seal ring region such that the seal ring region is located between the buffer region and the device region, and the density of the plurality of metallized structures in the seal ring region is higher than the density of the metallized structures in the buffer region.

[0005] According to embodiments of the present invention, the method includes forming a first semiconductor die of a semiconductor device on a first substrate, wherein the first semiconductor die includes a first device region, a first seal ring region laterally surrounding the first device region, and a first buffer region laterally surrounding the first seal ring region. The first buffer region includes a first dielectric region without a metallized structure. The method includes forming a second semiconductor die of a semiconductor device on a second substrate, wherein the second semiconductor die includes a second device region, a second seal ring region laterally surrounding the second device region, and a second buffer region laterally surrounding the second seal ring region. The second buffer region includes a second dielectric region without a metallized structure. The method includes forming a substrate laminate by bonding the first substrate to a second substrate, wherein the first semiconductor die of the semiconductor device is bonded to the second semiconductor die of the semiconductor device. The method includes forming a groove that penetrates a second buffer region of a second semiconductor die and reaches a first buffer region of a first semiconductor die. The method also includes cutting a scribe line region of a substrate stack adjacent to the groove in the lateral direction. [Effects of the Invention]

[0006] Embodiments of the present invention can provide semiconductor devices and methods that reduce the defect rate of semiconductor devices manufactured on a wafer, improve reliability, and / or increase yield. [Brief explanation of the drawing]

[0007] The aspects of the present invention will be best understood by reading the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard industry practice, various features are not depicted to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for the sake of clarity in the discussion. [Figure 1A] This figure shows an example of a semiconductor device described herein. [Figure 1B] This figure shows an example of a semiconductor device described herein. [Figure 2A] This figure shows an example of a semiconductor device formed on a wafer. [Figure 2B] This figure shows an example of a semiconductor device formed on a wafer. [Figure 3A] This figure shows an exemplary embodiment of forming a semiconductor device on a wafer as described herein. [Figure 3B] This figure shows an exemplary embodiment of forming a semiconductor device on a wafer as described herein. [Figure 3C] This figure shows an exemplary embodiment of forming a semiconductor device on a wafer as described herein. [Figure 4A] This figure shows an exemplary embodiment of a die-partitioning process for partitioning semiconductor devices from wafers as described herein. [Figure 4B] This figure shows an exemplary embodiment of a die-partitioning process for partitioning semiconductor devices from wafers as described herein. [Figure 4C] This figure shows an exemplary embodiment of a die-partitioning process for partitioning semiconductor devices from wafers as described herein. [Figure 4D] This figure shows an exemplary embodiment of a die-partitioning process for partitioning semiconductor devices from wafers as described herein. [Figure 4E] This figure shows an exemplary embodiment of a die-partitioning process for partitioning semiconductor devices from wafers as described herein. [Figure 4F]It is a diagram illustrating an exemplary embodiment of a die singulation process for singulating semiconductor devices from a wafer described in the present specification. [Figure 4G] It is a diagram illustrating an exemplary embodiment of a die singulation process for singulating semiconductor devices from a wafer described in the present specification. [Figure 5A] It is a diagram illustrating an exemplary embodiment of a die singulation process for singulating semiconductor devices from a wafer described in the present specification. [Figure 5B] It is a diagram illustrating an exemplary embodiment of a die singulation process for singulating semiconductor devices from a wafer described in the present specification. [Figure 5C] It is a diagram illustrating an exemplary embodiment of a die singulation process for singulating semiconductor devices from a wafer described in the present specification. [Figure 5D] It is a diagram illustrating an exemplary embodiment of a die singulation process for singulating semiconductor devices from a wafer described in the present specification. [Figure 5E] It is a diagram illustrating an exemplary embodiment of a die singulation process for singulating semiconductor devices from a wafer described in the present specification. [Figure 5F] It is a diagram illustrating an exemplary embodiment of a die singulation process for singulating semiconductor devices from a wafer described in the present specification. [Figure 5G] It is a diagram illustrating an exemplary embodiment of a die singulation process for singulating semiconductor devices from a wafer described in the present specification. [Figure 6A] It is a diagram illustrating an exemplary embodiment of a semiconductor device singulated from a wafer described in the present specification. [Figure 6B] It is a diagram illustrating an exemplary embodiment of a semiconductor device singulated from a wafer described in the present specification. [Figure 6C] It is a diagram illustrating an exemplary embodiment of a semiconductor device singulated from a wafer described in the present specification. [Figure 6D] It is a diagram illustrating an exemplary embodiment of a semiconductor device singulated from a wafer described in the present specification. [Figure 7A]It is a diagram illustrating an exemplary embodiment of a die singulation process for singulating semiconductor devices from a wafer described in the present specification. [Figure 7B] It is a diagram illustrating an exemplary embodiment of a die singulation process for singulating semiconductor devices from a wafer described in the present specification. [Figure 7C] It is a diagram illustrating an exemplary embodiment of a die singulation process for singulating semiconductor devices from a wafer described in the present specification. [Figure 7D] It is a diagram illustrating an exemplary embodiment of a die singulation process for singulating semiconductor devices from a wafer described in the present specification. [Figure 7E] It is a diagram illustrating an exemplary embodiment of a die singulation process for singulating semiconductor devices from a wafer described in the present specification. [Figure 7F] It is a diagram illustrating an exemplary embodiment of a die singulation process for singulating semiconductor devices from a wafer described in the present specification. [Figure 8] It is a flowchart of an exemplary process related to forming a plurality of semiconductor devices on a wafer described in the present specification. [Figure 9] It is a flowchart of an exemplary process related to forming a plurality of semiconductor devices on a wafer described in the present specification. [Figure 10A] It is a diagram illustrating an exemplary embodiment of a die singulation process for singulating semiconductor devices from a wafer described in the present specification. [Figure 10B] It is a diagram illustrating an exemplary embodiment of a die singulation process for singulating semiconductor devices from a wafer described in the present specification. [Figure 10C] It is a diagram illustrating an exemplary embodiment of a die singulation process for singulating semiconductor devices from a wafer described in the present specification. [Figure 10D] It is a diagram illustrating an exemplary embodiment of a die singulation process for singulating semiconductor devices from a wafer described in the present specification. [Figure 10E]This figure shows an exemplary embodiment of a die-partitioning process for partitioning semiconductor devices from wafers as described herein. [Figure 10F] This figure shows an exemplary embodiment of a die-partitioning process for partitioning semiconductor devices from wafers as described herein. [Modes for carrying out the invention]

[0008] The following disclosure provides many different embodiments or examples for carrying out different features of the subject matter of the present invention. Specific examples of components and arrangements are described below for the sake of brevity of the invention. These are, of course, merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features so that the first and second features do not come into direct contact. Furthermore, the present invention may use repeated reference numerals and / or letters in various examples. This repetition is for the sake of brevity and clarity and does not in itself define the relationships between the various embodiments and / or configurations discussed.

[0009] Furthermore, spatially relative terms such as “down,” “underside,” “downward,” “up,” and “top” may be used in this specification to facilitate the description of the relationship between one element or feature and another, as shown in the figures. These spatially relative terms are intended to encompass different orientations of the device during use or operation, in addition to the orientation shown in the figures. The device may also be oriented in other directions (90-degree rotation or other directions), and the spatially relative descriptions used herein may be interpreted accordingly.

[0010] When manufacturing semiconductor devices on a wafer, the wafer may be diced or cut to separate the semiconductor devices. After separation, the semiconductor devices may undergo further processing (e.g., testing or packaging). The wafer may include a scribe line region. A scribe line region is a region provided around a semiconductor device and manufactured to provide a dedicated area of ​​the wafer for cutting. In some cases, the scribe line region of the wafer may include structures for other purposes, such as process control monitoring (PCM) structures used to monitor various aspects of the semiconductor device during manufacturing.

[0011] Various die singulation techniques may be used to dice or cut a wafer into individual semiconductor devices. For example, a diamond-coated saw may be used to cut (e.g., saw) the scribe line region of the wafer. Alternatively, a laser beam may be used to cut (e.g., laser cutting) the scribe line region of the wafer. In some cases, laser cutting and sawing may be combined to cut the scribe line region of the wafer and cut the wafer into individual semiconductor devices.

[0012] The process of cutting a wafer into individual semiconductor devices can cause manufacturing defects in the semiconductor devices due to mechanical stresses induced in various areas of the semiconductor device by sawing and / or laser cutting, among other things. For example, in the process of cutting a wafer into individual semiconductor devices, debris is generated by removing material from the scribe line area of ​​the wafer, and this debris can damage the semiconductor device through mechanical wear of the layers and / or structure. Another example is that in the process of cutting a wafer into individual semiconductor devices, heat and vibration are generated in the structure of the scribe line area of ​​the wafer, which can propagate to the functional device area and / or structure of the semiconductor device, weakening and / or damaging those layers and structures. These mechanical stresses, and other mechanical stresses induced in various areas of the semiconductor device by the pieceization process, can cause cracks, delamination, and / or other physical damage to the layers and / or structural elements of the semiconductor device.

[0013] In some embodiments described herein, the semiconductor device is manufactured on a wafer to include one or more buffer regions that can be used to dice or cut the semiconductor device from the wafer in a die-partitioning process. The buffer regions of the semiconductor device may be located between the scribe line region of the wafer and the seal ring region of the semiconductor device. The seal ring region may laterally surround the device region of the semiconductor device, and the buffer regions may laterally surround the seal ring region of the semiconductor device.

[0014] In the die-partitioning process, a laser beam may be used to cut grooves in the buffer region of the semiconductor device rather than in the scribe line region of the wafer. Subsequently, another laser beam and / or wafer saw may be used to completely cut the scribe line region and dic or cut the wafer into individual semiconductor devices.

[0015] The pattern density (e.g., structural density) in the buffer region is lower than the pattern density in the scribe line region and the device region. The lower pattern density in the buffer region reduces the pathways through which thermal and mechanical vibrations from laser cutting and / or sawing propagate to the device region of the semiconductor device. In other words, the buffer region effectively buffers the device region from thermal and mechanical stresses generated during the die fragmentation process, reducing the likelihood that these other mechanical stresses generated during the die fragmentation process will cause cracks, delamination, and / or other types of physical damage to the layers and / or structure of the semiconductor device. In this way, the buffer region described herein can reduce the defect rate, increase reliability, and / or improve yield of semiconductor devices manufactured on wafers.

[0016] Figures 1A and 1B show an example 100 of the semiconductor device 102 described herein. Figure 1A shows a top view of the semiconductor device 102, and Figure 1B shows a cross-sectional view of the semiconductor device 102 along line AA in Figure 1A.

[0017] As shown in Figure 1A, the semiconductor device 102 may include a device region 104, a seal ring region 106 surrounding the device region 104, and a buffer region 108 surrounding the seal ring region 106.

[0018] The device region 104 may correspond to the active region of the semiconductor device 102. The semiconductor device 102 may be a system-on-a-chip (SoC) die, a central processing device (CPU) die, a graphics processing device (GPU) die, a digital signal processing (DSP) die, an application-specific integrated circuit (ASIC) die, an image sensor die, an HPC die, and / or other types of semiconductor dies including a plurality of functional regions 110-116 distributed laterally across the device region 104. The arrangement, number, size, shape, and / or configuration of the functional regions 110-116 in the top view of the semiconductor device 102 are examples, and other arrangements, quantities, sizes, shapes, and / or configurations are also within the scope of the present invention.

[0019] Each of the functional areas 110 to 116 may be manufactured to include an integrated circuit configured to perform a particular set of functions of the semiconductor device 102. For example, functional area 110 may be a memory area (or memory core) of the semiconductor device 102, including an integrated circuit configured to perform the memory functions of the semiconductor device 102. As another example, functional area 112 may be an analog circuit area (or analog core) of the semiconductor device 102, including an integrated circuit configured to perform the analog functions of the semiconductor device 102. As yet another example, functional area 114 may be an RF circuit area (or RF core) of the semiconductor device 102, including an integrated circuit configured to perform the RF communication functions of the semiconductor device 102. As yet another example, functional area 116 may be a logic circuit area (or logic core) of the semiconductor device 102, including an integrated circuit configured to perform the logic functions of the semiconductor device 102. In some embodiments, the semiconductor device 102 includes different types of functional areas or different combinations of functional areas.

[0020] As further shown in Figure 1A, the seal ring region 106 may laterally surround the functional regions 110-116 of the semiconductor device 102. The seal ring region 106 may include a ring of interconnection layers of the metallized structure and interconnection structure, which enhance the structural rigidity of the semiconductor device 102, thereby reducing the possibility of cracks, warping, and / or other types of physical damage that may occur due to physical stresses applied to the semiconductor device 102. In addition and / or alternatively, the interconnection layers of the seal ring region 106 may be configured to provide moisture sealing of the semiconductor device 102, thereby reducing the possibility of moisture ingress into the semiconductor package. The interconnection layers of the metallized structure can form a continuous seal around the outside of the device region 104 of the semiconductor device 102.

[0021] As further shown in Figure 1A, the buffer region 108 may laterally surround the seal ring region 106. The buffer region 108 may also include an annular region of the semiconductor device 102 that buffers the device region 104 and the seal ring region 106 from the scribe line region of the wafer on which the semiconductor device 102 is formed. The buffer region 108 can suppress disturbances such as vibration and heat from reaching the device region 104 and damaging the integrated circuit device contained therein.

[0022] The buffer region 108 may be a non-functional region of the semiconductor device 102 that includes a ring of metallized structure around the seal ring region 106. The density of the metallized structure in the buffer region 108 is lower than the density of the metallized structure in the seal ring region 106, which reduces the paths through which vibrations and heat propagate to the device region 104.

[0023] As shown in Figure 1B, the semiconductor device 102 may include a device layer 118 and an interconnection layer 120 located above the device layer 118. In some embodiments, the semiconductor device 102 includes the interconnection layer 120 on the upper and lower sides of the device layer 118 so that signals and / or power can be distributed to both sides of the device layer 118.

[0024] The device layer 118 may include a substrate layer 122. The substrate layer 122 may correspond to a portion of the wafer on which the semiconductor device 102 is formed. The substrate layer 122 may include a silicon (Si) substrate, a substrate formed of a silicon-containing material, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, or another type of wafer.

[0025] The device layer 118 may further include one or more integrated circuit devices 124 inside and / or in front of the substrate layer 122. The integrated circuit devices 124 may each include transistors (e.g., planar transistors, fin-type field-effect transistors (finFETs), gate-all-around (GAA) transistors), pixel sensors, capacitors, resistors, inductors, photodetectors, transceivers, transmitters, receivers, optical circuits, diodes, and / or other types of passive and / or other types of passive and / or active integrated circuit devices.

[0026] To provide electrical insulation to the integrated circuit device 124, isolation regions 126 may be provided in the substrate layer 122. One or more isolation regions 126 may include injection regions of the substrate layer 122 into which dopants have been injected. The dopants may include, for example, n-type dopants (such as phosphorus (P) and / or arsenic (As)) and / or p-type dopants (such as boron (B)). In addition and / or alternatively, one or more isolation regions 126 may include shallow trench isolation (STI) structures. The STI structure may be a dielectric structure extending to the front surface of the substrate layer 122, and may be made of a silicon oxide material (such as SiO2). x ), silicon nitride materials (Si3N4, etc.) x N y ), and / or may include one or more dielectric materials such as other suitable dielectric materials.

[0027] In the seal ring region 106, the substrate layer 122 may be provided with one or more isolation regions 128 for electrically isolating the integrated circuit device 124 from external influences such as vibration and humidity. The one or more isolation regions 128 may include injection regions of the substrate layer 122 into which the dopant has been injected. The dopant may include, for example, an n-type dopant (such as phosphorus (P) and / or arsenic (As)) and / or a p-type dopant (such as boron (B)). In addition and / or alternatively, the one or more isolation regions 128 may include an STI structure.

[0028] The interconnection layer 120 includes a dielectric region 130 located above the substrate layer 122. The dielectric region 130 may also include one or more backend dielectric layers (e.g., one or more interlayer dielectric (ILD) layers, one or more intermetallic dielectric (IMD) layers) and one or more etching stop layers (ESLs) alternately arranged within the interconnection layer 120. Each dielectric layer is made of an oxide (e.g., silicon oxide (SiO2)). x ) and / or other oxide materials), undoped silicate glass (USG), boron-containing silicate glass (BSG), fluorine-containing silicate glass (FSG), extremely low dielectric constant (ELK) dielectric materials with a dielectric constant of less than approximately 2.5, silicon nitride (Si x N y ), may also include silicon carbide (SiC), silicon oxynitride (SiON), and / or other suitable dielectric materials.

[0029] The interconnection layer 120 further includes one or more metallized structures 132 (e.g., conductive structures) within the dielectric region 130. The metallized structures 132 within the device region 104 may be electrically coupled to and / or physically coupled to one or more integrated circuit devices 124 within the device layer 118, and / or electrically interconnected with one another. The metallized structures 132 may correspond to circuit wiring that enables the supply of signals and / or power from and to the integrated circuit devices 124. The metallized structures 132 may include a combination of metal wires extending mainly horizontally within the interconnection layer 120 and interconnection structures (e.g., vias) extending mainly vertically within the interconnection layer 120 that electrically connect the layers of metal wires. The metallized structure 132 may also include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, as other examples of conductive materials.

[0030] In the device region 104, the layers of the metallized structure 132 may be arranged vertically to facilitate the wiring of electrical signals and / or power between the device layer 118 and the external connector connected to the semiconductor device 102. The metallized structure 132 may be arranged in alternating layers of metallization layers ("M" layers) and via layers ("V" layers). Each metallization layer may contain one or more metallized structures 132 arranged laterally within the interconnection layer 120, and each via layer may contain one or more metallized structures 132 interconnecting the metallization layers within the interconnection layer 120. For example, the via 0 (V0) layer may be located at the bottom of the interconnection layer 120 (e.g., interface with the front of the device layer 118) and may be coupled to the integrated circuit device 124 in the substrate layer 122; the metal 0 (M0) layer may be located above the V0 layer in the interconnection layer 120 and coupled to it; the via 1 (V1) layer may be located above the M0 layer in the interconnection layer 120 and coupled to it; the metal 1 (M1) layer may be located above the V1 layer in the interconnection layer 120 and coupled to it; the via 2 (V2) layer may be located above the M1 layer in the interconnection layer 120 and coupled to it, and so on. In some embodiments, the interconnection layer 120 includes nine stacked metallization layers (e.g., M0 to M8). In other embodiments, the contact layer (referred to as the "CO" layer) may be located at the bottom of the interconnection layer 120 and may be coupled to the integrated circuit device 124 in the substrate layer 122, and the V0 layer may be located above the CO layer of the interconnection layer 120 and coupled to it, and so on. In some embodiments, the interconnection layer 120 includes a number of other stacked metallization layers.

[0031] The seal ring region 106 may extend vertically through the dielectric region 130 of the interconnection layer 120 and laterally around the device region 104. The seal ring region 106 may include a plurality of vertically arranged layers (e.g., in the Z direction) of metallized structures 132 that laterally surround the device region 104 of the semiconductor device 102. The layers of the plurality of vertically arranged metallized structures 132 may be located above the isolation region 128 of the seal ring region 106 so that the electrical and / or environmental isolation provided by the seal ring region 106 can extend through the dielectric region 130 to the substrate layer 122.

[0032] The seal ring region 106 may be positioned laterally between the device region 104 and the buffer region 108. The buffer region 108 may extend vertically through the dielectric region 130 of the interconnection layer 120 and also extend laterally around the seal ring region 106. The buffer region 108 may include a plurality of vertically arranged layers (e.g., in the Z direction) of metallized structures 132 that laterally surround the device region 104 of the semiconductor device 102. The density of metallized structures 132 in the buffer region 108 is lower than the density of metallized structures 132 in the seal ring region 106, which reduces the paths through which vibrations and heat propagate to the device region 104.

[0033] In some embodiments, multiple vertically arranged layers of metallized structures 132 within the buffer region 108 are separated by a portion of the dielectric region 130. In other words, vertically adjacent layers of metallized structures 132 within the buffer region 108 do not need to be connected to each other. In some embodiments, vertically adjacent layers of metallized structures 132 within the buffer region 108 are connected to each other.

[0034] As mentioned above, Figures 1A and 1B are presented as examples. Other examples may differ from the explanations given for Figures 1A and 1B.

[0035] Figures 2A and 2B show an example 200 of a semiconductor device 102 formed on a wafer 202. Figure 2A shows a top view of the wafer 202, and Figure 2B shows a cross-sectional view of the wafer 202 along line BB in Figure 2A.

[0036] In other examples, wafer 202 may include semiconductor wafers such as silicon (Si) wafers, silicon carbide (SiC) wafers, and / or germanium (Ge) wafers. In some embodiments, wafer 202 is a multilayer wafer such as a silicon-on-insulator (SOI) wafer. In some embodiments, wafer 202 is a dielectric wafer such as a glass wafer. In some embodiments, wafer 202 is substantially circular, with a diameter of about 200 mm, a diameter of about 300 mm, or other diameters. In some embodiments, wafer 202 has other shapes.

[0037] As shown in Figure 2A, the semiconductor devices 102a to 102d may be formed on the wafer 202 such that they are spaced apart laterally and isolated by scribe line regions 204. The arrangement and number of semiconductor devices 102a to 102d shown in Figure 2A is just an example, and other arrangements and quantities are also within the scope of the present invention.

[0038] The scribe line region 204 is a region of wafer 202 surrounding semiconductor devices 102a-102d, providing space for cutting or dicing the wafer 202 to separate the semiconductor devices 102a-102d into individual devices. As shown in detail in Figure 2A, in some embodiments the scribe line region 204 may include various structures such as test structures 206. In some embodiments the scribe line region 204 may include other structures such as dummy structures (e.g., non-functional structures) 208, in other examples. The test structure 206 may include process control monitoring (PCM) structures included to monitor aspects of the manufacturing process performed on wafer 202. In some embodiments the test structure 206 may include wafer acceptance test (WAT) structures, stress test structures, test pads, test circuits, and / or other types of test structures.

[0039] As further shown in Figure 2A, semiconductor devices 102a to 102d may be manufactured to include multiple buffer regions around the device region 104 of the semiconductor devices 102a to 102d, for example, a buffer region 108 around the seal ring region 106, and another buffer region 208 around the buffer region 108. The buffer region 208 may be provided on the outside of the buffer region 108 such that the buffer region 208 surrounds the buffer region 108 laterally.

[0040] The buffer region 208 of the semiconductor device 102 (e.g., semiconductor device 102c) may include a portion of the dielectric region 130 of the semiconductor device 102. The density of the metallized structure 132 in the buffer region 108 and the buffer region 208 may be lower than the density of the metallized structure in the scribe line region 204 and the seal ring region 106, respectively. However, the density of the metallized structure 132 in the buffer region 208 is lower than the density of the metallized structure 132 in the buffer region 108. In some embodiments, the density of the metallized structure 132 in the buffer region 108 is about 25% to about 90% of the total area or volume of the buffer region 108, while the density of the metallized structure 132 in the buffer region 208 is at least about 5% lower than the density of the metallized structure 132 in the buffer region 108. In some embodiments, the buffer region 208 does not contain the metallized structure 132, the test structure 206, and / or the dummy structure, and the density of the metallized structure 132 in the buffer region 208 is approximately 0%.

[0041] The buffer regions 208 of semiconductor devices 102a-102d provide additional areas where cutting and / or sawing may be performed as part of the die-fragmentation process that cuts semiconductor devices 102a-102d from wafer 202. The low pattern density in the buffer regions 208 of semiconductor devices 102a-102d (e.g., low density of metallized structures 132) reduces the paths through which thermal and mechanical vibrations from laser cutting and / or sawing propagate to the device regions 104 of semiconductor devices 102a-102d during the die-fragmentation process. In other words, the buffer regions 208 provide a buffer that effectively protects the device regions 104 from thermal and mechanical stresses generated during the die-fragmentation process, reducing the likelihood that these other mechanical stresses generated from the die-fragmentation process will cause cracks, delamination, and / or other types of physical damage to the layers and / or structures of semiconductor devices 102a-102d. In this way, the buffer region 208 can reduce the defect rate of the semiconductor device 102 manufactured on the wafer 202, improve reliability, and / or increase yield.

[0042] As further shown in Figure 2A, buffer region 108 may have a lateral width (shown as dimension D1 in Figure 2A) in a direction substantially perpendicular to the length of buffer region 108. Buffer region 208 may have a lateral width (shown as dimension D2 in Figure 2A) in a direction substantially perpendicular to the length of buffer region 208. In some embodiments, the lateral widths of buffer region 108 and buffer region 208 may be approximately equal before the semiconductor devices 102a-102d are pieced from wafer 202. However, as described in relation to Figures 4A-4F, 5A-5G, 7A-7F, and / or other parts of this specification, grooves may be formed in the buffer region 208 of semiconductor devices 102a-102d during the process of cutting or pieced the semiconductor devices 102a-102d from wafer 202. Therefore, one or more segments of the buffer region 208 of semiconductor devices 102a to 102d may have a lateral width smaller than the lateral width of the buffer region 108 after the process of cutting or piecewise separating the semiconductor devices 102a to 102d from the wafer 202. In some embodiments, prior to piecewise separation, buffer region 108 and buffer region 208 may each have a lateral width in the range of about 50 μm to about 100 μm, providing a buffer that effectively protects the device region 104 of the semiconductor device from thermal and mechanical stress generated during the die piecewise separation process. However, other values ​​and ranges are also within the scope of the present invention.

[0043] As shown in Figure 2B, the buffer region 208 of the semiconductor device 102 (e.g., semiconductor device 102c, semiconductor device 102d) may include a portion of the dielectric region 130 of the semiconductor device 102. In some embodiments, the buffer region 208 of the semiconductor device 102 (e.g., semiconductor device 102c, semiconductor device 102d) may include one or more metallized structures 132 in a portion of the dielectric region 130. In some embodiments, no metallized structures 132 are present in a portion of the dielectric region 130 of the buffer region 208 of the semiconductor device 102 (e.g., semiconductor device 102c, semiconductor device 102d).

[0044] As mentioned above, Figures 2A and 2B are presented as examples. Other examples may differ from the explanations given for Figures 2A and 2B.

[0045] Figures 3A to 3C show exemplary embodiments 300 of forming a semiconductor device 102 on a wafer 202 as described herein. In some embodiments, one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, ion implantation tools, bonding tools, planarization tools, and / or other types of semiconductor processing tools, may be used to perform one or more processes described in relation to Figures 3A to 3C.

[0046] As shown in Figure 3A, wafer 202 may be provided. Wafer 202 may be provided in the form of a semiconductor wafer, an SOI wafer, a dielectric wafer (e.g., a glass wafer), and / or other types of workpieces. A portion of wafer 202 may correspond to the substrate layer 122 of the semiconductor device 102 on which the device layer 118 of the semiconductor device 102 is formed.

[0047] As shown in Figure 3B, an integrated circuit device 124 of the device region 104 of the semiconductor device 102 may be formed in and / or on the substrate layer 122 within the device layer 118 of the semiconductor device 102. One or more semiconductor processing tools may be used to form one or more parts of the integrated circuit device 124. For example, an ion implantation tool may be used to dope one or more regions in the substrate layer 122 with one or more types of dopants to form well regions, implant regions, and / or other types of doped regions in the substrate layer 122 for the integrated circuit device 124. As another example, a deposition tool may be used to perform various deposition processes for depositing layers and / or structures of the integrated circuit device 124 and / or for depositing photoresist layers for etching the substrate layer 122 and / or parts of the deposited layers. As yet another example, an exposure tool may be used to expose the photoresist layer and form a pattern on the photoresist layer. As yet another example, a development tool may be used to develop the pattern on the photoresist layer. As an alternative, an etching tool may be used to etch a portion of the substrate layer 122 and / or the deposited layer to form the integrated circuit device 124. As an alternative, a planarization tool may be used to planarize a portion of the integrated circuit device 124. As an alternative, a plating tool may be used to deposit the metallic structure and / or layers of the integrated circuit device 124.

[0048] As further shown in Figure 3B, one or more isolation regions 126 may be formed in the substrate layer 122 within the device region 104 of the semiconductor device 102. In addition, and / or alternatively, one or more isolation regions 128 may be formed in the substrate layer 122 within the seal ring region 106 of the semiconductor device 102. In some embodiments, forming the isolation regions 126 and / or isolation regions 128 may include etching the substrate layer 122 (e.g., using an etching tool) to form recesses in the substrate layer 122 and depositing dielectric material in the recesses (e.g., using a deposition tool). In some embodiments, forming the isolation regions 126 and / or isolation regions 128 may include implanting dopants into the substrate layer 122 (e.g., using an ion implantation tool).

[0049] As shown in Figure 3C, an interconnection layer 120 of the semiconductor device 102 may be formed above the device layer 118 of the semiconductor device 102. To form the interconnection layer 120, one or more dielectric layers of the dielectric region 130 may be deposited, or a layer of the metallized structure 132 may be formed within one or more dielectric layers.

[0050] A deposition tool may be used to deposit one or more dielectric layers using physical vapor deposition (PVD) techniques, atomic layer deposition (ALD) techniques, chemical vapor deposition (CVD) techniques, oxidation techniques, and / or other suitable deposition techniques. The one or more dielectric layers may be deposited in one or more deposition processes. In some embodiments, a planarization tool may be used to perform a planarization process (e.g., chemical mechanical planarization (CMP) process) to planarize the one or more dielectric layers after they have been deposited.

[0051] In some embodiments, a pattern of a photoresist layer is used to etch the dielectric layer and form recesses in the dielectric layer. In these embodiments, a deposition tool may be used to form the photoresist layer on the dielectric layer (e.g., using spin coating techniques and / or other suitable deposition techniques). An exposure tool may be used to expose the photoresist layer to a radiation source and pattern the photoresist layer. A developing tool may be used to develop and remove a portion of the photoresist layer and expose the pattern. An etching tool may be used to etch the dielectric layer based on the pattern and form recesses. In some embodiments, the etching process includes dry etching (e.g., plasma-based etching, gas-based etching), wet chemical etching, and / or other types of etching. In some embodiments, a photoresist removal tool may be used to remove the remaining portion of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique for etching the dielectric layer based on the pattern.

[0052] A deposition tool may be used to deposit the conductive material for the first layer of the metallized structure 132 using CVD technology, PVD technology, ALD technology, electroplating technology, and / or other suitable deposition technology. The first layer of the metallized structure 132 may be deposited in the device region 104, the seal ring region 106, and / or the buffer region 108. In some embodiments, one or more of the first layers of the metallized structure 132 may be deposited in the buffer region 108. The first layer of the metallized structure 132 may be deposited in one or more deposition processes. In some embodiments, a seed layer is deposited first, and then the first layer of the metallized structure 132 is deposited on top of the seed layer. In some embodiments, after the first layer of the metallized structure 132 has been deposited, a planarization process (e.g., CMP operation) is performed, and a planarization tool is used to planarize the first layer of the metallized structure 132.

[0053] Subsequent layers of the metallized structure 132 may be formed in a similar manner in the device region 104, the seal ring region 106, and / or the buffer region 108. In some embodiments, one or more layers of the metallized structure 132 may be deposited in the buffer region 208. Alternatively, a portion of the dielectric region 130 within the buffer region 208 may be manufactured so that the metallized structure 132 is not present.

[0054] As mentioned above, Figures 3A-3C are presented as examples. Other examples may differ from the explanations in Figures 3A-3C.

[0055] Figures 4A to 4G show exemplary embodiments 400 of the die-partitioning process for partitioning semiconductor devices 102 from a wafer 202 as described herein. One or more processes described in relation to Figures 4A to 4G may be performed using one or more semiconductor processing tools, such as a wafer / die transport tool, a laser grooving tool, a wafer sawing tool, and / or other semiconductor processing tools.

[0056] As shown in Figure 4A, semiconductor devices 102a to 102d may be formed on wafer 202. Semiconductor devices 102a to 102d may be formed on wafer 202 in the same manner as described in relation to Figures 3A to 3C. Semiconductor devices 102a to 102d may be manufactured to include a device region 104, a seal ring region 106 that laterally surrounds the device region 104, a buffer region 108 that laterally surrounds the seal ring region 106, and another buffer region 208 that laterally surrounds the buffer region 108. Furthermore, semiconductor devices 102a to 102d may be manufactured such that the buffer regions 208 of semiconductor devices 102a to 102d have a density lower than the density of the metallized structure 132 in the buffer regions 108 of semiconductor devices 102a to 102d. In some embodiments, the semiconductor devices 102a to 102d may be manufactured such that the buffer region 208 of the semiconductor devices 102a to 102d does not have a metallized structure 132.

[0057] As further shown in Figure 4A, the semiconductor devices 102a-102d may be formed on the wafer 202 such that they are spaced apart laterally and isolated by scribe line regions 204. In some embodiments, other structures, including a test structure 206, a dummy structure 208, and / or a metallized structure 132, may be formed in one or more of the scribe line regions 204 and used to monitor the manufacturing process of the wafer 202 and / or the semiconductor devices 102a-102d being manufactured thereon.

[0058] Figure 4A shows that semiconductor devices 102a to 102d are formed in a grid arrangement and the scribe line region 204 has a similar overall grid arrangement; however, the semiconductor devices 102a to 102d and the associated scribe line region 204 between them may have a different arrangement.

[0059] As shown in Figures 4B and 4C, a first laser grooving process may be performed on the wafer 202 as part of the die fragmentation process. The first laser grooving process includes forming a groove (e.g., a narrow groove) on the opposite side of the scribe line region 204. The groove may be formed within the buffer region 208 of the semiconductor devices 102a to 102d, or through the buffer region 208, such that the groove is positioned between the buffer region 108 and the scribe line region 204.

[0060] Figure 4B shows a groove path 402 for forming a groove. A laser grooving tool may be used to form the groove, and a laser beam emitted from the laser grooving tool moves along the groove path 402 to form the groove. Thus, the groove may cross one or more scribe line regions 204 between laterally adjacent semiconductor devices 102. For example, the laser beam moves along the groove path 402 that penetrates the buffer region 208 of semiconductor devices 102a and 102c, resulting in the formation of a groove that crosses the scribe line region 204 between semiconductor devices 102a and 102c.

[0061] As shown in Figure 4C, the groove path 402 can cut through a portion of the dielectric region 130 in the buffer region 208 of the semiconductor devices 102a-102d. The laser beam 404 of the laser grooving tool can also cut through a portion of the substrate layer 122 of the semiconductor devices 102a-102d. In some embodiments, the lateral cutting width of the laser beam 404 is in the range of about 6 μm to about 12 μm. However, other values ​​and ranges are also within the scope of the present invention.

[0062] Because the buffer region 208 has a low density of metallized structures 132 (or no metallized structures 132), the heat and vibration generated from the laser beam 404 cutting the dielectric region 130 are mainly contained within the dielectric region 130 and do not propagate (or their propagation is minimized) to the metallized structures 132 of the semiconductor devices 102a to 102d. This reduces and / or minimizes the possibility of cracking, delamination, and / or other types of physical damage in the device region 104 of the semiconductor devices 102a to 102d.

[0063] As shown in Figures 4D and 4E, a second laser grooving process may be performed on the wafer 202 as part of the die fragmentation process. The second laser grooving process includes forming grooves (e.g., wide grooves) in the scribe line region 204 of the wafer 202.

[0064] Figure 4D shows groove paths 408 for forming grooves. A laser grooving tool may be used to form the grooves, and a laser beam emitted from the laser grooving tool moves along the groove paths 408 to form the grooves.

[0065] As shown in Figure 4E, the groove path 408 can cut a portion of the dielectric region 130 in the scribe line region 204 between semiconductor devices 102a to 102d. The groove path 408 may be positioned laterally between grooves 410 formed within and / or through the buffer region 208 of the semiconductor devices 102a to 102d. The grooves 410 formed in the buffer region 208 of the semiconductor devices 102a to 102d can isolate the semiconductor devices 102a to 102d from head and / or mechanical disturbances (e.g., vibration) that occur during the formation of grooves through the scribe line region 204.

[0066] The laser beam 412 of the laser grooving tool can cut a portion of the substrate layer 122 of the semiconductor device 102a-102d. In some embodiments, the lateral cutting width of the laser beam 412 is in the range of about 40 μm to about 50 μm. However, other values ​​and ranges are also within the scope of the present invention.

[0067] As shown in Figures 4F and 4G, a wafer sawing tool may be used to completely separate the semiconductor devices 102a-102d from the wafer 202 by cutting the remaining portion that penetrates the substrate layer 122 within the scribe line region 204. As shown in Figure 4F, the cutting path 414 of the wafer sawing tool may penetrate laterally through the scribe line region 204 between the semiconductor devices 102a-102d.

[0068] As shown in Figure 4G, the cutting path 414 of the wafer sawing tool may penetrate the groove 416 formed in the second laser grooving process. The saw blade 418 may penetrate the groove 416 along the cutting path 414 and cut the remaining portion of the substrate layer 122 in the scribe line region 204.

[0069] As mentioned above, Figures 4A to 4G are presented as examples. Other examples may differ from the explanations given for Figures 4A to 4G.

[0070] Figures 5A to 5G show exemplary embodiments 500 of the die-partitioning process for partitioning semiconductor devices 102 from a wafer 202 as described herein. One or more processes described in relation to Figures 5A to 5G may be performed using one or more semiconductor processing tools, such as a wafer / die transport tool, a laser grooving tool, a wafer sawing tool, and / or other semiconductor processing tools.

[0071] As shown in Figures 5A to 5F, exemplary embodiment 500 of the die fragmentation process is similar to exemplary embodiment 400 of the die fragmentation process shown in Figures 4A to 4G. However, in exemplary embodiment 500 of the die fragmentation process, the buffer region 208 is not completely removed from the semiconductor devices 102a to 102d.

[0072] As shown in Figure 5D, the lateral width of the grooves 410 formed in the buffer regions 208 of semiconductor devices 102a to 102d (indicated by dimension D4 in Figure 4D) is smaller than the lateral width of the buffer region 208, and as a result, is smaller than the total portion of the dielectric region 130 removed from the buffer region 208. The lateral width of the grooves 410 formed in the buffer region 208 is smaller than the lateral width of the grooves formed in the scribe line region 204 (indicated by dimension D5 in Figure 5D).

[0073] As shown in Figure 5G, the semiconductor device 102 obtained as a result of fractionating from wafer 202 includes a portion of buffer region 208. The remaining portion of buffer region 208 may be included around buffer region 108. In other words, the remaining portion of buffer region 208 may be included on the four sides of semiconductor device 102.

[0074] The lateral width of the remaining portion of buffer region 208 (shown as dimension D3 in Figure 5G) may be smaller than the lateral width of buffer region 108 (dimension D1). In some embodiments, the width of the remaining portion of buffer region 208 may be in the range of about 3 μm to about 50 μm. However, other values ​​and ranges are also within the scope of the present invention.

[0075] As mentioned above, Figures 5A to 5G are presented as examples. Other examples may differ from the explanations given for Figures 5A to 5G.

[0076] Figures 6A to 6D show examples of semiconductor devices 102 separated from wafer 202 as described herein. The semiconductor devices 102 may be separated from wafer 202 by processes described in relation to Figures 4A to 4G, Figures 5A to 5G, and / or other parts of this specification.

[0077] Figure 6A shows an example 600 of a semiconductor device 102 pieced from a wafer 202. As shown in Figure 6A, grooves 410 may be formed in the buffer region 208 segment of the semiconductor device 102 so that the buffer region 208 segment is removed from the semiconductor device 102. The semiconductor device 102 obtained as a result after the die pieced process includes the remaining three segments of the buffer region 208 joined at the edges. The remaining three segments may be located on the three sides of the semiconductor device 102.

[0078] Figure 6B shows an example 602 of a semiconductor device 102 that has been pieced from a wafer 202. As shown in Figure 6B, grooves 410 may be formed in two segments of the buffer region 208 of the semiconductor device 102 so that the segments of the buffer region 208 can be removed from the semiconductor device 102. The semiconductor device 102 obtained as a result after the die pieced process will have the two segments of the buffer region 208 remaining on two adjacent sides of the semiconductor device 102.

[0079] Figure 6C shows an example 604 of a semiconductor device 102 that has been pieced from a wafer 202. As shown in Figure 6C, grooves 410 may be formed in two segments of the buffer region 208 of the semiconductor device 102 so that the segments of the buffer region 208 can be removed from the semiconductor device 102. The semiconductor device 102 obtained as a result after the die pieced process will have the two segments of the buffer region 208 remaining on two opposing sides of the semiconductor device 102.

[0080] Figure 6D shows an example 606 of a semiconductor device 102 that has been pieced from a wafer 202. As shown in Figure 6D, a groove 410 may be formed in the buffer region 208 of the semiconductor device 102 so that a segment of the buffer region 208 can be removed from the semiconductor device 102. The semiconductor device 102 obtained as a result after the die pieced process includes a single segment of the buffer region 208 on one side of the semiconductor device 102.

[0081] As mentioned above, Figures 6A to 6D are presented as examples. Other examples may differ from the explanations given for Figures 6A to 6D.

[0082] Figures 7A to 7F show exemplary embodiments 700 of a die-partitioning process for partitioning semiconductor devices 102 from a wafer stack as described herein. One or more processes described in relation to Figures 7A to 7F may be performed using one or more semiconductor processing tools, such as a wafer / die transport tool, a laser grooving tool, a wafer sawing tool, and / or other semiconductor processing tools.

[0083] As shown in Figures 7A to 7F, exemplary embodiment 700 of the die fragmentation process is similar to exemplary embodiment 500 of the die fragmentation process shown in Figures 5A to 5G. However, in exemplary embodiment 700 of the die fragmentation process, wafer 202 is bonded with another wafer 702 to form a wafer stack, and semiconductor devices 102a to 102d are fragmented from the wafer stack by the die fragmentation process.

[0084] As shown in Figure 7B, the semiconductor device 102 (for example, semiconductor device 102a) may be formed by joining a semiconductor die 704a to another semiconductor die 704b such that semiconductor dies 704a and 704b are stacked and arranged vertically within the semiconductor device 102. The semiconductor die 704a may be formed on the wafer 202 according to the process described in relation to Figures 3A to 3C, and the semiconductor die 704b may be formed on the wafer 702 according to the process described in relation to Figures 3A to 3C. The wafers 202 and 702 may be joined to each other such that dielectric bonds are formed between the dielectric regions 130 of the semiconductor dies 704a and 704b, and that metallic bonds are formed between the metallized structures 132 of the semiconductor dies 704a and 704b.

[0085] The device region 104 of the semiconductor device 102 (for example, semiconductor device 102a) may be laterally surrounded by a seal ring region 106 that extends through the semiconductor die 704a and semiconductor die 704b. The buffer region 108 of the semiconductor device 102 may extend through the semiconductor die 704a and semiconductor die 704b and laterally surround the seal ring region 106, and other buffer regions 208 of the semiconductor device 102 may extend through the semiconductor die 704a and semiconductor die 704b and laterally surround the buffer region 108.

[0086] As shown in Figure 7D, the grooves 410 formed in the buffer region 208 of the semiconductor devices 102a to 102d may penetrate the semiconductor devices 102a to 102d and extend to the semiconductor die 704a of the semiconductor devices 102a to 102d.

[0087] As shown in Figure 7F, the groove 416 formed in the scribe line region 204 of the wafer stack may penetrate the semiconductor devices 102a to 102d and extend to the semiconductor die 704a of the semiconductor devices 102a to 102d. As further shown in Figure 7F, the saw blade 418 may penetrate the groove 416 that penetrates the rest of the substrate layer 122 of the wafer 202.

[0088] As mentioned above, Figures 7A to 7F are presented as examples. Other examples may differ from the explanations given for Figures 7A to 7F.

[0089] Figure 8 is a flowchart of an exemplary process 800 relating to forming multiple semiconductor devices on a wafer as described herein. In some embodiments, one or more process blocks in Figure 8 are performed using one or more semiconductor processing tools, such as a deposition tool, exposure tool, development tool, etching tool, planarization tool, ion implantation tool, annealing tool, wafer / die transport tool, laser grooving tool, wafer cutting tool, and / or other types of semiconductor processing tools.

[0090] As shown in Figure 8, process 800 may include forming a plurality of semiconductor devices on a wafer (block 810). For example, one or more semiconductor processing tools may be used to form a plurality of semiconductor devices (e.g., semiconductor device 102, semiconductor devices 102a to 102d) on a wafer (e.g., wafer 202) as described herein. In some embodiments, each of the plurality of semiconductor devices is manufactured to include a device region (e.g., device region 104), a seal ring region laterally surrounding the device region (e.g., seal ring region 106), and a buffer region laterally surrounding the seal ring region (e.g., buffer region 108, buffer region 208).

[0091] As further shown in Figure 8, process 800 may also include forming a plurality of scribe line regions laterally between a plurality of semiconductor devices (block 820). For example, one or more semiconductor processing tools may be used to form a plurality of scribe line regions laterally between a plurality of semiconductor devices (e.g., scribe line region 204), as described herein. In some embodiments, the scribe line regions of the plurality of scribe line regions are arranged laterally between a first buffer region (e.g., buffer region 208) of a first semiconductor device (e.g., semiconductor device 102c) among the plurality of semiconductor devices and a second buffer region (e.g., buffer region 208) of a second semiconductor device (e.g., semiconductor device 102d) among the plurality of semiconductor devices.

[0092] As further shown in Figure 8, process 800 may also include forming a first groove in a first buffer region and a second groove in a second buffer region (block 830). For example, one or more semiconductor processing tools may be used to form a first groove (e.g., groove 410) in the first buffer region and a second groove (e.g., groove 410) in the second buffer region, as described herein.

[0093] As further shown in Figure 8, process 800 may also include cutting the scribe line region between the first groove and the second groove (block 840). For example, one or more semiconductor processing tools may be used to cut the scribe line region between the first groove and the second groove, as described herein.

[0094] Process 800 may include any single implementation or combination of implementations described below, and / or additional implementations such as implementations associated with one or more other processes described elsewhere in this Specified Publication.

[0095] In the first implementation, cutting the scribe line region includes cutting the scribe line region after forming the first groove and the second groove.

[0096] In the second implementation, cutting the scribe line region, either alone or in combination with the first implementation, includes forming a third groove (e.g., groove 416) in the scribe line region and cutting the third groove.

[0097] In the third implementation, forming the first groove and the second groove, either alone or in combination with one or more of the first and second implementations, includes performing a laser cutting process to form the first groove and the second groove.

[0098] In the fourth implementation, cutting the scribe line region, either alone or in combination with one or more of the first to third implementations, includes performing another laser cutting process after the laser cutting process to form a third groove in the scribe line region.

[0099] In the fifth implementation, cutting the scribe line region, either alone or in combination with one or more of the first through fourth implementations, includes performing a sawing process after other laser cutting processes to cut a third groove.

[0100] The sixth implementation involves forming multiple semiconductor devices, either alone or in combination with one or more of the first to fifth implementations, by forming the first semiconductor device such that the density of metallized structures in the first buffer region is less than the density of metallized structures in the seal ring region of the first semiconductor device, and the density of metallized structures in the first buffer region is less than the density of metallized structures in the scribe line region.

[0101] Figure 8 shows an exemplary block of process 800, but in some implementations, process 800 may include additional blocks, fewer blocks, different blocks, or blocks in different arrangements than those shown in Figure 8. Furthermore, or instead, two or more blocks of process 800 may be executed in parallel.

[0102] Figure 9 is a flowchart of an exemplary process 900 relating to forming multiple semiconductor devices on a substrate described herein. In some embodiments, one or more process blocks in Figure 9 are performed using one or more semiconductor processing tools, such as a deposition tool, exposure tool, developing tool, etching tool, planarizing tool, ion implantation tool, annealing tool, bonding tool, wafer / die transport tool, laser grooving tool, wafer cutting tool, and / or other types of semiconductor processing tools.

[0103] As shown in Figure 9, process 900 may include forming a first semiconductor die of a semiconductor device on a first substrate (block 910). For example, as described herein, one or more semiconductor processing tools may be used to form a first semiconductor die (e.g., semiconductor die 704a) of a semiconductor device (e.g., semiconductor device 102) on a first substrate (e.g., wafer 202). In some embodiments, the first semiconductor die is manufactured to include a first device region (e.g., device region 104), a first seal ring region (e.g., seal ring region 106) laterally surrounding the first device region, and a first buffer region (e.g., buffer region 108, buffer region 208) laterally surrounding the first seal ring region.

[0104] As further shown in Figure 9, process 900 may also include forming a second semiconductor die of a semiconductor device on a second substrate (block 920). For example, as described herein, one or more semiconductor processing tools may be used to form a second semiconductor die (e.g., semiconductor die 704b) of a semiconductor device on a second substrate (e.g., wafer 702). In some embodiments, the second semiconductor die is manufactured to include a second device region (e.g., device region 104), a second seal ring region (e.g., seal ring region 106) laterally surrounding the second device region, and a second buffer region (e.g., buffer region 108, buffer region 208) laterally surrounding the second seal ring region.

[0105] As further shown in Figure 9, process 900 may also include bonding a first substrate to a second substrate to form a substrate stack (block 930). For example, one or more semiconductor processing tools may be used to bond the first substrate to the second substrate and form a substrate stack (e.g., a wafer stack including wafers 202 and 702), as described herein. In some embodiments, a first semiconductor die of a semiconductor device is bonded to a second semiconductor die of a semiconductor device.

[0106] As further shown in Figure 9, process 900 may also include forming a groove (block 940) that penetrates the second buffer region of the second semiconductor die and leads to the first buffer region of the first semiconductor die. For example, one or more semiconductor processing tools may be used to form a groove (e.g., groove 410) that penetrates the second buffer region of the second semiconductor die and leads to the first buffer region of the first semiconductor die, as described herein.

[0107] As further shown in Figure 9, process 900 may also include cutting scribe line regions of substrate stacks adjacent to the groove in the lateral direction (block 950). For example, one or more semiconductor processing tools may be used to cut scribe line regions of substrate stacks adjacent to the groove in the lateral direction (e.g., scribe line region 204), as described herein.

[0108] Process 900 may include any single implementation or combination of implementations described below, and / or additional implementations such as implementations associated with one or more other processes described elsewhere in this specification.

[0109] In the first implementation, process 900 includes forming other grooves that penetrate a portion of the scribe line region of the second substrate and reach a portion of the scribe line region of the first substrate.

[0110] In the second implementation, cutting a scribe line region, either alone or in combination with the first implementation, includes cutting other grooves within the scribe line region.

[0111] In the third implementation, either alone or in combination with one or more of the first and second implementations, the lateral width of a groove (e.g., dimension D4) is smaller than the lateral width of other grooves (e.g., dimension D5).

[0112] In the fourth implementation, either alone or in combination with one or more of the first to third implementations, the process 900 includes forming a third buffer region (e.g., buffer region 108) laterally between a first buffer region and a first seal ring region, wherein the density of the metallized structure in the third buffer region is higher than the density of the metallized structure in the first buffer region; and forming a fourth buffer region (e.g., buffer region 108) laterally between a second buffer region and a second seal ring region, wherein the density of the metallized structure in the fourth buffer region is higher than the density of the metallized structure in the second buffer region.

[0113] In the fifth implementation, either alone or in combination with one or more of the implementations from the first to the fourth, the first buffer region includes a dielectric region without a metallized structure (e.g., dielectric region 130), and the second buffer region includes other dielectric regions without a metallized structure (e.g., dielectric region 130).

[0114] Figure 9 shows an exemplary block of process 900, but some implementations include additional blocks, fewer blocks, different blocks, or blocks in different arrangements than those shown in process 900 in Figure 9. Furthermore, or instead, two or more blocks of process 900 may be executed in parallel.

[0115] Figures 10A to 10F show exemplary embodiments 1000 of a die-partitioning process for partitioning semiconductor devices 102 from a wafer stack as described herein. One or more processes described in relation to Figures 10A to 10F may be performed using one or more semiconductor processing tools, such as a wafer / die transport tool, a laser grooving tool, a wafer sawing tool, and / or other semiconductor processing tools.

[0116] As shown in Figures 10A to 10F, exemplary embodiment 1000 of the die fragmentation process is similar to exemplary embodiment 700 of the die fragmentation process shown in Figures 7A to 7F. However, in exemplary embodiment 1000 of the die fragmentation process, wafer 202 is bonded to another wafer 702, and wafer 702 is bonded to wafer 1002 to form a wafer stack, and semiconductor devices 102a to 102d are fragmented from the wafer stack by the die fragmentation process.

[0117] As shown in Figure 10B, the semiconductor device 102 (for example, semiconductor device 102a) may be formed by joining a semiconductor die 704a and another semiconductor die 704b in the semiconductor device 102 such that the semiconductor die 704a and another semiconductor die 704b are stacked and arranged vertically, and by joining a semiconductor die 704b and another semiconductor die 704c in the semiconductor device 102 such that the semiconductor die 704b and another semiconductor die 704c are stacked and arranged vertically.

[0118] The semiconductor die 704a may be formed on the wafer 202 according to a process similar to that described in relation to Figures 3A to 3C, the semiconductor die 704b may be formed on the wafer 702 according to a process similar to that described in relation to Figures 3A to 3C, and the semiconductor die 704c may be formed on the wafer 702 according to a process similar to that described in relation to Figures 3A to 3C.

[0119] Wafer 202 and wafer 702 may be joined to each other such that dielectric bonds are formed between the dielectric regions 130 of semiconductor die 704a and semiconductor die 704b, and that metallic bonds are formed between the metallized structures 132 of semiconductor die 704a and semiconductor die 704b. Wafer 702 and wafer 1002 may be joined to each other such that dielectric bonds are formed between the dielectric regions 130 of semiconductor die 704b and semiconductor die 704c, and that metallic bonds are formed between the metallized structures 132 of semiconductor die 704b and semiconductor die 704c.

[0120] The device region 104 of the semiconductor device 102 (for example, semiconductor device 102a) may be laterally surrounded by a seal ring region 106 that extends through the semiconductor dies 704a, 704b, and 704c. The buffer region 108 of the semiconductor device 102 may extend through the semiconductor dies 704a, 704b, and 704c and laterally surround the seal ring region 106, and another buffer region 208 of the semiconductor device 102 may extend through the semiconductor dies 704a, 704b, and 704c and laterally surround the buffer region 108.

[0121] As shown in Figure 10D, the groove 410 formed in the buffer region 208 of semiconductor devices 102a to 102d may penetrate the semiconductor dies 704c and 704b of semiconductor devices 102a to 102d and extend to the semiconductor die 704a of semiconductor devices 102a to 102d.

[0122] As shown in Figure 10F, the groove 416 formed in the scribe line region 204 of the wafer stack may penetrate the semiconductor dies 704c and 704b of the semiconductor devices 102a to 102d and extend to the semiconductor die 704a of the semiconductor devices 102a to 102d. As further shown in Figure 10F, the saw blade 418 may penetrate the groove 416 that penetrates the rest of the substrate layer 122 of the wafer 202.

[0123] As stated above, Figures 10A to 10F are presented as examples. Other examples may differ from the descriptions of Figures 10A to 10F. For example, the number of semiconductor dies stacked to form the semiconductor device 102 described herein, as shown in relation to Figures 7A to 7F and 10A to 10F, is just one example. A different number of semiconductor dies may be stacked to form the semiconductor device 102 described herein and then sectionalized using the techniques described herein.

[0124] In this way, the semiconductor device is manufactured on a wafer to include one or more buffer regions that can be used to dice or cut the semiconductor device from the wafer in the die-partitioning process. The buffer region of the semiconductor device may be located between the scribe line region of the wafer and the seal ring region of the semiconductor device. The seal ring region may laterally surround the device region of the semiconductor device, and the buffer region may laterally surround the seal ring region of the semiconductor device. A laser beam may be used to cut grooves in the buffer region of the semiconductor device rather than in the scribe line region of the wafer. Another laser beam and / or a wafer saw may be used to completely cut the scribe line region and dice or cut the wafer into individual semiconductor devices. The pattern density (e.g., structure density) in the buffer region is lower than the pattern density in the scribe line region and the device region. The lower pattern density in the buffer region reduces the paths through which heat and mechanical vibrations from laser cutting and / or sawing propagate to the device region of the semiconductor device. In other words, the buffer region effectively shields the device region from thermal and mechanical stresses generated during the die fragmentation process, reducing the likelihood that these other mechanical stresses generated during the die fragmentation process will cause cracks, delamination, and / or other types of physical damage to the layers and / or structure of the semiconductor device. In this way, the buffer region described herein can reduce the defect rate of semiconductor devices manufactured on wafers, increase reliability, and / or improve yield.

[0125] As described in more detail above, some embodiments described herein provide a method. The method includes forming a plurality of semiconductor devices on a wafer, each of which is manufactured to include a device region, a seal ring region laterally surrounding the device region, and a buffer region laterally surrounding the seal ring region. The method includes forming a plurality of scribe line regions laterally between the plurality of semiconductor devices, the scribe line regions of which are laterally positioned between a first buffer region of a first semiconductor device among the plurality of semiconductor devices and a second buffer region of a second semiconductor device among the plurality of semiconductor devices. The method includes forming a first groove in the first buffer region and a second groove in the second buffer region. The method includes cutting the scribe line region between the first groove and the second groove.

[0126] As described in more detail above, some embodiments described herein provide semiconductor devices. A semiconductor device includes a device region. A semiconductor device includes a plurality of integrated circuit devices within the device region. A semiconductor device includes a seal ring region that laterally surrounds the device region, and the seal ring region includes a plurality of metallized structures. A semiconductor device includes a buffer region laterally adjacent to one or more sides of the seal ring region such that the seal ring region is laterally positioned between the buffer region and the device region, and the density of the plurality of metallized structures in the seal ring region is higher than the density of the metallized structures in the buffer region.

[0127] As described in more detail above, some embodiments described herein provide methods. The method includes forming a first semiconductor die of a semiconductor device on a first substrate, wherein the first semiconductor die is manufactured to include a first device region, a first seal ring region laterally surrounding the first device region, and a first buffer region laterally surrounding the first seal ring region. The method includes forming a second semiconductor die of a semiconductor device on a second substrate, wherein the second semiconductor die is manufactured to include a second device region, a second seal ring region laterally surrounding the second device region, and a second buffer region laterally surrounding the second seal ring region. The method includes bonding the first substrate to the second substrate to form a substrate laminate, wherein the first semiconductor die of the semiconductor device is bonded to the second semiconductor die of the semiconductor device. The method includes forming a groove that penetrates the second buffer region of the second semiconductor die and reaches the first buffer region of the first semiconductor die. The method involves cutting the scribe line region of the substrate stack adjacent to the groove in the lateral direction.

[0128] As described in more detail above, some embodiments described herein include a method. The method includes forming a first semiconductor die of a semiconductor device on a first substrate. The first semiconductor die is manufactured to include a first device region, a first seal ring region laterally surrounding the first device region, and a first buffer region laterally surrounding the first seal ring region. The first buffer region includes a first dielectric region without a metallized structure. The method includes forming a second semiconductor die of a semiconductor device on a second substrate. The second semiconductor die is manufactured to include a second device region, a second seal ring region laterally surrounding the second device region, and a second buffer region laterally surrounding the second seal ring region. The second buffer region includes a second dielectric region without a metallized structure. The method includes bonding the first substrate to the second substrate to form a substrate laminate. The first semiconductor die of the semiconductor device is bonded to the second semiconductor die of the semiconductor device. The method includes forming a groove that penetrates the second dielectric region of the second buffer region and reaches the first dielectric region of the first buffer region. The method also includes cutting a scribe line region of a substrate laminate adjacent to the groove in the lateral direction.

[0129] As described in more detail above, some embodiments described herein include methods. The method includes forming a first semiconductor device comprising a first device region, a first seal ring region laterally surrounding the first device region, and a first buffer region laterally surrounding the first seal ring region. The method includes forming a second semiconductor device comprising a second device region, a second seal ring region laterally surrounding the second device region, and a second buffer region laterally surrounding the second seal ring region. The method includes forming a scribe line region laterally between the first buffer region and the second buffer region. The method includes forming a first groove in the first buffer region and a second groove in the second buffer region. The method includes cutting the scribe line region between the first groove and the second groove.

[0130] The terms "approximately" and "substantially" can indicate that the value of a given quantity varies within 5% of that value (for example, ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are merely examples and not limiting. In view of the present invention, it should be understood that the terms "approximately" and "substantially" may refer to a percentage of the value of a given quantity.

[0131] The above outlines some features of embodiments so that those skilled in the art may better understand aspects of the present invention. Those skilled in the art should understand that the present invention can be readily used as a basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent configurations do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the present invention. [Industrial applicability]

[0132] The method and semiconductor device of the present invention can be applied to semiconductor dies. [Explanation of Symbols]

[0133] 100, 200, 600, 602, 604, 606: Example 102, 102a, 102b, 102c, 102d: Semiconductor devices 104: Device area 106: Seal ring area 108: Buffer area 110, 112, 114, 116: Functional area 118: Device Layer 120: Interconnection Layer 122: Substrate layer 124: Integrated Circuit Devices 126, 128: Isolation area 130: Dielectric region 132: Metallized structure 202, 702, 1002: Wafer 204: Scribe line area 206: Test Structure 208: Dummy structure 300, 400, 500, 700, 1000: Exemplary embodiments 402: Groove path 404, 412: Laser beam 408: Groove path 410, 416: Groove 414: Cutting path 418: Saw blade 704a, 704b, 704c: Semiconductor die 800, 900: Process 810, 820, 830, 840, 910, 920, 930, 940, 950: Block D1, D2, D3, D4, D5: Dimensions

Claims

1. To form a first semiconductor device including a first device region, a first seal ring region that laterally surrounds the first device region, and a first buffer region that laterally surrounds the first seal ring region, To form a second semiconductor device including a second device region, a second seal ring region laterally surrounding the second device region, and a second buffer region laterally surrounding the second seal ring region, A scribe line region is formed laterally between the first buffer region and the second buffer region, A first groove is formed in the first buffer region, and a second groove is formed in the second buffer region. Cutting the scribe line region between the first groove and the second groove, Methods that include...

2. Cutting the aforementioned scribe line region is After forming the first groove and the second groove, cut the scribe line region. The method according to claim 1, including the method described in claim 1.

3. Cutting the aforementioned scribe line region is To form a third groove in the scribe line region, Cutting the aforementioned third groove, The method according to claim 1, including the method described in claim 1.

4. Forming the first groove and the second groove is Perform a laser cutting process to form the first groove and the second groove. The method according to claim 1, including the method described in claim 1.

5. Cutting the aforementioned scribe line region is After the aforementioned laser cutting process, another laser cutting process is performed to form a third groove in the scribe line region. The method according to claim 4, including the method described in claim 4.

6. Cutting the aforementioned scribe line region is After the aforementioned other laser cutting process, a sawing process is performed to cut the third groove. The method according to claim 5, including the method described in claim 5.

7. Forming the first semiconductor device is The first semiconductor device is formed such that the density of the metallized structure in the first buffer region is less than the density of the metallized structure in the first seal ring region, and the density of the metallized structure in the first buffer region is less than the density of the metallized structure in the scribe line region. The method according to claim 1, including the method described in claim 1.

8. Device area and A seal ring region comprising multiple metallized structures surrounds the aforementioned device region laterally, The seal ring region is located between the buffer region and the device region, and the buffer region is laterally adjacent to one or more sides of the seal ring region. Includes, The density of the plurality of metallized structures in the seal ring region is higher than the density of the metallized structures in the buffer region. Semiconductor devices.

9. The buffer region surrounds the seal ring region in the lateral direction. The semiconductor device according to claim 8.

10. The buffer region is the first buffer region of the semiconductor device, The semiconductor device further includes a second buffer region laterally adjacent to one or more sides of the first buffer region. The first buffer region is positioned laterally between the second buffer region and the seal ring region. The semiconductor device according to claim 8.

11. The density of the metallized structure in the first buffer region is higher than the density of the metallized structure in the second buffer region. The semiconductor device according to claim 10.

12. The density of the metallized structure in the first buffer region is approximately equal to the density of the metallized structure in the second buffer region. The semiconductor device according to claim 10.

13. The width of the first buffer region in a direction substantially perpendicular to the length of the first buffer region is greater than the width of the second buffer region in a direction substantially perpendicular to the length of the second buffer region. The semiconductor device according to claim 10.

14. The first buffer region extends more along the side of the seal ring region than the second buffer region. The semiconductor device according to claim 10.

15. The first semiconductor die of a semiconductor device is formed on a first substrate, The first semiconductor die includes a first device region, a first seal ring region that laterally surrounds the first device region, and a first buffer region that laterally surrounds the first seal ring region. The first buffer region includes a first dielectric region without a metallized structure, and the formation of the first buffer region includes a first dielectric region without a metallized structure. The process involves forming a second semiconductor die of a semiconductor device on a second substrate, The second semiconductor die includes a second device region, a second seal ring region that laterally surrounds the second device region, and a second buffer region that laterally surrounds the second seal ring region. The second buffer region includes a second dielectric region without a metallized structure, and the formation of the second buffer region includes a second dielectric region without a metallized structure. The first substrate is bonded to the second substrate to form a substrate laminate, The first semiconductor die of the semiconductor device is joined to the second semiconductor die of the semiconductor device, and the formation is as follows: A groove is formed that penetrates the second dielectric region of the second buffer region and reaches the first dielectric region of the first buffer region, Cutting the scribe line region of the substrate laminate adjacent to the groove in the lateral direction, Methods that include...

16. Another groove is formed that penetrates a portion of the scribe line region of the second substrate and reaches a portion of the scribe line region of the first substrate. The method according to claim 15, further comprising:

17. Cutting the scribe line region means Cutting the other grooves within the scribe line region, The method according to claim 16.

18. The lateral width of the groove is smaller than the lateral width of the other grooves. The method according to claim 16.

19. A third buffer region is formed laterally between the first buffer region and the first seal ring region. The present invention further includes the fact that the density of the metallized structure in the third buffer region is higher than the density of the metallized structure in the first buffer region. The method according to claim 15.

20. A fourth buffer region is formed laterally between the second buffer region and the second seal ring region. The present invention further includes the fact that the density of the metallized structure in the fourth buffer region is higher than the density of the metallized structure in the second buffer region. The method according to claim 19.

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