A system and method for using signals based on signal characteristics.
Patent Information
- Application Number
- JP2026077936
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2018-05-09
- Filing Date
- 2026-05-07
- Publication Date
- 2026-09-01
Smart Images
Figure 2026139652000001_ABST
Abstract
Description
[Technical Field]
[0001] Technical Field
[0001] Embodiments contained in the present specification generally relate to cardiac electrophysiology (EP) signal collection and recording systems. More particularly, disclosed are system, apparatus and method embodiments for transmitting biomedical signals between a patient and a monitoring and therapeutic device. [Background Art]
[0002] Background
[0002] Catheter ablation is a procedure for treating arrhythmias such as atrial fibrillation, that is, myocardial diseases characterized by abnormal conduction. Depending on the severity of the problem, multiple ablation procedures may be required to achieve effective results. This is because current electrophysiology (EP) techniques have limitations in accurately identifying the location of tissue to be ablated that causes the abnormality.
[0003]
[0003] A conventional diagnostic process starts with an electrocardiogram (ECG) recorded from electrodes attached to the skin surface of a subject (e.g., a patient). The medical team evaluates the ECG signal to determine whether there is an indication for drug therapy and / or ablation. When ablation is indicated, an EP study is performed. A catheter is inserted into the heart through the patient's neck or groin, and the electrical activity of the heart is recorded. Based on this EP study, ablation is performed in the region of the heart that the medical team suspects is causing the abnormal heart rhythm.
[0004]
[0004] The ablation catheter is inserted into the patient's blood vessels and guided to the site of tissue causing abnormal electrical propagation in the heart. The catheter can scar the tissue using different energy sources (most commonly heat or cold) to reduce the tissue's ability to cause and / or transmit abnormal electrical pulses, thereby eliminating the abnormal heart rhythm. ECG signals can be recorded from surface electrodes on the patient's skin, and intracardiac (IC) signals can be obtained from a catheter inside the patient's heart and recorded as an electrocardiogram (EGM). Both ECG and IC (EGM) signals are small signals that need to be accurately evaluated for adjustment and amplification.
[0005]
[0005] In conventional EP systems, in order to confirm whether ablation treatment of a specific tissue site is successful, the medical team often has to stop the ablation process and collect physiological signals (e.g., cardiac signals) from a monitoring device (e.g., an ECG monitor). This is because current systems are not capable of accurately detecting, collecting, and isolating small cardiac signals (amplitude in the range of 0.1 to 5 mV and frequency in the range of DC to 1 kHz) in near real-time while a large ablation signal (several hundred volts at a frequency of approximately 450 kHz) is being applied.
[0006]
[0006] Specifically, Francischelli et al.'s U.S. Patent Application Publication No. 2006 / 014275 The 3A1 system monitors the ablation process and the depolarization ECG signal from an electrode adjacent to the tissue to be ablated, thereby determining the completeness or transmurality of the ablation. They propose a system and method for evaluation. Francischelli et al. To minimize noise detection problems during measurement of ECG signals from the electrodes of the device, it is noted that the measurement is preferably performed during an interruption in the delivery of ablation energy to the ablation electrode.
[0007]
[0007] Generally, some current EP recording systems can effectively assist in the treatment of arrhythmias such as atrial flutter and supraventricular tachycardia, which manifest as large-amplitude, low-frequency signals. However, in more complex and widespread arrhythmias such as atrial fibrillation and ventricular tachycardia, which are characterized as low-amplitude, high-frequency signals, effective evaluation of all relevant signals has not been found.
[0008]
[0008] This signal detection, acquisition, and feature extraction can be further complicated by equipment power line noise and pacing signals. Current EP recorders use low-pass filters, high-pass filters, and notch filters to reduce noise and artifacts from various electrical signal information. Unfortunately, conventional filtering techniques can alter the signal and make it difficult or impossible to see low-amplitude, high-frequency signals that may be specific to cardiac monitoring (visualization of these signals can be helpful in the treatment of atrial fibrillation and ventricular tachycardia). It has been recognized in recent years that certainty of waveform integrity, such as for low-noise acquisition of IC and ECG signals in an EP environment, has not been achieved previously due to contamination by artifacts and noise.
[0009]
[0009] Specifically, in their paper entitled Waveform Integrity in Atrial Fibrillation: The Forgotten Issue of Cardiac Electrophysiology (Annals of Biomedical Engineering, April 18, 2017), Martinez-Iniesta et al. point out that high-frequency, broadband instrument noise is "inevitably recorded" during signal acquisition, and that further complexity of acquisition is brought about by various other signals, including 50 or 60 Hz power supply voltage, high-frequency patient muscle activity, and low-frequency baseline fluctuations from respiration or catheter movement or unstable catheter contact. Martinez-Iniesta et al. further point out that regular filtering results in insufficient noise reduction, along with significant changes in waveform and spectral characteristics. However, aggressive filtering of 30-300 Hz remains a common practice in EP.
[0010]
[0010] Conventional practices distort the morphological features of the resulting signal, leading to the loss of relevant (target) signal information and affecting signal validity. Martinez-Iniesta et al. have proposed a partial software solution for reducing only mid-frequency and high-frequency noise using preprocessing and denoising methods, but there is no solution that combines a software low-frequency noise reduction component with a hardware noise reduction component. A desired feature of an EP system is that it can maintain the integrity of the original signal information by using a combination of hardware and software that can reduce noise from the signal (or promote a high signal-to-noise ratio) while minimizing hardware filtering that would otherwise remove the target signal content. [Overview of the project] [Problems that the invention aims to solve]
[0011]
[0011] Currently, the leading ablation technique for paroxysmal and persistent atrial fibrillation is pulmonary vein isolation (PVI), in which a medical team uses a cardiac mapping system to recreate the geometric shape of the heart in 3D and perform ablation at anatomical locations such as the pulmonary veins where atrial fibrillation occurs. The procedure takes 2 to 8 hours, and the physician may not achieve a persistent ablation lesion / scar to isolate potentially problematic tissue from the left atrium. Therefore, the patient often needs to be returned for additional ablation procedures to complete the treatment. However, additional ablation procedures and possible complications can be minimized by clearly visualizing cardiac signals during ablation and determining whether the ablation lesion is transmural or not.
[0012]
[0012] Conventional EP systems may have several other limitations. Firstly, users often want to process and display multiple characteristics of a signal in near real-time. For example, a medical team might want to display multiple versions of ECG, IC, and other physiological signals simultaneously in near real-time to evaluate different signal attributes. However, conventional EP systems are often unable to process and display multiple versions of signals simultaneously in near real-time.
[0013]
[0013] Secondly, users often want to dynamically apply new digital signal processing functions to a signal without interfering with other digital signal processing functions already applied to that signal. However, conventional solutions do not allow users to dynamically apply new digital signal processing functions to a signal without stopping the acquisition of that signal or interfering with other digital signal processing functions already applied to that signal.
[0014]
[0014] Finally, users often want to synchronize the processing and display of multiple signals in near real-time. For example, a user may want to synchronize the display of multiple processed versions of the same signal. Furthermore, a medical team may want to synchronize the display of multiple processed versions of ECG, IC, and other physiological signals. This is because a medical team's ability to make an effective clinical diagnosis depends on comparing multiple signals at the same time. However, conventional solutions may not be able to process and synchronize the display of multiple processed signals in near real-time. [Means for solving the problem]
[0015] Overview of the Embodiment
[0015] Disclosed are apparatus, systems and methods for EP signal acquisition and recording, which include numerous improvements in noise and artifact reduction for various biomedical applications.
[0016]
[0016] The disclosed EP system embodiment can record raw (unmodified) cardiac signals and other physiological signals with multiple display options, low noise, and a large input signal dynamic range. The raw signals collected by the acquisition module are filtered and processed by accompanying software using a digital processing module, with minimal use of hardware filters (for example, hardware filters are used only for AC coupling, anti-aliasing, and high-frequency suppression). The use of software-based digital signal processing algorithms allows the signals to be displayed in real time as raw signals, or simultaneously in real time in a single window or multiple windows as a combination of raw and processed signals. Furthermore, the visualization and redisplay capabilities of the disclosed EP system allow the user to mark features specified in the algorithm on a real-time trace.
[0017]
[0017] The disclosed EP system can simultaneously display signals to which two or more signal processing algorithms have been applied, a feature not found in conventional systems. This allows the user to view signals filtered in multiple ways for predetermined reasons. In the real-time window, the waveform of interest can be displayed as the raw signal or as any combination of the raw signal and the filtered signal, enabling better visualization of the signal when noise and artifacts are present.
[0018]
[0018] All displayed signals are time-synchronized. The user can view the results of various signal processing algorithms independently of real-time tracing, and has the option to open multiple review windows.
[0019]
[0019] From a clinical standpoint, the disclosed EP system can greatly assist medical teams in making decisions regarding patients undergoing various medical therapies (such as ablation), and the advantages include, but are not limited to, clearer and more reliable recording of intracardiac signals. This includes suppressing RF energy to reduce baseline fluctuations and noise; improving dynamic range, in particular, for better visualization of very low-amplitude signals that are temporarily located within large-amplitude signals; real-time digital processing and recording of raw signals to facilitate signal filtering and reduce artifacts and noise without affecting the original information; high-quality unipolar signals to aid in determining tissue type and catheter location; improved waveform integrity and artifact reduction as by-products of signal processing, enabling medical teams to improve treatment outcomes; and improved signal information, enabling medical teams to provide more accurate catheter tip positioning for ablation as well as other levels of treatment and duration for therapeutic efficacy.
[0020]
[0020] In some embodiments of a system for visualizing signals using late potentials, the memory includes a first signal module, which includes a first digital signal processor (DSP) configured to match heartbeats in a first packet relating to a first cardiac signal with known signal characteristics, and a second signal module, which includes a second DSP configured to look up late potentials in a second packet relating to a second cardiac signal in response to the matching. The memory also includes a display module coupled to the first and second signal modules, which displays a portion of the first cardiac signal and, based on the lookup, displays a portion of the second cardiac signal, including the late potential, in time-synchronized with the displayed portion of the first cardiac signal. The system also includes at least one processor coupled to the memory and configured to run the first signal module, the second signal module, and the display module. Various method embodiments of visualizing signals using late potentials are carried out by the execution of the system components by a computer system. The computer system includes a non-temporary computer-readable device, which, when run by at least one computing device, stores instructions that cause that at least one computing device to perform actions that realize the method steps.
[0021]
[0021] In some embodiments of a system for visualizing signals using early activation, the memory includes a first signal module, which includes a first DSP configured to match a heartbeat in a first packet associated with a first cardiac signal to known signal characteristics, and a second signal module, which includes a second DSP configured to search for early activation in a period prior to a matched heartbeat in a second cardiac signal. The memory also includes a display module coupled to the first and second signal modules, which displays a portion of the first cardiac signal and, based on the search, displays a portion of the second cardiac signal, including early activation, in time-synchronized with the displayed portion of the first cardiac signal. The system also includes at least one processor coupled to the memory and configured to run the first signal module, the second signal module, and the display module. Several method embodiments and non-temporary computer-readable device embodiments for visualizing signals using early activation are also disclosed.
[0022]
[0022] Several methods and non-temporary computer-readable device embodiments perform steps including accessing a first cardiac signal associated with a body surface lead, matching the heartbeat of the first cardiac signal with a known signal pattern, and searching for early excitation or delayed potentials in the second cardiac signal for a period before and after the matched heartbeat.
[0023]
[0023] Other methods and non-transient computer-readable device embodiments for filtering noise from an input signal using notch filtering include the steps of accessing an input signal having a first harmonic frequency and noise, and a quiet period in the input signal. The steps include determining the first high, storing samples of the input signal noise in a buffer during the quiescent period, and subtracting a sample from a single cycle of noise in the buffer from the input signal to generate a filtered signal, wherein the subtraction results in the input signal having a first high performing: a subtraction step, in which fundamental frequencies and harmonic frequencies are removed, and introduction of transient responses in the filtered signal is avoided; and a step of refining the filtered signal by repeating determining, storing, and subtracting.
[0024]
[0024] Some methods and non-transitory computer-readable device embodiments for filtering noise from an input signal using high-frequency filtering comprise: accessing an input signal comprising noise and a target high-frequency signal; high-pass filtering the input signal to generate a filtered signal; isolating artifacts associated with noise in the filtered signal from the target high-frequency signal; optionally, selecting a filter based on the isolated artifacts; invalidating (blank ) the filtered signal for a certain period of time before and after the isolated artifacts, wherein invalidation removes the isolated artifacts and allows passage of the target high-frequency signal.
[0025]
[0025] Some methods and non-transitory computer-readable device embodiments for pattern matching comprise: accessing an input cardiac signal; matching a portion of the input cardiac signal to a known signal pattern; displaying an indication of a degree of matching. Other embodiments of pattern matching match a portion of an input cardiac signal to a known signal pattern based on a detection threshold, and display a highlighted portion of the input cardiac signal based on the matching.
[0026]
[0026] A system embodiment for generating a clean unipolar signal, wherein the electrocardiogram The present invention also discloses a system embodiment comprising an ECG circuit board configured to process an ECG signal and a plurality of intracardiac (IC) circuit boards, each configured to process a corresponding IC signal, wherein the ECG circuit board and the plurality of IC circuit boards share substantially the same circuit configuration and components, and the ECG circuit board processes the ECG signal using substantially the same path as that each IC circuit board uses to process its corresponding IC signal.
[0027]
[0027] Other system embodiments for performing electrophysiological (EP) processing are also disclosed, comprising an ECG circuit board configured to process ECG signals, a plurality of IC circuit boards, each configured to process a corresponding IC signal, a communication interface communicatively coupled to a remote device, and a processor coupled to the ECG circuit board, the plurality of IC circuit boards and the communication interface. Such system embodiments receive feedback from the remote device via the communication interface and control the remote device via the communication interface based on the ECG signal, the IC signal and the feedback from the remote device.
[0028] Brief explanation of the drawing
[0028] The accompanying drawings, which are incorporated into this specification and form part of this specification, illustrate this embodiment, along with the description, and further help to enable those skilled in the art to create and use this embodiment. [Brief explanation of the drawing]
[0029] [Figure 1]
[0029] A block diagram of a conventional electrophysiological (EP) environment including the patient connection and interference source is shown. [Figure 2]
[0030] Hardware system block diagrams of the disclosed EP hardware system are shown according to several embodiments. [Figure 3]
[0031] Block diagrams of the multi-channel analog-to-digital input / output of the input stage of an EP hardware system, according to several embodiments, are shown. [Figure 4]
[0032] The following are block diagrams of a single channel input stage of an EP hardware system according to several embodiments. [Figure 5A]
[0033] A block diagram of the overall EP system is shown, according to several embodiments. [Figure 5B]
[0034] This document provides an overview of the overall EP system hardware and software in several embodiments. [Figure 6A]
[0035] A schematic diagram of the large-signal input protection portion of the input protection circuit of an EP hardware system, according to several embodiments, is shown. [Figure 6B]
[0036] Schematic diagrams of the electrostatic discharge (ESD) protection portion of the input protection circuit of an EP hardware system, according to several embodiments, are shown. [Figure 7]
[0037] Schematic diagrams of the high-frequency (RF) filtering portion of the input protection circuit of an EP hardware system are shown according to several embodiments. [Figure 8A]
[0038] A voltage signal plot of a typical defibrillation signal at the input to an input protection circuit, according to an exemplary embodiment, is shown. [Figure 8B]
[0038] A typical voltage signal plot of a defibrillation signal at the input to the input protection circuit according to an exemplary embodiment is shown. [Figure 8C]
[0038] A typical voltage signal plot of a defibrillation signal at the input to the input protection circuit according to an exemplary embodiment is shown. [Figure 8D]
[0038] A typical voltage signal plot of a defibrillation signal at the input to the input protection circuit according to an exemplary embodiment is shown. [Figure 8E]
[0038] A typical voltage signal plot of a defibrillation signal at the input to the input protection circuit according to an exemplary embodiment is shown. [Figure 9A]
[0039] A voltage signal plot of a typical ablation signal at the input to an input protection circuit, according to an exemplary embodiment, is shown. [Figure 9B]
[0039] A voltage signal plot of a typical ablation signal at the input to the input protection circuit according to an exemplary embodiment is shown. [Figure 9C]
[0039] A voltage signal plot of a typical ablation signal at the input to the input protection circuit according to an exemplary embodiment is shown. [Figure 9D]
[0039] A voltage signal plot of a typical ablation signal at the input to the input protection circuit according to an exemplary embodiment is shown. [Figure 9E]
[0039] A voltage signal plot of a typical ablation signal at the input to the input protection circuit according to an exemplary embodiment is shown. [Figure 10]
[0040] Schematic diagrams of the instrumentation and gain stages of the EP hardware system according to several embodiments are shown. [Figure 11]
[0041] Schematic diagrams of large signal detection / high-speed recovery circuits for EP hardware systems according to several embodiments are shown. [Figure 12]
[0042] The voltage signal plot shows a slow recovery that occurs after a large, undesirable signal has bypassed the input protection stage, instrumentation stage, and gain stage of the EP hardware system circuit, when the large signal detection / fast recovery circuit is disconnected, according to an exemplary embodiment. [Figure 13A]
[0043] The voltage signal plot shows a fast recovery that occurs after a large undesirable signal is presented to the input protection stage, instrumentation stage, and gain stage of the EP hardware system circuit, when a large signal detection / fast recovery circuit is connected, according to an exemplary embodiment. [Figure 13B]
[0043] An exemplary embodiment shows a voltage signal plot illustrating a fast recovery that occurs after a large undesirable signal is presented to the input protection stage, instrumentation stage and gain stage of the EP hardware system circuit when a large signal detection / fast recovery circuit is connected. [Figure 13C]
[0043] An exemplary embodiment shows a voltage signal plot illustrating a fast recovery that occurs after a large undesirable signal is presented to the input protection stage, instrumentation stage and gain stage of the EP hardware system circuit when a large signal detection / fast recovery circuit is connected. [Figure 14A]
[0044] The following shows signal plots for voltage signals at various internal nodes passing through the large signal detection / fast recovery circuit when the large signal detection / fast recovery circuit is connected, according to an exemplary embodiment. [Figure 14B]
[0044] The following shows a signal plot for voltage signals at various internal nodes passing through the large signal detection / fast recovery circuit when the large signal detection / fast recovery circuit is connected, according to an exemplary embodiment. [Figure 14C]
[0044] The following shows a signal plot for voltage signals at various internal nodes passing through the large signal detection / fast recovery circuit when the large signal detection / fast recovery circuit is connected, according to an exemplary embodiment. [Figure 14D]
[0044] The following shows a signal plot for voltage signals at various internal nodes passing through the large signal detection / fast recovery circuit when the large signal detection / fast recovery circuit is connected, according to an exemplary embodiment. [Figure 15A]
[0045] The following shows a signal plot for a current signal across a resistor at the output of a connected large-signal detection / fast-recovery circuit, according to an exemplary embodiment. [Figure 15B]
[0045] A signal plot for the current signal across a resistor at the output of a connected large-signal detection / fast-recovery circuit is shown according to an exemplary embodiment. [Figure 16]
[0046] Schematic diagrams of low-frequency feedback circuits that serve as dynamic current sources for EP hardware systems, according to several embodiments, are shown. [Figure 17A]
[0047] The following shows a signal plot for a typical in-band voltage differential input signal affected by 60 Hz common-mode noise to an EP hardware system, according to an exemplary embodiment. [Figure 17B]
[0047] A signal plot for a typical in-band voltage differential input signal affected by 60 Hz common-mode noise to the EP hardware system is shown according to an exemplary embodiment. [Figure 17C]
[0047] A signal plot for a typical in-band voltage differential input signal affected by 60 Hz common-mode noise to the EP hardware system is shown according to an exemplary embodiment. [Figure 17D]
[0047] A signal plot for a typical in-band voltage differential input signal affected by 60 Hz common-mode noise to the EP hardware system is shown according to an exemplary embodiment. [Figure 18A]
[0048] The following shows a signal plot of a typical differential voltage signal affected by 60 Hz common-mode noise passing through an EP hardware system, according to an exemplary embodiment. [Figure 18B]
[0048] A typical differential voltage signal affected by 60 Hz common-mode noise passing through the EP hardware system is shown in a signal plot according to an exemplary embodiment. [Figure 18C]
[0048] A typical differential voltage signal affected by 60 Hz common-mode noise passing through the EP hardware system is shown in a signal plot according to an exemplary embodiment. [Figure 18D]
[0048] A typical differential voltage signal affected by 60 Hz common-mode noise passing through the EP hardware system is shown in a signal plot according to an exemplary embodiment. [Figure 19A]
[0049] The following shows a signal plot of a typical 500 kHz ablation input system in the frequency range attenuated by the RF filter of the EP hardware system, according to an exemplary embodiment. [Figure 19B]
[0049] A signal plot of a typical 500 kHz ablation input system in the frequency range attenuated by the RF filter of the EP hardware system is shown according to an exemplary embodiment. [Figure 19C]
[0049] A signal plot of a typical 500 kHz ablation input system in the frequency range attenuated by the RF filter of the EP hardware system is shown according to an exemplary embodiment. [Figure 19D]
[0049] A signal plot of a typical 500 kHz ablation input system in the frequency range attenuated by the RF filter of the EP hardware system is shown according to an exemplary embodiment. [Figure 20A]
[0050] The following shows a signal plot of a typical 500 kHz ablation input signal at a shielded input, allowing the RF filter to attenuate the input signal to the EP hardware system, according to an exemplary embodiment. [Figure 20B]
[0050] An exemplary embodiment shows a signal plot of a typical 500 kHz ablation input signal at a shielded input, which allows the RF filter to attenuate the input signal to the EP hardware system. [Figure 21A]
[0051] The signal plot of a typical 500 kHz ablation input signal, attenuated after passing through an instrumentation amplifier and then a fully differential operational amplifier in the EP hardware system, is shown according to an exemplary embodiment. [Figure 21B]
[0051] The signal plot of a typical 500 kHz ablation input signal, attenuated after passing through the instrumentation amplifier and then the fully differential operational amplifier of the EP hardware system, is shown according to an exemplary embodiment. [Figure 21C]
[0051] The signal plot of a typical 500 kHz ablation input signal, attenuated after passing through the instrumentation amplifier and then the fully differential operational amplifier of the EP hardware system, is shown according to an exemplary embodiment. [Figure 21D]
[0051] The signal plot of a typical 500 kHz ablation input signal, attenuated after passing through the instrumentation amplifier and then the fully differential operational amplifier of the EP hardware system, is shown according to an exemplary embodiment. [Figure 22A]
[0052] This illustrates an improvement in the visualization of ECG signals or IC signals according to an exemplary embodiment. [Figure 22B]
[0053] An exemplary embodiment demonstrates that an EP system can reveal low-amplitude cardiac signals and minute components of artifacts in the EP signal when noise and large-signal processing are present. [Figure 22C]
[0054] An exemplary embodiment demonstrates that an EP system can remove 60Hz noise without saturation or delayed recovery while preserving the 60Hz signal component belonging to the original waveform. [Figure 23]
[0055] Schematic diagrams of improved Wilson Central Terminal-Right Leg Drive (WCT-RLD) circuits according to several embodiments are shown. [Figure 24]
[0056] Schematic diagrams of twin-T type feedback networks interfaced with the RLD circuit of a WCT-RLD circuit are shown in several embodiments. [Figure 25]
[0057] The signal plot of the output of the Twin-T type feedback network of the WCT-RLD circuit according to an exemplary embodiment is shown. [Figure 26]
[0058] This is a block diagram of a system that processes and displays multiple signals in near real-time, according to several embodiments. [Figure 27]
[0059] This is a block diagram of a queuing module for storing generated packets associated with different base signals, according to several embodiments. [Figure 28]
[0060] This is a block diagram of a configuration path module that generates a runtime-time-allocated signal, processed from a set of base signals, according to several embodiments. [Figure 29]
[0061] This is a block diagram of a signal module generated by a signal factory module, according to several embodiments. [Figure 30]
[0062] This is a block diagram of a display module for displaying one or more signals, according to several embodiments. [Figure 31]
[0063] This is a block diagram of a monitoring module that performs error checking according to several embodiments. [Figure 32]
[0064] Examples of adjusting the sweep speed for the display module in several embodiments are shown. [Figure 33]
[0065] This document illustrates signal management for a display module according to several embodiments. [Figure 34]
[0066] Examples of adjusting the zoom and clipping ratios for the display module in several embodiments are shown. [Figure 35]
[0067] This document describes pattern search management for a display module according to several embodiments. [Figure 36]
[0068] The following shows the delayed potential search results highlighted in the display module display according to several embodiments. [Figure 37A]
[0069] The use of a display module configured as a waterfall view is shown in several embodiments. [Figure 37B]
[0070] This illustrates the correspondence between signals in a standard display module and a display module configured as a waterfall view, according to several embodiments. [Figure 37C]
[0071] This document demonstrates the use of a display module configured as a dynamic view in several embodiments. [Figure 37D]
[0072] This document demonstrates the use of a display module configured as a trigger view in several embodiments. [Figure 38]
[0073] The acquisition of signals in the display of a display module configured as a review window, according to several embodiments, is shown. [Figure 39]
[0074] This shows amplitude measurements performed in the display of a display module configured as a review window, according to several embodiments. [Figure 40]
[0075] This is a flowchart of a method for processing and displaying multiple signals in near real-time, according to one embodiment. [Figure 41]
[0076] This is a flowchart illustrating how to configure one or more signal modules according to several embodiments. [Figure 42]
[0077] This is a flowchart illustrating a method for generating a signal module from a signal processing specification, according to several embodiments. [Figure 43]
[0078] This is a flowchart of a method for equalizing the processing delay associated with each DSP of one or more signal modules, according to several embodiments. [Figure 44]
[0079] This is a flowchart illustrating, in several embodiments, a method for receiving one or more signal samples for one or more signals using an input module. [Figure 45]
[0080] This is a flowchart illustrating a method, according to several embodiments, of converting one or more signal samples into one or more packets using a packetizer. [Figure 46]
[0081] This is a flowchart illustrating a method for dispatching a packet containing one or more signal samples to a queuing module, according to several embodiments. [Figure 47]
[0082] This is a flowchart illustrating a method for dispatching packets from a queuing module to the signaling module associated with those packets, according to several embodiments. [Figure 48]
[0083] This is a flowchart illustrating a method for processing packets using the signaling module associated with those packets, according to several embodiments. [Figure 49]
[0084] This is a flowchart illustrating a method for displaying processed packets on a screen using a display module, according to several embodiments. [Figure 50]
[0085] Examples of signals with superimposed noise, according to several embodiments, are shown. [Figure 51]
[0086] This document presents an example of a conventional method for removing noise using a notch filter, based on several embodiments. [Figure 52]
[0087] An example of the results obtained by applying the conventional filter shown in Figure 51, according to several embodiments, is shown. [Figure 53]
[0088] An example of the 180 Hz harmonic still present in the output of the conventional filter shown in Figure 51, according to several embodiments, is presented. [Figure 54]
[0089] Examples of notch filtering for signals containing 60Hz and 180Hz noise, according to several embodiments, are shown. [Figure 55]
[0090] This document presents an example of a notch filter that uses 100 samples to store exactly 3 cycles of 60Hz, according to several embodiments. [Figure 56]
[0091] An example of a notch filter for calculating quiet time, according to several embodiments, is shown. [Figure 57]
[0092] Here are some examples of notch filters that accumulate copies of noise and subtract them from a signal containing the noise, according to several embodiments. [Figure 58]
[0093] Examples of notch filter results from several embodiments are shown. [Figure 59]
[0094] This is a flowchart of a process for notch filtering noise from an input signal, according to several embodiments. [Figure 60]
[0095] Several embodiments of a conventional high-pass filter are shown. [Figure 61]
[0096] Examples of signals from several embodiments include both high-frequency signals from the cardiac conduction region and steep local spikes from various sources. [Figure 62]
[0097] An example of the resulting output from filtering the signal in Figure 61 using the high-pass filter in Figure 60, according to several embodiments, is shown. [Figure 63]
[0098] An example of the output obtained by filtering the signal in Figure 61 using a high-pass filter that removes impulses while allowing the target high-frequency signal to pass through, according to several embodiments, is shown. [Figure 64]
[0099] This is a flowchart of a process for high-pass filtering noise from an input signal, according to several embodiments. [Figure 65]
[0100] The following are examples of review windows that use a vertical caliper to select the range of data, according to several embodiments. [Figure 66]
[0101] This document presents an example of saving a selected pattern as a reference heart rate according to several embodiments. [Figure 67]
[0102] Examples of windows for selecting patterns to search, according to several embodiments, are shown. [Figure 68]
[0103] Figure 65 shows an example of a pattern search overview view in the review window where multiple matching patterns are displayed according to several embodiments. [Figure 69]
[0104] Figure 68 shows an example of a pattern search overview view in the review window according to several embodiments, where a single matching pattern is displayed and other patterns are hidden. [Figure 70]
[0105] An example of a detailed view of the review window in Figure 65, according to several embodiments, is shown. [Figure 71]
[0106] Examples of pattern matching confidence values provided by induction in several embodiments are shown. [Figure 72]
[0107] This is a flowchart of the pattern matching process according to several embodiments. [Figure 73]
[0108] This is a flowchart of the pattern matching process according to several embodiments. [Figure 74]
[0109] An example of a search definition window for creating and managing searches for delayed potentials and early excitations, according to several embodiments, is shown. [Figure 75]
[0110] An example of a delay potential detection configuration window that defines various search parameters for delay potentials, according to several embodiments, is shown. [Figure 76]
[0111] An example is shown illustrating the location of the delayed potential along with its detection reliability, according to several embodiments. [Figure 77]
[0112] This document presents an example of an early excitement detection configuration window that defines various search parameters for early excitement, based on several embodiments. [Figure 78]
[0113] This example shows the location of early excitation along with their detection confidence levels, according to several embodiments. [Figure 79]
[0114] An example of a search definition window for managing already defined delayed potential and early excitation searches, according to several embodiments, is shown. [Figure 80]
[0115] This is a flowchart of a process for detecting early excitation or delayed potential according to several embodiments. [Figure 81]
[0116] An example of a waterfall display configuration window according to several embodiments is shown. [Figure 82]
[0117] The following are examples of waterfall views using time mode in several embodiments. [Figure 83]
[0118] The following are examples of waterfall models using heart rate mode, based on several embodiments. [Figure 84]
[0119] Examples of display parameter windows in several embodiments are shown. [Figure 85]
[0120] Several examples of computer systems according to various embodiments are shown. [Modes for carrying out the invention]
[0030]
[0121] The features and advantages of this embodiment will become clearer from the detailed description below, in conjunction with the drawings. Throughout the drawings, similar reference numerals identify corresponding elements. In the drawings, similar reference numerals generally indicate identical, functionally similar, and / or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit of the corresponding reference numeral. Detailed description of the invention
[0031]
[0122] Disclosed are devices, systems, and methods relating to a unique amplifier topology for tuning cardiac (e.g., ECG and IC) signals and other physiological signals to clearly define and record low-amplitude, low-frequency information that may be collected during ablation, as well as other similar large-signal disturbances such as pacing and stimulation. During the procedure, the tip of a catheter (or other electrode) can be connected to a pacing, ablation, and stimulation device system to enable visualization, pacing, ablation, and stimulation without mode switching. For example, the disclosed devices, systems, and methods can effectively isolate ablation signals from cardiac signals during ablation while simultaneously providing input protection against high voltages from defibrillation signals, etc. Similarly, the disclosed devices, systems, and methods can effectively isolate stimulation signals from physiological signals during stimulation.
[0032]
[0123] Since it is not possible to simultaneously satisfy different system recording requirements for each signal type, each block or module of the system can be optimized for performance to achieve multiple signal adjustment requirements desired by the clinician. In various embodiments, the system can simultaneously process cardiac, pacing, ablation, defibrillation, stimulator, and other physiological signal types by detecting, adjusting, and displaying the target signals, for example, to monitor the effect of an ongoing procedure on cardiac signals.
[0033]
[0124] Furthermore, various embodiments can ensure the collection of multiple low-amplitude cardiac signals in the presence of numerous electrical noise sources and environmental interference, separate from the large signals injected during ablation and stimulation procedures, pacing, or defibrillation. The target cardiac signals can be displayed in a simple and clinically relevant manner by processing the signals in real time or near real time to show the comprehensive causal relationship between the physician-initiated procedure and the resulting cardiac signals, while simultaneously identifying signal artifacts and removing undesirable noise. This disclosure reveals both hardware and software embodiments to achieve these objectives.
[0034]
[0125] This disclosure refers to both “monopole signals” and “bipolar signals,” both of which are widely used in EP recording, but are used for complementary purposes. Both monopole and bipolar signals are used, for example, to measure ECG signals, on the patient’s body, particularly the patient’s limbs and chest. To measure the IC signal in two (or more) different, isolated electrodes, or, as an alternative example, in two (or more) different, isolated electrodes placed directly in cardiac tissue, the potential difference is obtained from the signal recorded in these electrodes.
[0035]
[0126] Conventionally, a 12-lead ECG system is used, consisting of connections to the limbs, namely the right arm (RA), left arm (LA), right leg (RL), and left leg (LL), and to six separate electrodes placed at various locations on the patient's chest, each connected to six anterior chest connectors V1-V6. Each ECG electrode wire is connected to a terminal block at the end of the patient's table and wired from there to the data acquisition system. All leads are connected to protective circuits to prevent damage to the measuring device, conventionally caused by defibrillation potentials or static electricity from the environment.
[0036]
[0127] Bipolar signals are standard for some ECG measurements (leads I, II, and III), but IC signals can also be obtained directly from the cardiac surface. Bipolar signals can be obtained by attaching two (or more) electrodes in close proximity to a given area of the heart or cardiac tissue and measuring the potential difference between the electrodes, providing information about local electrical activity, such as delayed potentials produced by damaged myocardium. However, bipolar IC signals do not provide information about the direction of electrical impulse propagation. For example, one of the challenges of bipolar mapping today is that it is not possible to know whether the signal in question originates from the distal or proximal electrode. This is important because pacing and energy delivery are provided by the distal electrode.
[0037]
[0128] A unipolar signal is generated from a point source by placing one IC electrode on the surface of the patient's heart and the other electrode spaced apart from the first electrode to act as a reference signal, so that it can be obtained from the IC potential. The unipolar leads from the IC electrode are connected such that one lead acts as the active lead, while the other lead is at an inactive location or a calculated inactive location (WCT, described later). Thus, the electrode flowing toward the active electrode produces a positive deflection, and the electrode flowing away from the active electrode produces a negative deflection. This provides information about the direction of cardiac signal propagation. Unipolar recording is particularly useful when directional information is desired, such as in determining depolarization and repolarization pathways in the endocardium and epicardium. This specification discloses a method using the first derivatives of both unipolar signals.
[0038]
[0129] Induction can also be connected to the limbs, generating a virtual triangle called "Einthoven's triangle." In this way, true bipolar induction can occur. This can be obtained by referenced to each of the other two connections (for example, LA referenced to RA is lead I, LL referenced to RA is lead II, and finally, LA referenced to LL is lead III). The average of the three limb codes RA, LA, and LL approximates the zero potential point and provides a reference electrode (WCT, described later). Here, the vector sum of lead I and lead III is lead II.
[0039]
[0130] Using the concept of Einthoven's triangle, a Wilson coupled electrode (WCT) is an electrical circuit concept used in the art (and further discussed in this disclosure) that can be used as an indifferent electrode acting as the electrical center of the heart as a reference. A WCT can be used when it is desired that the IC signal be displayed in a unipolar manner. When a WCT is used as a reference for a unipolar signal, the unipolar signal can approximate a widely separated bipolar signal for a consistent unipolar recording. A WCT eliminates the need for an additional catheter to be used as a reference for unipolar recording of the IC signal.
[0040]
[0131] In this disclosure, "near real time" means from the moment the signal passing through the EP system is generated at the input of the EP system's hardware circuitry to the EP system display monitor. This refers to the collection and visualization of signals passing through the EP system, either in their raw (unprocessed) form up to the point of initial display, or after processing by the EP system's main processing unit (MPU) and one or more digital signal processing (DSP) modules. "Approximately real-time" for raw signals can be less than approximately 5 milliseconds, and less than approximately 50 milliseconds for processed signals.
[0041]
[0132] Figure 1 is a block diagram representing a conventional EP environment 100 including patient connections and interference sources. As will be understood by those skilled in the art, the patient 118 may be connected to a pulse oximeter 104, one or more ECG units 106, an infusion pump 108, an electroanatomical mapping system 110, a data acquisition system 112 such as the EP system disclosed herein, an ablation generator 114, a nerve stimulator 128, other diagnostic equipment such as an external defibrillator, and several IC catheters. These diagnostic devices may be connected to and powered by an AC power supply 102 of 120-240V, 50 / 60Hz. Laboratory diagnostic equipment may be connected to ground 120 through its power connections.
[0042]
[0133] As the number of connections to patient 118 increases, the leakage current 122 from all patient connections through patient 118 to ground 120 increases, increasing the potential for interference and adverse effects. The total leakage current 122 when such devices are connected and operating simultaneously may be up to several tens of microamperes safely and tolerably at a basic power supply frequency of 50 or 60 Hz, but harmonics extend up to several thousand Hz. This leakage current 122 may substantially interfere with the processing of ECG and IC signals. Furthermore, patient 118 may be inductively coupled 126, as well as capacitively coupled 124 to the 120 / 240 AC power supply 102. Patient 118 may also pick up RF interference 116 from devices in close proximity to the EP environment, such as wireless headsets, mobile phones, and wireless monitors.
[0043]
[0134] For reference, Table 1 outlines the signals that may be found in conventional medical device / EP environments, both desirable and undesirable, and their signal characteristics.
[0044] [Table 1]
[0045]
[0135] As a result of instrument noise and other EP environmental interference, the measured voltage in the patient's body may be higher than 1–3V RMS (root mean square) across a frequency spectrum ranging from 50Hz to several tens of megahertz. However, the measured amplitude of the cardiac signal may be in the range of 25 microvolts to 5mV. To display these signals in a noisy environment, the cardiac signal is conventionally amplified and displayed with no loss of detail (e.g., so as not to miss relevant information) and with minimal added noise (e.g., so as not to obscure signal details) while delivering RF ablation energy at approximately 70V RMS at 500kHz or cardiac stimulation at up to 25mA.
[0046]
[0136] In this environment, a very high signal-to-noise ratio (SNR) (around 30 dB) is desirable for properly collecting and identifying the target cardiac signal, but there is no method to minimize or eliminate electrical interference sources before electrical processing by software becomes necessary. This is not achievable. Conventional hardware techniques used to adjust signals in such noisy environments include cable shielding, equipment grounding, input-output balancing, differential amplification, filtering, circuit impedance reduction, electrical isolation, or signal enhancement techniques. These conventional methods have had limited effect in achieving a sufficient signal-to-noise ratio (SNR).
[0047]
[0137] The disclosed hardware embodiments can reduce interference by applying novel electrical circuit topologies to minimize noise, isolate target IC and ECG signals, adjust those signals, and remove undesirable artifacts. This can be done before the signals are passed to processing software that provides electrophysiologists with near real-time visualization and comprehensive signal review capabilities. The EP system embodiments described herein can achieve a substantial improvement in signal-to-noise ratio (SNR).
[0048]
[0138] Figure 2 is a hardware system block diagram representing the disclosed EP hardware system 200, including, for example, an EP workstation 201 and an EP console 214, according to several embodiments. The system may include an EP console 214 with an optical interface 216 for EP measurement hardware from a user input, visualization, and review workstation (hereinafter, "EP workstation 201"). The EP workstation 201 may include, for example, a keyboard / mouse 210 and a conventional laboratory PC 208, along with a monitor distributor 206 that facilitates multiple monitors 202 to provide multiple signal, multiple context display capabilities to EP signal visualization and review software. The EP workstation 201 may also include a further optical interface 212 for electrically isolated data transmission from the EP console 214, for example, via USB 2.0.
[0049]
[0139] The EP console 214 may include one or more ECG amplifiers 218, one or more unipolar amplifiers 220 for processing unipolar signals, and a bipolar amplifier 222 for processing bipolar signals from the ECG and EGM monitoring unit 224. The EP console 214 may also include a dedicated AC input filter 234, an AC / DC power supply 236, and a DC / DC power supply 238 for adjusting and converting the main line's 120 / 240V, 50 / 60Hz power supply to DC power for use by the diagnostic equipment. ECG and EGM electrode inputs 232 can enter the EP console 214 through a yoke 226 that provides additional input impedance for protection. Junction boxes (1 and 2) 228, 230 may provide a convenient plug-in interface for an IC catheter input (not shown) for subsequent processing by the EGM monitoring unit 224.
[0050]
[0140] Figure 3 is a block diagram representing a multi-channel analog-to-digital input / output module 300 of the EP hardware system input stage, including an ECG board 302 and an IC board 316, according to several embodiments. The ECG board 302 and IC board 316 represent parts of the ECG amplifier 218, unipolar amplifier 220, and bipolar amplifier 222 of Figure 2. The ECG board 302 and IC board 316 include multiple EP hardware system input stages 400, which will be described later (see Figure 4). Figure 3 shows one 8-channel ECG board and one multi-channel IC board according to an exemplary embodiment. Some embodiments have at least 16 channels. Other embodiments may include more or fewer channels.
[0051]
[0141] In Figure 3, analog inputs V1-V6 304 represent six separate ECG (anterior chest) electrodes that can be placed in various locations on the patient's chest. Analog inputs LL, RA, and LA 306 represent limb leads for the left leg, right arm, and left arm, respectively. Output RL308 represents the patient return line driving the right bundle branch, as will be discussed later in this disclosure. Similarly, WCT314 on the ECG board 302, also discussed later in this disclosure, is a Wilson coupled electrode, which also uses analog inputs LL, RA, and LA306. The output of WCT314 can be input to each channel of the EP hardware system input stage 400 corresponding to analog inputs V1-V6 304. Each of the digital outputs V1-V6 310 represents a tuned and digitized version of their respective analog inputs V1-V6 304. In exemplary embodiments, digital outputs I, II312 may include LA referenced to RA as lead I and LL referenced to RA as lead II in a tuned and digitized form. The average of the three limb codes LL, RA, and LA306 can approximate the zero potential point and provide a reference level for generating RL308.
[0052]
[0142] In Figure 3, multiple analog inputs to the IC board 316 represent possible connections and channels from the intracardiac catheter through the EP hardware system input stage 400 (see Figure 4). The IC board 316 can accept IC signals that are either unipolar or bipolar. INDIF 318 represents an indifferent electrode, providing a reference for multiple unipolar indifferent leads. ICUniWCT1,2~N signals 320 represent unipolar IC signals referenced to the WCT. ICUniINDIF1,2~N signals 322 represent the active electrode for each IC unipolar signal. ICDiff1,2~N signals 324 represent multiple bipolar differential signals from the IC catheter. Multiple digital outputs represent tuned and digitized versions of the analog inputs, in particular ICUniWCT1,2~N signals 326, ICUniINDIF1,2~N signals 328, and ICDiff1,2~N signals 330.
[0053]
[0143] Figure 4 is a block diagram representing a single channel of the EP hardware system input stage 400, which has input protection, signal filtering, detection, feedback, and amplification circuits according to several embodiments. The circuit is shown in the block diagram by numbered blocks 1 to 11, each representing a part of the hardware functionality. This division and coding of the blocks is for ease of explanation and is not intended to limit the scope of protection provided by the appended claims. The input protection and signal filtering section of the EP hardware system input stage 400 includes symmetric positive and negative circuits that generate differential versions of each input signal for the differential signal amplification stage 532, which will be described later.
[0054]
[0144] Figure 5A is a block diagram 500 of an overall EP system disclosed herein, in several embodiments, and generally shows the interface from the main system unit (MSU) (hardware component) 504 to the main processing unit (MPU) (software component) 514. Figure 5A will be discussed in more detail later in this disclosure.
[0055]
[0145] Figure 5B is a block diagram 524 representing the main sections of the EP hardware system input stage 400, where sections 530, 532, and 534 are cross-referenced with the sections shown in the EP hardware system input stage 400.
[0056]
[0146] In Figure 5B, the analog input protection / filtering stage 530 includes block 1 - input protection 402a, block 2 - RF filter 404a, block 3 - buffer 406a, block 4 - DC block 408a, block 10 - low frequency feedback 420a, and block 11 - shielded drive 422a. The symmetrical negative circuit includes block 1 - input protection 402b, block 2 - RF filter 404b, block 3 - buffer 406b, block 4 - DC block 408b, block 10 - low frequency feedback 420b, and block 11 - shielded drive 422b. The signal amplification stage 532 includes block 5 - instrumentation amplifier / filter 410, block 6 - differential amplifier 1 / filter 412, block The A / D converter stage 534 includes a differential circuit, including block 7 - differential amplifier 2 / filter 414 and block 9 - large signal detection / fast return 418. The A / D converter stage 534 also includes block 8 - A / D converter 416. The A / D converter stage 534 also includes a communication module 510 (shown in Figure 5A) which can format signals for transmission over an optical fiber link 512 to a digital processing stage 528, represented by an MPU 514 in some embodiments.
[0057]
[0147] The functionality of the specified blocks 1 to 11 in Figure 4, that is, a single channel of the EP hardware system input stage 400, will be explained in the following paragraphs.
[0058] Analog input protection / filtering stage
[0148] The analog input protection / filtering stage 530 of the EP system shown in Figure 5B includes block 1 - input protection 402a, 420b, block 2 - RF filters 404a, 404b, block 3 - buffers 406a, 406b, block 4 - DC blocks 408a, 408b, block 10 - low-frequency feedback 420a, 420b, and block 11 - shielded drivers 422a, 422b. These elements according to several embodiments will be described in more detail in the following paragraphs.
[0059] Input protection circuit
[0149] Figures 6A, 7, and 6B show circuits including an analog input protection / filtering stage 530 of the disclosed EP system in several embodiments. Figure 6A shows an overvoltage protection circuit 600 (represented by block 1 (402a, 402b) in Figure 4) that can protect other EP hardware system input stage 400 circuits from large transient voltages, specifically from defibrillation pulses, for example. The analog input protection / filtering stage 530 can protect against input voltages that are outside the range that the circuit can actually handle.
[0060]
[0150] Specifically, the analog input protection / filtering circuit 530 can reduce high-voltage transients in ECG, IC, and other electrode lead inputs connected to the patient's body to, for example, less than 10 volts at the input to the EP system buffer. The analog input protection / filtering circuit 530 can also prevent, for example, a large signal from a defibrillator from damaging other parts of the system. Furthermore, the analog input protection / filtering circuit 530 can perform these functions without reducing the energy of the applied defibrillation pulse by more than, for example, 10%, without clamping, or without adding nonlinearity if an ablation signal is applied.
[0061]
[0151] Figure 6A shows an exemplary embodiment of the overvoltage protection circuit 600 in Block 1, which includes a commercially available gas discharge tube (GDT) 608 that can be started at very high voltages, such as voltages exceeding 300V, to provide high-voltage surge protection. The GDT 608 is coupled to two stages of diodes 610, 612 (and resistors 602, 604) designed to sequentially clip the signal to, for example, 18V to remove defibrillation signals up to 5000V. Diode 610 represents a commercially available electrostatic discharge (ESD) voltage suppressor device that can assist the GDT 608 until it is fully turned on. Diode 612 represents a commercially available bidirectional ESD protection diode that can limit the In2 input of the RF filter (Block 2) to 18V at the node labeled (a) in Figures 6A and 7.
[0062]
[0152] Conventionally, a defibrillation signal of approximately 5000V is clamped to ±5V to prevent damage. In this disclosure, the defibrillation signal can be clamped in the same way, but for example, an ablation signal having an ablation voltage of approximately 200V at 500kHz is passed linearly through input resistors RCable, 602, 604 and block 2 (Figures 4, 4). 04a, 404b), i.e., it can be attenuated by the RF filter 702.
[0063]
[0153] Figure 7 shows the RF filter / shielded drive 700, including the RF filter 702 and the shielded drive 730. The RF filter / shielded drive 700 is connected to the overvoltage protection circuit 600 in Figure 6A at the node labeled (a) to transmit the signal In12 through the analog input protection / filtering stage 530. The RF filter 702 of the RF filter / shielded drive 700 will be described in more detail later. The shielded drive 730 of the RF filter / shielded drive 700 will also be described later.
[0064]
[0154] The input overvoltage protection circuit 600 does not clamp the ablation signal; on the contrary, the ablation signal is linearly attenuated (e.g., proportionally reduced by input resistors RCable, 602, 604 and RF filter 702) to prevent accidental alteration. For example, if the ablation signal were clamped by the input overvoltage protection circuit 600, it would be impossible to access the contents of the signal beyond the clamping. Advantageously, the linear attenuation of the ablation signal by the disclosed EP system allows for the recording of small heart signals of a few millivolts during ablation. Those skilled in the art will understand that the apparatus, systems, and methods disclosed herein are similarly applicable to other high-frequency signals that need to pass through a protection circuit (e.g., not clamped) to prevent the occurrence of nonlinearities affecting the signal in question.
[0065]
[0155] Figure 6B shows the ESD input protection circuit 620 in the final section of the analog input protection / filtering stage 530. The ESD input protection circuit 620 is coupled to the RF filter / shield drive 700 at the node labeled as (b) in Figure 7. The ESD protection chip 622 can provide ESD protection up to 30kV for data lines and can respond to overvoltage conditions in nanoseconds. Any number of commercially available ESD protection devices can be used for this purpose.
[0066]
[0156] Transient Voltage Suppressor (TVS) diodes 628 and 630 can provide ESD protection above 16kV by shunting excess current when the induced voltage exceeds their breakdown voltage. TVS diodes 628 and 630 can function as "clumping" or limiting devices to suppress overvoltages exceeding their breakdown voltage and can automatically reset once the overvoltage subsides. TVS diodes 622 and 630 can also respond to overvoltages faster than other common overvoltage protection components; for example, "clumping" occurs in approximately 1 millisecond. TVS diodes can generally be advantageous for protection against voltage transients that can cause very rapid damage.
[0067]
[0157] Figures 8A–8E and 9A–9E show sample signal plots demonstrating how a front-end input protection circuit handles high-voltage transients and ESD according to an exemplary embodiment. Figure 8A shows a typical defibrillator signal, V(Defib), voltage applied to the input of the input protection circuit, labeled "EP signal" in Figure 6A. In a laboratory setting, the defibrillator signal can be derived by applying 5000 volts to a 32 μF capacitor and then discharging the capacitor to connected electrodes on a patient. Due to inductance and resistance, the amplitude received at the electrodes is approximately 4500 volts and lasts for several tens of milliseconds.
[0068]
[0158] Figures 8B to 8E show the different voltage levels as the defibrillation signal travels through the circuit. V(In) in Figure 8B is the voltage at the GDT608 in Figure 6A. The GDT has very low capacitance (e.g., less than 1pF) and high impedance (even if) when off. The GDT has a resistance (exceeding 100 M ohms). The GDT acts as a gap between the two electrodes. When ionized and turned on, the GDT can have a very low resistance (e.g., a few ohms) with a large current-carrying capacity (e.g., conducting tens of amperes), and therefore acts as a short circuit. The disadvantage of the GDT is that it can take some time to turn on, as the plot of V(In) in Figure 8B shows. The GDT should be triggered at 230V, but the voltage rises to a much higher level before it effectively turns on and begins to conduct. The turn-on time can be several hundred nanoseconds. The resistor RCable in Figure 6A limits the current going to the GDT608. This reduces the power dissipated in the system and also ensures that the analog input protection / filtering stage 530 does not shunt the equivalent power intended for the patient.
[0069]
[0159] The ESD voltage suppressor diode 610 in Figure 6A can turn on much faster, for example, in nanoseconds, but can have a lower power / energy capacity so that it can become active quickly. They can hold a voltage up to about 30V at P1, as shown in the signal plot of V(P1) in Figure 8C, while the GDT608 is fully turned on. Once the GDT608 is fully turned on, the ESD voltage suppressor diode 610 becomes inactive.
[0070]
[0160] The next step in Figure 6A is a pair of bidirectional ESD protection diodes 612, which can limit the signal at In12, i.e., the input to the RF filter (block 2), to approximately 18V, as shown in the signal plot for V(In12) in Figure 8D. The signal passing through the RF filter will be discussed further in the RF filter (block 2) section.
[0071]
[0161] Finally, as shown in Figure 6B, in In13, after the signal has been filtered by the RF filter of block 1, the ESD protection chip 622 can clip the signal with a VDD ± diode drop (e.g., ±5.7 volts), as shown in the signal plot against V(In13) in Figure 8E.
[0072]
[0162] Those skilled in the art will understand that the combination of input protection circuits shown in Figures 6A and 6B, including the GDT608, diode 610, diode 612, ESD protection chip 622, and TVS diodes 628 and 630, protects the circuits of the EP recording system. However, this circuit alone may be detrimental to achieving high-quality EP recording during ablation. For example, if the ablation signal is clipped, the resulting nonlinearity may introduce noise and mask the target cardiac signal. Since medical teams may want to see the cardiac signal during ablation, integrating a block 2 RF filter with the input protection circuit is an improvement over conventional solutions. The disclosed embodiment allows for linear filtering of the ablation signal and attenuation of potentially destructive or damaging signals while monitoring the ECG and IC signals.
[0073]
[0163] Figures 9A to 9E are signal plots showing the propagation of the ablation signal through the input protection circuits in Figures 6A, 7, and 6B. The ablation input is 400Vpp at the sensor electrode, as shown by plot V(Defib) in Figure 9A. As the signal progresses through the stages of the input protection circuit, it is attenuated by resistor RCable (shown as plot V(In) in Figure 9B), by resistor 602 (shown as plot V(P1) in Figure 9C), by resistor 604 (shown as plot V(In12) in Figure 9D), and by capacitor 716 (shown as plot V(In13) in Figure 9E). The ablation signal voltage level is 100Vpp at node In in Figure 6A. Yes, it is 12Vpp at node In12 in Figure 6A and 60mV at node In13 after the RF filter in Figure 7. The ablation signal does not trigger the protection device but is linearly attenuated, allowing observation and / or recording of the cardiac signal during ablation. The ablation signal can be further filtered in each of blocks 5, 6 and 7 of the signal amplification stage 532 (see Figures 4, 5B and 10) and in the A / D converter (block 8 in Figure 4) which has a 100dB low-pass filter at 950Hz.
[0074] RF filter circuit including low-frequency feedback and shielded drive
[0164] In addition to contributing to the input protection circuit that filters and linearly attenuates the ablation signal at the EP system input, the RF filter 702 works in conjunction with the low-frequency feedback of block 10 (see Figures 4, 420a and 420b, and Figures 16, 1600) to enable the entire circuit to pass small cardiac signals (for example, having a frequency range of approximately 0.01 Hz to approximately 500 Hz) while maintaining near real-time linear attenuation of the ablation signal (for example, having a voltage amplitude of approximately 200 V in a frequency range of approximately 300 kHz to approximately 600 kHz) during cardiac monitoring.
[0075]
[0165] The RF filter 702 can be designed to linearly attenuate the amplitude of the ablation signal, for example, by at least 75% in some embodiments, or at least 90% in other embodiments. The RF filter 702 can also be designed to provide substantially no attenuation to input signals having frequencies below 5 kHz, for example. The RF filter 702 can also function in conjunction with the shielded drive 730 of block 11 (see Figures 4, 422a and 422b and Figure 7), which, together with the input capacitors 706, 714, and 716 of the RF filter 702, can help maintain a high input impedance for the entire circuit. This high input impedance can help minimize input loss of the target heart signal. The shielded drive 730 will be discussed further later.
[0076] Low-frequency feedback circuit
[0166] Block 10 (see Figures 4, 420a and 420b), i.e., the low-frequency feedback circuit 1600, provides positive feedback to the block 2 RF filter (see Figures 4, 404a and 404b and Figure 7, 702) to increase the input impedance to the EP system and thus reduce signal attenuation. This is advantageous because the input impedance of the EP system in the frequency range of the cardiac signal may be compromised by the RF filter 702.
[0077]
[0167] Specifically, the high input impedance of the instrumentation amplifier 1001 in Figure 10 can be significantly reduced depending on the frequency of the input signal (for example, to 1 / 100th at 60 Hz) due to the presence of RLC network elements 706, 708, 714, and 716 of the RF filter 702. While the RF filter 702 is advantageous at ablation frequencies, the reduction in impedance at low frequencies may reduce the amplitude of the cardiac signal and affect common-mode rejection. If the effects of the RF filter 702 are not mitigated, the advantages of the instrumentation amplifier 1001 will be lost.
[0078]
[0168] To mitigate this loss and maintain high common-mode rejection (e.g., around 100 dB), it is desirable to maintain high impedance at power line frequencies so that fluctuations in power supply impedance do not convert common-mode signals into differential signals. Block 10, the low-frequency feedback circuit 1600 shown in Figure 16, receives a buffered version of the signal in question from block 3 buffers 406a and 406b as Buf1 1602. The low-frequency feedback circuit 1600 then applies the operational amplifier 1606 to the bases (i.e., lower plate) of capacitors 706, 714, and 716 of the RF filter 702. In this configuration, the shield 1728 is driven. Specifically, the operational amplifier 1606 acts as a drive circuit, eliminating load effects and maintaining the high input impedance of the analog input protection / filtering stage 530 to the signal amplification stage 532.
[0079]
[0169] When the low-frequency feedback circuit 1600 of block 10 drives the RF filter 702 at low frequencies, the voltage fluctuation across capacitors 714 and 716 is small or nonexistent. Therefore, at low frequencies, capacitors 706, 714, and 716 act as open circuits, maintaining a high input impedance. However, at higher frequencies, the low-pass filtering functionality of block 10 reduces the feedback from the low-frequency feedback circuit 1600 of block 10.
[0080]
[0170] Specifically, the combination of capacitor 1666 and resistor 1693 at the inverting input to operational amplifier 1606 filters out high frequencies. The output of this circuit no longer tracks the input, keeping Shield 1 728 (which is also the reference node of RF filter 702) at a constant level with respect to high-frequency signals. This allows the passive RLC network 706, 708, 710, 712, 714, 716 of RF filter 702 to attenuate high-frequency signals.
[0081]
[0171] Specifically, block 10, the low-frequency feedback circuit 1600 (see also Figures 4, 420a and 420b), acquires the buffered signal from block 3, the buffer circuit (see Figures 4, 406a and 406b), and generates a corrected signal for Shield 1 728 in Figure 7, i.e., an equivalent signal of the input as a feedback signal in capacitors 706, 714, and 716 of the RF filter 702 in block 2 (see Figures 4, 404a and 404b). This feedback to capacitors 706, 714, and 716 is provided as a dynamic current source for the circuit.
[0082]
[0172] The RF filters 702 in blocks 2 404a and 404b are effective for filtering at high frequencies, but become ineffective at low frequencies when receiving feedback from the low-frequency feedback circuit 1600 in blocks 10 420a and 420b. At high frequencies, capacitors 706, 714, and 716 in the RF filter 702 function as shunt capacitors that effectively short-circuit the signal at RF frequencies. The impedance of capacitors 706, 714, and 716 decreases linearly with increasing frequency. The low-frequency feedback circuit 1600 does not affect the EP system at high frequencies.
[0083]
[0173] At low frequencies, the low-frequency feedback correction signal, specifically Shield1 728 from block 10 (see Figure 16) to block 11 (shield drive 730 in Figure 7), drives the lower plates of capacitors 706, 714, and 716 so that they mimic the input signal. This controls the reference node of the RF filter 702. Specifically, the voltages at the plates of capacitors 706, 714, and 716 change synchronously with each other, and the low-frequency feedback circuit 1600 drives the lower plates of capacitors 706, 714, and 716 of the RF filter 702 to have the same voltage as the upper plates, so that the voltage difference between the plates of capacitors 706, 714, and 716 becomes zero, causing capacitors 706, 714, and 716 to act as open circuits.
[0084]
[0174] The purpose of the low-frequency feedback is to make the difference between Shield1 728 and Buf1 1602 zero, so that Shield1 728 is equal to Buf1 1602. When this happens, the input capacitance can be eliminated. At high frequencies, the positive feedback from operational amplifier 1606 is reduced to zero. Furthermore, at high frequencies, capacitor 722 (for example, 30 times larger than other capacitors in the circuit) acts as a short circuit between Shield1 728 and ground. This causes RF filter 702 With the reference node effectively grounded, the RF filter 702 completely attenuates the RF frequency. Thus, the low-frequency feedback circuit 1600 in block 10 works in conjunction with the unique configuration of the elements of the RF filter 702 in block 2 to eliminate the load effect of the RF filter 702 before passing the signal to the instrumentation amplifier 1001 in block 5.
[0085]
[0175] Thus, the instrumentation amplifier 1001 can adjust the cardiac signal without the ablation signal overlapping. As a result, the input to the entire circuit at low frequencies still has a very high input impedance (e.g., several tens of M ohms), which is advantageous for visualizing high-fidelity cardiac signals in an EP environment. Furthermore, block 10 is a symmetric (e.g., mirror image) circuit, and therefore common-mode noise is reduced as the signal propagates through the circuit. Another advantage of the low-frequency feedback circuit 1600 is that its output Shield 1 728 can be used to drive the outer shield of the input cable, for example, at OutS1 of the shield drive 730 in Figure 7.
[0086] Shielded drive circuit
[0176] Block 11 (see Figures 4, 422a and 422b), specifically the shield drive 730 shown in Figure 7, receives the output of the low-frequency feedback circuit 1600 (Shield1 728 in Figure 16) of Block 10 (see Figures 4, 420a and 420b), providing positive feedback to the cable shield at OutS1, and thus reducing the effective input capacitance of the input cable. Therefore, the path from the lower plates of the input capacitors 714 and 716 in the RF filter 702 of Block 2 (see Figures 4, 404a and 404b) to the shield of the input cable further contributes to maximizing the input impedance. This high input impedance minimizes input loss of the target heart signal. In some embodiments, the shield drive connection is grounded when the shield drive is not desired.
[0087] Signal buffering and DC blocking circuits
[0177] Block 3 (Figure 4, 406a and 406b) is a low-noise unity-gain driver that helps minimize input loss of the cardiac signal. Specifically, Block 3 can minimize the load on the input stage to the cardiac signal and provide a high input impedance to drive the signal amplification stage 532. In Block 3, two operational amplifiers (circuits not shown) form two buffers that act as unity-gain infrasors, buffering the input and providing a high input impedance to the input.
[0088]
[0178] Block 4, or DC block (Figure 4, 408a, 408b), is a high-pass module (circuit not shown) that prevents input offsets from the patient's body sensor / tissue interface from entering the amplifier gain stage. In block 4, two DC blocking capacitors (not shown) ensure that the input is not affected by large offsets from the catheter.
[0089] Cardiac amplification stage
[0179] The signal amplification stage 532 of the EP system (see Figure 5B) includes differential circuits, namely, block 5 - instrumentation amplifier / filter 410, block 6 - differential amplifier 1 / filter 412, block 7 - differential amplifier 2 / filter 414, and block 9 - large signal detection / fast recovery circuit 418. These circuits will be described in more detail in the following paragraphs.
[0090] Instrumentation amplifier / filter circuit
[0180] Block 5 (see Figure 4, 410) is for amplification of differential signals and unwanted signals from the equipment laboratory or medical environment, specifically power line noise and associated harmonics. This is an instrumentation amplifier / filter that provides monmode rejection. Block 5, detailed in Figure 10, has a gain stage 1001 with a differential gain of approximately 20 at its output and provides further filtering of RF attenuation through its RC network 1008, 1010, 1012, 1014. For example, two operational amplifiers 1006, 1016 are low-noise devices designed to receive the heart signal at the input to instrumentation amplifier 1001 before the heart signal is amplified. The differential signal from instrumentation amplifier 1001 in block 5 then enters the precision resistor block 1018 of differential amplifier 1017 in block 6.
[0091] Differential amplifier / filter circuit
[0181] Block 6 (see Figure 4, 412) has a differential amplifier 1020 that generates a fully differential output with unity gain, referenced to the common-mode voltage. The differential amplifier 1017 in Block 6 can provide further filtering against RF attenuation. Maintaining a fully differential signal path helps reduce noise from the digital portion of the system. This noise primarily appears as common-mode noise and is removed. This part of the signal amplification stage 532 also shifts the DC bias of the heart signal from 0 to 2.5V and limits its output to 0 to 5V.
[0092]
[0182] At the output of block 6, which has a first fully differential amplifier 1020 referenced to the common mode, the common mode level is set to 2.5V when the signal enters the block 7 differential amplifier 2 1021. This circuit continues low-pass filtering of the ablation signal to the outputs of block 7 (B2OutP, B2OutN). Block 7, which has a second fully differential amplifier 1034 similar to the differential amplifier 1020 of block 6, has a gain of approximately 0.5, and further filtering for RF attenuation is provided by circuit elements 1022, 1024, 1026, 1028, 1030, 1032, 1036, 1038, 1040, 1042. This part of the signal amplification stage 532 maintains that the fully differential signal path continues to remove noise.
[0093]
[0183] The gain introduced by block 7 allows the circuit to clip signals to the input limit of an A / D converter, i.e., block 8 (see Figure 4, 416), which may be, for example, a delta-sigma converter (not shown). As described above, the block 6 differential amplifier 1 1017 clips each output signal to ±2.5 volts for a bias level of 2.5 volts. With a gain of 0.5, the output of the block 7 differential amplifier 2 1021 generates biased signals at 2.5 volts in a range of ±1.25 volts for each output, or at a peak-to-peak differential voltage of 2.5 volts. In some embodiments, this represents, for example, the limit of a 24-bit A / D converter 416. By clipping and matching the output limit, the input to the A / D converter 416 is prevented from being overdriven. Since a delta-sigma converter can behave at an unstable point when overdriven, potentially resulting in spurious consequences, it is advantageous that this embodiment allows but does not exceed the full range of inputs to the A / D converter.
[0094]
[0184] The total gain of the signal amplification stage 532 of the disclosed EP system can be, for example, 20 or less in some embodiments, or 50 or less in other embodiments. For example, in some embodiments, a system gain of about 10 at the input of the A / D converter 416 is generated by a gain of about 20 at the output of the instrumentation amplifier 1001, a unity gain at the output of the differential amplifier 1 1017, and a gain of about 0.5 at the output of the differential amplifier 2 1021. Generally, the signal amplification stage 532 may include an instrumentation amplifier 1001 with a gain greater than 1 at its output, a differential amplifier 1 1017 with a gain of about 1 at its output, and a differential amplifier 2 1021 with a gain of less than 1 at its output.
[0095]
[0185] The overall system's performance improves due to the system's ability to eliminate noise. The increased gain provides further improvements compared to conventional systems. Conventional systems with 16-bit A / D converters require high gain to visualize small signals that become obscured in the presence of higher amplitude signals. Conventional systems can have gains of up to 5000, for example, leading to rapid signal saturation. Furthermore, when lower gains are used with 16-bit converters, quantization noise can negatively impact the output. The disclosed system, coupled with a 24-bit A / D converter and having a low gain of approximately 10, prevents saturation and avoids quantization noise, for example, with small signal inputs of at least 250mV.
[0096] High-signal detection / high-speed recovery circuit
[0186] The output from the differential amplifier 1 1017 in block 6 is passed to the differential amplifier 2 1021 in block 7, as well as to block 9 (see Figures 4, 418 and 10), namely the large signal detection / fast recovery circuit 1100 in Figure 11. The large signal detection / fast recovery circuit 1100 can remove large signals and recover quickly from large transient events. Therefore, this circuit is called a "fast recovery" circuit because it improves the ability to recover from saturation much faster than previously achieved.
[0097]
[0187] Specifically, the large signal detection / fast recovery circuit 1100 can detect when the differential input signal exceeds a duration of at least 10 milliseconds, for example, 100 mV, which is identified as an abnormal operating range. When this condition is detected, the large signal detection / fast recovery circuit 1100 can reduce the time constant after block 4DC blocking stage (see Figure 4, 408a and 408b) to ensure that the heart signal does not remain saturated. However, the large signal detection / fast recovery circuit 1100 has only a minimal effect under normal operation and cannot have any effect on fast transient events caused by pacing, which may be signals to be monitored and recorded in an EP environment and which generally have transient events lasting less than 10 milliseconds.
[0098]
[0188] In one embodiment, the first stage of the large signal detection / fast recovery circuit 1100 includes, for example, two operational amplifiers 1108 and 1112. The gain of operational amplifier 1108 (for example, about 40) determines the activation threshold, i.e., the signal amplitude at which the large signal detection / fast recovery circuit 1100 can act to limit (or "soft clamp") the signal. This activation threshold determines how large the signal must be before the large signal detection / fast recovery circuit 1100 becomes active and begins pulling the voltage towards common-mode levels at nodes In14 and In24. For example, an operational amplifier 1108 with a gain of approximately 80 can activate the large signal detection / fast recovery circuit 1100 at approximately 50 mV, an operational amplifier 1108 with a gain of approximately 40 can activate the large signal detection / fast recovery circuit 1100 at approximately 100 mV, and an operational amplifier 1108 with a gain of approximately 20 can activate the large signal detection / fast recovery circuit 1100 at approximately 200 mV. When the signal amplitude reaches a set amplitude level determined by the gain, the voltage becomes sufficient to exceed the activation threshold of the first pair of diode stages 1114, 1116 in order to activate the large signal detection / fast recovery circuit 1100.
[0099]
[0189] The operational amplifier 1112 generates unity gain to buffer the common-mode (CM) signal, which provides a common-mode reference to the signal through the operational amplifier 1108. The operational amplifier 1108 receives the U4Out1 and U4Out2 signals from block 6 (see Figure 10). Therefore, the average of the U4Out1 and U4Out2 signals is referenced to the common-mode node (CMB in Figure 11). The signal output from the operational amplifier 1108 passes through the first pair of diode stages 1114, 1116, which limit the charge of the subsequent capacitors 1120, 1124, 1128, and 1132. These capacitors 1120, 1124, 1128, and 1132, which store charge from the inverted U4Out1 and U4Out2 signals, generate maximum positive (+) and maximum negative (-) charges for both the inverted and non-inverted versions of the signals U4Out1 and U4Out2.
[0100]
[0190] Capacitors 1120, 1124, 1128, and 1132, together with resistors 1118, 1122, 1126, and 1130, form an RC network at nodes C, D, E, and F, which together serve as a timing network that determines the time constant. The time constant determines how long the signal can remain at its maximum amplitude before the large signal detection / fast return circuit 1100 pulls the voltage toward CM at nodes In14 and In24. This RC network will hereafter be referred to as the "timing bank" 1158. Some embodiments of the timing bank 1158 can be designed to generate a time constant of, for example, at least 10 milliseconds, to prevent activation of the large signal detection / fast return circuit 1100 during pacing signals with durations of, for example, 2 milliseconds to 10 milliseconds. Other embodiments can be designed to generate a time constant of at least 5 milliseconds.
[0101]
[0191] When capacitors 1120, 1124, 1128, and 1132 are charged, a difference is detected, and the signal passes through a second pair of diode stages 1146, 1148, which limits (or "soft-clamps") the input to, for example, approximately ±100mV. This prevents the system from saturating for any significant amount of time (e.g., less than 100 milliseconds). The second pair of diode stages 1146, 1148 also ensure that there is no interaction between the large signal detection / fast recovery circuit 1100 and the EP system when the signal is not large / long enough to require limiting. In other words, if the large signal detection / fast recovery circuit 1100 is not beneficial, the second pair of diode stages 1146, 1148 disconnects the large signal detection / fast recovery circuit 1100. Block 9, the large signal detection / fast recovery circuit 1100, ensures that the EP system is not affected by large signal spikes, enabling a steady-state response when, for example, the operational amplifier 1108 has a gain of approximately 40 and the difference between the inverted U4Out1 signal and the non-inverted U4Out2 signal is, for example, approximately 100mV.
[0102]
[0192] Block 9, the large signal detection / fast recovery circuit 1100, is located where large signal voltage offsets are to be removed in the EP system. Those skilled in the art will understand that the large signal detection / fast recovery circuit 1100 can be located elsewhere in the EP system where possible large signal spikes may occur and are undesirable. Those skilled in the art will also understand that electronic components such as capacitors 1120, 1124, 1128, 1132 and resistors 1118, 1122, 1126, 1130 of the timing bank 1158 can be replaced within the large signal detection / fast recovery circuit 1100 to change the circuit activation level and time. As those skilled in the art will understand, the large signal detection / fast recovery circuit 1100 can be used in various embodiments of other signal acquisition and processing systems to remove large signal voltage offsets from other types of electrical signals.
[0103]
[0193] In some embodiments, the outputs In14 and In24 of the block 9 big signal detection / fast recovery circuit 1100 (see Figure 4, 418) are fed back to block 4, i.e., the DC block (Figure 4, 408a and 408b). A DC blocking capacitor (not shown) in block 4 adds further bias (e.g., a compensatory bias) to the input signal. Therefore, the signal from block 9 big signal detection / fast recovery circuit 1100 is not fed back to block 4 DC block unless the signal supplied to block 9 is large (e.g., has an amplitude of 100mV or more). In other words, unless a big signal event occurs, the output signal of block 9 does not enter block 4. In24 is normally disconnected.
[0104]
[0194] An exemplary embodiment of the large-signal detection / fast-recovery circuit 1100 shown in Figure 11 will be described in detail with respect to the signal plots in Figures 12, 13A-13C, 14A-14D, and 15A and 15B. A sample signal is applied to the input of the EP system, and this sample signal will be described at various points throughout the circuit. In this example, the signal used to demonstrate the large-signal detection / fast-recovery circuit 1100 is generated by applying a 20mVpp signal at node In12 in Figures 6A and 7, and applying a zero input at node In22 (a symmetrical negative node, not shown), specifically at the input of the RF filter 702. At 10 msec, a 200mV step is added to the signal at node In12. This becomes a 200mV differential signal as it traverses the EP system, which may cause the signal to be outside the display range of most conventional monitoring devices. Such 200mV signals should generally be removed so that the signal can be seen in the EP environment.
[0105]
[0195] Figure 12 shows what happens to such input signals when the large signal detection / fast recovery circuit 1100 is not connected. If a sample input 20mVpp signal with an undesirable 200mV step-up passes through the analog input protection / filtering stage 530, instrumentation amplifier 1001, and differential amplifier 1017 to reach the large signal detection / fast recovery circuit 1100, and then the large signal detection / fast recovery circuit 1100 is not connected, the EP hardware system cannot recover quickly from the 200mV step signal. This slow recovery complicates the identification of the cardiac signal.
[0106]
[0196] The resistors 1002 and 1004 located before the instrumentation amplifier 1001 in Figure 10 eventually pull the offset signal back to ground level, but the product of the DC blocking capacitor (not shown) in block 4 and resistor 1002 generates a time constant of approximately 2.7 seconds. This introduced delay is too long to recover off-screen or saturated signals. Figure 12 shows that the signal at input node In14 moves only slightly downward at approximately 100 msec and only a few millivolts at approximately 400 msec (not shown). Such large transient signals can negatively impact the operation of the EP system without a large signal detection / fast recovery circuit 1100, because large transient events push the monitored signal to a saturated state, resulting in a loss of waveform detail in the signal.
[0107]
[0197] Figures 13A to 13C show the same 200mV large transient signal when using the connected large signal detection / fast recovery circuit 1100. In this example, as shown in Figures 13A and 13B, both input nodes of the large signal detection / fast recovery circuit 1100, namely In14 and In24 (shown in Figure 11), are pulled (forced) toward a common-mode signal V(CMB) (see Figure 13C) with an amplitude of approximately 100mV. In14, i.e., the positive input node of the large signal detection / fast recovery circuit 1100, is pulled down, and In24, i.e., the negative input node of the large signal detection / fast recovery circuit 1100, is pulled up. V(CMB) is the average of the voltages at nodes In14 and In22 (symmetrical negative input to the entire circuit). The desired bias level is applied directly to the differential amplifiers in blocks 6 and 7 (1020 and 1034, respectively), thereby setting the common-mode voltage in those differential amplifiers 1020 and 1034, so that the actual common-mode levels at nodes In14 and In24 do not have any effect.
[0108]
[0198] The plots in Figures 13A and 13B show that the voltages at nodes In14 and In24 are drawn into the monitoring range after approximately 50 milliseconds. Thus, the limiting or "soft clamping" is performed gradually, avoiding discontinuities in signal acquisition and visualization. Other embodiments may allow for gradual "clamping" over approximately 100 milliseconds. Cut.
[0109]
[0199] Figures 14A to 14D demonstrate how a large transient signal is adjusted as it traverses various internal nodes of the large signal detection / fast recovery circuit 1100. Signal plot V(A) in Figure 14A and signal plot(B) in Figure 14B represent the output of the operational amplifier 1108 of the large signal detection / fast recovery circuit 1100 in Figure 11. In this example, the operational amplifier 1108 has a gain of approximately 40 for the input and generates a differential signal of (40 × 200 mV =) 8 volts across nodes A and B in Figure 11.
[0110]
[0200] As shown in plot V(C) of Figure 14C, following node B in Figure 11, the negative signal pulls the voltage down at node C in Figure 11. Here, the signal is filtered to remove the in-band signal generated at node B, leaving a low-frequency control voltage at node C. The negative voltage at node C is connected to In14 through resistor 1140, diode 1150, and resistor 1144. This generates a current that pulls In14 down toward the common-mode voltage as shown in Figure 13A. Similarly, as shown in plot V(E) of Figure 14D, node A pulls In24 toward the common-mode voltage through nodes E and J in Figure 11.
[0111]
[0201] The diodes in the large signal detection / fast recovery circuit 1100 in Figure 11 control the direction of the current. The first pair of diodes in the diode stage, 1114, 1116 (limiting diodes), allow for different time constants to charge and discharge nodes C, D, E, and F. They also provide a non-operating range where nodes C, D, E, and F are not charged when outputs A and B are less than the diode forward voltage drop. The "clamping" diodes 1150, 1152, 1154, 1156 in the second pair of diodes in the diode stage, 1146, 1148, ensure that input nodes In14 and In24 are pulled in the correct direction.
[0112]
[0202] Figures 15A and 15B show signal plots of the current through resistors 1144 and 1142 at outputs In14 and In24, respectively, of the large signal detection / fast recovery circuit 1100 in Figure 11. Under normal operation, the current is 0, and the instrumentation amplifier / filter 410 circuit is unaffected. If the differential level is too high (i.e., a large signal exceeding 100mV is detected for several milliseconds, for example), the current through those two resistors 1144 and 1142 helps pull the signal back towards the common-mode voltage V (CMB).
[0113] A / D converter
[0203] The A / D converter 416, i.e., block 8 (see Figure 4), is a fully differential A / D converter designed to accept differential signals from the rest of the circuit. In some embodiments, each of the EP system circuit modules is duplicated eight times to be supplied as differential pairs within eight separate channels of the A / D converter 416. For example, a TI ADS1278 24-bit, 8-channel delta-sigma converter can be used. Those skilled in the art may choose other A / D converters with similar specifications.
[0114]
[0204] In some embodiments, the A / D converter 416 is highly linear and exhibits the characteristics of a delta-sigma converter. This high linearity allows for precise digital signal processing in software, as will be discussed later. This configuration minimizes hardware filtering, which is advantageous for RF attenuation and anti-aliasing, and allows for greater flexibility in software filtering and signal processing. The advantage of choosing a fully differential A / D converter is that common-mode noise signals from any digital circuitry (e.g., digital clock signals) are removed.
[0115] Wilson coupled electrode-right bundle branch drive (WCT-RLD) circuit
[0205] The input common-mode signal can be of any frequency, but the dominant signal is generally the power line frequency of 60 Hz in the United States, for example. In conventional EP environments, ECG (and similar) equipment mitigates a large amount of 60 Hz noise, which can be up to 100 times louder than the signal under consideration. Furthermore, distortion in the power line signal often results in a strong third harmonic at 180 Hz, which is generally the most noise-covering harmonic. Higher harmonics and other common-mode signals are generally smaller and / or above the target frequency band relative to the ECG and IC signals.
[0116]
[0206] In some embodiments, a Wilson coupled electrode-right bundle branch drive (WCT-RLD) circuit is used to eliminate noise, particularly at 60 Hz and 180 Hz, by common-mode rejection, i.e., by enhancing the first and third harmonics of the power line signal and selectively supplying those signals back to the patient to cancel them out. Figure 23 shows schematic diagrams of improved WCT-RLD circuits according to some embodiments.
[0117]
[0207] For example, the WCT circuit 2332 in Figure 23 provides a virtual ground by summing and averaging two or three limb electrodes (e.g., right arm 2304 and left arm 2306, or right arm 2304, left arm 2306 and left leg 2308) connected to a coupling electrode (center electrode) 2336 through two or three large resistors 2334 (e.g., 20 kilohms at each electrode). Those skilled in the art will understand that the average of the right arm (RA) 2304, left arm (LA) 2306 and left leg 2308 provides a more accurate estimate of the common-mode signal in patient 2302 than the average of the right arm (RA) 2304 and left arm (LA) 2306. As those skilled in the art will understand, the RA and LA signals are, alternatively, buffered (see buffer 2312) versions of the RL positive (RLP) signal 2338 and RL negative (RLN) signal 2340. WCTs are conventionally designed to reduce the overall 60Hz common-mode noise signal by bringing the net potential difference of these limb dielectrics close to zero.
[0118]
[0208] By applying an active current to the WCT circuit 2332 via the right bundle branch, i.e., the "right bundle branch drive" (RLD) circuit 2330, the patient 2302 can be driven to the same voltage as the common amplifier, and thus the common-mode voltage at the inputs of the ECG electrodes (LA, RA, LL and V1-V6) is reduced. This can be done by generating an inverted common-mode signal and applying it as the output to the right bundle branch. Specifically, the right bundle branch drive is represented by the limb electrode RL. Through the RL electrode, the patient 2302 receives the RLD output 2310, i.e., a summed and inverted version of other IC catheter signals or ECG electrode signals, which neutralizes interference present in the patient's body. This, combined with the common-mode rejection characteristics of the signal amplification stage 532, can reduce common-mode low-frequency interference to an acceptable level (for example, as specified by the standard IEC60601-2-25).
[0119]
[0209] However, since 60Hz and 180Hz noise are not equal in all parts of the body, common-mode rejection alone cannot eliminate all noise. The WCT-RLD circuit 2300 in Figure 23 provides a reference signal that is approximately equal to the power line frequency entering the system, thereby further reducing the overall common-mode signal. Therefore, the combination of the disclosed WCT-RLD circuit 2300 and conventional common-mode rejection advantageously improves the reduction of the common-mode signal.
[0120]
[0210] In exemplary embodiments using WCT, the WCT input in the EP system can provide the block 3 buffer circuit (see Figures 4, 406a and 406b) with an optional unipolar input to replace the bipolar positive (+) or negative (-) catheter input. Specifically, the WCT-RLD circuit 2300 is located in the right arm 2304, left arm 2306, and left leg 2308. The electrode signals are averaged. The result is buffered by operational amplifier 2314, and the output WCTBuf 2316 is transmitted as a unipolar feedback signal whenever desired in the EP system, which is specifically used in the embodiment whenever a patient is connected. The WCT-RLD disclosed herein enhances conventional unipolar WCT solutions by a novel method for generating the RLD signal.
[0121]
[0211] In some embodiments, a novel approach in the WCT-RLD circuit 2300 is to provide an additional filter circuit, referred to as a "Twin-T" feedback network 2440 (see Figures 23 and 24), which can generate a stronger RLD at a power line frequency of 60 Hz or a third harmonic frequency of 180 Hz. This is particularly useful during ablation. The Twin-T feedback network 2440 resonates at both 60 Hz and 180 Hz, but advantageously prevents phase oscillation by reducing feedback at other frequencies.
[0122]
[0212] Figure 24 shows a schematic diagram of a Twin-T type feedback network 2440 interfaced with the RLD circuit 2330 of the WCT-RLD circuit 2300, according to several embodiments. The Twin-T type feedback network 2440 in Figure 24 functions as an improved notch filter. Resistors 2406, 2407, 2408, 2409, 2410, 2411 and capacitors 2401, 2402, 2403, 2404 form a single Twin-T type network that generates a notch at 60 Hz. The next stage, i.e., resistors 2412, 2413, 2414, 2417, 2418, 2419 and capacitors 2415, 2416, 2420, 2421 similarly generates a notch at 180 Hz. However, when the network is in the operational amplifier feedback path, the inverse function is obtained.
[0123]
[0213] For example, as shown in plot 2500 in Figure 25, the RLD output of the Twin-T type feedback network 2440 in the operational amplifier 2425 generates two peaks, namely peak 2510 at 60 Hz and peak 2520 at 180 Hz. At higher frequencies, such as above 10 kHz, the phase shift approaches zero. This prevents the phase shift of the RLD circuit 2330 at these higher frequencies, which could lead to oscillation. This minimal phase shift at these higher frequencies prevents oscillation near the ablation frequency, which is inherently more difficult to remove by filtering.
[0124]
[0214] Twin-T type circuits are used in electronic design, but previously they were not used in WCT-RLD circuits as disclosed herein. The twin-T type feedback network 2440 removes power line signals that would conventionally be passed by known circuits when generating an RLD signal, so that the power line signals do not affect the phase response at higher frequencies. Therefore, the twin-T type feedback network 2440 has advantageous applications for generating an RLD signal from electrode induction.
[0125]
[0215] In the embodiment shown in Figure 23, the RLD circuit 2330 tracks the power line by supplying the RLD output 2310 to the patient 2302 as a separate signal. In this circuit, the differential input signals of the right bundle branch positive (RLP) 2338 and the right bundle branch negative (RLN) 2340, which may alternatively be the RA and LA signals, are buffered 2312. The Twin-T type feedback network 2440 then enhances / amplifies the buffered right bundle branch signal at 60 Hz and 180 Hz, and this signal is inverted and buffered again by the RLD circuit 2330. The RLD circuit 2330 includes an operational amplifier 2328, resistors 2320, 2324, 2326 and capacitors 2318, 2322. After passing through the RLD circuit 2330, the signal is RLD in the body surface leads of the patient's right bundle branch. The output is 2310 (RLDrv). This effect means that the entire circuit tracks the power lines, and the common mode of the circuit removes power line noise. Furthermore, the right bundle branch drive circuit protects against any signal greater than approximately 1 microampere returning to the patient.
[0126]
[0216] In some embodiments, by using the first derivatives of both unipolar signals, a physician can determine whether the signal of a subject originates from the distal or proximal electrode. The bipolar signal can be displayed in a color-coded format to identify which component of the bipolar signal originates from the cathode and which component originates from the anode. The physician can then move to the proximal electrode if the primary signal of the subject originates from that electrode. The system can also be automated with a robotic system that provides movement as part of a closed feedback loop.
[0127] Case study
[0217] The following examples demonstrate how the disclosed hardware circuit configurations enable improved cardiac monitoring during procedures that introduce signals found in an EP environment, between equipment and ambient noise, and that could potentially introduce significant interference into the monitoring environment.
[0128] Signal Example 1 - Common-mode 60Hz and in-band 500Hz differential signals
[0218] Signal Example 1 presents a typical common-mode 60Hz noise signal containing an in-band (less than 1000Hz) differential signal, as found in conventional IC induction. This example shows an example signal plot representing the signals at an exemplary node of the disclosed circuit. The circuit amplifies the differential signal and removes the common-mode signal.
[0129]
[0219] Figures 17A and 17B show the input signals for a 2Vpp 60Hz sine (power line) signal applied to input nodes In12 (see Figure 6A) and In22 (negative, downward branch of the circuit, not shown), respectively. A 0.2Vpp, 500Hz sine wave signal is superimposed on In12 (see plot V(In12) in Figure 17A), and a -0.2V, 500Hz sine wave signal is superimposed on In22 (see plot V(In22) in Figure 17B). This results in a 2Vpp, 60Hz common-mode signal and a 0.4V, 500Hz differential signal. These signals may be too low in frequency to be affected by the RF filter 702 in block 2, so the same signals appear at the output of block 3 (buffers 406a, 406b) and after block 4 (DC blocks 408a, 408b).
[0130]
[0220] Figures 17C and 17D show shield input signals (Shield1, Shield2), which are the same as the corresponding input signals shown in Figures 17A and 17B. These signals are fed back from block 10 (low-frequency feedback circuit 1600) to the RF filter 702, removing the load from the RF filter 702 (Shield1 in Figure 7). See 728. Shield 2, i.e., the negative downward branch of the circuit, is not shown. The voltage changes at capacitors 714, 716, and 706 of the upper branch of the RF filter 702 in Figure 7, along with the corresponding capacitors (not shown) of the symmetrical downward branch of the RF filter, are close to zero and effectively remove them from the circuit at low frequencies.
[0131]
[0221] Figures 18A and 18B show the outputs of block 5 (instrumentation amplifier 1001 in Figure 10), Out1 and Out2, respectively, with a differential gain of 20. The common-mode signal has a gain of 1, and the differential signal has a gain of 20. At this point, the signals at each output are 2Vpp, 60Hz sine waves, with a 4Vpp, 500Hz signal superimposed at Out1 (see Figure 18A), and a -4Vpp, 500Hz signal superimposed at Out2 (see Figure 18B). (Reference), it produces an 8Vpp differential signal.
[0132]
[0222] Figures 18C and 18D show the outputs B2OutP and B2OutN of Figure 10, respectively. At B2OutP and B2OutN, the signals pass through the fully differential operational amplifiers (blocks 6 and 7, 1017, and 1021) of Figure 10, eliminating common-mode signals and setting the common-mode output voltage and output reference to VOCM (2.5V bias level). The gain of 0.5 in amplifier 1034 of block 7 results in the final pair of a 2Vpp 500Hz signal at B2OutP (see Figure 18C) and -2Vpp at B2OutN (see Figure 18D), which is equivalent to a 4Vpp differential 500Hz signal. From input to output, the common-mode gain is 0 and the differential gain is 10. Thus, common-mode signals can be eliminated through the coupled response of the instrumentation amplifier (block 5) and the fully differential operational amplifiers (blocks 6 and 7).
[0133] Signal Example 2 - 500kHz Ablation Signal
[0223] Signal Example 2 presents a typical 500 kHz ablation signal applied to the EP system input as cardiac monitoring continues during the ablation procedure. Unwanted ablation signals are filtered and attenuated before reaching the A / D converter of the disclosed circuit (see Figure 4, Block 8, 416).
[0134]
[0224] As shown in Figures 19A and 19B, the ablation signal inputs are a 0.2Vpp, 500kHz sine wave applied to In12 (Figure 19A) and a -0.2Vpp, 500kHz sine wave applied to In22 (Figure 19B). This results in a 0.4V, 500kHz differential signal. This signal is in the frequency range that should be attenuated by the RF filter 702 in block 2 (Figures 4, 404a and 404b).
[0135]
[0225] Figures 19C and 19D show plots of the output of RF filter 702 (block 2) In13 (and the output of the symmetrically downward-branched RF filter In23) when the circuit receives an ablation signal. Plots V(In13) in Figure 19C and V(In23) in Figure 19D are shown on the same scale as the input. It can be seen that the signal is attenuated to a few millivolts.
[0136]
[0226] The plots of V(Shield1) and V(Shield2) shown in Figures 20A and 20B, respectively, demonstrate that the same signal across the shield input (see, for example, Shield1 in Figure 7) is also significantly attenuated, showing that the RF filter can attenuate the 500 kHz ablation signal by effectively grounding the lower plates of capacitors 714, 716, and 706 of the upper branch of the RF filter 702 in Figure 7, and the corresponding capacitors (not shown) of the symmetrical lower branch of the RF filter.
[0137]
[0227] Figures 21A and 21B show plots of signals V(Out1) and V(Out2) at the output of block 5 (instrumentation amplifier 1001 in Figure 10) with a gain of 20. The remaining 500kHz signal passes through this 20x gain stage, but filtering in this stage (from capacitors 1010 and 1012) limits the gain at 500kHz to approximately 1x.
[0138]
[0228] As shown in Figures 21C and 21D, the consecutive fully differential operational amplifiers 1017 and 1021 (and their negative downward branch circuit equivalents) in blocks 6 and 7 of Figure 10 continue filtering the 500 kHz signal until it is less than 0.5 mV at B2OutP (Figure 21C) and B2OutN (Figure 21D). The remaining signal is removed by a filter in block 8 A / D converter (see Figure 4, 416), which provides a 100 dB attenuation above 1000 Hz. Thus, the ablation signal is removed by the RF filter (block (2) It is eliminated through the combined response of the instrumentation amplifier (block 5) and the fully differential operational amplifiers (blocks 6 and 7).
[0139] Hardware / Software Interface
[0229] Figure 5A shows the relationship between the hardware and software of the disclosed EP recording system in several embodiments. The main system unit (MSU) 504 includes the hardware circuitry of the EP recording system. In Figure 5A, the ECG board 506, including the WCT 507, corresponds to the ECG boards 302 and 314 shown in Figure 3 (for cross-reference, the digital signal outputs of ECG boards 302 and 506 are V1-V6 310 and I-II 312). Similarly, the IC board 508 corresponds to the IC board 316 in Figure 3 (for cross-reference, the digital signal outputs IC1...ICN of IC boards 316 and 508 are ICUniWCT1-ICUniWCT2 326, ICUniINDIF1-ICUniINDIF2 328 and ICDiff1...ICDiffN 330). A communication module 510 and an optical fiber link 512 are provided to communicate the digital signal outputs from the ECG board 506 and IC board 508 to the software of the main processing unit (MPU) 514.
[0140]
[0230] According to some embodiments, the communication module 510 of the MSU 504 transmits independent digital signals from A / D converters 416 and 534 of the ECG board 506 and IC board 508 to the MPU 514 via the optical fiber link 512 for digital signal processing. The communication module 510 samples the output channels from the A / D converters 416 and 534, converts them to serial format, and transmits the data via the optical fiber link 512. The signals are converted back to parallel format at the receiving end of the optical fiber link 512 in the MPU 514.
[0141]
[0231] In this specification, ECG boards 302, 506 and IC boards 316, 508 are referred to by these names for convenience. As will be understood by those skilled in the art, the circuits of ECG boards 302, 506 and IC boards 316, 508 can accept other physiological signals from various types of electrodes other than ECG electrodes and IC electrodes.
[0142] Description of EP recording system software
[0232] This specification provides embodiments of systems, apparatus, devices, methods and / or computer program products, and / or combinations and subcombinations thereof, for processing and displaying multiple signals in near real-time. For example, embodiments may include processing and displaying multiple biomedical signals (e.g., EP signals) in near real-time. Before describing further details of these embodiments, a brief overview of digital signal processing is provided.
[0143]
[0233] In summary, digital signal processing involves the use of digital processing to identify specific features in a signal, or to generate a signal of higher quality than the original signal (for example, by removing noise from the signal). Digital signal processing can be performed on digitized electrocardiogram (ECG) signals or intracardiac (IC) signals that represent the electrical activity of the heart over a period of time.
[0144]
[0234] In order to perform digital signal processing on an analog signal, it is necessary to convert the analog signal into a digital format. As is well known to those skilled in the art, an analog-to-digital (AD) converter such as the A / D converter 416 can convert an analog signal into a digital signal.
[0145]
[0235] Digital signal processing uses digital signal processing functions to process signal samples of a given signal. This may include applying it to one or more signal samples in a signal. Digital signal processing functions may be sequences of mathematical operations and computational algorithms. Digital signal processing functions can, for example, measure, filter, compress, or optimize signal samples.
[0146]
[0236] Digital signal processing can utilize different digital signal processing functions depending on the type of analysis and the type of signal being processed. For example, digital signal processing can use different digital signal processing functions to identify specific words in an audio signal or to remove motion blur from a video signal.
[0147]
[0237] Digital signal processing systems have many applications, including audio signal processing, audio compression, digital image processing, video compression, speech processing, speech recognition, digital communications, digital synthesizers, radar, sonar, financial signal processing, and seismology. However, conventional digital signal processing systems are often unsuitable for some applications, such as biomedical signal processing. This is because conventional digital signal processing systems, including current EP solutions, often cannot display multiple signals simultaneously in near real-time. Furthermore, conventional solutions do not allow users to dynamically apply new digital signal processing functions to a base signal. Also, conventional solutions often cannot synchronize the processing and display of multiple signals in near real-time. This is often problematic in clinical settings, as a physician's ability to make an effective clinical diagnosis may depend on comparing multiple signals at the same time. Finally, conventional EP systems using analog filters often cannot fully utilize digital signal processing. This is because the options are severely limited when functions are implemented in hardware. For example, functions cannot be removed, and therefore the full potential of digital signal processing cannot be obtained.
[0148]
[0238] The digital signal processing (DSP) disclosed herein goes further to solve the problems of these conventional systems. In addition to using multiple simultaneous DSP filters to process, time-align, and display multiple signals in near real-time, the system clarifies the operational endpoints for biomedical procedures such as ablation, making the operator's work more efficient. For example, this disclosure provides high-fidelity surface ECG signals for automating and creating averaged, delayed-potential electrocardiograms. Ablation procedures use an internal cardiac map so that the operator can visualize the cardiac tissue for ablation. Once the internal cardiac map is created, the validity of the map is determined by a percentage map of surface averaged, delayed-potential ECGs. In other words, if a complete map is created, all intracardiac signals, including delayed potentials, should, when summed, reproduce both the timing and amplitude of the averaged, delayed-potential map from the high-fidelity ECG. A score representing the validity of the map is displayed. For example, a score of 50% means that the mapping catheter has not reached the area where some of the delayed signal must be present to explain the high-fidelity averaging delayed potential map data. Following the ablation of the delayed potential, a real-time high-fidelity averaging delayed potential ECG determines whether the abnormal delayed potential has actually improved. If it has not improved, further ablation of the previously tabulated delayed potential can be performed using a delayed potential filter and a dynamic window for leads. The disclosed system provides data that directs the operator to the precise delayed potential region in the map to reduce the need for further ablation.
[0149]
[0239] Figure 26 is a block diagram of a system 2600 that processes and displays multiple signals in near real-time, according to several embodiments. System 2600 represents the MPU (software) 514 in Figure 5A and can implement the digital processing stage 528 in Figure 5B. System 2600 includes a signal path module 2602, a configuration path module 2620, and a monitoring module 2622. The signal path module 2602, the configuration path module 2620, and the monitoring module 2622 may be software modules that can be executed by one processor (or more processors), such as the processor 8504 in Figure 85. Alternatively, multiple processors can be used.
[0150]
[0240] The signal path module 2602 includes an input module 2604, a timer 2605, a packetizer 2606, a queuing module 2608, a packet dispatcher 2610, a global signal table 2612, and an output module 2616. The input module 2604, timer 2605, packetizer 2606, queuing module 2608, packet dispatcher 2610, global signal table 2612, and output module 2616 may be software modules that can be executed by one (or more) processors, such as processor 5004. The signal path module 2602 solves at least the technical problem of how to synchronize the processing and display of multiple signals in near real-time. The signal path module 2602 solves this technical problem using a novel multi-stage process, including packetization, queuing, and processing delay equalization, as described later.
[0151]
[0241] In the first stage, the input module 2604 can receive signal samples for one or more base signals. The base signals may be signals before any digital signal processing is applied. For example, the base signals may be biomedical signals such as ECG signals or IC signals. As will be understood by those skilled in the art, the base signals may be various other types of signals. The input module 2604 can receive signal samples for multiple base signals. For example, the input module 2604 can receive signal samples of an IC signal and signal samples of an ECG signal.
[0152]
[0242] The input module 2604 can receive signal samples of the base signal from hardware devices associated with the MSU (hardware) 504 in Figure 5. For example, the input module 2604 can receive signal samples from hardware devices such as the EGG board 302 or IC board 316 in Figure 3. The input module 2604 can also receive signal samples from data stored in a computer file. For example, the computer file may contain previously recorded signal samples received from hardware devices.
[0153]
[0243] The input module 2604 can receive signal samples from hardware devices via the A / D converter stage 534. For example, the input module 2604 can receive a signal sample of the base signal from the EGG board 302.
[0154]
[0244] The input module 2604 can receive signal samples of the base signal from electrodes attached to hardware devices. For example, the input module 2604 can receive signal samples from each of the eight electrodes attached to the ECG board 302. As will be understood by those skilled in the art, the input module 2604 can receive more or fewer signal samples depending on the number of hardware devices connected to the input module 2604 and the number of electrodes attached to each hardware device.
[0155]
[0245] The input module 2604 can store one or more signal samples for each base signal in a computer storage device for later analysis by the review module 2624. For example, the input module 2604 can store one or more signal samples in the main memory 8508 or the hard disk drive 8512 in Figure 85. This allows the user (for example, a physician) to redisplay one or more signal samples for each base signal after they have been collected.
[0156]
[0246] The input module 2604 can dispatch one or more signal samples for each base signal to the packetizer 2606. The packetizer 2606 can perform preprocessing on the received signal samples. The packetizer 2606 performs preprocessing on the received signal samples to ensure that the resulting signal is compatible with later stages in the signal path module 2602. As will be understood by those skilled in the art, the type of preprocessing performed by the packetizer 2606 may depend on the type of base signal. For example, the packetizer 2606 may convert the binary values of the received signal samples into their corresponding physical values, for example, to represent the base signals.
[0157]
[0247] The packetizer 2606 can preprocess the received signal samples and then store one or more signal samples of the base signal in a packet. A packet can be a consecutive sequence of N signal samples belonging to the same base signal. By storing signal samples in packets by the packetizer 2606, the signal path module 2602 can synchronize the processing and display of multiple signals in near real-time, especially in non-real-time operating systems. In other words, a packet is a unit of processing in the signal path module 2602.
[0158]
[0248] The packetizer 2606 can store one or more signal samples in a packet based on the timer 2605. The timer 2605 may be a high-resolution timer. For example, the timer 2605 may have a resolution of 1 millisecond (Microsoft Windows registered trademark). It may be a high-resolution timer. Timer 2605 can be set to an amount of time relating to receiving a certain number of signal samples (e.g., N signal samples) from a hardware device or a computer file. The certain number of signal samples may correspond to the number of signal samples that can be stored in a packet.
[0159]
[0249] The packetizer 2606 can use the timer 2605 to ensure that each packet contains the same number of signal samples. Specifically, the packetizer 2606 can set the timer 2605 to an amount of time related to receiving a given number of signal samples of the base signal. In other words, the packetizer 2606 can anticipate receiving a specific number of signal samples when the timer 2605 is triggered.
[0160]
[0250] The packetizer 2606 can start the timer 2605. Then, the packetizer 2606 can store the signal samples received from the input module 2604 into packets until the timer 2605 is triggered. The packetizer can then dispatch the packets to the queuing module 2608. Then, the packetizer 2606 can restart the timer 2605. Then, the packetizer 2606 can store a new set of signal samples received from the input module 2604 into a new packet until the timer 2605 is triggered again.
[0161]
[0251] The packetizer 2606 can assign a tag to each packet. The packetizer 2606 can assign the same tag to each packet associated with different base signals for the same period. This assignment allows the signal path module 2602 to synchronize the processing and display of packets for different base signals for the same period. The assigned tags can be used by the display module 2618 to synchronize the outputs of different signals. In other words, the display module 2618 can work with the same tag at any given time.
[0162]
[0252] The assigned tags can correspond to the period during which the signal sample in the corresponding packet was received. Specifically, the tags can correspond to the sample number of the first signal sample in the corresponding packet. For example, the packetizer 2606 can store 16 signal samples in each packet. In this case, the packetizer 2606 can store the first set of signal samples in the packet with the tag 0. The packetizer 2606 can store the second set of signal samples in the packet with the tag 15. The packetizer 2606 can store subsequent sets of signal samples in the packet with tags such as 31, 47, 64, etc. Other tag assignment conventions can be adopted, as will be understood by those skilled in the art.
[0163]
[0253] After packetization, the packetizer 2606 can store each generated packet associated with a given base signal in the queuing module 2608. The queuing module 2608 is shown in Figure 27.
[0164]
[0254] Figure 27 is a block diagram of a queuing module 2608 that stores each generated packet associated with a different base signal, according to several embodiments. The queuing module 2608 solves at least the technical problem of how to dynamically apply multiple different digital signal processing functions to the same base signal. The queuing module 2608 solves this technical problem by storing each generated packet associated with a different base signal in a separate queue that can be dynamically processed by different signaling modules 2614. Figure 27 will be described with reference to Figure 26.
[0165]
[0255] Queuing module 2608 includes one or more queues 2702. For example, in FIG. 27, queuing module 2608 includes queue 2702-1, queue 2702-2, and queue 2702-N. Each queue 2702 can be associated with a given base signal. Queue 2702 may be a queue data structure that stores elements in the order in which they are inserted. For example, the first element inserted into queue 2702 is the first element removed from queue 2702. In other words, queue 2702 is a first-in first-out (FIFO) data structure. As will be appreciated by those skilled in the art, queue 2702 may be implemented with an array, a linked list, or various other data structures.
[0166]
[0256] Packetizer 2606 can store each generated packet associated with a given base signal in the corresponding queue 2702. For example, packetizer 2606 can store generated packets associated with an IC signal in queue 2702-1, and generated packets associated with an ECG signal in queue 2702-2.
[0167]
[0257] Packetizer 2606 can store each packet in queue 2702 in the order in which they are generated. This can ensure that signal samples in generated packets are processed in the order in which they were received from a hardware device or from a computer file.
[0168]
[0258] Returning to FIG. 26, packet dispatcher 2610 can dispatch generated packets from queue 2702 of FIG. 27 to one or more signal modules 2614 in global signal table 2612 for digital signal processing. Packet dispatcher 2610 solves at least the technical problem of how to dynamically apply a plurality of different digital signal processing functions to the same base signal. Packet dispatcher 2610 solves this technical problem by dynamically dispatching generated packets associated with each base signal to one or more appropriate signal modules 2614 for digital signal processing.
[0169]
[0259] Packet dispatcher 2610 can continuously scan one or more queues 2702 in queuing module 2608. Each time packet dispatcher 2610 detects a new packet available in queue 2702 of queuing module 2608, it can retrieve the new packet from queue 2702. Then, packet dispatcher 2610 can dispatch the new packet to one or more signal modules 2614 in global signal table 2612 for digital signal processing. Packet dispatcher 2610 can dispatch the same packet to a plurality of signal modules 2614, thereby enabling simultaneous processing of a base signal using different digital signal processing functions. Furthermore, since packet dispatcher 2610 can dispatch packets from different queues 2702 to different signal modules 2614, different base signals can be processed simultaneously using different digital signal processing functions.
[0170]
[0260] The packet dispatcher 2610 can dispatch new packets from queue 2702 to one or more signaling modules 2614. The packet dispatcher 2610 can use the global signaling table 2612 to dispatch new packets to one or more signaling modules 2614. The global signaling table 2612 may be a fixed-size array. Each element of the array can be associated with a given base signal, and therefore with a given queue 2702. For example, if there are 100 base signals, the global signaling table 2612 may be a fixed-size array of 100 elements. Furthermore, for each element of the array, there may be one or more signaling modules 2614 designed to process the corresponding base signal. In some embodiments, each element of the array may be the fixed-size array itself. Each element of this subarray can be associated with a given signaling module 2614. For example, if there are 10 signaling modules 2614, this subarray may contain 10 elements. Therefore, as an example rather than an limitation, the global signal table 2612 could be a 100 x 10 array.
[0171]
[0261] The packet dispatcher 2610 can dispatch a new packet to the signaling module 2614 by examining the corresponding element in the subarray associated with the base signal of the new packet. Specifically, the packet dispatcher 2610 can determine whether the corresponding element in the subarray indicates that the signaling module 2614 is assigned to the base signal associated with the packet.
[0172]
[0262] In some embodiments, the global signal table 2612 may indicate whether a given signal module 2614 is assigned to a given base signal by storing "0" or "1" in the corresponding element in the subarray associated with that given signal module 2614. For example, the global signal table 2612 may indicate that a given signal module 2614 is not assigned to a given base signal by storing "0" in the corresponding element in the subarray. In some other embodiments, the global signal table 2612 may indicate whether a given signal module 2614 is assigned to a given base signal by storing a reference to the given signal module 2614 in the corresponding element in the subarray. As will be understood by those skilled in the art, the reference may be a memory pointer, a flag, a handle, or other type of identifier.
[0173]
[0263] The packet dispatcher 2610 can also use a lookup table to dispatch new packets to one or more signaling modules 2614. The lookup table assigns a given number of packets to one or more signaling modules 2614. -2702 can be mapped. The packet dispatcher 2610 can dynamically determine, using a lookup table, whether one or more signaling modules 2614 are associated with a given queue 2702. The packet dispatcher 2610 can then dispatch the packet to one or more determined signaling modules 2614 for digital signal processing.
[0174]
[0264] Before the packet dispatcher 2610 can begin dispatching packets to one or more signaling modules 2614 for digital signal processing, the configuration path module 2620 can configure the signaling path module 2602. The configuration path module 2620 can perform this configuration during the initialization of the system 2600 or when a user applies a new configuration to the signaling path module 2602. The configuration path module 2620 is shown in Figure 28.
[0175]
[0265] Figure 28 is a block diagram of a configuration path module 2620 that configures a signal path module 2602 to synchronize the processing and display of multiple signals in near real-time according to several embodiments. The configuration path module 2620 solves the technical problem of how to synchronize the processing and display of multiple signals related to at least one or more base signals in near real-time. The configuration path module 2620 solves this technical problem by equalizing the processing delays of each signal module 2614 so that each signal module 2614 completes the processing of the same corresponding packets approximately simultaneously. Figure 28 will be considered with reference to Figure 26.
[0176]
[0266] The configuration path module 2620 includes a signal configuration module 2802, a signal factory module 2804, a digital signal processor (DSP) equalizer 2806, and a DSP factory module 2808. The configuration path module 2620 is a software module that can be executed by one (or more) processors, such as processor 5004. The configuration path module 2620 controls the execution of the signal factory module 2804, the DSP equalizer 2806, and the DSP factory module 2808. The signal factory module 2804, the DSP equalizer 2806, and the DSP factory module 2808 may be software modules that can be executed by one (or more) processors, such as processor 5004.
[0177]
[0267] During the initialization of system 2600, or in response to a user applying a new configuration to system 2600, the configuration path module 2620 can generate and configure one or more signal modules 2614 in the global signal table 2612. In some embodiments, the execution of signal path modules 2602 and monitoring module 2622 can be suspended while the configuration path module 2620 is running.
[0178]
[0268] The configuration path module 2620 includes a signal configuration module 2802. The signal configuration module 2802 can receive one or more signal processing specifications. The signal processing specifications can be used to generate and configure the signal module 2614. The signal processing specifications can specify the base signal to be processed, the lengths of the input and output packet queues for the signal module 2614, and the digital signal processing functions to be used to process the base signal. The signal configuration module 2802 can also receive one or more signal processing specifications from a computer file. This file may contain one or more signal processing specifications previously specified by the user. The signal configuration module 2802 can also receive signal processing specifications via a graphical user interface (GUI), in which the user can input signal processing specifications using a set of computer mouse, touch, keyboard and / or voice recognition data input techniques, as will be understood by those skilled in the art.
[0179]
[0269] Upon receiving one or more signal processing specifications, the signal configuration module 2802 can transfer one or more signal processing specifications to the signal factory module 2804. The signal factory module 2804 can generate a signal module 2614 based on the signal processing specifications. For example, the signal factory module 2804 can generate a signal module 2614 as shown in Figure 29.
[0180]
[0270] Figure 29 is a block diagram of a signal module 2614 generated by a signal factory module 2804, according to several embodiments. The signal module 2614 can generate a processed signal from a base signal. The signal module 2614 includes an input packet queue 2902, a digital signal processor (DSP) 2904, and an output packet queue 2906. Figure 29 can be considered with reference to Figures 26 and 28.
[0181]
[0271] The signaling module 2614 includes an input packet queue 2902, a DSP 2904, and an output packet queue 2906. The signaling factory module 2804 can generate the input packet queue 2902, the DSP 2904, and the output packet queue 2906 based on signaling processing specifications from the signaling configuration module 2802. The input packet queue 2902 can store one or more packets from the packet dispatcher 2610 to be processed by the DSP 2904. The input packet queue 2902 can be a queue data structure that stores elements in the order in which they are inserted. For example, the first element inserted into the input packet queue 2902 is the first element to be removed from the input packet queue 2902. In other words, the input packet queue 2902 can be a first-in, first-out (FIFO) data structure. As will be understood by those skilled in the art, the input packet queue 2902 can be implemented using a linked list, an array, or various other data structures.
[0182]
[0272] The output packet queue 2906 can store one or more packets to be processed by the DSP 2904. The output packet queue 2906 can be a queue data structure that stores elements in the order in which they are inserted. For example, the first element inserted into the output packet queue 2906 is the first element to be removed from the output packet queue 2906. In other words, the output packet queue 2906 can be a first-in, first-out (FIFO) data structure. As will be understood by those skilled in the art, the output packet queue 2906 can be implemented using a linked list, an array, or various other data structures.
[0183]
[0273] The signal factory module 2804 can generate the DSP 2904 based on the signal processing specifications from the signal configuration module 2802. Specifically, the signal factory module 2804 can request the DSP factory module 2808 to generate the DSP 2904. The DSP factory module 2808 can generate the DSP 2904 based on the digital signal processing functions specified in the signal processing specifications. The DSP factory module 2808 can further generate the DSP 2904 based on one or more signal processing parameters related to the digital processing functions. For example, the DSP factory module 2808 can generate the DSP 2904 based on the low-pass filter function and cutoff frequency specified in the signal processing specifications.
[0184]
[0274] The DSP2904 is a software module that can be executed by one processor (or more processors), such as the processor 8504 in Figure 85. The DSP2904 performs digital processing functions on one or more packets, and therefore one or more signal packets. It can be applied simply. As those skilled in the art will understand, a digital processing function can be a mathematical algorithm that takes one or more signal samples as input, processes them, and generates one or more potentially modified signal samples as output. A digital processing function can be implemented using one or more mathematical operations, such as the Fast Fourier Transform. As those skilled in the art will understand, various types of digital processing functions can be applied to the DSP2904. For example, as those skilled in the art will understand, the DSP2904 can be used to apply low-pass filters, high-pass filters, band-pass filters, band-stop filters, notch filters, comb filters, all-pass filters, or various other filters.
[0185]
[0275] The DSP2904 can also be subjected to digital processing functions that analyze the signal for various features. For example, the DSP2904 can be subjected to digital processing functions that determine whether or not there are noise anomalies or signal patterns in the signal. The DSP2904 can also analyze the signal by detecting repeating patterns in the signal. This may include comparing the signal with previously detected (or recorded or synthesized) signal patterns.
[0186]
[0276] For example, the DSP2904 can determine the presence of a delayed potential in a signal. Specifically, the DSP2904 can determine the presence of a noise anomaly and subsequent noise anomalies occurring simultaneously for a matched heartbeat. Each subsequent noise anomaly at the same relative position can increase the confidence level at which the delayed potential was located. The display module 2618 can then display an indication of the delayed potential.
[0187]
[0277] For example, such determination of delayed potentials by DSP2904 can be used for pulmonary vein potential filters. Specifically, by combining the filtering for rapid conduction of separate electrograms after the delayed mid-P wave, pulmonary vein potentials can be identified separately from adjacent atria and other structures. These signals can serve as endpoints for ostial ablatio n to rapidly identify delay and exclusion. This system can be applied to other thoracic veins, ventricular delayed electrograms above the semilunar valve, delayed potentials in diseased myocardium, as well as the coronary sinus and Marshall vein.
[0188]
[0278] Similarly, DSP2904 can determine the presence of premature excitation in a signal. Specifically, DSP2904 can determine the presence of the earliest steep intracardiac signal exceeding a selected threshold that occurs within a predetermined segment before the reference point of a matched heartbeat. The display module 2618 can then display an indication of premature excitation.
[0189]
[0279] DSP2904 can detect patterns in signals using a correlation function. For example, DSP2904 can detect patterns using a mean absolute deviation algorithm. As will be appreciated by those skilled in the art, DSP2904 can use various other types of pattern matching algorithms.
[0190]
[0280] DSP2904 can detect patterns based on various signal characteristics (also referred to as signal patterns). For example, DSP2904 can detect patterns based on shape, amplitude and temporal characteristics. As will be appreciated by those skilled in the art, DSP2904 can detect patterns based on various other types of signal characteristics.
[0191]
[0281] The DSP2904 can also include one or more signal processing parameters. These signal processing parameters can control how the DSP2904 applies its digital processing capabilities. For example, the DSP2904 can include a threshold for filtering. The DSP2904 may include one or more signal processing parameters that specify a value frequency or amplitude. The DSP2904 may also include one or more signal processing parameters that specify a signal pattern to be detected, or a noise threshold.
[0192]
[0282] The DSP2904 can apply its digital processing capabilities to packets in the input packet queue 2902. In some embodiments, the DSP2904 can scan the input packet queue 2902 for new packets to be processed. In some other embodiments, the DSP2904 can receive notification that new packets are available in the input packet queue 2902. The DSP2904 can then retrieve a packet from the input packet queue 2902.
[0193]
[0283] The DSP2904 can apply its digital processing capabilities to the extracted packets. In other words, the DSP2904 can apply its digital processing capabilities to one or more signal samples in a packet. The DSP2904 can control how its digital processing capabilities are applied to one or more signal samples in a packet based on one or more signal processing parameters. After processing the packets, the DSP2904 can store the packets in the output packet queue 2906 for display by the output module 2616.
[0194]
[0284] As will be described later, each DSP2904 may have an associated processing delay. The processing delay can represent the amount of time it takes for the DSP2904's digital processing function to complete processing of a packet. The processing delay may differ between different DSP2904s. This difference in processing delay between different DSP2904s allows the DSP2904s to output packets for display at different points in time, as will be described later.
[0195]
[0285] After the signal factory module 2804 has finished generating the input packet queue 2902, DSP 2904, and output packet queue 2906, it can connect the output of the input packet queue 2902 to the input of the DSP 2904 and the output of the DSP 2904 to the input of the output packet queue 2906. Once the signal factory module 2804 has completed the connections, the DSP 2904 can receive packets representing the unprocessed base signal from the input packet queue 2902. The DSP 2904 can then process the packets using its digital processing capabilities. The DSP 2904 can output the processed packets to the output packet queue 2906. The signal factory module 2804 can further configure the input packet queue 2902 to receive packets from the base signal specified in the signal processing specification.
[0196]
[0286] Once signal module 2614 is created, signal factory module 2804 can add it to global signal table 2612. As described above, global signal table 2612 can be a fixed-size array. A given base signal can be associated with each element of the array. Furthermore, each element of the array can be a fixed-size array itself. A given signal module 2614 can be associated with each element of this subarray.
[0197]
[0287] In some embodiments, the signal factory module 2804 can add the created signal modules 2614 to the global signal table 2612 by adding a new array element to each subarray associated with the base signal. This new array element can correspond to the newly created signal module 2614. For example, if the global signal table 2612 previously contained 10 signal modules 2614, the newly created signal modules 2614 can be added, for example, to array number 11 of each subarray.
[0198]
[0288] Once the created signal module 2614 is added to the global signal table 2612, a user (for example, a physician) can assign the created signal module 2614 to a given base signal. In some embodiments, the global signal table 2612 may indicate whether the created signal module 2614 is assigned to a given base signal by storing "0" or "1" in the corresponding element of the subarray associated with the created signal module 2614. In some other embodiments, the global signal table 2612 may indicate whether the created signal module 2614 is assigned to a given base signal by storing a reference to the created signal module 2614 in the corresponding element of the subarray.
[0199]
[0289] The signal factory module 2804 can generate multiple signal modules 2614. Each signal module 2614 may have a DSP 2904 that applies different digital signal processing functions. As a result, each signal module 2614 can generate different processed versions of the same base signal. This allows the user to analyze the same base signal in various ways. The user may also want to analyze the time-matched outputs of multiple versions of the same base signal. This allows the user to compare different versions of the same signal at the same or different points in time.
[0200]
[0290] As mentioned above, conventional digital signal processing systems are often unable to synchronize the display of multiple processed signals in near real-time. This may be because different digital signal processing functions have different processing delays. For example, current EP systems may apply two different digital signal processing functions to the same base signal. However, a medical team may want to synchronize the display of two processed signals. For example, a medical team may want to compare IC signals and ECG signals at the same time to determine a clinical diagnosis. In other words, a medical team may want to time-match the delay of the first processed signal with the delay of the second processed signal in near real-time. However, this may not be possible because the two different digital processing functions have different processing delays. This is because one of the digital processing functions may complete processing the base signal more quickly than the other digital signal processing function. As a result, one processed signal may appear before the other processed signal.
[0201]
[0291] Processing delays associated with digital processing functions can be determined by the complexity of the function. For example, a digital processing function that performs low-pass filtering on a signal may be relatively uncomputationally intensive and use minimal memory. As a result, such a digital processing function may have short processing delays. In contrast, another digital processing function may analyze a signal with respect to specific signal characteristics. This type of digital processing function is more computationally intensive, uses more memory, and therefore may have longer processing delays.
[0202]
[0292] Due to differing processing delays, one processed signal may appear before another. This synchronization error can increase over time. For example, this error can be significant when multiple signals are processed and displayed in near real-time. This is because the difference in processing delays between two digital signal processing functions can propagate to each new signal sample.
[0203]
[0293] For example, the first digital signal processing function may have a processing delay of 10 milliseconds for a given base signal. The second digital signal processing function may have a processing delay of 20 milliseconds for the same base signal. The first digital signal processing may be completed in 10 milliseconds, while the second digital signal processing may take 20 milliseconds to process the same first signal sample. Therefore, the first signal sample processed by the first digital signal processing function may appear in 10 milliseconds, while the first signal sample processed by the second digital signal processing function may appear in 20 milliseconds. In other words, the first signal sample processed by the first digital signal processing function may appear 10 milliseconds earlier than the first signal sample processed by the second digital signal processing function.
[0204]
[0294] This synchronization shift can increase when the second signal sample is processed. For example, the second signal sample might be received at 10 milliseconds for processing by the first digital signal processing function, and then received at 20 milliseconds for processing by the second digital signal processing function. As a result, the second signal sample processed by the first digital signal processing function might appear at 20 milliseconds, and the second signal sample processed by the second digital signal processing function might appear at 40 milliseconds. In other words, the synchronization shift can increase by 10 milliseconds for the second signal sample; that is, the synchronization shift is initially 10 milliseconds, and then it becomes 20 milliseconds.
[0205]
[0295] This synchronization issue can be exacerbated when digital signal processing is performed in a non-real-time operating system. Unlike non-real-time operating systems, real-time operating systems are time-constrained systems with clear, fixed time constraints. Real-time operating systems can ensure that application tasks are accepted and completed within a certain amount of time. In other words, real-time operating systems can provide a certain level of consistency regarding the amount of time it takes to complete a task.
[0206]
[0296] In contrast, non-real-time operating systems cannot provide any guarantee that application tasks will be completed within a certain amount of time. For example, a non-real-time operating system cannot guarantee that the execution of a particular digital signal processing function will be completed within a certain amount of time. As a result, there may be a high degree of variability in the amount of time it takes to complete a task. This can be problematic when trying to synchronize the processing and display of multiple processed signals, because the processing delay associated with digital processing functions may differ for each execution. For example, a digital signal processing function may typically complete its execution in 10 milliseconds. However, in a non-real-time operating system, there may be no guarantee that the digital signal processing function will complete its execution in 10 milliseconds. For example, the digital processing function may complete its execution in 30 milliseconds. This variability in processing delay can further increase the synchronization issues.
[0207]
[0297] In some embodiments, this display synchronization problem is solved in a multifaceted way by using the input packet queue 2902 and output packet queue 2906 of the signal module 2614, storing signal samples in packets along with associated tags, and equalizing processing delays among one or more DSPs 2904.
[0208]
[0298] The input packet queue 2902 and output packet queue 2906 can solve the delay synchronization problem in three ways. First, they ensure that packets, and therefore signal samples, are processed and displayed sequentially. Second, the output packet queue 2906 can synchronize the display of packets at the same time by blocking the processing of further packets until existing packets are consumed by the output module 2616. In other words, the output packet queue 2906 prevents the DSP 2904 from processing further packets. A feedback mechanism can be provided to the DSP2904 to indicate when it can stop processing. Finally, the input packet queue 2902 ensures that the DSP2904 has packets to process. For example, when the input packet queue 2902 is empty, the DSP2904 can stop processing further packets. In other words, the input packet queue 2902 can provide the DSP2904 with a feedback mechanism to indicate that there are no packets to process.
[0209]
[0299] The DSP delay equalizer 2806 can also solve the delay synchronization problem by equalizing the processing delays across one or more DSPs 2904. As described above, different digital signal processing functions have different processing delays, which can cause processed signals to appear out of sync. Therefore, the configuration path module 2620 generates multiple signal modules 2614, each having a DSP 2904 with a different digital signal processing function, and each signal module 2614 can complete packet processing with a different processing delay. These different processing delays can cause processed signals to appear out of sync by the output module 2616. The DSP delay equalizer 2806 can solve this problem by equalizing the processing delays across the generated signal modules 2614.
[0210]
[0300] In some embodiments, after the configuration path module 2620 has generated one or more signal modules 2614, the signal factory module 2804 can use a DSP delay equalizer 2806 to equalize the processing delay of each generated signal module 2614 so that each signal module 2614 outputs processed packets to its output packet queue 2906 at the same time. For example, the DSP delay equalizer 2806 can determine the relative processing delay between two signal modules 2614. The DSP delay equalizer 2806 can then use the determined relative delay to configure the DSP 2904 of the first signal module 2614 to complete packet processing at approximately the same time that the DSP 2904 in the second signal module 2614 is designed to complete packet processing.
[0211]
[0303] In some embodiments, the DSP delay equalizer 2806 can perform equalization by scanning each generated signal module 2614. During the scan, the DSP delay equalizer 2806 can request the processing delay associated with the DSP 2904 of each signal module 2614. The DSP delay equalizer 2806 can request the processing delay using the application programming interface (API) of each signal module 2614. In response, each signal module 2614 can return its associated processing delay.
[0212]
[0302] The signal module 2614 can store the processing delay associated with its DSP 2904. The processing delay may be a predefined value specified in the signal processing specification used to generate the DSP 2904. In some other embodiments, the DSP factory module 2808 can calculate the processing delay of the DSP 2904 based on various factors, including the digital processing functions used by the DSP 2904, selected signal processing parameters, and hardware characteristics such as the speed of the processor, such as the processor 5004, the size of the memory, and the I / O latency.
[0213]
[0303] After determining the processing delay associated with the DSP 2904 in each signal module 2614, the DSP delay equalizer 2806 can determine the maximum processing delay among the signal modules 2614. For example, the DSP delay equalizer 2806 determines that signal module 2614-1 has a processing delay of 10 milliseconds, signal module 2614-2 has a processing delay of 20 milliseconds, and signal module 2614-N has a processing delay of 50 milliseconds. It is possible to determine that the maximum processing delay between the signal modules 2614 is 50 milliseconds.
[0214]
[0304] After determining the maximum processing delay, the DSP delay equalizer 2806 can configure the DSP 2904 of each signal module 2614 to have the maximum processing delay. For example, the DSP delay equalizer 2806 can use an API to set the processing delay of the DSP 2904 of each signal module 2614. In response, each DSP 2904 can be designed to process packets using its digital processing capabilities and to output processed packets to its associated output packet queue 2906 at the end of the maximum processing delay. For example, in some embodiments, the DSP 2904 can block its output to the output packet queue 2906 if it has finished processing packets before the end of the maximum processing delay. In some other embodiments, the DSP 2904 can insert idle computation cycles while processing packets. As will be understood by those skilled in the art, various other techniques can be used to cause the DSP 2904 to output processed packets to its output packet queue 2906 at the end of the maximum processing delay.
[0215]
[0305] Packetization and tagging of packets can solve the display synchronization problem. As mentioned above, each generated packet can contain a certain number of signal samples. Each packet can also contain a tag indicating its relative position within a sequence of packets. To synchronize the delays of multiple signals, the display module 2618 can display packets that have the same tag. In other words, the display module 2618 can use tags to synchronize its display.
[0216]
[0306] As shown in Figure 26, the output module 2616 may include one or more display modules 2618-1 to 2618-N and a review module 2624. The review module 2624 may be a software module that can be executed by one (or more) processors, such as processor 5004. The review module 2624 can display one or more signals processed by one or more signal modules 2614 at a preceding time. Each display module 2618 may be a software module that can be executed by one (or more) processors, such as processor 5004. Each display module 2618 can display one or more live signals processed by one or more signal modules 2614. Each display module 2618 can operate independently of other display modules 2618. In other words, each display module 2618 can simultaneously display one or more signals on one or more display devices, such as the input / output device 8503 in Figure 85. In some embodiments, each display module 2618 can display one or more of its associated signals in a specific GUI window on a given display device.
[0217]
[0307] Each display module 2618 can display one or more signals. Each display module 2618 can receive packets from the associated output packet queue 2906 in the signal module 2614 in the global signal table 2612. The display module 2618 can display signals based on those packets.
[0218]
[0308] Figure 30 is a block diagram of the display module 2618 according to several embodiments. The display module 2618 includes a local signal table 3002, a packet index 3004, and a display setting 3006. Figure 30 will be discussed with reference to Figure 29.
[0219]
[0309] As described above, the display module 2618 is located in the signal module 2614. The display module 2618 can receive packets from the associated output packet queue 2906. To receive packets, the display module 2618 can maintain a reference to the associated output packet queue 2906 in the signal module 2614. If the display module 2618 is designed to display multiple signals, it can maintain a reference to the output packet queue 2906 associated with each signal being displayed. The display module 2618 can store references in its local signal table 3002. The local signal table 3002 may contain a list of one or more references to the output packet queue 2906 associated with each signal being displayed. When the associated signal module 2614 becomes inactive, the display module 2618 can remove the references from its local signal table 3002.
[0220]
[0310] In some embodiments, the display module 2618 can continuously scan one or more associated output packet queues 2906 for new packets. If the display module 2618 is associated with a single output packet queue 2906, it can display a new packet on the display device whenever it detects it. However, if the display module 2618 is associated with multiple output packet queues 2906, it may not immediately display a new packet detected in a particular output packet queue 2906. This is because the display module 2618 can be designed to synchronize the display of multiple signals.
[0221]
[0311] In some embodiments, if a given display module 2618 is designed to synchronize the display of multiple signals, the display module 2618 can detect a new packet in a particular output packet queue 2906. The display module 2618 can then determine a tag associated with the new packet. Using this determined tag, the display module 2618 can synchronize the display of new packets from other output packet queues 2906. For example, the display module 2618 may wait to display any packets on the display device until it detects a new packet in another output packet queue 2906 with the same determined tag. Once the display module 2618 detects a new packet with the same tag in another related output packet queue 2906, it can simultaneously display packets from that related output packet queue 2906. The display module 2618 can display multiple signals in a non-overlapping stacked format. Because the display module 2618 can display packets with the same tag, the resulting displayed signals can be time-coordinated.
[0222]
[0312] As described above, the type of preprocessing that the packetizer 2606 can perform on any one of the multiple signals may depend on the type of signal. In some embodiments, the selection of signal preprocessing by the packetizer 2606 can be automated. This allows for the automated placement of appropriate filters based on the ratio of the far-field signal to the adjacent and near-field signals with minimal filtering, for example, to minimize noise and focus on the target signal. As those skilled in the art will understand, this type of automation may be effective in minimizing treatment time, for example, when there is a small or moderate number of practitioners. The display module 2618 can also display multiple signals synchronously as new packets are detected from the automated process.
[0223]
[0313] The display module 2618 can maintain the currently active tag to be displayed in packet index 3004. When a new packet is detected in a specific output packet queue 2906, the display module 2618 can determine the tag of the new packet. Then, the display module 2618 displays the determined tag in packet index 30 You can set it to 04.
[0224]
[0314] In some embodiments, a high-frequency rapid conduction signal filter can be applied to multiple electrodes, such as basket or balloon-based catheters, to identify conduction tissues, such as distal Purkinje and annular rapid conduction tissue. These annular tissues can be rapidly targeted for ablation due to their signal protrusions. Based on dynamic tagging of packets from the packetizer 2606, the display module 2618 can continue to visualize the signals as reference points to guide the movement of the ablation catheter, and can be used to terminate local energy delivery when the target pathogen signal decays during ablation. As shown in this example, system pre-processing and continued processing allow the physician to continue monitoring the signals even during ablation.
[0225]
[0315] The display module 2618 may include a display setting 3006. The display setting 3006 may include one or more parameters that control how the display module 2618 displays one or more associated signals. The display setting 3006 may specify the color in which one or more associated signals are displayed. The display setting 3006 may specify a view format, such as a waterfall view, dynamic view, or trigger view, as described later. The display setting 3006 may specify a sweep rate for one or more signals. The display setting 3006 may include various other types of display settings, as will be understood by those skilled in the art. The display setting 3006 may be designed by the user, as described later.
[0226]
[0316] The review module 2624 can display one or more signals that have been processed by one or more signal modules 2614 at a preceding time. This allows a user (e.g., a physician) to analyze one or more signals considerably later than they were generated and displayed. In some embodiments, the review module 2624 can capture the display of one or more signals in the display module 2618 in response to a command. For example, a user can capture the current display of the display module 2618 by clicking a button in the GUI. The captured display may include previously displayed visualizations of one or more signals at the time of capture. In some embodiments, the display module 2618 can pause the display of its new packets in response to the capture of its current display.
[0227]
[0317] In some embodiments, the review module 2624 can capture the display of one or more signals in the display module 2618 by determining the capture configuration of the display module 2618. The capture configuration may include, as will be understood by those skilled in the art, one or more active signal modules 2614 to the display module 2618, an capture time, a selected view to the display module 2618, a color scheme for one or more displayed signals, and various other settings. After determining the capture configuration, the review module 2624 can apply the capture configuration to previously stored signal samples.
[0228]
[0318] As described above, the input module 2604 can store one or more signal samples for each base signal in a memory device for later analysis by the review module 2624. The review module 2624 can capture the display of one or more signals in the display module 2618 by applying a determined acquisition configuration to these stored signal samples. Specifically, the review module 2624 can select the stored signal samples at the acquisition time in the acquisition configuration. The review module 2624 can then process the selected signal samples using the active signal module 2614 in the acquisition configuration. The review module 2624 can also display selected signal samples using the selected view, color scheme, and various other settings in the acquisition configuration. Thus, the review module 2624 allows the user to redisplay one or more processed signals to the display module 2618 at a specific point in time, according to a specific configuration.
[0229]
[0319] In some embodiments, the review module 2624 allows the user to change the redisplay interval for the display module 2618. For example, the user can "go back" to a different point in the past (e.g., 5 minutes ago). After the acquisition time has been changed, the review module 2624 can display one or more processed signals to the display module 2618 with a new redisplay time index.
[0230]
[0320] Figure 31 is a block diagram of a monitoring module 2622 according to several embodiments. The monitoring module 2622 includes a queue monitor 3102 and a reporting module 3104. The queue monitor 3102 and the reporting module 3104 may be software that can be executed by one (or more) processors, such as processor 5004.
[0231]
[0321] The monitoring module 2622 can run continuously while the signal path module 2602 is running. For example, the monitoring module 2622 can run as a separate thread from the processor's execution. The monitoring module 2622 can determine whether or not there are any problems in the execution of the signal path module 2602.
[0232]
[0322] In some embodiments, the queue monitor 3102 can periodically scan queues in the signal path module 2602. For example, the queue monitor 3102 can scan queue 2702 in the queuing module 2608. The queue monitor 3102 can also scan input packet queues 2902 and output packet queues 2906 in one or more signal modules 2614. The queue monitor 3102 can determine the status of each queue being scanned. For example, the queue monitor 3102 can determine the length of each queue being scanned. In some embodiments, if the queue monitor 3102 determines that a queue has an error status, it can request the reporting module 3104 to display the error status on a display device. For example, the queue monitor 3102 may determine that the length of a queue is continuously increasing. Accordingly, the queue monitor 3102 can request the reporting module 3104 to display an error indicating that a particular queue has an incorrect length.
[0233]
[0323] Figure 32 shows examples of adjusting the sweep speed for the display module 2618 according to several embodiments. Figure 32 includes the live view display area 3202 and the sweep speed 3204. Figure 32 will be discussed with reference to Figure 26.
[0234]
[0324] The live view display area 3202 may include a near real-time display of the display module 2618. In Figure 32, the live view display area 3202 includes a near real-time display of 14 different signals (for example, processed signals or base signals).
[0235]
[0325] The sweep speed 3204 may be a GUI widget that allows the user to select a sweep speed for the live view display 3202. The sweep speed can represent a time scale for one or more signals displayed in the live view display area 3202. For example, the sweep speed may be in the range of 10 mm / second to 1000 mm / second. In Figure 32, the sweep speed 3204 appears to be selected to be 50 mm / second. As shown therein, as will be understood by those skilled in the art, the selection of sweep speed can affect the level of detail displayed and therefore can be set based on the size of the display screen.
[0236]
[0326] Figure 33 shows signal management for the display module 2618 according to several embodiments. Figure 33 includes a signal management window 3302. Figure 33 is discussed with reference to Figure 26.
[0237]
[0327] The signal management window 3302 may include available signals 3304 and signal settings 3306. Available signals 3304 may include one or more signals that can be selected to be displayed by the display module 2618. For example, in Figure 33, available signals 3304 includes 14 signals that can be selected to be displayed by the display module 2618. Available signals 3304 may display various information around each signal. For example, available signals 3304 may display the name of the signal and whether or not that signal is processed by a particular signal module 2614.
[0238]
[0328] The signal settings 3306 can display various settings that can be set for each signal. For example, in Figure 33, the signal settings 3306 allows the user to change the name of each signal or assign a specific color to each signal. These settings can be stored in the display settings 3006 of the display module 2618. The signal settings 3306 also allows the user to change various processing parameters associated with each signal. These processing parameters can be stored in one or more signal processing parameters of the DSP 2904 of the signal module 2614 associated with a given signal.
[0239]
[0329] Figure 34 shows examples of adjusting the zoom and clipping ratios for the display module 2618 in several embodiments. Figure 34 includes the live view display area 3402 and the display settings window 3404. Figure 34 will be discussed with reference to Figure 26.
[0240]
[0330] The live view display area 3402 may include a near real-time display of the display module 2618. In Figure 34, the live view display area 3402 includes a near real-time display of 14 different signals (for example, processed signals or base signals).
[0241]
[0331] The display settings window 3404 may include a zoom ratio 3406 and a clipping ratio 3408. The zoom ratio 3406 may be a GUI widget that selects the zoom ratio for a particular signal in the live view display area 3402. The selected zoom ratio can increase or decrease the size of the particular signal. For example, the zoom ratio 3406 can increase the size of a particular signal from 0.02 to 40 times.
[0242]
[0332] The clipping rate 3408 may be a GUI widget that allows the user to select a clipping rate for a particular signal in the live view display area 3402. The selected clipping rate can control how much the signal overshoots across the display screen. For example, the user can adjust the clipping rate to reduce the actual area in which a particular signal is displayed so that it does not spread beyond the entire display screen to the point where it becomes partially invisible if the signal is large.
[0243]
[0333] Figure 35 shows pattern search management for the display module 2618 in several embodiments. Figure 35 includes the live view display area 3502 and the pattern search window 3504. Figure 35 will be discussed with reference to Figure 26.
[0244]
[0334] The live view display area 3502 may include a near real-time display of the display module 2618. The pattern search window 3504 may be a GUI window that allows the user to load or specify signal patterns to search for. For example, in Figure 35, the user can create or load a search for delayed potentials or early excitations in one or more signals. The user can also specify various parameters for the search, such as the search interval, heart rate detection confidence percentage, detection confidence percentage, or other parameters, as will be understood by those skilled in the art. The signal patterns to search for can be stored in one or more signal processing parameters of the DSP 2904 of the signal module 2614 associated with a given signal.
[0245]
[0335] Figure 36 shows the delayed potential search results highlighted in the display of the display module 2618 in several embodiments. Figure 36 includes the live view display area 3602. Figure 36 will be discussed with reference to Figure 26.
[0246]
[0336] The live view display area 3602 may include a near real-time display of the display module 2618 following a delayed potential search. The user can create or load a search for delayed potentials, as previously shown in Figure 35. Once a search is initiated, the live view display area 3602 can display the delayed potentials found in one or more signals. The live view display area 3602 can display the found delayed potentials along with a detection confidence percentage. For example, in Figure 36, the found delayed potential 3604 is shown with an 83% detection confidence. The live view display area 3602 can also display a tally of the total delayed potentials found.
[0247]
[0337] Figure 37A shows the use of a display module 3618 configured as a waterfall view in several embodiments. Figure 37A includes a live view display area 3702. Figure 37A is discussed with reference to Figure 26.
[0248]
[0338] The live view display area 3702 may include a near real-time display of the display module 2618. The live view display area 3702 can display a near real-time display of the display module 2618 using a waterfall view. In the waterfall view, signals can be displayed side by side and stacked vertically when patterns match. Specifically, the user can select a matching pattern (e.g., a predetermined heart rate pattern) in a first signal. When that pattern is detected in the first signal, the display module 2618 can display the portion of the first signal that matches that pattern next to the corresponding portion of the second signal (e.g., an IC signal). The user can select the size of the portion of the first signal and the portion of the second signal to display. For example, the user can select the size of the portion of the first signal using a time interval (e.g., 150 milliseconds).
[0249]
[0339] In the waterfall view, each time a pattern is detected in the first signal, the display module 2618 can display each new portion of the first signal that matches the pattern, vertically along with the corresponding portion of the second signal. In other words, in the waterfall view, the display module 2618 can display the signal along a vertical time axis.
[0250]
[0340] In Figure 37A, the live view display area 3702 shows a near real-time display of two different signals (e.g., V2[P1] and ABL.d) in the waterfall view. In Figure 37A, signals V2[P1] and ABL.d are displayed stacked side by side. For example, at approximately 10 seconds, signal portion 3704 is displayed alongside signal portion 3706. Signal portion 3704 is at approximately 10 seconds, given the signal The signal portion 3706 can represent the portion of signal V2[P1] that coincides with a turn (for example, heart rate P1, lead V2). The signal portion 3706 can represent the corresponding portion of signal ABL.d at the point when the given pattern coincides with signal V2[P1].
[0251]
[0341] Users (for example, doctors) will find the waterfall view advantageous. Firstly, the waterfall view allows users to compare corresponding portions of two signals side by side. Secondly, because the signals are stacked vertically in the waterfall view, signals can be displayed on the screen for a longer period of time. In contrast, when signals are displayed from left to right, it is often difficult for users to analyze the signals because they disappear from the screen after a short period of time.
[0252]
[0342] Figure 37B shows the signal correspondence between a normal display module 2618 and a display module 2618 configured as a waterfall view in several embodiments. Figure 37B includes a live view display area 3708 and a waterfall view 3710. Figure 37B is discussed with reference to Figure 26.
[0253]
[0343] In Figure 37B, the live view display area 3708 shows a near real-time display of two different signals (for example, V2[P] and ABL.d). The waterfall view 3710 shows a near real-time display of the same two signals, except that signals V2[P] and ABL.d are displayed side by side so that they appear to be superimposed. In the waterfall view 3710, whenever a signal pattern is detected in the signals, the display module 2618 can display the portion of the signal that matches that signal pattern vertically together with the corresponding portion of the second signal.
[0254]
[0344] For example, in Figure 37B, the signal portion 3712 of signal V2[P1] contains a certain signal pattern. The corresponding signal portion 3714 of signal ABL.d corresponds to the signal portion 3712 at the time of detection. In Figure 37B, the waterfall view 3710 displays the signal portion 3712 and the corresponding signal portion 3714 side by side (for example, together) whenever the signal pattern is detected in signal V2[P1]. In Figure 37B, the waterfall view 3710 displays the portions of signal V2[P1] that match the signal pattern, together with the corresponding portions of signal ABL.d, from oldest to newest. In other words, in Figure 37B, the waterfall view 3710 displays heartbeats scrolling up, with the oldest heartbeat at the top and the newest heartbeat at the bottom. As those skilled in the art will understand, the waterfall view 3710 can display heartbeats in various other ways, such as the newest heartbeat at the top and the oldest heartbeat at the bottom.
[0255]
[0345] Figure 37C shows the use of the display module 2618 configured as a dynamic view in several embodiments. Figure 37C includes the live view display area 3716. Figure 37C is discussed with reference to Figure 26.
[0256]
[0346] The live view display area 3716 can include a near real-time display of the display module 2618. The live view display area 3716 can display a near real-time display of the display module 2618 using a dynamic view. In the dynamic view, the user can select a trigger for the signal (e.g., matching with a stored heartbeat). The user can select a trigger from several trigger types. The trigger type may be a signal characteristic of the subject related to a secondary event of the subject. When a trigger occurs, the display module 2618 can dynamically adjust the signal offset so that it is pinned to the baseline. This prevents the signal from progressing out of the display screen. This is useful in clinical settings where, for example, the height of the signal peak may indicate a particular type of injury, and a signal plateau may indicate the effectiveness of an ablation lesion. And that is often important.
[0257]
[0347] In Figure 37C, the live view display area 3716 shows a reference heart rate measured with a unipolar signal (e.g., Uni1) at a reference time (e.g., reference time 3724). For example, this may occur during ablation. In Figure 37C, signal 3718 can be the initial heart rate, signal 3720 can be the current heart rate, and signal 3722 can be the maximum recorded heart rate since signal Uni1 was acquired at reference time 3724. As described above, in the dynamic view, the user can specify a reference location that determines the point of the signal to be pinned to the baseline. In Figure 37C, this point is at the on-screen pinning location 3726 (e.g., 0.0mV) for signal Uni1. This allows signal Uni1 to be offset so that it is pinned to pinning location 3726.
[0258]
[0348] Figure 37D shows the use of the display module 2618 configured as a trigger view in several embodiments. Figure 37D includes the live view display area 3728 and the trigger view 3730. Figure 37D is discussed with reference to Figure 26.
[0259]
[0349] The live view display area 3728 may include a near real-time display of the display module 2618. In Figure 37D, the trigger view 3730 shows the display of the live view display area 3728 using the trigger view. In the trigger view 3730, the user can select a first signal (e.g., pacing signal 3732) that triggers the display of other signals (e.g., II signal 3734, Uni Dist signal 3736, and Uni Prox signal 3738). The user can select a specific trigger for the first signal. The user can select a trigger from several trigger types. The trigger type may be a signal characteristic of the subject related to a secondary event of the subject. For example, the user can select a specific voltage (e.g., 60 millivolts) for the first signal. Those skilled in the art will understand that other signal characteristics can be selected. When a trigger occurs, the display module 2618 can display the specified one or more signals in synchronous time and stacked vertically on the display. The user (e.g., a physician) will find the trigger view advantageous. This is because it makes it easier for the user to see what happens in response to an event (for example, the start of pacing signal 3732).
[0260]
[0350] In Trigger View 3730, the user can also specify a point in time after the trigger occurs when the data is pinned to the baseline. For example, in Figure 37D, the user sets the time to approximately 70ms after the trigger occurs. In Figure 37D, in response to the user setting the time to approximately 70ms after the trigger occurs, Uni The Dist signal 3736 and Uni Prox signal 3738 are pinned and always displayed in the trigger view 3730. In contrast, in Figure 37D, the Uni Dist signal 3736 and Uni Prox signal 3738 are not displayed in the live view display area 3728 because they are not pinned to the baseline.
[0261]
[0351] Figure 38 shows signal acquisition in the display of a display module 2618 configured as a review window in several embodiments. Figure 38 includes a live view display area 3802 and a review window 3804. Figure 38 will be discussed with reference to Figure 26.
[0262]
[0352] The live view display area 3802 can include a near real-time display of the display module 2618. The review window 3804 can include a preceding display shown in the live view display area 3802. To do this, the user can submit an import request. For example, in Figure 38, the user can click the Review button 3806. Accordingly, the review module 2624 can determine the acquisition configuration for the display module 2618. The acquisition configuration may include one or more active signal modules 2614 for the display module 2618, acquisition time, selected view for the display module 2618, color scheme for one or more display signals, and various other settings, as will be understood by those skilled in the art. After determining the acquisition configuration, the review module 2624 can apply the acquisition configuration to previously stored signal samples and display the output in the review window 3802.
[0263]
[0353] Figure 39 shows amplitude measurements performed on the display of the display module 2618, configured as a review window, using several implementation tests. Figure 39 includes the live view display area 3902 and the review window 3904. Figure 39 is discussed with reference to Figure 26.
[0264]
[0354] The live view display area 3902 may include a near real-time display of the display module 2618. The review window 3904 may include a previously captured display shown in the live view display area 3802. In the review window 3904, the user can analyze the previously captured output using the vertical and horizontal calipers. The horizontal caliper may be a GUI selection widget. The user can use the horizontal caliper to measure the amplitude of a particular signal in millivolts (mV). For example, as shown in Figure 39, the user can click the top and bottom of the V1 signal to generate two horizontal lines (e.g., caliper lines 3908 and 3910). The user can then hover the cursor along the V signal to display the measured amplitude (e.g., measurement 3906) at a specific point in time. Similarly, the vertical caliper may also be a GUI selection widget. The user can use the vertical caliper to measure time in milliseconds or heart rate per minute (BPM). The user can click on the left and right points along the signal to generate two vertical lines, as shown in Figure 65, and display the measured time or heart rate per minute between the two vertical lines. For example, the time between vertical caliper 6502 and vertical caliper 6504 is 464 msec or 129 BPM, as shown in the pop-up box 6506.
[0265]
[0355] The following description of methods for processing and displaying multiple signals in near real-time is provided for embodiments relating to the visualization of ECG and IC signals. Those skilled in the art will understand that these methods can be equally applied to the visualization of other small physiological signals.
[0266]
[0356] Figure 40 is a flowchart of a method 4000 for processing and displaying multiple signals in near real-time, according to several embodiments.
[0267]
[0357] Method 4000 will be described with reference to Figure 26. However, Method 4000 is not limited to its embodiments.
[0268]
[0358] In 4002, the configuration path module 2620 constitutes one or more signal modules 2614. 4002 can be implemented by the method 4100 shown in Figure 41.
[0269]
[0359] In 4004, the input module 2604 receives one or more signal samples for one or more signals. For example, the input module 2604 receives one or more signal samples for the IC signal and one or more signal samples for the ECG signal. You can receive the pull. Method 4400 in Figure 44 can be used to carry out 4004.
[0270]
[0360] In 4006, the input module 2604 dispatches one or more signal samples to the packetizer 2606.
[0271]
[0361] In step 4008, the packetizer 2606 converts one or more signal samples into one or more packets. Step 4008 can be carried out by method 4500 shown in Figure 45.
[0272]
[0362] In step 4010, the packetizer 2606 dispatches one or more packets to the queuing module 2608. Step 4010 can be performed using the method shown in Figure 46.
[0273]
[0363] In step 4012, the packet dispatcher 2610 dispatches packets from the queuing module 2608 to the signaling module 2614 associated with the packets. Step 4012 can be performed using the method shown in Figure 47.
[0274]
[0364] In 4014, the signal module 2614 of 4012 processes packets using the DSP 2904. 4014 can be implemented using the method shown in Figure 48.
[0275]
[0365] In 4016, the display module 2618 associated with the signal module 2614 of 4012 displays the processed packets on the display screen. 4016 can be implemented by method 4900 shown in Figure 49.
[0276]
[0366] Figure 41 is a flowchart of a method 4100 for configuring one or more signal modules 2614 according to several embodiments.
[0277]
[0367] Method 4100 will be described with reference to Figure 26. However, Method 4100 is not limited to its embodiments.
[0278]
[0368] In 4102, the signal configuration module 2802 can receive one or more signal processing specifications. The signal processing specifications can specify the base signal to be processed, the lengths of the input and output packet queues for the signal module 2614, the digital signal processing function to process the base signal, and one or more associated parameters for the digital signal processing function. In some embodiments, the signal configuration module 2802 can receive signal processing specifications from a file stored in memory. In some other embodiments, the signal configuration module 2802 can receive signal processing specifications from a GUI that allows the user to manually input the signal processing specifications.
[0279]
[0369] In 4104, the signal configuration module 2802 dispatches one or more signal processing specifications to the signal factory module 2804.
[0280]
[0370] In 4106, the signal factory module 2804 generates a signal module 2614 for each signal processing specification. 4106 can be implemented by method 4200 shown in Figure 42.
[0281]
[0371] Figure 42 is a flowchart of a method 4200 for generating a signal module 2614 from a signal processing specification, according to several embodiments.
[0282]
[0372] Method 4200 will be described with reference to Figure 26. However, Method 4200 is not limited to its embodiments.
[0283]
[0373] In 4202, the signal factory module 2804 generates the input packet queue 2902 for the signal module 2614 based on the signal processing specifications in 4106 of Figure 41. For example, the signal factory module 2804 generates the input packet queue 2902 by creating a queue data structure of the length specified in the signal processing specifications.
[0284]
[0374] In 4204, the signal factory module 2804 generates the output packet queue 2906 for the signal module 2614 based on the signal processing specifications. For example, the signal factory module 2804 generates the output packet queue 2806 by creating a queue data structure of the length specified in the signal processing specifications.
[0285]
[0375] In 4206, the signal factory module 2804 generates the DSP 2904 of the signal module 2614 using the DSP factory module 2808 based on the signal processing specifications. Specifically, the signal factory module 2804 can request the DSP module 2808 to generate the DSP 2904 based on the signal processing functions and one or more signal processing parameters specified in the signal processing specifications. For example, the DSP factory module 2808 can generate the DSP 2904 based on the low-pass filter function and a predetermined cutoff frequency specified in the signal processing specifications.
[0286]
[0376] In 4207, the signal factory module 2804 connects the input packet queue 2902 of the signal module 2614, the generated DSP 2904, and the generated output packet queue 2906. Specifically, the signal factory module 2804 connects the output of the input packet queue 2902 to the input of the DSP 2904. The signal factory module 2804 further connects the output of the DSP 2904 to the input of the output packet queue 2906.
[0287]
[0377] In 4210, the signal factory module 2804 configures the input packet queue 2902 to receive packets dispatched from the packet dispatcher 2610. In some embodiments, the signal factory module 2804 can add rules to a lookup table associated with the packet dispatcher 2610. These rules may specify that packets associated with a given signal can be processed by a given signal module 2614.
[0288]
[0378] In 4212, the signal factory module 2804 uses the DSP delay equalizer 2806 to equalize the associated processing delays of each created signal module 2614 so that each signal module 2614 outputs processed packets to its output packet queue 2906 at the same time. 4210 can be implemented by method 4300 in Figure 43.
[0289]
[0379] Figure 43 is a flowchart of a method 4300 for equating the processing delay associated with each DSP 2904 of one or more signal modules 2614, according to several embodiments.
[0290]
[0380] Method 4300 will be described with reference to Figure 26. However, Method 4300 is not limited to its embodiments.
[0291]
[0381] In 4302, the DSP delay equalizer 2806 requests the processing delay associated with each DSP 2904 of one or more signal modules 2614. The DSP delay equalizer 2806 can request the processing delay of the DSP 2904 using the API of its associated signal module 2614.
[0292]
[0382] In 4304, the DSP delay equalizer 2806 receives the processing delay of the DSP 2904 from each of the one or more signal modules 2614.
[0293]
[0383] In 4306, the DSP delay equalizer 2806 determines the maximum processing delay among one or more received processing delays.
[0294]
[0384] In 4308, the DSP delay equalizer 2806 sets the maximum processing delay for each DSP 2904 of one or more signal modules 2614. For example, the DSP delay equalizer 2806 can use an API to set the processing delay for each DSP 2904 of each signal module 2614. Accordingly, each DSP 2904 can be designed to process packets using its digital processing capabilities and output processed packets to the output packet queue 2906 at the end of the maximum processing delay. In some embodiments, if a DSP 2904 completes processing a packet using its digital processing capabilities before the end of the maximum processing delay, it can block its output to the output packet queue 2906.
[0295]
[0385] Figure 44 is a flowchart of a method 4400 for receiving one or more signal samples for one or more signals using an input module 2604, according to several embodiments.
[0296]
[0386] Method 4400 will be described with reference to Figure 26. However, Method 4400 is not limited to its embodiments.
[0297]
[0387] In 4402, the input module 2604 receives signal samples for a base signal from a hardware device (e.g., electrodes attached to a patient) or data stored in a computer file. For example, the computer file may contain previously recorded sessions of signal samples received from the hardware device. As will be understood by those skilled in the art, the input module 2604 can receive signal samples for multiple base signals simultaneously.
[0298]
[0388] In 4404, the input module 2604 dispatches the received signal sample to the packetizer 2606.
[0299]
[0389] Figure 45 is a flowchart of a method 4500 that uses a packetizer 2606 to convert one or more signal samples into one or more packets, according to several embodiments.
[0300]
[0390] Method 4500 will be described with reference to Figure 26. However, Method 4500 is not limited to its embodiments.
[0301]
[0391] In 4502, the packetizer 2606 receives one or more signal samples from the input module 2604.
[0302]
[0392] In 4504, the packetizer 2606 can optionally preprocess one or more signal samples. For example, the packetizer 2606 may preprocess one or The binary values of multiple signal samples can be converted into their corresponding physical values. As those skilled in the art will understand, the packetizer 2606 can perform various other types of preprocessing.
[0303]
[0393] In 4506, the packetizer 2606 generates packets containing one or more signal samples for a given base signal. The packetizer 2606 can store a predefined number of signal samples in a packet. In some embodiments, the packetizer 2606 can use a timer 2605 to ensure that each packet contains the same number of signal samples. Specifically, the packetizer 2606 can store signal samples received from the input module 2604 in packets until the timer 2605 is triggered.
[0304]
[0394] In 4508, the packetizer 2606 assigns a tag to the generated packet. The tag can correspond to the period during which one or more signal samples in the packet were received. The packetizer 2606 can assign a new tag to each subsequent packet. For example, the packetizer 2606 can initially generate a packet containing 16 signal samples for a given base signal. In this case, the packetizer 2606 can store the first set of signal samples in the packet with the tag 0. The packetizer 2606 can store a second set of signal samples in the packet with the tag 15. The packetizer 2606 can store subsequent sets of signal samples in the packet with tags such as 31, 47, 64, etc.
[0305]
[0395] Figure 46 is a flowchart of a method 4600 for dispatching a packet containing one or more signal samples to a queuing module 2608, according to several embodiments.
[0306]
[0396] Method 4600 will be described with reference to Figure 26. However, Method 4600 is not limited to its embodiments.
[0307]
[0397] In 4602, the packetizer 2606 determines the base signal associated with the newly generated packet.
[0308]
[0398] In 4604, the packetizer 2606 determines the queue 2702 of the queuing module 2608 associated with the determined base signal. The packetizer 2606 can determine, using a lookup table, that the queue 2702 is associated with the determined base signal.
[0309]
[0399] At 4606, the packetizer 2606 dispatches a packet containing one or more signal samples to the determined queue 2702.
[0310]
[0400] Figure 47 is a flowchart of a method 4700 for dispatching packets from a queuing module 2608 to a signaling module 2614 associated with those packets, according to several embodiments.
[0311]
[0404] Method 4700 will be described with reference to Figure 26. However, Method 4700 is not limited to its embodiments.
[0312]
[0402] In 4702, the packet dispatcher 2610 continuously scans queue 2702 in the queuing module 2608.
[0313]
[0403] In 4704, packet dispatcher 2610 detects a new packet in queue 2702.
[0314]
[0404] In 4706, the packet dispatcher 2610 determines one or more signaling modules 2614 in the global signaling table 2612 that are designed to process new packets. A new packet can be dispatched to multiple signaling modules 2614 (for example, multiple copies or "instances" of the packet) so that the base signals associated with that packet can be processed simultaneously using the different digital processing capabilities of the signaling modules 2614.
[0315]
[0405] In some embodiments, the packet dispatcher 2610 can use a global signaling table 2612 to determine one or more signaling modules 2614 designed to process an instance of a new packet. For example, the global signaling table 2612 may be a fixed-size array. Each element of the array can be associated with a given base signal, and therefore with a given queue 2702. Furthermore, each element of the array may be the fixed-size array itself. Each element of this subarray can be associated with a given signaling module 2614. Thus, the packet dispatcher 2610 can determine one or more signaling modules 2614 designed to process a new packet by examining the corresponding element in the subarray associated with the base signal of the new packet.
[0316]
[0406] In some other embodiments, the packet dispatcher 2610 may use a lookup table to determine one or more signaling modules 2614 that are designed to process new packets. Specifically, the lookup table may map queues 2702 to one or more signaling modules 2614.
[0317]
[0407] In 4706, the packet dispatcher 2610 dispatches a new packet to one or more signaling modules 2614 determined in the global signaling table 2612 for processing. Specifically, the packet dispatcher 2610 inserts the new packet into the input packet queue 2902 of the determined one or more signaling modules 2614.
[0318]
[0408] Figure 48 is a flowchart of a method 4800 for processing packets using a packet-related signaling module 2614, according to several embodiments.
[0319]
[0409] Method 4800 will be described with reference to Figure 26. However, Method 4800 is not limited to its embodiments.
[0320]
[0410] In 4802, the DSP 2904 detects whether a new packet is available in the input packet queue 2902 of the signaling module 2614. In some embodiments, the DSP 2904 can scan the input packet queue 2902 for new packets to be processed. In some other embodiments, the DSP 2904 can receive notification that a new packet is available in the input packet queue 2902.
[0321]
[0411] In 4804, the DSP2904 acquires a new packet from the input packet queue 2902 of the signal module 2614.
[0322]
[0412] In the 4806, the DSP2904 performs its associated digital signal processing functions. The DSP2904 processes new packets using its digital processing capabilities. Specifically, the DSP2904 can apply its digital processing capabilities to one or more signal samples in a packet. In some embodiments, the DSP2904 can control how it processes packets using its digital processing capabilities based on one or more signal processing parameters designed for the DSP2904.
[0323]
[0413] In 4808, the DSP2904 outputs processed packets to the output packet queue 2906. In some embodiments, the DSP2904 may output processed packets to the output packet queue 2906 based on its designed maximum processing delay.
[0324]
[0414] Figure 49 is a flowchart of a method 4900 for displaying processed packets on a display screen using a display module 2618, according to several embodiments.
[0325]
[0415] Method 4900 will be described with reference to Figure 26. However, Method 4900 is not limited to its embodiments.
[0326]
[0416] In 4902, the display module 2618 determines one or more signal modules 2614 to display processed packets. In some embodiments, the display module 2618 can determine one or more signal modules 2614 to display processed packets by maintaining references to the output packet queue 2906 of one or more signal modules 2614. The display module 2618 can store the references in the local signal table 3002.
[0327]
[0417] At 4904, the display module 2618 detects that a new packet is available in one of the output packet queues 2906 of the determined signal modules 2614.
[0328]
[0418] At 4906, the display module 2618 receives a new packet from one of the output packet queues 2906 of the determined signal modules 2614.
[0329]
[0419] In step 4908, the display module 2618 determines the tag associated with the new packet.
[0330]
[0420] In 4910, the display module 2618 receives a new packet from another output packet queue 2906 that matches the confirmed tag.
[0331]
[0421] In 4912, the display module 2618 simultaneously displays new packets received by one or more determined signal modules on the display screen. The display module 2618 synchronizes the display of signals associated with new packets in order to display new packets with the same tag.
[0332]
[0422] Methods 4000, 4100, 4200, 4300, 4400, 4500, 4600, 4700, 4800, and 4900 can be carried out by processing logic that may include hardware (e.g., circuits, dedicated logic circuits, programmable logic circuits, microcode, etc.), software (e.g., instructions to be executed on a processing device), or a combination thereof. It should be understood that not all steps may be necessary to carry out the disclosures provided herein. Furthermore, as will be understood by those skilled in the art, some of the steps may be carried out simultaneously or in a different order than those shown in Figures 40 to 49.
[0333]
[0423] In some embodiments, the DSP2904 can be based on a notch filter. Electrophysiology laboratories with numerous instruments may tend to have substantial power line frequencies and harmonics (e.g., noise) that interfere with cardiac recordings. In North America, this can primarily be 60 Hz + harmonics. Figure 50 shows an example of a signal (e.g., a triangular spike 5002) superimposed with 60 Hz noise 5004 according to some embodiments.
[0334]
[0424] To obtain accurate cardiac recordings, it is often desirable to remove noise while preserving the target signal. Conventional methods for removing 60Hz noise include using a notch filter with zero transmission at 60Hz. Figure 51 shows an example of a conventional method for removing 60Hz noise using a notch filter with zero transmission at 60Hz (single notch) 5102, according to several embodiments.
[0335]
[0425] Figure 52 shows an example of the results of applying the conventional filter shown in Figure 51 according to several embodiments. As shown in Figure 52, the 60Hz signal is removed from the input signal 5202 to produce the filtered signal 5204. However, conventional filters can have several problems. For example, after a large spike 5206, conventional filters may introduce overshoot and ringing (e.g., transient response) into the signal. This overshoot and ringing may be filter artifacts and not part of the original input signal. This can result in less accurate signal recording.
[0336]
[0426] Furthermore, conventional 60Hz notch filters may not reduce any 60Hz harmonics. For example, as shown in Figure 53, if interference in the input signal 5302 is evaluated at both 60Hz and 180Hz, the 180Hz harmonic may still be present at the output of a conventional filter. Figure 53 shows an example of a 180Hz harmonic still present in the filtered signal 5304 at the output of a conventional filter in Figure 51, according to several embodiments.
[0337]
[0427] Therefore, as shown in Figure 53, conventional notch filters may have two problems. First, conventional notch filters may introduce overshoot and ringing into the signal. Second, conventional notch filters may not reduce any of the higher-level harmonics.
[0338]
[0428] In some embodiments, the DSP2904 can apply a notch filter that reduces not only first harmonics but also higher levels of harmonics without introducing overshoot and ringing into the signal. The DSP2904's notch filter can solve the above-mentioned technical problems of conventional notch filters by extracting interference noise and subtracting it from the noisy signal. This makes it possible to remove interference without generating artifacts (e.g., overshoot and ringing) associated with conventional notch filters. The DSP2904's notch filter can extract the original data by duplicating one cycle of the interference signal in a separate buffer (also referred to as a cycle buffer, noise buffer, or data buffer) and subtracting it from the noisy signal. Since power line frequency noise can be constant or approximately constant, the DSP2904's notch filter can refine the estimate over time using some variation of averaging. Since the frequency can be known, the buffer size can be determined in advance. Furthermore, a buffer that stores exactly one cycle can also store integer higher frequency harmonics that can be subtracted from the noisy data. Figure 54 shows an example of notch filtering of the DSP2904 for signals containing 60Hz and 180Hz noise in several embodiments. Since the power line frequency noise is constant, one cycle of interference 5402 is replicated. Each cycle 5404 of the continuous cycle in the input signal can be subtracted.
[0339]
[0429] With a noise level of 60 Hz and a sample rate of 2000 samples / second, the buffer can store 33 and a half samples. Since the buffer can have an integer number of samples, the notch filter of the DSP2904 can be selected to use 100 samples to store exactly three cycles of 60 Hz. Figure 55 shows an example of the notch filter of the DSP2904 using 100 samples of the input signal 5502 to store exactly three cycles of 60 Hz 5504, according to several embodiments.
[0340]
[0430] To accumulate steady-state noise in a buffer, data can be collected during the "quiet period" of the waveform. As will be understood by those skilled in the art, the quiet period may be a period in the input signal that has no large spikes or edges. The quiet period can be determined by calculating the gradient of the signal. Figure 56 shows an example of a notch filter of the DSP2904 for calculating the quiet period in an input signal 5602 according to several embodiments. During the quiet period 5606, three cycles of noise data (interference) 5604 can be collected in the buffer. By averaging the subsequent cycles 5608, 5610, and 5612, an accurate replica of the interference 5604 is constructed. Since the cycle time is constant for cycles 5606, 5608, 5610, and 5612, the fundamental frequency and harmonic frequencies of one cycle are accumulated. Cycles of other frequencies average out to zero.
[0341]
[0431] For each new point sampled from incoming data, a decision can be made to determine whether it is in a "quiet period" of the signal. The quiet period can be determined by calculating the gradient of the signal. If the gradient exceeds a threshold, it can be determined that the quiet period has begun. If a new point is in a quiet period, it can be averaged with the previously stored data at that location in the buffer. As time progresses, this averaging process can accumulate copies of noise, which can be subtracted from the signal containing the noise. For those locations that are not in a quiet period, the buffer cannot be updated, but the accumulated signal can still be subtracted. Figure 57 shows an example of a notch filter in the DSP2904 by accumulating three cycles of noise copies in a buffer at each of the quiet periods 5702, 5704, 5706, and 5708, and subtracting them from the signal containing the noise, according to several embodiments. Since the contents of buffers 5710, 5712, 5714, and 5716 match the noise data during quiet times 5702, 5704, 5706, and 5708, respectively, the noise can be modeled more accurately, and when subtracted, the noise component of the display signal can be significantly reduced.
[0342]
[0432] As each sample is added to the buffer, averaging can result in a filter with peaks at power line frequency 5802 and all harmonics (5804, 5806, etc.). This allows for the selective accumulation of power line frequency and all harmonics, while excluding all other frequencies, thereby enabling the DSP2904's notch filter to subtract only fixed-frequency additional noise. Figure 58 shows an example of the results of the DSP2904's notch filter or buffer filter according to several embodiments. To produce the buffer filter shown in Figure 58, for example, the buffer is updated by adding 5% new samples to 95% of the accumulated value. In the specific circumstances of the embodiments, other combined percentages of each new sample and accumulated value can be combined.
[0343]
[0433] Figure 59 is a flowchart of method 5900 for notch filtering noise from an input signal, according to several embodiments. Method 5900 will be described with reference to Figure 29. However, method 5900 is not limited to its embodiments.
[0344]
[0434] In 5902, the DSP2904 includes noise having a first harmonic frequency. Furthermore, it accesses an input signal that contains noise. The frequency of the noise in the input signal may be substantially constant.
[0345]
[0435] In 5904, the DSP2904 determines the quiescent period in the input signal. The DSP2904 can determine the quiescent period by calculating the gradient of the input signal. Then, the DSP2904 can determine the existence of the quiescent period based on whether the calculated gradient falls below a threshold.
[0346]
[0436] In the 5906, during the quiescent period, the DSP2904 stores samples of noise from the input signal in a buffer. The size of the buffer can be based on the frequency of the noise in the input signal.
[0347]
[0437] As part of the storage process, the DSP2904 can generate an averaged sample by averaging a sample of the input signal with the corresponding sample of noise in a buffer. The DSP2904 can then replace the corresponding sample of noise in the buffer with the averaged sample.
[0348]
[0438] In the 5908, the DSP2904 generates a filtered signal by subtracting a single-cycle noise in the buffer from the input signal. Subtraction allows for the removal of the major and second harmonic frequencies from the input signal while avoiding the introduction of transient responses (e.g., ringing) in the filtered signal. The first harmonic frequency can be 60 Hz, and the second harmonic frequency can be 120 Hz or 180 Hz.
[0349]
[0439] In step 5910, the DSP2904 refines the filtered signal by repeating steps 5904-5908. As those skilled in the art will understand, the sample can be anywhere in the cycle. Furthermore, the sample does not need to constitute a single cycle. In other words, the DSP2904 can buffer the noise of multiple cycles of the input signal.
[0350]
[0440] In some embodiments, the DSP2904 can be based on a high-pass filter. Certain areas of the heart generate very low-amplitude, high-frequency signals that may be targeted during cardiac procedures. Physicians often want these signals highlighted so they can reconsider if murmurs and other larger cardiac signals are present.
[0351]
[0441] This can be achieved using a high-pass filter. Figure 60 shows an example of a conventional high-pass filter 6002 according to several embodiments. In this case, the 3dB frequency 6004 of the conventional high-pass filter may be approximately 200Hz to suppress low frequencies. Furthermore, since the target frequency often exceeds the power line frequency (e.g., 60Hz), conventional high-pass filtering techniques may include placing a notch 6006 therein to eliminate interference from potentially large power line interference.
[0352]
[0442] However, a typical signal from an intracardiac catheter may include high-frequency signals from the cardiac conduction region, along with sharp local spikes from various sources. Figure 61 shows an example of a signal that includes both high-frequency signals from the cardiac conduction region and sharp local spikes from various sources, according to several embodiments. As shown in Figure 61, there are sharp spikes 6102 that resemble local near-field impulses (e.g., QRS, local spikes, transient events, etc.) and short bursts 6104 of high-frequency (e.g., 300 Hz) cardiac signals.
[0353]
[0443] Figure 62 shows an example of the resulting output from filtering the signal in Figure 61 using the high-pass filter in Figure 60, according to several embodiments. As shown in Figure 62, the low-frequency components (e.g., baseline fluctuations) are removed, and the high-frequency cardiac signal 6202 is highlighted as needed. However, the transient response of the high-pass filter may leave undesirable impulses (e.g., artifacts) 6204 and some ringing in the output. In a complex and larger waveform, these impulses 6204 can easily be confused with the high-frequency cardiac signal 6202 by a physician. This poses a problem for accurate diagnosis and treatment.
[0354]
[0444] In some embodiments, the DSP2904 can be based on a high-pass filter that removes impulses while allowing the target high-frequency signal to pass through. To remove impulses, the input signal can be monitored for large deviations and high signal gradients (e.g., derivatives). If these conditions exist, the output can be disabled for a certain period before and after their occurrence, thereby preventing transients from appearing in the displayed waveform. Figure 63 shows an example of the resulting output of filtering the signal in Figure 61 using a high-pass filter that removes impulses 6302 while allowing the target high-frequency heart signal 6304 to pass through, according to some embodiments.
[0355]
[0445] Figure 64 is a flowchart of Method 6400, a method for high-pass filtering noise from an input signal, according to several embodiments. Method 6400 will be described with reference to Figure 29. However, Method 6400 is not limited to its embodiments.
[0356]
[0446] In 6402, the DSP2904 accesses an input signal containing noise and the target high-frequency signal. Applications of the DSP2904 include performing rapid conduction tissue recognition filtering to identify, for example, Purkinje fibers (i.e., highly isotropic / low anisotropic portions) and preferred conduction pathways in affected tissue from myocardial structures. In such applications, the DSP2904 can access, for example, the Purkinje signal (i.e., the target high-frequency signal) in the presence of noise. The DSP2904 can filter this input signal using a notch filter.
[0357]
[0447] Artifacts, once recognized in the target signal, can be clearly introduced and characterized, thereby allowing for the application of direct automation of filtering, where these diagnosed signals are used as templates to subtract / filter or otherwise process the signals from the entire extracted electrophoresis. For example, the system can record signals with and without irrigation through the catheter, under certain catheter contact and catheter stability conditions. This difference may represent an artifact, which can then be automatically characterized, a template created, and that template can be used so that the system's filtering and addition techniques can remove the artifact. As those skilled in the art will understand, such systems are beneficial when employed in existing defibrillators as well as in subcutaneous implantable cardioverter-defibrillators (ICDs).
[0358]
[0448] In the 6404, the DSP2904 generates a filtered signal by high-pass filtering the input signal.
[0359]
[0449] In the 6406, the DSP2904 isolates artifacts related to noise in the filtered signal from the target high-frequency signal. For example, the DSP2904 can isolate the impulse response.
[0360]
[0450] The DSP2904 calculates the gradient of the filtered input. Artifacts can be isolated. The DSP2904 can then determine the presence of artifacts based on whether the calculated gradient exceeds a threshold. The DSP can characterize the artifacts with an artifact template. The DSP2904 can optionally select filters based on the isolated artifacts so that the artifact template can be applied as a filter.
[0361]
[0451] In the 6408, the DSP2904 disables the filtered signal for a certain period before and after the isolated artifact. The DSP2904 can optionally perform this disabling using a selected filter. This disabling removes the isolated artifact and allows the target high-frequency signal to pass through. The DSP2904 can buffer the filtered signal for a certain period before and after the isolated artifact.
[0362]
[0452] In some embodiments, the DSP2904 can perform pattern (or signal characteristic) matching. Pattern matching of cardiac signals can be based on some version of correlation. For example, the correlation may be a statistical correlation function or mean absolute deviation.
[0363]
[0453] The correlation function (CF) can be specified by Equation 1.
number
[0364]
[0454] The mean absolute deviation function (MAD) can be specified by Equation 2.
number
[0365]
[0455] In surface ECGs, there are often 12 leads in a set. In pace-matching applications, all 12 leads need to be correlated with all 12 leads of a reference heartbeat. The reference heartbeat may be the one taken when an abnormal heartbeat is observed and compared to the pacing heartbeat from the catheter during electrophysiological treatment. In other cases, only a subset of leads needs to be correlated. For correlation functions, a perfect match in shape can be +1, an exact opposite can be -1, and there may be no measure of amplitude similarity. For MAD functions, a perfect match can be 0, an exact opposite can be 1, and the difference in amplitude... This could result in a less satisfactory agreement.
[0366]
[0456] To compare multiple leads, it may be necessary to establish some measure of similarity. This could be the mean, median, or an extension of Equation 1 or 2, which involves adding the numerator and denominator for all leads in the set. Furthermore, leads with relatively large amplitudes or a predetermined range of heartbeats (e.g., Q waves) that represent features to be emphasized may be given relatively larger weights.
[0367]
[0457] In all comparisons, the induction can be normalized to have a 0DC offset. This is possible because only the shape (and amplitude) is important in the comparison.
[0368]
[0458] In some embodiments, a vertical caliper can be used to select a pattern (or signal characteristic). The vertical caliper may be a GUI selection widget. Figure 65 shows an example of a review window 6500 that uses vertical calipers 6502, 6504 to select a range of data (typically one heartbeat) according to some embodiments.
[0369]
[0459] Next, the selected pattern can be saved as a reference heartbeat (or known signal pattern). Figure 66 shows an example of saving a selected pattern as a reference heartbeat according to several embodiments. The Save New Pattern window 6600 shown in Figure 66 allows the user to look at previously saved heartbeats (e.g., known signal patterns) 6602 and determine whether the newly identified heartbeat is unique enough to be saved separately from the previously saved heartbeats. Once a heartbeat is stored, it can be assigned a unique name 6604, a color 6606, and / or a description (i.e., a comment) 6608.
[0370]
[0460] When a user wishes to start a search, they click the Select Patterns button 6510 in the review window 6500 in Figure 65. This allows you to open a window of selectable search patterns. Figure 67 shows an example of the Select Patterns to Search window 6700 in several embodiments. Select Patterns to Search window U6700 can display a scrollable list 6710 of all stored patterns. A checkbox 6720 to the left of each list item allows the user to select the associated pattern. The selection may remain valid until the user decides to change them. When the user clicks on each pattern in list 6710, the corresponding signal can be displayed below the list box in window 6730. Window 6730 can also display a field that allows the user to enter a confidence threshold (also referred to as the pattern detection threshold 6740) that can be used to detect patterns. For example, in Figure 67, the pattern detection threshold 6740 is set to 80%.
[0371]
[0461] The user can enable the search by selecting the pattern to search for, clicking OK 6750, and then clicking the Enable / Disable Patterns search button 6512 to start the search. This button 6512 can be enabled in the review window 6500 shown in Figure 65. After clicking this button, the search for patterns begins, and heart rates that match the reference heart rate (for example, those with a confidence level equal to or greater than the selected confidence threshold) are displayed in the review window 6500. The found patterns can be displayed in two different modes in the review window 6500 shown in Figure 65: the summary view and the detail view. As shown in the review window 6800 in Figure 68, the user can click the Summary button. These two modes can be toggled using 6802 and Detail 6804.
[0372]
[0462] In the overview view, signal segments displayed in the review window that match a pattern can be highlighted with a color associated with each pattern. Multiple patterns can overlap on the same segment of a signal. In the overview view, overlapping areas can be displayed in different colors to make the patterns within each segment more recognizable and distinguishable.
[0373]
[0463] Figure 68 shows an example of a pattern search overview view in the review window of Figure 65, where multiple matching patterns are displayed according to several embodiments. As shown in Figure 68, in the review window 6800, four parts 6806, 6808, 6810, and 6812 of the body surface ECG signal are highlighted. In this example, the two left parts 6806 and 6808 are displayed in two colors (or line types), which can mean that the patterns of these parts overlap. The two right parts 6810 and 6812 are displayed in the color assigned to pattern P1, which indicates that only the P1 pattern was found in those parts.
[0374]
[0464] Figure 69 shows an example of the pattern search overview view 6900 in the review window of Figure 68, in which a single matching pattern is displayed while other patterns are hidden, according to several embodiments. When a matched pattern segment is displayed, a small window 6910 can be displayed on the right. This window allows the user to show or hide the matching portion associated with each found pattern. In its initial state, all found patterns can be checked. When the user unchecks the checkboxes 6912 and 6914 next to each pattern name, the corresponding highlighted portion is hidden. As shown in Figure 69, the matching portions 6810 and 6812 associated with pattern P1 6916 are hidden. Therefore, the monochrome portions 6810 and 6812 in Figure 68, which are on the right and match only pattern P1, are not displayed in Figure 69. However, the left portions 6806 and 6808, where patterns P1 and P4 overlapped, are now displayed in Figure 69 in the color associated with pattern P4 6918.
[0375]
[0465] In the detail view, pattern details can be displayed one segment at a time. The detail view can be enabled by selecting detail 6804 in the review signal 6800 in Figure 68. In the detail view, the actual pattern can be displayed on the matching segment using the color assigned to that pattern. Figure 70 shows an example of a detail view for a signal in the review window of Figure 65 according to several embodiments.
[0376]
[0466] As shown in Figure 70, the detail view 7000 can display pattern details one segment at a time. For each segment, if multiple patterns overlap, the pattern with the highest confidence factor can be displayed first. However, the user can choose to view other overlapping patterns (e.g., those with lower confidence values) by clicking their corresponding checkboxes 7002, 7004 in the detail view list 7006. In this case, the signals displayed in the detail view 7000 can be automatically changed to reflect the newly selected patterns. For example, as shown in Figure 70, pattern P1 7008 has the highest confidence value (e.g., 87.0%) and is therefore displayed first.
[0377]
[0467] In the detailed view, the confidence factor per lead can be displayed using the horizontal bars in the Confidence Factor Per Lead table 7010, as shown in Figure As shown in 70, actual confidence values can be provided above those bars. For example, lead I7012 shows a confidence value of 79.6%. Confidence values exceeding the confidence level set by the user (for example, if a searched pattern is selected) can be displayed in green, and values below this threshold can be displayed in orange, visually indicating whether the confidence level for each individual lead meets the user's desired threshold. When the user clicks on any lead name in the lead-by-lead confidence coefficient table 7010, the matching portion in the corresponding pattern and signal traces is displayed below the lead-by-lead confidence coefficient table 7010. This can be displayed within window 7014. Below this window, there may be two buttons that allow the user to change the time 7016 and amplitude scale 7018 to see the shape details of the displayed signal more precisely. If the selected time 7016 or amplitude scale 7018 makes the signal partially visible, a scroll bar can be automatically displayed to allow the user to access any part of the signal.
[0378]
[0468] The detail view 7000 can also highlight signal segments and associated matching patterns, which are displayed using parentheses 7020. This allows the user to easily identify the portion of the signal shown in the detail view 7000. The matching confidence coefficient 7022 for that pattern can also be displayed alongside one of the parentheses.
[0379]
[0469] Figure 71 shows a window 7100 as an example of having pattern matching confidence values (confidence coefficient 7102 per lead) provided by inductions, according to several embodiments. As shown in Figure 71, leads V1 7104 and V2 7106 are below the confidence threshold and are shown in orange.
[0380]
[0470] The disclosed system also allows for the use of the concept of creating templates for predetermined artifact generation events in pattern matching, as described for the method in Figure 64. For example, using patterns of valve motion artifacts associated with unipolar signals collected above and below the valve and within the coronary artery, a pattern template can be created that allows the operator to immediately know whether the catheter is above the valve, below the valve, or within the coronary artery. When the coronary artery profile in the pattern template is met, the system can respond, for example, by not allowing energy delivery during the ablation procedure.
[0381]
[0471] Figure 72 is a flowchart of the pattern matching method 7200 according to several embodiments. The method 7200 will be described with reference to Figure 29. However, the method 7200 is not limited to its embodiments.
[0382]
[0472] In 7202, the DSP2904 accesses the input cardiac signal.
[0383]
[0473] In the 7204, the DSP2904 matches a portion of the input cardiac signal to a known signal pattern. This known signal pattern can be acquired during a preceding or current patient procedure and stored in a pattern template. It is also possible to store the known signal pattern in a database.
[0384]
[0474] The DSP2904 can match a portion of the input cardiac signal to a known signal pattern based on a correlation function. For example, the DSP2904 can match a portion of the input cardiac signal to a known signal pattern based on the mean absolute deviation (MAD) function. The DSP2904 can also match a portion of the input cardiac signal to a known signal pattern based on a confidence value. It is also possible to match it with a number pattern.
[0385]
[0475] In 7206, the display module 2618 displays an indication of the degree of match. This indication can specify where cardiac pacing should be performed.
[0386]
[0476] Figure 73 is a flowchart of the pattern matching method 7300 according to several embodiments. The method 7300 will be described with reference to Figure 29. However, the method 7300 is not limited to its embodiments.
[0387]
[0477] In 7302, the DSP2904 accesses the input cardiac signal.
[0388]
[0478] In 7304, DSP2904 accesses the detection threshold.
[0389]
[0479] In the 7306, the DSP2906 matches a portion of the input cardiac signal to known signal patterns based on a detection threshold. These known signal patterns can be acquired during preceding or current patient treatment. The known signal patterns can be stored in a database.
[0390]
[0480] The DSP2904 can match a portion of the input cardiac signal to a known signal pattern based on a correlation function. For example, the DSP2904 can match a portion of the input cardiac signal to a known signal pattern based on the mean absolute deviation (MAD) function.
[0391]
[0481] The DSP2904 can match a portion of the input cardiac signal with a known signal pattern based on the weighted region of the known signal pattern. The DSP2904 can perform a first matching of a portion of the input cardiac signal with a known signal pattern. The DSP2904 can determine a first confidence value based on the first matching. The DSP2904 can perform a second matching of a portion of the input cardiac signal with a known signal pattern. The DSP2904 can determine a second confidence value based on the second matching. The DSP2904 can create an average confidence value by averaging the first and second confidence values. The DSP2904 can then determine that the average confidence value exceeds the detection threshold.
[0392]
[0482] In 7308, the display module 2618 displays highlighted portions of the input cardiac signal based on matching. The display module 2618 can, for example, display highlighted portions of the input cardiac signal based on colors associated with known signal patterns.
[0393]
[0483] In some embodiments, the DSP2904 can perform delayed potential and early excitation detection. By interpolating signal data from early excitation sites, which are displayed independently of normal and delayed potential filters, with signal data from detected delayed excitation sites, the system can infer conduction delay sites. These sites (or regions) can be block-highlighted by any compatible 3D mapping system, thereby allowing physicians to guide catheter placement, record slow conduction at these sites, and target them for ablation. These features are extremely difficult, if not impossible, to achieve in systems that saturate when applying gain to small signals, and therefore, slow conduction sites may inherently remain invisible to physicians.
[0394]
[0484] Embodiments of this specification interpolate data from early excitation sites to data from detected delayed excitation sites and display the data independently of conventional filters and delayed potential filters. The system benefits from its high dynamic range. These embodiments can detect delayed potentials and early excitations in the main signal display window in real time (e.g., live) and during session playback. By clicking the "create and manage searches" button in the main signal display window, the user can create search criteria for delayed potentials or early excitations, launch searches, and manage existing searches.
[0395]
[0485] Figure 74 shows an example of a search definition window 7400 for creating and managing late potential and early excitation searches according to several embodiments. To add a late potential search to the main signal display window, the user can click the "Add Late Potentials Search" button 7402 within the search definition window (the Search Definitions window 7400 in Figure 74). In response, the late potential detection configuration window can be displayed, allowing the user to define various search parameters. Figure 75 shows an example of a late potential detection configuration window 7500 for defining various search parameters for late potentials according to several embodiments.
[0396]
[0486] A user can create at least one pattern for performing a delayed potential search. A user can specify various delayed potential search parameters that enable different types of searches. As shown in Figure 75, a user can define one or more of the following parameters: name of the search (7502), selection of the heart rate pattern used for the search (7504), reference point for starting the search (7506), selection of the ECG lead used for heart rate detection (7508), selection of the intracardiac lead used for delayed potential detection (7510), search interval using the start time and length from the pattern reference (7512), heart rate detection confidence threshold as a percentage (e.g., 80%) (7514), selection of the delayed potential detection confidence threshold as a percentage (e.g., 80%) (7516), and selection of the delayed potential amplitude threshold (e.g., 0.015mV) (7518). As those skilled in the art will understand, a user can define various other patterns.
[0397]
[0487] Once all parameters are defined, the search can be initiated. When delayed potentials are detected, the signal display window can indicate the location of the delayed potentials along with their detection confidence levels. Figure 76 shows an example signal display window 7600 showing the locations of delayed potentials 7602, 7604, 7606, 7608, and 7610 along with their detection confidence levels, according to several embodiments. The review window can also display all detected delayed potentials under the search results tab. Newly created delayed potential searches can be listed within the search definition window (for example, the search definition window 7400 in Figure 74). Newly created delayed potential searches can be listed under the currently defined search section within the search definition window.
[0398]
[0488] The user can add early excitation searches in a similar manner to delayed potential searches. The user can specify various early excitation search parameters that enable different types of searches. These parameters may be equivalent to the delayed potential search parameters. The difference is that searches may occur at search intervals defined before the baseline. Figure 77 shows an example of an early excitation detection configuration window 7700 that defines various search parameters for early excitation (similar to those described in Figure 75) according to several embodiments.
[0399]
[0489] Once all parameters are defined in the early excitation detection configuration window 7700, the search can be initiated. When early excitation is detected, the signal display window can show the location of the early excitation, along with their detection confidence and duration. Figure 78 shows: An example signal display window 7800 is shown, indicating the locations of early excitations 7802, 7804, and 7806 along with their detection confidence levels, according to several embodiments. The review window can also display all detected early excitations under the search results tab. Newly created early excitation searches can be listed within the search definition window (for example, the search definition window 7400 in Figure 74). Newly created early excitation searches can be listed under the currently defined search section within the search definition window.
[0400]
[0490] The user can manage predefined delayed potential and early excitation searches using the search definition window. Figure 79 shows an example of a search definition window 7900 for managing predefined delayed potential and early excitation searches according to several embodiments.
[0401]
[0491] In the search definition window 7900, all active searches can be listed in the Currently Defined Searches window 7902, and the user can run, stop, delete, or modify these searches. If a search is stopped, the user can restart the search by clicking the Run button 7904. For example, as shown in Figure 79, search EA1 is stopped 7906, and search LP1 is running 7908. In this case, the user can restart the EA1 search and stop the LP1 search 7910, or use other options (for example, delete 7912 and modify 7914).
[0402]
[0492] Figure 80 is a flowchart of method 8000 for detecting early excitation or delayed potential according to several embodiments. Method 8000 will be described with reference to Figure 29. However, method 8000 is not limited to its embodiments.
[0403]
[0493] In 8002, the first DSP2904 accesses the first cardiac signal associated with the body surface lead.
[0404]
[0494] In 8004, the first DSP2904 matches the heartbeat of the first cardiac signal to a known cardiac pattern. The first DSP2904 can match the heartbeat of the first cardiac signal to a known cardiac pattern based on a correlation function. The first DSP2904 can match the heartbeat of the first cardiac signal to a known cardiac pattern based on, for example, the mean absolute deviation (MAD) function. The first DSP2904 can match the heartbeat of the first cardiac signal to a known cardiac pattern based on a confidence value. The confidence value can be defined by the user.
[0405]
[0495] In 8006, the second DSP2904 searches for early excitation or delayed potentials in the second cardiac signal for a certain period before and after the matched heartbeat. This period may be a user-defined period.
[0406]
[0496] The second DSP2904 can search for a buffer containing the portion of the second cardiac signal with respect to early excitation or delayed potential. The second DSP2904 can search for early excitation based on amplitude threshold.
[0407]
[0497] Using either early excitation or delayed potentials, the system can interpolate signal data from the catheter at the early excitation site with signal data at the delayed potential site. The system can display this signal data independently of normal and delayed potential filters. Using the interpolated signal data, the system can infer the conduction delay site. The system can also be combined with a 3D mapping system to use the interpolated signal data at a site to guide further catheter placement, record slow conduction at that site, or target that site for ablation. .
[0408]
[0498] In some embodiments, the display module 2618 can display one or more signals using a waterfall view (for example, the waterfall views in Figures 37A and 37B). The waterfall view window can vertically stack heartbeats that match a selected pattern of a given ECG lead, and alongside each detected heartbeat, it can display user-selected intracardiac signals. These user-selected intracardiac signals can be displayed at user-defined intervals relative to a reference point within the heartbeat pattern.
[0409]
[0499] To set the parameters for the waterfall view, the user can click the "Create Waterfall View Window" button located on the main signal display toolbar. A waterfall display configuration window can be displayed. Figure 81 shows an example of a waterfall display configuration window 8100 according to several embodiments.
[0410]
[0500] As shown in Figure 81, the user can define one or more of the following parameters: The user can select a heart rate pattern 8102 to search for (for example, from already saved heart rate patterns used in the waterfall view). The user can define a reference point 8104 in the heart rate pattern used for the display interval. If a reference point has not yet been selected, the user can add one by clicking the heart rate pattern display window located below the list of heart rate patterns. Similarly, the position of an existing reference point can be changed by clicking the heart rate pattern display window. The user can select a surface ECG lead 8106 for heart rate detection. The user can define a display interval 8108 for the ECG lead (for example, a start point and length relative to the pattern reference point). The user can select an intracardiac channel 8110 for searching. The user can define a display interval 8112 for the intracardiac lead (for example, a start point and length relative to the pattern reference point). The user can also select a vertical scroll mode 8114, such as time or heart rate.
[0411]
[0501] Figure 82 shows an example of a waterfall view 8200 using time mode according to several embodiments. When the vertical scroll mode 8114 is set to time mode, matching signals can be scrolled up continuously over time. Therefore, when no heartbeats matching the selected pattern are detected, time mode can show the gaps 8202 between heartbeats. In time mode, the last heartbeat timestamp 8204 can be shown in the lower left corner of the window.
[0412]
[0502] When vertical scrolling mode 8114 is set to heart rate mode, the automatic vertical scrolling of the waterfall view window can be disabled, and the heart rate can only be scrolled up when a new heart rate matching the selected pattern is detected. Figure 83 shows an example of a waterfall view 8300 using heart rate mode according to several embodiments. In heart rate mode, each individual beat can be time-stamped 8302.
[0413]
[0503] Once the user has defined all the parameters for the waterfall view, the waterfall view window can display two signals side-by-side, as shown in both Figures 82 and 83. The waterfall view window can display signals using either time mode or heart rate mode. Lead names 8304 and 8306 can be shown at the top of the window. Heart rate pattern name 8208 It can also be shown alongside the ECG lead name 8206.
[0414]
[0504] For example, the toolbar of the waterfall view window may contain buttons, namely a waterfall parameter button 8210 and a display parameter button 8212. The waterfall parameter button 8210 allows the user to adjust the display parameters while the waterfall view window is open. For example, the user may change the display interval, vertical scroll mode, or any other parameter, as will be understood by those skilled in the art.
[0415]
[0505] The user can disable this feature. Figure 84 shows an example of a display parameter window 8400 according to several embodiments. The display parameter window 8400 allows the user to change various display parameters. For example, the user can adjust the zoom 8402, 8404 for each lead and has the option to reset 8416, 8418 to default. The user can add 8406 or remove 8408 clipping. The user can change the color 8410, 8412 for each lead or a subset of leads. The user can disable 8414 fading of the displayed heart rate. In some embodiments, the displayed heart rate can fade as it moves towards the upper part of the waterfall view window.
[0416]
[0506] In some embodiments, the EP hardware system can generate a clean single-pole signal. The system can generate a noise-free unipolar signal based on the fact that it has an ECG circuit board and multiple IC circuit boards that share substantially the same circuit configuration and components, and that the ECG circuit board processes the ECG signal having substantially the same path as each IC circuit board uses to process its corresponding IC signal. A single Wilson coupled electrode (WCT) signal can be used for the ECG circuit board and multiple IC circuit boards.
[0417]
[0507] In some embodiments, the EP hardware system can act as a central processing system for all other systems. The EP hardware system may include an ECG circuit board configured to receive ECG signals, a plurality of IC circuit boards, each configured to receive IC signals, a communication interface communicatively coupled to a remote device, and a processor coupled to the ECG circuit board, the plurality of IC circuit boards, and the communication interface. The EP hardware system can act as a central processing system by having its processor receive feedback from the remote device via the communication interface and control the remote device based on the ECG signals, IC signals, and feedback from the remote device via the communication interface.
[0418]
[0508] The EP hardware system can receive feedback from and control remote devices selected from the group consisting of, but not limited to, ultrasound devices, radio frequency (RF) generators, stimulators, 3D imaging devices, intracardiac echocardiography (ICE) devices, X-ray fluoroscopy devices, and defibrillators. As will be understood by those skilled in the art, the remote devices may be various other types of devices. The EP hardware system can use, but not limited to, communication protocols selected from the group consisting of Digital Imaging and Communications in Medicine (DICOM), Ethernet, Universal Serial Bus (USB), and Institute of Electrical and Electronics Engineers (IEEE) 802.11 to control the remote devices. It can communicate with remote devices via a communication interface attached to the chair. As those skilled in the art will understand, the EP hardware system can communicate with remote devices using a variety of other communication protocols.
[0419] Implementation of a computer system
[0509] For example, various embodiments can be implemented using one or more well-known computer systems, such as the computer system 8500 shown in Figure 85. For example, one or more computer systems 8500 can be used to implement any of the embodiments discussed herein, as well as combinations and subcombinations thereof.
[0420]
[0510] The computer system 8500 may include one or more processors (also referred to as a central processing unit, or CPU), such as processor 8504. Processor 8504 may be connected to a communication infrastructure or bus 8506.
[0421]
[0511] The computer system 8500 may also include user input / output devices 8503 such as a monitor, keyboard, and pointing device, which can communicate with the communication infrastructure 8506 via a user input / output interface 8502.
[0422]
[0512] One or more of the processors 8504 may be graphics processing units (GPUs). In one embodiment, the GPU may be a processor that is a dedicated electronic circuit designed to process mathematically intensive applications. The GPU may have a parallel structure that is efficient for parallel processing of large data blocks, such as mathematically intensive data common to computer graphics applications, images, videos, etc.
[0423]
[0513] The computer system 8500 may also include main memory or primary memory 8508, such as random access memory (RAM). The main memory 8508 may include one or more levels of cache. The main memory 8508 can store control logic (e.g., computer software) and / or data.
[0424]
[0514] The computer system 8500 may also include one or more auxiliary storage devices or secondary memory 8510. The secondary memory 8510 may include, for example, a hard disk drive 8512 or a removable storage device or drive 8514. The removable storage drive 8514 may be a floppy disk drive, a magnetic tape drive, a compact disk drive, an optical storage drive, a tape backup device, or any other storage device / drive.
[0425]
[0515] The removable storage drive 8514 can interact with the removable storage unit 8518. The removable storage unit 8518 may include a computer-accessible or readable storage device that stores computer software (control logic) or data. The removable storage unit 8518 may be a floppy disk, magnetic tape, compact disk, DVD, optical storage disk, or any other computer storage device. The removable storage drive 8514 can read from or write to the removable storage unit 8518.
[0426]
[0516] The secondary memory 8510 may include other means, devices, components, instrumentalities, or other methods that enable computer programs or other instructions or data to be accessed by the computer system 8500. Such means, devices, components, mediators, or other methods include, for example, rims. Examples of removable storage units 8522 and interfaces 8520 include program cartridges and cartridge interfaces (such as those found in video game devices), removable memory chips (such as EPROMs or PROMs) and associated sockets, memory sticks and USB ports, memory cards and associated memory card slots, or any other removable storage units and associated interfaces.
[0427]
[0517] The computer system 8500 may further include a communication or network interface 8524. The communication interface 8524 allows the computer system 8500 to communicate with and interact with any combination of external devices, external networks, external entities, etc. (referred to individually and collectively by reference number 8528). For example, the communication interface 8525 allows the computer system 8500 to communicate with an external or remote device 8528 via a communication path 8526, which can be wired or wireless (or a combination thereof) and may include any combination of LAN, WAN, Internet, etc. Control logic or data can be transmitted to and from the computer system 8500 via the communication path 8526.
[0428]
[0518] Computer system 8500 may also be any of the following, to give some non-limiting examples: personal digital assistants (PDAs), desktop workstations, laptop or notebook computers, netbooks, tablets, smartphones, smartwatches or other wearables, appliances, parts of the Internet of Things, or embedded systems, or any combination thereof.
[0429]
[0519] Computer System 8500 includes, but is not limited to, remote or distributed cloud computing solutions; local or on-premises software ("on-premises" cloud-based solutions); and "as a service" models (e.g., Content as a Service (CaaS), Digital Content as a Service (DCaaS), Software as a Service (SaaS), etc.). Managed software as a service (MSaa) S), Platform as a Service (PaaS), Desktop as a Service (DaaS), Framework as a Service (FaaS), Backend as a Service (BaaS), Mobile Backend as a Service (MBaaS), Infrastructure as a Service (Infrastructure as a Service) (IaaS), etc.); or the above examples or other services A client or server that accesses or hosts any application or data through any delivery paradigm, including a hybrid model that includes any combination of delivery paradigms.
[0430]
[0520] Any applicable data structures, file formats, and schemas in the computer system 8500 are, but are not limited to, JavaScript Object Notation (JSON), Extensible Markup Language (XML), and Yet Another Markup Language (YAM). L), Extensible Hypertext Markup Language (XHTML), Wireless Markup Language (WML), MessagePack, XML User Interface Language (XUL), or individually, Alternatively, they can be combined and derived from any other standard containing a functionally similar representation. Alternatively, proprietary data structures, formats, or schemas can be exclusively... Alternatively, it can be used in combination with known or open standards.
[0431]
[0521] In some embodiments, a tangible non-temporary device or product including a tangible non-temporary computer-readable or computer-compatible medium in which control logic (software) is stored may also be referred to as a computer program product or program storage device. This includes, but is not limited to, a tangible product embodying any combination of the above, together with the computer system 8500, main memory 8508, secondary memory 8510, and removable storage units 8518 and 8522. When such control logic is executed by one or more processing devices (such as the computer system 8500), these data processing devices can be made to operate as described herein.
[0432]
[0522] Based on the teachings contained herein, it will be apparent to those skilled in the art how to create and use embodiments of the disclosure using data processing devices, computer systems, or computer architectures other than those described in Figure 85. In particular, embodiments may operate with software, hardware, and / or operating system embodiments other than those described herein.
[0433] conclusion
[0523] The EP recording system disclosed herein effectively removes noise and eliminates or isolates undesirable large signals while preserving relevant components of the raw small signals, i.e., maintaining the integrity of the original information in the EP environment. Conventional EP systems can effectively filter out noise, but they may also filter out the noisy signal components that the medical team wishes to see. Conventional EP systems may also generate and introduce additional noise and undesirable artifacts that were not originally present in the raw signal, due to well-intentioned software filtering algorithms. Conventional EP systems, even when utilizing the latest noise reduction measures, cannot effectively capture high-fidelity, noise-free small signals when simultaneous large-signal procedures such as defibrillation and ablation are present. This is because conventional EP systems lack comprehensive signal acquisition and filtering solutions across relevant frequency ranges, i.e., low (e.g., 0-100 Hz), intermediate (e.g., approximately 100 Hz to less than 300 kHz), and high (e.g., above 300 kHz), and cannot effectively handle simultaneous signals that differ by hundreds or thousands of orders of magnitude. In contrast, the EP recording systems disclosed herein integrate and apply novel hardware circuit configurations, software methods, and system topologies to remove unwanted signals while preserving the original signal waveforms over the frequencies relevant to the signals found in the EP environment.
[0434]
[0524] The disclosed EP system does not require the trade-offs that conventional EP systems must make. On the contrary, the disclosed EP system allows hardware and software to work together to simultaneously (1) operate amplifiers at high gain to view small signals, (2) prevent both clipping and saturation by minimizing destructive large-signal filtering in hardware to view large signals, (3) process signals by separating them in independent displays, removing any remaining noise, and synchronizing the separated signals, and finally (4) enable the user to process and analyze both large and small signals so that signal artifacts and events can be accurately correlated in time and by events.
[0435]
[0525] The exemplary signals 2200 in Figures 22A and 22B illustrate these concepts and, after being collected, filtered, and processed by the EP system disclosed herein, represent the EC in the presence of major transient events, ablation signals, defibrillation signals, and EP ambient noise. This exhibits an improvement in the visualization of G or IC cardiac signals. Figure 22A shows the removal of noise from both small and large signals and the avoidance of clipping in the processing of large signals. Conventional EP systems provide a cardiac signal 2203 containing noise and may artificially clip the signal 2202 to limit the amplitude of the displayed signal to avoid the effects of saturation. The disclosed EP system collects and clearly displays both the weak signal 2214 and the strong signal 2205. With the disclosed EP system, artificial clipping is unnecessary and the strong signal 2204 is fully defined (not clipped).
[0436]
[0526] Figure 22B shows that the EP system can reveal low-amplitude cardiac signals and associated random artifacts in the EP signal in the presence of noise and large-signal processing. Window 2216 shows a noisy signal 2208, which includes both high-amplitude and low-amplitude minute components 2206 of the desired signal revealed by the disclosed EP system. In contrast, as shown in window 2218, the conventional EP system is unable to effectively reveal both low-amplitude and high-amplitude minute components of the desired signal. In noisier signals, the conventional EP system can reveal the low-amplitude minute component 2210 of the desired signal, but it is more easily lost amidst the noise 2212. The high-amplitude component 2211 of the desired signal may be lost by artificial clipping in the conventional EP system.
[0437]
[0527] Figure 22C shows that the disclosed EP system can remove 60Hz noise 2220 without saturation or delayed recovery, while preserving the 60Hz signal component 2222 belonging to the original waveform 2224. Specifically, the component 2222 of the original waveform 2224 that occurs simultaneously as artifact 2220 is not lost. In other words, when a large signal overlaps a small signal simultaneously, the disclosed EP system can clearly identify, collect, and process both.
[0438]
[0528] It should be understood that the detailed description section is intended to be used to interpret the claims, and no other section is intended to be used. Other sections may show one or more exemplary embodiments contemplated by the inventors, but may not show all exemplary embodiments, and are therefore not intended to limit the scope of the claims of this disclosure or the appended claims in any way.
[0439]
[0529] While this disclosure describes exemplary embodiments for exemplary fields and applications, it should be understood that this disclosure is not limited thereto. Other embodiments and modifications thereof are possible and are within the scope and spirit of this disclosure. For example, without limiting the generality of this paragraph, embodiments are not limited to software, hardware, firmware, or entities illustrated in the figures or described herein. Furthermore, embodiments (whether expressly described herein or not) may have significant utility in fields and applications beyond those described herein.
[0440]
[0530] In this specification, embodiments are described using functional units that exemplify the specified functions and their associated embodiments. The boundaries of these functional units are arbitrarily defined in this specification for the sake of clarity. Alternative boundaries can be defined as long as the specified functions and relationships (or their equivalents) are adequately performed. Furthermore, alternative embodiments may implement functional blocks, steps, operations, methods, etc., in a different order than those described herein. This disclosure also extends to methods relating to using or otherwise implementing the hardware and software features disclosed herein.
[0441]
[0531] References in this specification to “one embodiment,” “one embodiment,” “exemplary embodiment,” or similar phrases indicate that the embodiments described may include certain features, characteristics, or properties, but not all embodiments may necessarily include those specific features, characteristics, or properties. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, if certain features, characteristics, or properties are described in relation to one embodiment, it is within the knowledge of those skilled in the art to incorporate such features, characteristics, or properties into other embodiments, whether or not they are explicitly mentioned or described herein. Furthermore, some embodiments may be described using the terms “combined” and “connected,” along with their derivatives. These terms are not necessarily intended to be synonymous with each other. For example, some embodiments may be described using the terms “connected” or “combined” to indicate that two or more elements are in direct physical or electrical contact with each other. However, the term “combined” may also mean that two or more elements are not in direct contact with each other but still cooperate or interact with each other.
[0442]
[0532] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the following claims and their equivalents.
Claims
1. A signal visualization system, It is memory, A first signal module including a first digital signal processor (DSP) configured to match the heartbeat in a first packet associated with a first cardiac signal with known signal characteristics, A second signal module including a second DSP configured to search for a delay potential in a second packet related to a second cardiac signal in response to the matching, A display module coupled to the first signal module and the second signal module, A portion of the aforementioned first cardiac signal is displayed, Based on the search, a portion of the second cardiac signal, including the delayed potential, is displayed in time synchronization with the displayed portion of the first cardiac signal. A display module configured as follows, Memory including, At least one processor coupled to the memory and configured to execute the first signal module, the second signal module, and the display module, A system equipped with these features.
2. The aforementioned display module The portion of the first heart signal and the portion of the second heart signal are displayed side by side. The system according to claim 1, further configured as follows.
3. The aforementioned display module The system according to claim 1, further configured to display the portion of the second heart signal corresponding to the displayed portion of the first heart signal, wherein the portion of the first heart signal and the portion of the second heart signal are displayed stacked vertically on top of each other.
4. The system according to claim 3, wherein the display module is further configured to adjust the offset of the first heart signal based on the known signal characteristics, thereby pinning the first heart signal to the baseline.
5. A computer implementation method for visualizing signals, At least one processor executing the first digital signal processor (DSP) of the first signal module matches the heartbeat in the first packet related to the first cardiac signal with the signal characteristics, The at least one processor executing the second DSP of the second signal module searches for the delay potential in the second packet related to the second cardiac signal in response to the matching, The at least one processor that executes the display module coupled to the first signal module and the second signal module displays a portion of the first heart signal, The at least one processor that executes the display module coupled to the first signal module and the second signal module displays, based on the search, a portion of the second cardiac signal including the delayed potential in time synchronization with the displayed portion of the first cardiac signal, Methods that include...
6. The first heart is controlled by the at least one processor that executes the display module. Displaying the aforementioned portion of the signal and the aforementioned portion of the second cardiac signal side by side. The method according to claim 5, further comprising:
7. The at least one processor executing the display module displays the portion of the second heart signal corresponding to the displayed portion of the first heart signal, wherein the portion of the first heart signal and the portion of the second heart signal are displayed stacked vertically on top of each other. The method according to claim 5, further comprising:
8. The at least one processor executing the display module adjusts the offset of the first heart signal based on the known signal characteristics, thereby pinning the first heart signal to the baseline. The method according to claim 7, further comprising:
9. When executed by at least one computing device, the at least one computing device, The first digital signal processor (DSP) of the first signal module matches the heartbeat in the first packet related to the first cardiac signal with known signal characteristics, The second DSP of the second signal module searches for the delay potential in the second packet related to the second cardiac signal in response to the matching, A display module coupled to the first signal module and the second signal module displays a portion of the first cardiac signal, A display module coupled to the first signal module and the second signal module displays a portion of the second cardiac signal, including the delayed potential, in time synchronization with the displayed portion of the first cardiac signal, based on the search. A non-temporary computer-readable device that stores instructions for performing actions including [specific actions].
10. The aforementioned operation, The display module displays the portion of the first cardiac signal and the portion of the second cardiac signal side by side. A non-temporary computer-readable device according to claim 9, further comprising:
11. The aforementioned operation, The display module displays the portion of the second heart signal corresponding to the displayed portion of the first heart signal, wherein the portion of the first heart signal and the portion of the second heart signal are displayed stacked vertically on top of each other. A non-temporary computer-readable device according to claim 9, further comprising:
12. The aforementioned operation, The display module adjusts the offset of the first heart signal based on the known signal characteristics, thereby pinning the first heart signal to the baseline. A non-temporary computer-readable device according to claim 11, further comprising:
13. A signal visualization system, It is memory, A first signal module including a first digital signal processor (DSP) configured to match the heartbeat in a first packet associated with a first cardiac signal with known signal characteristics, A second signal module including a second DSP configured to search for early excitation in a period preceding a matched heartbeat in the second cardiac signal, A display module coupled to the first signal module and the second signal module, A portion of the aforementioned first cardiac signal is displayed, Based on the search, a portion of the second cardiac signal, including the pre-excitation, is displayed in time synchronization with the displayed portion of the first cardiac signal. A display module configured as follows, Memory including, At least one processor coupled to the memory and configured to execute the first signal module, the second signal module, and the display module, A system equipped with these features.
14. The aforementioned display module The portion of the first heart signal and the portion of the second heart signal are displayed side by side. The system according to claim 13, further configured as follows.
15. The aforementioned display module The system according to claim 13, further configured to display the portion of the second heart signal corresponding to the displayed portion of the first heart signal, wherein the portion of the first heart signal and the portion of the second heart signal are displayed stacked vertically on top of each other.
16. The system according to claim 15, wherein the display module is further configured to adjust the offset of the first heart signal based on the known signal characteristics, thereby pinning the first heart signal to the baseline.
17. A computer implementation method for visualizing signals, At least one processor running the first digital signal processor (DSP) of the first signal module matches the heartbeat in the first packet associated with the first cardiac signal with known signal characteristics, The at least one processor executing the second DSP of the second signal module searches for early excitation in a period prior to a matched heartbeat in the second cardiac signal, The at least one processor that executes the display module coupled to the first signal module and the second signal module displays a portion of the first heart signal, The at least one processor that executes the display module coupled to the first signal module and the second signal module displays, based on the search, a portion of the second cardiac signal including the early excitation in time synchronization with the displayed portion of the first cardiac signal, Methods that include...
18. The at least one processor executing the display module displays the portion of the first heart signal and the portion of the second heart signal side by side. The method according to claim 17, further comprising:
19. The at least one processor executing the display module displays the portion of the second heart signal corresponding to the displayed portion of the first heart signal, wherein the portion of the first heart signal and the portion of the second heart signal are displayed stacked vertically on top of each other. The method according to claim 17, further comprising:
20. The at least one processor that executes the display module, the known signal The offset of the first cardiac signal is adjusted based on the characteristics, thereby pinning the first cardiac signal to the baseline. The method according to claim 19, further comprising:
21. When executed by at least one computing device, the at least one computing device, The first digital signal processor (DSP) of the first signal module matches the heartbeat in the first packet related to the first cardiac signal with known signal characteristics, The second DSP of the second signal module searches for early excitation in a period preceding a matched heartbeat in the second cardiac signal, A display module coupled to the first signal module and the second signal module displays a portion of the first cardiac signal, The display module coupled to the first signal module and the second signal module displays a portion of the second cardiac signal, including the early excitation, in time synchronization with the displayed portion of the first cardiac signal, based on the search. A non-temporary computer-readable device that stores instructions for performing actions including [specific actions].
22. The aforementioned operation, The display module displays the portion of the first cardiac signal and the portion of the second cardiac signal side by side. A non-temporary computer-readable device according to claim 21, further comprising:
23. The aforementioned operation, The display module displays the portion of the second heart signal corresponding to the displayed portion of the first heart signal, wherein the portion of the first heart signal and the portion of the second heart signal are displayed stacked vertically on top of each other. A non-temporary computer-readable device according to claim 21, further comprising:
24. The aforementioned operation, The display module adjusts the offset of the first heart signal based on the known signal characteristics, thereby pinning the first heart signal to the baseline. A non-temporary computer-readable device according to claim 23, further comprising:
25. A computer implementation method, Access to the first cardiac signal related to surface-to-body leads by at least one processor, The at least one processor matches the heartbeat of the first cardiac signal with a known signal pattern, The aforementioned at least one processor searches for early excitation or delayed potentials in the second cardiac signal during a certain period before and after the matched heartbeat, Methods that include...
26. The method according to claim 25, wherein the aforementioned period is a period defined by the user.
27. The aforementioned search is The at least one processor searches for the early excitation based on the amplitude threshold. The method according to claim 25, further comprising:
28. The aforementioned search is The at least one processor searches a buffer containing a portion of the second cardiac signal with respect to the early excitation or the delayed potential. The method according to claim 25, further comprising:
29. The matching described above The at least one processor matches the heartbeat of the first cardiac signal with the known signal pattern based on a correlation function. The method according to claim 25, further comprising:
30. The matching described above The at least one processor matches the heartbeat of the first cardiac signal with the known signal pattern based on the mean absolute deviation (MAD) function. The method according to claim 25, further comprising:
31. The matching described above The at least one processor matches the heartbeat of the first cardiac signal with the known signal pattern based on a confidence value. The method according to claim 25, further comprising:
32. The method according to claim 31, wherein the confidence value is defined by the user.
33. The at least one processor interpolates the signal data from the catheter at the site of early excitation to the signal data at the site of delayed potential. The method according to claim 25, further comprising:
34. The at least one processor displays the signal data from the catheter independently of the delayed potential filter. The method according to claim 33, further comprising:
35. The at least one processor estimates the location of conduction delay between the site of early excitation and the site of delayed potential. The method according to claim 33, further comprising:
36. When executed by at least one computing device, the at least one computing device, Accessing the first cardiac signal related to surface-level leads, Matching the heartbeat of the first cardiac signal with a known signal pattern, Searching for early excitation or delayed potentials in the second cardiac signal during a period before and after a matched heartbeat, A non-temporary computer-readable device that stores instructions for performing actions including [specific actions].
37. The non-temporary computer-readable device according to claim 36, wherein the aforementioned period is a period defined by the user.
38. The aforementioned search is Searching for the aforementioned early excitation based on the amplitude threshold A non-temporary computer-readable device according to claim 36, further comprising:
39. The aforementioned search is With respect to the aforementioned early excitation or the delayed potential, a buffer containing a portion of the second cardiac signal is detected. Searching A non-temporary computer-readable device according to claim 36, further comprising:
40. The matching described above Matching the heartbeat of the first cardiac signal with the known signal pattern based on a correlation function. A non-temporary computer-readable device according to claim 36, further comprising:
41. The matching described above Matching the heartbeat of the first cardiac signal with the known signal pattern based on the mean absolute deviation (MAD) function. A non-temporary computer-readable device according to claim 36, further comprising:
42. The matching described above Matching the heartbeat of the first cardiac signal with the known signal pattern based on the confidence value. A non-temporary computer-readable device according to claim 36, further comprising:
43. The non-temporary computer-readable device according to claim 42, wherein the confidence value is defined by the user.
44. The aforementioned operation, Interpolating the signal data from the catheter at the site of early excitation with the signal data at the site of delayed potential. A non-temporary computer-readable device according to claim 36, further comprising:
45. The aforementioned operation, A non-temporary computer-readable device according to claim 44, further comprising displaying the signal data from the catheter independently of the delayed potential filter.
46. The aforementioned operation, To estimate the site of conduction delay between the site of the early excitation and the site of the delayed potential. A non-temporary computer-readable device according to claim 44, further comprising:
47. A computer implementation method for filtering noise from an input signal, Accessing the input signal having a first harmonic frequency and the noise using at least one processor, The at least one processor determines the quiescent period in the input signal, During the aforementioned quiescent period, at least one processor stores samples of the noise in the input signal in a buffer, The at least one processor subtracts a sample from the noise in a single cycle in the buffer from the input signal to generate a filtered signal, wherein the subtraction removes the first and second harmonic frequencies from the input signal and avoids the introduction of transient responses in the filtered signal. The at least one processor repeatedly performs the actions of determining, storing, and subtracting to refine the filtered signal, Methods that include...
48. The above decision is The at least one processor calculates the gradient of the input signal, The aforementioned at least one processor determines that the gradient falls below a threshold, thereby determining the existence of the quiet period. The method according to claim 47, further comprising:
49. The aforementioned storage, The at least one processor averages the samples of the input signal with the corresponding samples of the noise of the input signal in the buffer to create an averaged sample. The at least one processor replaces the corresponding samples of the noise in the input signal in the buffer with the average samples, The method according to claim 47, further comprising:
50. The method according to claim 47, wherein the first harmonic frequency is 60 Hz and the second harmonic frequency is 120 Hz or 180 Hz.
51. The method according to claim 47, wherein the frequency of the noise in the input signal is substantially constant.
52. The method according to claim 51, wherein the size of the buffer is based on the frequency of the noise in the input signal.
53. When executed by at least one computing device, the at least one computing device, Accessing an input signal that has a first harmonic frequency and noise, To determine the quiescent period in the aforementioned input signal, During the aforementioned quiescent period, samples of the noise in the input signal are stored in a buffer. The method involves subtracting a sample from the noise in a single cycle in the buffer from the input signal to generate a filtered signal, wherein the subtraction removes the first and second harmonic frequencies from the input signal, thereby avoiding the introduction of transient responses in the filtered signal. The filtering of the signal is refined by repeatedly performing the aforementioned determination, storage, and subtraction. A non-temporary computer-readable device that stores instructions for performing actions including [specific actions].
54. The above decision is Calculating the gradient of the aforementioned input signal, The non-temporary computer-readable device according to claim 53, further comprising determining that the gradient falls below a threshold, thereby determining the existence of the quiet period.
55. The aforementioned storage, A sample of the input signal is averaged with the corresponding sample of the noise in the buffer to create an averaged sample. Replacing the corresponding samples of the noise in the input signal in the buffer with the average samples, A non-temporary computer-readable device according to claim 53, further comprising:
56. The non-temporary computer-readable device according to claim 53, wherein the first harmonic frequency is 60 Hz and the second harmonic frequency is 120 Hz or 180 Hz.
57. The non-transient computer-readable device according to claim 53, wherein the frequency of the noise in the input signal is substantially constant.
58. The non-transient computer-readable device according to claim 53, wherein the size of the buffer is based on the frequency of the noise in the input signal.
59. A computer implementation method for filtering noise from an input signal, Accessing the input signal, including the noise and minimum high-frequency signals, by at least one processor, The at least one processor generates a filtered signal by high-pass filtering the input signal, The at least one processor isolates artifacts related to the noise in the filtered signal from the target high-frequency signal, Disabling the filtered signal for a certain period before and after the isolated artifact by at least one processor, wherein the isolated artifact is removed and the target high-frequency signal can pass through. Methods that include...
60. The at least one processor filters the input signal using a notch filter. The method according to claim 59, further comprising:
61. Isolating the aforementioned artifacts The at least one processor calculates the gradient of the filtered input signal, The aforementioned at least one processor determines that the gradient exceeds a threshold, thereby determining the presence of the artifact, The method according to claim 59, further comprising:
62. Isolating the aforementioned artifacts The at least one processor characterizes the artifact in the artifact template, wherein the invalidation applies the artifact template as the selected filter over the isolated artifact in the filtered signal. The method according to claim 59, further comprising:
63. The method according to claim 59, wherein accessing the input signal, which includes the noise and the high-frequency signal of the target, further comprises accessing the Purkinje signal.
64. The method according to claim 59, wherein access to the input signal including the noise and the target high-frequency signal is achieved by performing rapid conduction tissue recognition filtering.
65. The method according to claim 59, further comprising isolating the artifact by isolating the impulse response by the at least one processor.
66. The at least one processor buffers the filtered signal for a certain period before and after the isolated artifact. The method according to claim 59, further comprising:
67. The at least one processor selects a filter based on the isolated artifact, The at least one processor applies the selected filter to disable the isolated signal in the filtered signal, The method according to claim 59, further comprising:
68. When executed by at least one computing device, the at least one computing device, Accessing the input signal which includes noise and the target high-frequency signal, The input signal is high-pass filtered to generate a filtered signal, To isolate artifacts related to the noise in the filtered signal from the target high-frequency signal, Disabling the filtered signal for a certain period before and after the isolated artifact, wherein the isolated artifact is removed and the target high-frequency signal can pass through. A non-temporary computer-readable device that stores instructions for performing actions including [specific actions].
69. The aforementioned operation, Filtering the input signal using a notch filter. A non-temporary computer-readable device according to claim 68, further comprising:
70. The aforementioned isolation is The gradient of the filtered input signal is calculated, The gradient is determined to exceed a threshold, and thereby the existence of the artifact is determined. A non-temporary computer-readable device according to claim 68, further comprising:
71. The aforementioned isolation is Characterizing the artifact in the artifact template, wherein the invalidation applies the artifact template as the selected filter over the isolated artifact in the filtered signal. A non-temporary computer-readable device according to claim 68, further comprising:
72. The non-transient computer-readable device according to claim 68, wherein accessing the input signal, which includes the noise and the high-frequency signal of the target, further includes accessing a Purkinje signal.
73. The non-temporary computer-readable device according to claim 68, wherein access to the input signal, which includes the noise and the target high-frequency signal, is achieved by performing rapid conduction tissue recognition filtering.
74. The non-transient computer-readable device according to claim 68, wherein isolating the artifact further comprises isolating the impulse response.
75. The aforementioned operation, Buffering the filtered signal for a certain period before and after the isolated artifact. A non-temporary computer-readable device according to claim 68, further comprising:
76. The aforementioned operation, Selecting a filter based on the aforementioned isolated artifacts, Applying the selected filter to disable the isolated signal in the filtered signal, A non-temporary computer-readable device according to claim 68, further comprising:
77. A computer implementation method, Accessing the input heart signal via at least one processor, The at least one processor matches a portion of the input cardiac signal with a known signal pattern, The at least one processor displays an indication of the degree of matching, Methods that include...
78. The method according to claim 77, wherein the known signal pattern is captured during a preceding or current patient procedure and stored in a pattern template.
79. The method according to claim 77, wherein the known signal pattern is stored in a database.
80. The matching described above The at least one processor matches the portion of the input cardiac signal with the known signal pattern based on a correlation function. The method according to claim 77, further comprising:
81. The matching described above The at least one processor matches the portion of the input heart signal with the known signal pattern based on the mean absolute deviation (MAD) function. The method according to claim 77, further comprising:
82. The matching described above The at least one processor matches the portion of the input cardiac signal with the known signal pattern based on a confidence value. The method according to claim 77, further comprising:
83. The method according to claim 77, wherein the instruction for the degree of agreement specifies a location where cardiac pacing should be performed.
84. When executed by at least one computing device, the at least one computing device, Accessing the input cardiac signal, Matching a portion of the input cardiac signal with a known signal pattern, To indicate the degree of agreement, A non-temporary computer-readable device that stores instructions for performing actions including [specific actions].
85. The non-temporary computer-readable device according to claim 84, wherein the known signal pattern is captured during a preceding or current patient procedure and stored in a pattern template.
86. The known signal pattern is stored in a database, as described in claim 84. Computer-readable device.
87. The matching described above Matching the portion of the input cardiac signal with the known signal pattern based on a correlation function. A non-temporary computer-readable device according to claim 84, further comprising:
88. The matching described above Matching the portion of the input cardiac signal with the known signal pattern based on the mean absolute deviation (MAD) function. A non-temporary computer-readable device according to claim 84, further comprising:
89. The matching described above Matching the portion of the input cardiac signal with the known signal pattern based on the confidence value. A non-temporary computer-readable device according to claim 84, further comprising:
90. The non-temporary computer-readable device according to claim 84, wherein the indication of the degree of matching specifies a location where cardiac pacing should be performed.
91. A computer implementation method, Accessing the input heart signal via at least one processor, The aforementioned at least one processor accesses the detection threshold, The at least one processor matches a portion of the input cardiac signal with a known signal pattern based on the detection threshold, The at least one processor displays the highlighted portion of the input cardiac signal based on the matching, Methods that include...
92. The method according to claim 91, wherein the known signal pattern is incorporated during a preceding or current patient treatment.
93. The method according to claim 91, wherein the known signal pattern is stored in a database.
94. The matching described above The at least one processor matches the portion of the input cardiac signal with the known signal pattern based on a correlation function. The method according to claim 91, further comprising:
95. The matching described above The at least one processor matches the portion of the input heart signal with the known signal pattern based on the mean absolute deviation (MAD) function. The method according to claim 91, further comprising:
96. The matching described above The at least one processor performs a first matching of the portion of the input cardiac signal with the known signal pattern, The at least one processor determines a first confidence value based on the first matching, The at least one processor processes a portion of the second input signal using the known signal pattern. To match with the second time, The at least one processor determines the second confidence value based on the second matching, The at least one processor averages the first confidence value and the second confidence value to create an average confidence value, The at least one processor determines that the average confidence value exceeds the detection threshold, The method according to claim 91, further comprising:
97. To display the above, The at least one processor displays the highlighted portion of the input heart signal based on the color associated with the known signal pattern. The method according to claim 91, further comprising:
98. The matching described above The at least one processor matches the portion of the input cardiac signal with the known signal pattern based on a weighted region of the known signal pattern. The method according to claim 91, further comprising:
99. When executed by at least one computing device, the at least one computing device, Accessing the input cardiac signal, Accessing the detection threshold, Based on the aforementioned detection threshold, a portion of the input cardiac signal is matched with a known signal pattern. Based on the matching described above, the highlighted portion of the input cardiac signal is displayed, A non-temporary computer-readable device that stores instructions for performing actions including [specific actions].
100. The non-temporary computer-readable device according to claim 99, wherein the known signal pattern is captured during a preceding or current patient procedure.
101. The non-temporary computer-readable device according to claim 99, wherein the known signal patterns are stored in a database.
102. The matching described above Matching the portion of the input cardiac signal with the known signal pattern based on a correlation function. A non-temporary computer-readable device according to claim 99, further comprising:
103. The matching described above Matching the portion of the input cardiac signal with the known signal pattern based on the mean absolute deviation (MAD) function. A non-temporary computer-readable device according to claim 99, further comprising:
104. The matching described above The above portion of the input cardiac signal is first matched with the known signal pattern, Based on the first matching, the first confidence value is determined, A portion of the second input signal is second-matched with the known signal pattern, The second confidence value is determined based on the second matching described above, The first confidence value and the second confidence value are averaged to create an average confidence value, It is determined that the average confidence value exceeds the detection threshold, A non-temporary computer-readable device according to claim 99, further comprising:
105. To display the above, To display the highlighted portion of the input cardiac signal based on the color associated with the known signal pattern. A non-temporary computer-readable device according to claim 99, further comprising:
106. The matching described above Matching the portion of the input cardiac signal with the known signal pattern based on a weighted specific region of the known signal pattern. A non-temporary computer-readable device according to claim 99, further comprising:
107. A system that generates a noise-free unipolar signal, An ECG circuit board configured to process electrocardiogram (ECG) signals, Multiple IC circuit boards, each configured to process a corresponding IC signal, Equipped with, The ECG circuit board and the plurality of IC circuit boards share substantially the same circuit configuration and components. A system in which the ECG circuit board processes the ECG signal using substantially the same path as that each IC circuit board uses to process its corresponding IC signal.
108. The system according to claim 107, wherein a single Wilson coupled electrode (WCT) signal is used for the ECG circuit board and the plurality of IC circuit boards.
109. A system for performing electrophysiological (EP) processing, An ECG circuit board configured to process electrocardiogram (ECG) signals, Multiple IC circuit boards, each configured to process a corresponding IC signal, A communication interface connected to a remote device for communication, The ECG circuit board, the plurality of IC circuit boards, and the communication interface are coupled together. The communication interface receives feedback from the remote device, The remote device is controlled via the communication interface based on the ECG signal, the corresponding IC signals, and the feedback from the remote device. A processor configured as follows, A system equipped with these features.
110. The system according to claim 109, wherein the remote device is selected from the group consisting of an ultrasound device, a radio frequency (RF) generator, a stimulator, a three-dimensional imaging device, an intracardiac echocardiography (ICE) device, an X-ray fluoroscopy device, and a defibrillator.
111. The system according to claim 109, wherein the communication interface is coupled to the remote device using a communication protocol selected from the group consisting of Digital Imaging and Communications in Medical Technology (DICOM), Ethernet, Universal Serial Bus (USB), and IEEE 802.11.