Semiconductor devices, display devices, and electronic devices

Abstract

To provide a semiconductor device that operates stably. [Solution] A semiconductor device having first to tenth transistors MN1 to MN10 and first to fourth capacitors C1 to C4, wherein the gates of the first and fourth transistors are electrically connected to each other, and the first terminals of the first, second, fifth, and eighth transistors are electrically connected to the first terminal of the fourth capacitor. The second terminal of the fifth transistor is electrically connected to the gate of the sixth transistor and the first terminal of the second capacitor, and the second terminal of the eighth transistor is electrically connected to the gate of the ninth transistor and the first terminal of the third capacitor. The gates of the second, seventh, and tenth transistors are electrically connected to the first terminals of the third and fourth transistors respectively and to the first terminal of the first capacitor. The first terminals of the sixth and seventh transistors are electrically connected to the second terminal of the second capacitor, and the first terminals of the ninth and tenth transistors are electrically connected to the second terminal of the third capacitor.

Description

[Technical Field]

[0001] One aspect of the present invention relates to semiconductor devices, display devices, and electronic devices.

[0002] One aspect of the present invention is not limited to the above-mentioned technical field. The technical field relates to objects, driving methods, or manufacturing methods. Or, one aspect of the present invention. This refers to a process, machine, manufacture, or composition of matter. -) is the subject matter. Therefore, one aspect of the present invention disclosed herein is more specifically Technical fields include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, energy storage devices, and imaging devices. Devices, memory devices, signal processing devices, processors, electronic devices, systems, methods for driving them, and Examples of these manufacturing methods or inspection methods can be given. [Background technology]

[0003] In recent years, for example, VR (Virtual Reality), AR (Augmented Reality) XR (Extended Reality, or Cross Reality) Electronic devices for Reality, mobile phones (e.g., smartphones), tablets In the display devices of information terminals and notebook PCs (personal computers), various Improvements are being made across the board. For example, increasing the resolution and improving color reproduction (NTSC ratio). Development of display devices is underway to reduce the size of the drive circuit and power consumption. ru.

[0004] For example, in order to improve the display quality of a display device, the characteristics of the drive transistors included in the pixels Development of circuits to reduce variations is also underway. In particular, the driving transistors Patent Document 1 describes an invention of a pixel circuit having a circuit for correcting high-value voltages.

[0005] Furthermore, oxide semiconductors are used as switching elements in the pixel circuits of the display device. Examples include technologies that utilize transistors made of semiconductor thin films.

[0006] Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors. Furthermore, oxide semiconductors are attracting attention as materials other than silicon-based semiconductor materials. Examples of oxide semiconductors include oxides of monocrystalline metals such as indium oxide and zinc oxide. In addition, oxides of multi-component metals are also known. Among the oxides of multi-component metals, in particular, I Research on n-Ga-Zn oxide (hereinafter also referred to as IGZO) is actively being conducted. .

[0007] Transistors using IGZO as the active layer have extremely low off-current (Non-patent document) (See reference 1), LSIs and display devices utilizing this characteristic have been reported (see Non-Patent Document 2 and See also Non-Patent Document 3). Furthermore, Patent Document 2 describes a transistor that includes IGZO in its active layer. An invention for use in the pixel circuit of a display device has been disclosed. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] Japanese Patent Publication No. 2017-10000 [Patent Document 2] Japanese Patent Publication No. 2010-156963 [Non-patent literature]

[0009] [Non-Patent Document 1] K. Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p.021201-1-021201-7 [Non-Patent Document 2] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, p.T216-T217 [Non-Patent Document 3] S. Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, p.626-629 [Overview of the project] [Problems that the invention aims to solve]

[0010] When fabricating a semiconductor device, the channel shape of the multiple transistors in the semiconductor device The materials included in the compounding region are all the same material, which improves the semiconductor device manufacturing process. It may be possible to shorten it. Specifically, for example, the material in question is the aforementioned I Metal oxides such as GZO can be used.

[0011] However, metal oxides containing indium (e.g., In oxide), or gold containing zinc. While n-type semiconductors can be fabricated using group oxides (e.g., Zn oxide), p-type semiconductors are not readily available. It is difficult to manufacture in terms of mobility and reliability. Therefore, when manufacturing semiconductor devices, n-type semiconductors are used. The circuit should be a unipolar circuit composed of transistors (n-channel transistors) that include a body. It is preferable.

[0012] Furthermore, n-channel transistors in which metal oxides are included in the channel formation region are fabricated. The threshold voltage tends to be lower due to the influence of the process, etc. In other words, the transistor When the switch is off, the leakage current tends to be large. Therefore, the leakage current is large. In semiconductor devices with large transistors, the desired operation may not occur under certain circumstances. This can happen.

[0013] One aspect of the present invention aims to provide a semiconductor device that operates stably. Alternatively, one aspect of the present invention aims to provide a highly reliable semiconductor device. Alternatively, one aspect of the present invention aims to provide a display device including the semiconductor device described above. One aspect of the present invention is to provide an electronic device including the above-described display device. This is one of the issues. Alternatively, one aspect of the present invention relates to a novel semiconductor device, a novel display device, or a new One of our objectives is to provide standard electronic equipment.

[0014] Furthermore, the problems addressed by one embodiment of the present invention are not limited to those listed above. This does not preclude the existence of other issues. These other issues are described below. This is an issue not mentioned in the section. Issues not mentioned in this section can be understood by those skilled in the art through the details. This can be derived from descriptions in documents or drawings, and can be appropriately extracted from these descriptions. It is possible. Furthermore, one aspect of the present invention addresses at least one of the problems listed above and other problems. This invention solves the following problems. One aspect of the present invention addresses the problems listed above, and other problems. You don't need to solve all the problems. [Means for solving the problem]

[0015] (1) One aspect of the present invention comprises a first transistor, a second transistor, a third transistor, The fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, The 8th transistor, the 9th transistor, the 10th transistor, the 1st capacitor, and the 2nd capacitor This is a semiconductor device having a quantity, a third capacitance, and a fourth capacitance. The gate is electrically connected to the first gate of the fourth transistor, and the saw of the first transistor Either the source or drain of the second transistor is connected to either the source or drain of the fifth transistor. The source or drain of the zista and the source or drain of the 8th transistor The first terminal of the fourth capacitance is electrically connected to the source or of the fifth transistor. The other side of Rain is electrically connected to the first gate of the sixth transistor and the first terminal of the second capacitor. They are connected. The source or drain of the 8th transistor is connected to the other of the 9th transistor. The first gate and the first terminal of the third capacitance are electrically connected. The first gate is connected to the first terminal of the first capacitor and to either the source or drain of the third transistor. , the source or drain of the fourth transistor and the first gate of the seventh transistor, The first gate of the 10th transistor is electrically connected to the 7th transistor's socket. Either the source or the drain of the sixth transistor is connected to either the source or the drain of the second capacitor. The second terminal of the 10th transistor is electrically connected to the source or drain of the 10th transistor. One side is connected to either the source or drain of the ninth transistor and the second terminal of the third capacitor. They are connected by energy.

[0016] (2) Alternatively, one aspect of the present invention comprises a first transistor, a second transistor, and a third transistor The fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor The 8th transistor, the 9th transistor, the 10th transistor, and the 11th transistor. This is a semiconductor device having a diast, a first capacitance, a second capacitance, and a third capacitance. The first gate of the transistor is electrically connected to either the source or the drain of the 11th transistor. Connected, the source or drain of the 11th transistor is connected to the first of the 4th transistor. It is electrically connected to the gate. Either the source or the drain of the first transistor is One of the sources or drains of the two transistors, and the source or drain of the fifth transistor. One side of the eighth transistor is electrically connected to either the source or the drain. The source or drain of the fifth transistor is connected to the first gate of the sixth transistor. The first terminal of the second capacitance is electrically connected to the source or drain of the eighth transistor. The other end of the input is electrically connected to the first gate of the ninth transistor and the first terminal of the third capacitor. It continues. The first gate of the second transistor is connected to the first terminal of the first capacitor and the third transistor One of the source or drain of the 4th transistor, The first gate of the 7th transistor and the first gate of the 10th transistor are electrically connected. It is done. Either the source or drain of the 7th transistor is connected to the source of the 6th transistor. It is electrically connected to either the drain or the second terminal of the second capacitance. One of the transistor's sources or drains is one of the sources or drains of the 9th transistor. It is electrically connected to the second terminal of the third capacitance.

[0017] (3) Alternatively, in one aspect of the present invention, in (2) above, the first gate of the 11th transistor is The configuration may also involve electrically connecting to the second gate of the 11 transistors.

[0018] (4) Alternatively, one aspect of the present invention comprises a first transistor, a second transistor, and a third transistor The fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor The 8th transistor, the 9th transistor, the 10th transistor, and the 11th transistor. A semiconductor having a zista, a twelfth transistor, a first capacitor, a second capacitor, and a third capacitor. It is a conductive device. The first gate of the first transistor is the source or gate of the eleventh transistor. One side of the rain is electrically connected to either the source or drain of the 12th transistor. The other of the source or drain of the 11th transistor is the first gate of the 11th transistor. The first gate of the fourth transistor and the source or drain of the twelfth transistor. It is electrically connected to the first transistor. Either the source or the drain of the first transistor is connected to the second transistor. One of the sources or drains of the two transistors, and the source or drain of the fifth transistor. One side of the eighth transistor is electrically connected to either the source or the drain. The source or drain of the fifth transistor is connected to the first gate of the sixth transistor. The first terminal of the second capacitance is electrically connected to the source or drain of the eighth transistor. The other end of the input is electrically connected to the first gate of the ninth transistor and the first terminal of the third capacitor. It continues. The first gate of the second transistor is connected to the first terminal of the first capacitor and the third transistor One of the source or drain of the 4th transistor, The first gate of the 7th transistor and the first gate of the 10th transistor are electrically connected. It is done. Either the source or drain of the 7th transistor is connected to the source of the 6th transistor. It is electrically connected to either the drain or the second terminal of the second capacitance. One of the transistor's sources or drains is one of the sources or drains of the 9th transistor. The source of the sixth transistor is electrically connected to the second terminal of the third capacitance. The other end of the drain is electrically connected to the first gate of the 12th transistor.

[0019] (5) Alternatively, in one aspect of the present invention, in any one of (1) to (4) above, the fifth transient The first gate of the sta is electrically connected to the second gate of the fifth transistor, and the eighth transistor Even if the first gate of the eighth transistor is electrically connected to the second gate of the eighth transistor, good.

[0020] (6) Alternatively, one aspect of the present invention comprises a first transistor, a second transistor, and a third transistor The fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor The 8th transistor, the 9th transistor, the 10th transistor, and the 1st capacitor, A semiconductor device having a second capacitance and a third capacitance. The first gate of the first transistor It is electrically connected to the first gate of the fourth transistor, and the source or One of the drains is connected to either the source or drain of the second transistor, and to the fifth transistor. The source or drain of one of the transistors, and the source or drain of the eighth transistor, They are electrically connected. The source or drain of the 5th transistor is connected to the 6th transistor. The first gate of the transistor and the first terminal of the second capacitor are electrically connected. The eighth transistor The source or drain of the transistor is connected to the first gate of the ninth transistor and the first capacitor of the third capacitor. The terminals are electrically connected to the first capacitor. The first gate of the second transistor is connected to the first capacitor. The terminal, either the source or drain of the third transistor, and the source or drain of the fourth transistor This is connected to one side of the drain, the first gate of the 7th transistor, and the first gate of the 10th transistor. The second gate of the fifth transistor and the second gate of the eighth transistor are electrically connected. They are connected. Either the source or drain of the 7th transistor is connected to the 6th transistor. The first capacitor is electrically connected to either the source or the drain, and to the second terminal of the second capacitor. Either the source or drain of transistor 0 is connected to the source or drain of transistor 9. One side of it is electrically connected to the second terminal of the third capacitance.

[0021] (7) Alternatively, one aspect of the present invention comprises a first transistor, a second transistor, and a third transistor The 4th transistor, the 6th transistor, the 7th transistor, and the 9th transistor A semiconductor having a 10th transistor, a 1st capacitor, a 2nd capacitor, and a 3rd capacitor. It is a device. The first gate of the first transistor is electrically connected to the first gate of the fourth transistor. It is connected to the source or drain of the first transistor, and one of the sources or drains of the second transistor is connected to the source of the second transistor. The drain or the other, the first gate of the sixth transistor, the first terminal of the second capacitor, and the It is electrically connected to the first gate of the 9 transistor and the first terminal of the 3 capacitor. The first gate of the two transistors is connected to the first terminal of the first capacitor and to the source or of the third transistor. One side of the drain, one side of the source or drain of the fourth transistor, and the seventh transistor The first gate of the 7th transistor is electrically connected to the first gate of the 10th transistor. Either the source or drain of the transistor is the source or drain of the sixth transistor. One side is electrically connected to the second terminal of the second capacitance. The 10th transistor's saw Either the source or the drain of the 9th transistor is connected to either the source or the drain of the 3rd capacitor. It is electrically connected to the second terminal.

[0022] (8) Alternatively, in one aspect of the present invention, in any one of (1) to (7) above, the first transient The first gate of the sta is electrically connected to the second gate of the first transistor, and the third transistor The first gate of transistor 6 is electrically connected to the second gate of transistor 3, and transistor 6 The first gate of the 6th transistor is electrically connected to the second gate of the 9th transistor. The first gate may be electrically connected to the second gate of the ninth transistor. .

[0023] (9) Alternatively, in one aspect of the present invention, in any one of (1) to (8) above, the seventh transition The second gate of the 7th transistor is electrically connected to the other of the source or drain of the 7th transistor. The second gate of the 10th transistor is connected to the other side of the source or drain of the 10th transistor. It may also be configured to be electrically connected.

[0024] (10) Alternatively, in one aspect of the present invention, in any one of (1) to (9) above, the second transient The first and fourth transistors are both multi-gate transistors. It can also be used as a composition.

[0025] (11) Alternatively, one aspect of the present invention includes a semiconductor device comprising any one of the above (1) to (10). A gate driver circuit having a sub-resistor, a source driver circuit, and a pixel array, It is a display device.

[0026] (12) Alternatively, one aspect of the present invention is an electronic device having the display device described in (11) above and a housing. be.

[0027] In this specification, a semiconductor device is a device that utilizes semiconductor properties. A circuit including structural elements (e.g., transistors, diodes, and photodiodes), and the same This refers to devices that have a circuit, etc. It also refers to all devices that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronics in which chips are housed in a package. Each component is an example of a semiconductor device. Other examples include memory devices, display devices, light-emitting devices, and lighting. Devices and electronic equipment may themselves be semiconductor devices, and may possess semiconductor devices. There are cases where this is the case.

[0028] Furthermore, if it is stated in this specification, etc., that X and Y are connected, then X and When Y is electrically connected, when X and Y are functionally connected, and when X and The case in which Y and are directly connected is disclosed in this specification, etc. Furthermore, the predetermined connection relationships, for example, the connection relationships shown in the diagram or text, are not limited to those shown in the diagram or text. Other connection relationships besides those shown are also disclosed in the diagram or text. X and Y are, Let's assume the object is (for example, a device, element, circuit, wiring, electrode, terminal, conductive film, and layer). .

[0029] One example of a case where X and Y are electrically connected is when the electrical connection between X and Y is possible. Elements that perform this function (for example, switches, transistors, capacitive elements, inductors, resistive elements, etc.) One or more (electrodes, display devices, light-emitting devices, and loads) are connected between X and Y. It is possible to do so. Furthermore, the switch has a function that controls on / off. In other words, the switch can be in a conductive state (on state) or a non-conductive state (off state), and current flows. It has a function to control whether or not to release the fluid.

[0030] Note that between X and Y, there are elements and power lines (for example, VDD (high power potential), VSS (low power potential) Both the source potential, GND (ground potential), or wiring that provides the desired potential are provided. In such cases, it shall not be stipulated that X and Y are electrically connected. If only power lines are placed between X and Y, then there are no other elements between X and Y. Therefore, X and Y are directly connected. Thus, there is a power supply between X and Y. If only lines are present, it can also be said that "X and Y are electrically connected." However, if both the element and the power line are located between X and Y, then X and the power line Y and the power line are electrically connected (through the element). However, this does not mean that X and Y are electrically connected. For example, X and the gate of a transistor are electrically connected, and Y and the socket of the transistor are connected. When X and Y are electrically connected, it is not defined as X and Y being electrically connected. It shall be assumed that there is no such thing. Also, X and the gate of the transistor are electrically connected, and Y and the transistor If the drain of the inverter is electrically connected, then X and Y are electrically connected. It shall not be stipulated that X and the drain of the transistor are electrically When connected to and Y and the source of the transistor are electrically connected, X and Y and It shall be defined that they are electrically connected. Furthermore, a capacitive element is provided between X and Y. If they are arranged, it is specified that X and Y are electrically connected. There are cases where this does not occur. For example, in the configuration of a digital circuit or logic circuit, between X and Y It is not defined that if a capacitive element is placed, X and Y are electrically connected. In some cases, this does not happen. On the other hand, for example, in the configuration of an analog circuit, there is a capacitance between X and Y. In cases where elements are present, it is sometimes specified that X and Y are electrically connected. be.

[0031] One example of a functional connection between X and Y is a functional connection between X and Y. Circuits that can perform this function (for example, logic circuits (for example, inverters, NAND gates, and NOR gates) ), signal conversion circuits (for example, digital-to-analog conversion circuits, analog-to-digital conversion circuits, and (and gamma correction circuit), potential level conversion circuit (for example, a power supply such as a boost circuit or a buck circuit) Circuits, and level shifter circuits that change the potential level of signals, voltage sources, current sources, switching circuits Paths, amplification circuits (for example, circuits that can increase signal amplitude or current, operational amplifiers, differentials) Amplifier circuit, source follower circuit, and buffer circuit), signal generation circuit, memory circuit, and control One or more of these circuits can be connected between X and Y. For example, If a signal output from X is transmitted to Y, even if another circuit is placed between X and Y, Assume that X and Y are functionally connected.

[0032] Furthermore, if it is explicitly stated that X and Y are electrically connected, then X and Y are electrically connected. When connected electrically (i.e., connected with another element or circuit in between X and Y) (if such a connection exists) and (if X and Y are directly connected) This includes cases where the elements or other circuits are connected without an intervening element.

[0033] Also, for example, "X and Y and the source of the transistor (either the first terminal or the second terminal) (This may be rephrased as) and drain (the other of the first or second terminal) (There is) means that they are electrically connected to each other, and X, the source of the transistor, the transistor It can be expressed as: "The drain of T is electrically connected, followed by Y." Or, The source of the transistor is electrically connected to X, and the drain of the transistor is electrically connected to Y. Connected in this order: X is the source of the transistor, Y is the drain of the transistor. It can be expressed as "electrically connected". Or, "X is the transistor's saw Y is electrically connected to X via the drain, and X is the source of the transistor. This can be expressed as "the drain of the sta, Y, is provided in this connection order." Using a similar method of expression as in the example, we will specify the order of connections in the circuit configuration. Therefore, distinguishing between the source and drain of a transistor helps determine its technical scope. Yes, it is possible. Note that these expressions are just examples and are not limited to these. Here, X and Y are objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films, or Let's assume it's a layer.

[0034] Note that, in circuit diagrams, independent components are shown as being electrically connected to each other. Even if such a combination exists, one component may possess the functions of multiple components. Yes. For example, if part of the wiring also functions as an electrode, one conductive film will function as the wiring, and It possesses the functions of both components of the electrode. Therefore, in this specification Electrically connected means that a single conductive film combines the functions of multiple components. This also falls under that category.

[0035] Furthermore, in this specification, etc., "resistive element" refers, for example, to an element having a resistance value higher than 0Ω. It can be a circuit element or wiring with a resistance value higher than 0Ω. Therefore, In this specification, etc., "resistive element" refers to a wiring having a resistance value, with current flowing between the source and drain. This includes transistors, diodes, coils, etc., through which current flows. The term "child" can be rephrased as "resistance," "load," or "region with resistance." In some cases, this is possible. Conversely, "resistance," "load," or "region having resistance" The term can sometimes be replaced with the term "resistive element." For example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, More preferably, the resistance can be between 10 mΩ and 1 Ω. Also, for example, 1 Ω or more × 10 9 It may also be less than or equal to Ω.

[0036] Furthermore, in this specification, "capacitive element" refers to, for example, a capacitance value higher than 0F. A circuit element having a capacitance value higher than 0F, a region of wiring having a capacitance value higher than 0F, parasitic capacitance, or It can be used as the gate capacitance of a transistor. Also, it can be referred to as a "capacitive element," "parasitic capacitance," or The term "gate capacity" can sometimes be replaced with the term "capacity." Conversely, the term "capacitance" is used in phrases such as "capacitive element," "parasitic capacitance," and "gate capacitance." In some cases, the term can be rephrased. Also, the term "capacitance" and "pair of electrodes" This can be rephrased as "a pair of conductors," "a pair of conductive regions," or "a pair of regions." It is possible. Furthermore, the capacitance value should be, for example, between 0.05 fF and 10 pF. This is possible. Alternatively, for example, it may be set to between 1pF and 10μF.

[0037] Furthermore, in this specification, a transistor is referred to as gate, source, and drain. It has three terminals. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as source or drain are the input and output terminals of the transistor. The input / output terminals specify the transistor's conductivity type (n-channel type, p-channel type) and the transistor's... Depending on the potential applied to the three terminals of the sta, one becomes the source and the other the drain. Therefore, in this specification, the terms source and drain are used interchangeably. It may be possible to change them. Furthermore, this specification and other documents describe the connection relationships of transistors. When doing so, "either the source or the drain" (or the first electrode or the first terminal), "source or The notation "the other side of the drain" (or second electrode, or second terminal) is used. Depending on the structure of the connector, it may have a back gate in addition to the three terminals mentioned above. In this case, in this specification, etc., one of the gate or back gate of the transistor is the first The gate is referred to as the gate, and the other of the gate or back gate of a transistor is referred to as the second gate. This can happen. Furthermore, in the same transistor, the terms "gate" and "back gate" are... They can sometimes be swapped with each other. Also, a transistor has three or more gates. In this specification, the respective gates are referred to as the first gate, the second gate, and the third gate. It is sometimes referred to as a gate.

[0038] For example, in this specification, an example of a transistor is one with two or more gate electrodes. A multi-gate transistor can be used. With a multi-gate structure, Because the channel formation regions are connected in series, the structure is such that multiple transistors are connected in series. Therefore, the multi-gate structure reduces off-current and improves the transistor's breakdown voltage (trust). (Improved reliability) can be achieved. Alternatively, the multi-gate structure can be used to operate in the saturation region. When this happens, even if the voltage between the drain and source changes, the current between the drain and source remains constant. A voltage-current characteristic with little change and a flat slope can be obtained. By utilizing the voltage-current characteristics, an ideal current source circuit or a very high resistance value can be created. This enables the realization of an active load. As a result, a differential circuit or current mirror with good characteristics can be achieved. - Circuits and other features can be implemented.

[0039] Furthermore, even if a single circuit element is shown in the circuit diagram, if there are multiple such circuit elements... It may have circuit elements. For example, if one resistor is shown on the circuit diagram This includes cases where two or more resistors are electrically connected in series. Also, for example... If only one capacitor is shown on the circuit diagram, it means that two or more capacitors are electrically connected in parallel. This includes cases where a single transistor is shown on the circuit diagram. If so, two or more transistors are electrically connected in series, and each This includes cases where the gates of transistors are electrically connected to each other. For example, if one switch is shown on the circuit diagram, then if there are two or more of those switches... Having the above transistor, two or more transistors are electrically connected in series or parallel. This includes the case where the gates of each transistor are electrically connected to each other. .

[0040] Furthermore, in this specification, etc., a node is defined as having terminals, depending on the circuit configuration and device structure. These terms can be rephrased as wiring, electrodes, conductive layers, conductors, impurity regions, etc. Also, terminals. Wiring and other components can be referred to as nodes.

[0041] Furthermore, in this specification and other documents, "voltage" and "potential" may be used interchangeably as appropriate. Voltage is the potential difference from a reference potential. For example, if the reference potential is ground... If we consider it as the ground potential, then "voltage" can be replaced with "potential." Round potential does not necessarily mean 0V. Also, potential is relative. The potential applied to the wiring, the potential applied to the circuit, etc., changes as the reference potential changes. The electric potential, including the potential output from circuits, also changes.

[0042] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" are defined as follows: This does not mean a specific potential. For example, in two wires, both are "high level" If it is stated that it functions as a wire that supplies potential, then both wires will provide that potential. These high-level potentials do not have to be equal. Similarly, in two wires, If both are described as "functioning as wiring that supplies a low level potential", then both The low-level potentials provided by each wire do not have to be equal to each other.

[0043] Furthermore, "electric current" refers to the phenomenon of electric charge movement (electrical conduction), for example, "positive charge The statement "electrical conduction is occurring in the body" means "electrical conduction is occurring in the opposite direction for negatively charged bodies." This can be rephrased as "current is." Therefore, in this specification, "electric current" means, in particular Unless otherwise specified, this refers to the phenomenon of charge transfer associated with carrier movement (electrical conduction). Examples of carriers in this context include electrons, holes, anions, cations, and complex ions. The carriers differ depending on the system through which the current flows (e.g., semiconductors, metals, electrolytes, and vacuum). In addition, the "direction of current" in wiring is the direction in which the positively charged carriers move. It is expressed as a positive current. In other words, the direction in which negatively charged carriers move is the direction of the current. It is in the opposite direction to the direction and is expressed as a negative current quantity. Therefore, in this specification, etc., current If there is no indication of the positive or negative sign (or direction of the current), it means that "current flows from element A to element B." The statement " " can be rephrased as "current flows from element B to element A". Also, the statement "current is input to element A" should be rephrased as "current is output from element A." It shall be possible to obtain it.

[0044] Furthermore, in this specification, the ordinal numbers "1st," "2nd," and "3rd" refer to constituent elements. This was added to avoid confusion. Therefore, it does not limit the number of constituent elements. Furthermore, this does not limit the order of the components. For example, one of the embodiments described herein The components referred to as "first" in this invention may be used in other embodiments or claims. It may also be the component referred to in "Section 2". For example, in this specification, etc. In one embodiment, the component referred to as "first" may be used in other embodiments, or in other embodiments. It may be possible to omit certain details within the scope of the permitted claim.

[0045] Furthermore, in this specification, phrases indicating placement such as "above" and "below" refer to the composition. In some cases, the relative positions of elements are used for convenience when explaining them by referring to diagrams. The positional relationships between the elements change appropriately depending on the direction in which each element is depicted. Therefore, the terminology is not limited to what is explained in the specifications, etc., but can be appropriately rephrased depending on the situation. For example, the expression "insulator located on the upper surface of the conductor" is used when the orientation of the drawing shown is 180°. By rotating it by a certain degree, it can be rephrased as "an insulator located on the underside of the conductor." .

[0046] Furthermore, the terms "up" or "down" refer to situations where the relative positions of the constituent elements are directly above or directly below, and directly below. It does not necessarily mean that they are in contact. For example, the expression "electrode B on insulating layer A" Therefore, it is not necessary for electrode B to be directly in contact with insulating layer A, and insulating layer A and electrode B This does not exclude cases that include other components between them.

[0047] Furthermore, in this specification, the matrix-like arrangement of components and their positional relationships are described as follows: To explain, terms such as "row" and "column" may be used. The positional relationships of the elements change appropriately depending on the direction in which each component is depicted. Therefore, the specification The terms explained above are not the only ones that can be used; they can be appropriately rephrased depending on the situation. For example, The expression "row direction" is used when the orientation of the drawing shown is rotated by 90 degrees to become "column direction". It can sometimes be rephrased as "towards".

[0048] Furthermore, in this specification, the terms "membrane" and "layer" may be used interchangeably depending on the context. It is possible to replace the term "conductive layer" with "conductive film". In some cases, it may be possible to change the word. Or, for example, the term "insulating film" can be changed to "insulating film." It may be possible to change the term to "layer". Or, in some cases, or in some situations. Depending on the context, the terms "membrane" and "layer" can be replaced with other terms. It is possible. For example, the term "conductive layer" or "conductive film" can be changed to the term "conductor". It may be possible to change it. Or, for example, the term "insulating layer" or "insulating film". In some cases, it may be possible to change the term to "insulator".

[0049] Furthermore, in this specification, the terms "electrode," "wiring," and "terminal" are used in accordance with these This does not functionally limit the components. For example, "electrodes" are part of "wiring". It can be used in this way, and vice versa. Furthermore, the terms "electrode" or "wiring" are used in this way. The terminology also includes cases where multiple "electrodes" or "wirings" are formed as a single unit. Also, for example, "terminal" can be used as part of "wiring" or "electrode". and vice versa. Furthermore, the term "terminal" also includes cases where one or more elements selected from a plurality of "electrodes", "wirings", and "terminals" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or a "terminal", and for example, a " terminal" can be part of a "wiring" or an "electrode". In addition, terms such as "electrode", "wiring", or "terminal" may be replaced with terms such as "region" depending on circumstances. .

[0050] In addition, in this specification and the like, terms such as "wiring", "signal line", or "power supply line" can be interchanged with each other depending on the case or situation. For example, a " wiring" may be changed to the term "signal line" in some cases. In addition, for example, the term "wiring" may be changed to a term such as "power supply line" in some case s. Also, vice versa, terms such as "signal line" or "power supply line" may be changed to the term " wiring" in some cases. The term "power supply line" may be changed to the term "signal line" in some cases. Also, vice versa, the term "signal line" may be changed to the term "power supply line" in some cases. In addition, the term " potential" applied to a wiring may be changed to the term "signal" depending on the case or situation in some cases. Also, vice versa, the term "signal" may be changed to the term " potential" in some cases.

[0051] In this specification and the like, an impurity in a semiconductor refers to, for example, a component other than the main component constituting a semiconductor layer. For example, an element having a concentration of less than 0.1 atomic% is an impurity. Due to the inclusion of impurities, For example, this may lead to an increase in the density of defect states in the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 ele ments, Group 14 elements, Group 15 elements, transition metals other than the main component, and in particular, for example, hydro gen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like. Specifically, when the semiconductor is silicon, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements (provided that oxygen and hydrogen are not included).

[0052] In this specification and the like, a switch refers to a device that can be in a conducting state (on state) or a non-conducting state (off state) and has a function of controlling whether current flows or not. Alternatively, a swit ch refers to a device that has a function of selecting and switching a current flow path. Therefore, a swit ch may have two or three or more current-carrying terminals in addition to a control terminal. As an example, an electrical switch, a mechanical switch, or the like can be used. That is a switch is not limited to a specific type as long as it can control current flow.

[0053] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) di odes, MIS (Metal Insulator Semiconductor) di Odes, diode-connected transistors, etc., or logic circuits combining these. There is. Furthermore, when using a transistor as a switch, the "conductivity state" of the transistor... For example, if the source and drain electrodes of a transistor are electrically short-circuited... A state in which current can be passed between the source electrode and the drain electrode. Also, the "non-conductive state" of a transistor refers to the state where the source electrode and drain electrode of the transistor are connected. This refers to a state in which the poles can be considered electrically blocked. Note that a transistor is not simply a switch. When operating in this manner, the polarity (conductivity type) of the transistor is not particularly limited.

[0054] One example of a mechanical switch is MEMS (Micro-Electro-Mechanical Systems). There is a switch that uses STEMS technology. This switch is mechanically operated It has electrodes, and operates by controlling the transition between conductivity and non-conductivity through the movement of these electrodes.

[0055] Furthermore, in this specification, etc., metal mask, or FMM (Fine Metal Mask, High Devices fabricated using a fine metal mask are called MM (metal mask) structure devices. It may be referred to as "S". Also, in this specification, etc., metal mask or FMM is used. Devices manufactured without the need for a metal mask are called MML (Metal Maskless) devices. There are cases where this occurs.

[0056] In this specification, etc., each color of light-emitting device (here, blue (B), green (G), and A structure that creates or paints different light-emitting layers using red (R) is called SBS (Side It is sometimes referred to as a By Side structure. Also, in this specification, etc., it emits white light. A light-emitting device capable of this may be referred to as a white light-emitting device. Note that a white light-emitting devic ce can be used as a full-color display device by combining it with a colored layer (e.g., a color filter). device.

[0057] Furthermore, light-emitting devices can be broadly classified into a single structure and a tandem structure. A singl le-structure device has one light-emitting unit between a pair of electrodes, and this light-emitting unit preferably has a configuration including one or more light-emitting layers. To obtain white light emission, two or more ligh t-emitting layers may be selected such that the light emission of each light-emitting layer has a complementary color relationship. For example, by making the ligh t emission color of the first light-emitting layer and the light emission color of the second light-emitting layer have a complementary color relationship, the light-emitting devic e as a whole can be configured to emit white light. The same applies to a light-emittin g device having three or more light-emitting layers.

[0058] A tandem-structure device has two or more light-emitting units between a pair of electrodes, and each ligh t-emitting unit preferably has a configuration including one or more light-emitting layers. To obtain white light emission, the configuration may be such that white light emission is obtained by combining light from the light-emitting layers of the plurality of light-emitting units. The configuration for obtaining white light emission is the same as that of the single structure. Note that in a tand em-structure device, it is preferable to provide an intermediate layer such as a charge generation layer between the plurality of light-emitting units . It is suitable to provide such an intermediate layer.

[0059] Furthermore, when comparing the above-described white light-emitting device (of single structure or tandem structure) with a light-emitting device having an SBS structure light-emitting device, the SBS-structure light-emitting device can achieve lower power consumption than the white light-emitting device. When it is desired to keep power consumption low, an SBS-structure light-emittin g device can also reduce power consumption. When it is desired to keep power consumption low, an SBS-structure light-emittin It is preferable to use a device. On the other hand, white light-emitting devices have an SBS structure in their manufacturing process. Because it is simpler than manufactured light-emitting devices, manufacturing costs can be lowered, or manufacturing It is preferable because it can increase the yield.

[0060] In this specification, "parallel" means that two lines are positioned at an angle of -10° or more and 10° or less. This refers to a state in which it is in a certain condition. Therefore, it also includes cases where the angle is between -5° and 5°. Also, "abbreviated "Parallel" or "approximately parallel" means that two lines are positioned at an angle of -30° or more and 30° or less. It refers to a state in which two lines are aligned at an angle of 80° to 100°. This refers to the state in which something is placed. Therefore, it also includes cases where the angle is between 85° and 95°. Also, "Approximately perpendicular" or "roughly perpendicular" means that two lines are positioned at an angle of 60° to 120°. This refers to a state of being in a certain condition. [Effects of the Invention]

[0061] According to one aspect of the present invention, a semiconductor device that operates stably can be provided. Alternatively, a highly reliable semiconductor device can be provided according to one aspect of the present invention. According to one aspect of the present invention, a display device including the above-described semiconductor device can be provided. Alternatively, according to one aspect of the present invention, to provide an electronic device including the above-described display device. This can be done. Alternatively, according to one aspect of the present invention, a novel semiconductor device, a novel display device, or a new We can provide standard electronic equipment.

[0062] The effects of one embodiment of the present invention are not limited to those listed above. This does not preclude the existence of other effects. These other effects are described below. This is an effect not mentioned in the item. An effect not mentioned in this item would be apparent to someone skilled in the art in the details. This can be derived from descriptions in documents or drawings, and can be appropriately extracted from these descriptions. It is possible. Furthermore, one aspect of the present invention provides at least one of the effects listed above and other effects. It has the following effects. Therefore, in some cases, one aspect of the present invention may have the above-listed effects. It may not always be effective. [Brief explanation of the drawing]

[0063] [Figure 1] Figures 1(A) and 1(B) are circuit diagrams showing examples of semiconductor device configurations. [Figure 2] Figure 2 is a block diagram showing an example of a display device configuration. [Figure 3] Figures 3(A) and 3(B) are circuit diagrams showing examples of semiconductor device configurations. [Figure 4] Figure 4 is a timing chart showing an example of the operation of a semiconductor device. [Figure 5] Figure 5 is a circuit diagram showing an example of a semiconductor device configuration. [Figure 6] Figures 6(A) and 6(B) are circuit diagrams showing examples of semiconductor device configurations. [Figure 7] Figures 7(A) and 7(B) are circuit diagrams showing examples of semiconductor device configurations. [Figure 8] Figure 8 is a circuit diagram showing an example of a semiconductor device configuration. [Figure 9] Figures 9(A) and 9(B) are circuit diagrams showing examples of semiconductor device configurations. [Figure 10] Figures 10(A) and 10(B) are circuit diagrams showing examples of semiconductor device configurations. [Figure 11] Figure 11 is a circuit diagram showing an example of a semiconductor device configuration. [Figure 12] Figures 12(A) and 12(B) are circuit diagrams showing examples of semiconductor device configurations. [Figure 13]Figure 13 is a circuit diagram showing an example of a semiconductor device configuration. [Figure 14] Figures 14(A) and 14(B) are circuit diagrams showing examples of semiconductor device configurations. [Figure 15] Figures 15(A) and 15(B) are circuit diagrams showing examples of semiconductor device configurations. [Figure 16] Figure 16 is a circuit diagram showing an example of a semiconductor device configuration. [Figure 17] Figure 17 is a layout diagram showing an example of a semiconductor device configuration. [Figure 18] Figure 18 is a schematic cross-sectional view showing an example of the configuration of a display device. [Figure 19] Figure 19 is a block diagram showing an example of a display device configuration. [Figure 20] Figure 20 is a block diagram showing an example of the configuration of an imaging device. [Figure 21] Figures 21(A) and 21(B) are circuit diagrams showing an example of an imaging pixel. [Figure 22] Figure 22 is a block diagram showing an example of a display device configuration. [Figure 23] Figure 23 is a block diagram showing an example of a display device configuration. [Figure 24] Figure 24 is a schematic cross-sectional view showing an example of the configuration of a display device. [Figure 25] Figures 25(A) to 25(D) are schematic diagrams showing examples of the configuration of a light-emitting device. [Figure 26] Figure 26 is a schematic cross-sectional view showing an example of the configuration of a display device. [Figure 27] Figures 27(A) and 27(B) are schematic cross-sectional diagrams showing examples of the configuration of a display device. [Figure 28] Figures 28(A) and 28(B) are schematic cross-sectional diagrams showing examples of the configuration of a display device. [Figure 29] Figures 29(A) and 29(B) are schematic cross-sectional diagrams showing examples of the configuration of a display device. [Figure 30] Figures 30(A) and 30(B) are schematic cross-sectional diagrams showing examples of the configuration of a display device. [Figure 31] Figures 31(A) to 31(F) are cross-sectional views showing an example of a method for manufacturing a display device. [Figure 32] Figure 32(A) is a circuit diagram showing an example of the configuration of a pixel circuit included in a display device, and Figure 32(B) is a schematic perspective view showing an example of the configuration of a pixel circuit included in a display device. [Figure 33] Figures 33(A) to 33(D) are circuit diagrams showing examples of the configuration of pixel circuits included in a display device. [Figure 34] Figures 34(A) to 34(D) are circuit diagrams showing examples of the configuration of pixel circuits included in a display device. [Figure 35] Figures 35(A) and 35(B) are plan views showing examples of the configuration of a light-emitting device and a light-receiving device included in a display device. [Figure 36] Figures 36(A) to 36(D) are schematic cross-sectional diagrams showing examples of the configuration of a light-emitting device, a light-receiving device, and connecting electrodes included in a display device. [Figure 37] Figures 37(A) to 37(G) are plan views showing an example of a pixel. [Figure 38] Figures 38(A) to 38(F) are plan views showing examples of pixels. [Figure 39] Figures 39(A) to 39(H) are plan views showing an example of a pixel. [Figure 40] Figures 40(A) to 40(D) ​​are plan views showing an example of a pixel. [Figure 41] Figures 41(A) to 41(D) are plan views showing an example of a pixel, and Figure 41(E) is a cross-sectional view showing an example of a display device. [Figure 42] Figures 42(A) and 42(B) show examples of the configuration of a display module. [Figure 43] Figures 43(A) through 43(F) show examples of the configuration of electronic equipment. [Figure 44] Figures 44(A) through 44(D) show examples of the configuration of electronic equipment. [Figure 45] Figures 45(A) to 45(C) show examples of the configuration of electronic equipment. [Figure 46] Figures 46(A) through 46(H) show examples of the configuration of electronic equipment. [Modes for carrying out the invention]

[0064] In this specification, metal oxide refers to metal in a broad sense. It is an oxide. Metal oxides are oxide insulators and oxide conductors (including transparent oxide conductors). ), oxide semiconductor (also called OS) They are classified into categories such as: For example, metal oxides are included in the channel formation region of transistors. In some cases, the metal oxide in question may be referred to as an oxide semiconductor. In other words, the metal oxide increases A transistor having one or more functions selected from widening, rectifying, and switching functions. If a channel-forming region can be formed, the metal oxide is a metal oxide semiconductor (metal It can also be called an oxide semiconductor. When referred to as a transistor, it means a transistor having a metal oxide or oxide semiconductor. This can be rephrased as follows:

[0065] Furthermore, in this specification, metal oxides containing nitrogen are also referred to as metal oxides (metal oxides). They are sometimes collectively referred to as metal oxynitrides (metal oxides). Also, metal oxides containing nitrogen are sometimes called metal oxynitrides (metal oxides). It may also be called tal oxynitride.

[0066] Furthermore, in this specification, the configurations shown in each embodiment are different from the configurations shown in other embodiments. By combining them as appropriate, one embodiment of the present invention can be formed. If multiple configuration examples are provided, it is possible to combine them as appropriate.

[0067] Furthermore, the content described in one embodiment (even a part of it) may be subject to change in implementation. Other details (even partial details) described in the form, and one or more other embodiments The content to be stated (even if only a part of it) should be applied to or combined with at least one other content. It is possible to replace or otherwise perform actions such as [doing something else].

[0068] Furthermore, the content described in each embodiment refers to the use of various figures in each embodiment. This refers to the content described or the content described using the text included in the specification.

[0069] Note that a diagram (even a part of it) described in one embodiment may be a part of that diagram. In that embodiment, another figure (even if only a part of it) and one or more other figures For at least one of the diagrams (even if only a part of it) described in the form of the installation, the combination By doing so, even more diagrams can be constructed.

[0070] Embodiments described herein are explained with reference to the drawings. However, implementation may differ. The form can be implemented in many different ways, and it does not deviate from the purpose and scope. It will be easily understood by those skilled in the art that its form and details can be changed in various ways. Therefore, the present invention is not to be interpreted as being limited to the contents described in the embodiments. In the configuration of the invention in the form of application, the same reference numeral is used for identical parts or parts having similar functions. In some cases, explanations of repetitions used across different drawings may be omitted. Also, perspective drawings. In some cases, the description of certain components may be omitted in order to ensure clarity in the drawings. be.

[0071] In this specification, when the same reference numeral is used for multiple elements, it is particularly important to distinguish between them. When necessary, add identifying codes such as "_1", "[n]", or "[m,n]" to the code. It may be noted and written. Also, in drawings, etc., the symbols “_1”, “[n]”, “[ If identification codes such as "m, n" are attached, there is no need to distinguish them in this specification, etc. In some cases, the identification code may not be included.

[0072] Furthermore, in the drawings of this specification, the size, thickness of the layers, or the area may be exaggerated for clarity. In some cases, this may be the case. Therefore, it is not necessarily limited to that scale. Note that the drawings are This is a schematic representation of a hypothetical example and is not limited to the shapes or values ​​shown in the drawing. This can be due to variations in signals, voltages, or currents caused by noise, or to timing discrepancies. This can include variations in signals, voltages, or currents.

[0073] (Embodiment 1) This embodiment describes a semiconductor device according to one aspect of the present invention.

[0074] Figure 2 shows an example configuration of a display device having a semiconductor device according to one aspect of the present invention. The DSP device, as an example, includes a drive circuit GD, a drive circuit SD, and a pixel array PA. do.

[0075] In Figure 2, the drive circuit GD, the drive circuit SD, the pixel array PA, and the wiring GL[1 ], wiring GL[m], wiring SL[1], wiring SL[n], pixel circuit PX[1,1], pixel Extracting circuit PX[m,1], pixel circuit PX[1,n], and pixel circuit PX[m,n] It is showing.

[0076] A pixel array PA has, for example, multiple pixel circuits PX. Furthermore, the pixel circuits PX are In the pixel array PA, they are arranged in an m x n matrix.

[0077] Note that the sign of the pixel circuit PX shown in Figure 2 indicates the address of that pixel circuit. If the sign of the pixel circuit PX[1,1] is located in the pixel array PA at a position of 1 row and 1 column, This shows the pixel circuit PX. Also, for example, the sign of the pixel circuit PX[m,1] is This shows the pixel circuit PX located at the m-row, 1-column position in the pixel array PA. For example, the sign of pixel circuit PX[1,n] corresponds to the position in row 1, column n of the pixel array PA. This shows the pixel circuit PX located at [location]. Also, for example, the pixel circuit PX[m,n] The sign indicates a pixel circuit PX located at the m-row and n-column position in the pixel array PA. Yes, they are.

[0078] Furthermore, in the i row and j column of the pixel array PA, (where i is an integer between 1 and m, and j is an integer between 1 and n) The pixel circuit PX located at (where it is an integer) is called the pixel circuit PX[i,j] (not shown). Let's assume that the pixel circuit PX[i,j] is electrically connected to the wiring GL[i] as an example. Furthermore, the pixel circuit PX[i,j] is electrically connected to the wiring SL[j], for example. It is being done.

[0079] The drive circuit GD is, for example, electrically connected to wiring GL[1] to wiring GL[m]. Furthermore, the drive circuit SD, as an example, supplies electricity to wiring SL[1] to wiring SL[n]. They are directly connected.

[0080] Each of the wiring GL[1] to wiring GL[m] is, for example, in the pixel array PA. Therefore, the wiring can be extended in the row direction. Also, the wiring GL is attached to [x ] indicates the row number to which the wiring is extended. For example, the sign for wiring GL[1] is This refers to the wiring extending to the first row in the pixel array PA. Also, for example, The sign of wiring GL[m] indicates that the wiring extends to the mth row in the pixel array PA. It is.

[0081] Each of the wirings SL[1] to SL[n] is, for example, in the pixel array PA. Therefore, the wiring can be extended in the row direction. Also, the wiring GL is attached to [y ] indicates the row number to which the wiring is extended. For example, the sign for wiring GL[1] is This refers to the wiring extending to the first row in the pixel array PA. Also, for example, The sign of the wiring GL[n] indicates the wiring that extends to the nth column in the pixel array PA. It is.

[0082] Pixel circuits PX are, for example, liquid crystal display devices, light-emitting devices including organic EL materials, and One or more light-emitting devices selected from light-emitting diodes (e.g., microLEDs) The applied pixel circuit can be made. In this embodiment, the pixel array PA The basic circuit PX is described as having a light-emitting device containing organic EL material applied to it. In particular, the brightness of light emitted from a light-emitting device capable of high-brightness emission is, for example, 50 0 cd / m 2 Preferably 1000 cd / m² 2 More than 10000cd / m 2 The following, Preferably 2000 cd / m² 2 More than 5000cd / m 2 The following is possible. Pixel circuits applicable to pixel circuits such as PX will be described in detail in Embodiment 4.

[0083] The drive circuit GD, as an example, in the pixel array PA of a display device DSP, processes image data. It has a function to select the pixel circuit PX to which the transmission will be sent. For this reason, the drive circuit GD is a gateway This can be referred to as a to-driver circuit, etc.

[0084] Furthermore, as described above, the wiring GL that electrically connects the drive circuit GD and the pixel circuit PX is For example, it functions as a wire that transmits a selection signal. Note that the wire GL transmits a selection signal. It may function not only as a signaling wire, but also, for example, as a wire supplying a constant potential.

[0085] The drive circuit SD is, as an example, the pixel circuit PX in the pixel array PA of a display device DSP. It has the function of transmitting image data to the source drive. For this reason, the drive circuit SD is a source drive This can be called an IBA circuit, for example.

[0086] Furthermore, as described above, the wiring SL that electrically connects the drive circuit SD and the pixel circuit PX is For example, it functions as wiring that transmits image data as a signal. Note that wiring SL is It functions not as wiring to transmit image data, but, for example, as wiring to supply a constant potential. That's fine.

[0087] Note that the display device DSP shown in Figure 2 has wiring GL[1] to wiring GL[m], and wiring Other wiring besides SL[1] to wiring SL[n] may be extended. For example, display device D SP may have wiring extending from it that provides a constant potential to supply to the pixel circuit PX.

[0088] Next, we will describe an example configuration of the drive circuit GD.

[0089] Figure 3(A) shows a drive circuit according to one embodiment of the present invention, which can be applied to the display device DSP of Figure 2. This shows an example of the configuration of GD. The drive circuit GD shown in Figure 3(A) is, as an example, a rotation It has a path 100[1] or a circuit 100[m].

[0090] Each of circuits 100[1] through 100[m] includes, for example, terminal IT and terminal OT. It has terminals CLK1, CLK2, and GT.

[0091] In each of circuits 100[1] to 100[m], for example, terminal CLK1 is Electrically connected to wiring CL1, terminal CLK2 is electrically connected to wiring CL2, terminal P WC is electrically connected to wiring PL.

[0092] Wiring CL1, wiring CL2, and wiring PL are each connected to a signal such as a clock signal. It functions as wiring that provides a voltage change (sometimes referred to as pulse voltage in this specification). In addition, one or more wires selected from wiring CL1, wiring CL2, and wiring PL will be at a variable potential. Alternatively, it can be used as wiring that provides a constant potential.

[0093] The terminal OT of circuit 100[k] (where k is an integer between 1 and m-1) is, for example, It is electrically connected to terminal IT of 100[k+1].

[0094] Terminal GT of circuit 100[i] is electrically connected to, for example, wiring GL[i].

[0095] Each of circuits 100[1] to 100[m] is, for example, input to terminal IT. The function of retaining the information and the function of displaying the retained information to one or both of terminals OT and GT. It has the function of outputting.

[0096] Also, for example, when a variable potential is input to terminal CLK1, circuit 100[i] It has the function of outputting the information held in path 100[i] to terminal OT. Also, for example When a variable potential is input to terminal PWC, circuit 100[i] It has a function to output the held information to terminal GT. Also, for example, circuit 100[i ] is held in circuit 100[i] when a variable potential is input to terminal CLK2. It has a function to reset the information. Also, circuit 100[i] holds After the information is reset, new information is input to terminal IT of circuit 100[i]. It is preferable to configure the circuit 100[i] to retain new information by doing so.

[0097] As described above, in circuit 100[1] to circuit 100[m], circuit 100[1] After information is input to terminal IT, terminals CLK1 and CLK2 are activated at the appropriate timing. When a variable potential is input to this, the information is sequentially transmitted to the circuit 100[2] and subsequent circuits. This is possible. Also, after information is input to terminal IT of circuit 100[1], an appropriate tie When a variable potential is input to terminal PWC during the ming, circuit 100[1] to circuit 1 The information held in each of 00[m] is transmitted to circuits 100[1] through 100[m] Outputs can be made from each of the terminals GT. For this reason, in this specification, etc., circuit 10 A configuration of 0[1] to 100[m] can be called a shift register.

[0098] Furthermore, the information mentioned above refers, for example, to the image data that is written to the pixel array PA. This can be used as a selection signal to select the elementary circuit PX. Note that in Figure 3(A), The selection signal is illustrated as signal SS.

[0099] In the drive circuit GD shown in Figure 3(A), terminal OT is shown in circuit 100[m]. However, circuits 100[1] to 100[m] are configured as shift registers. Therefore, circuit 100[m] may be configured without providing terminal OT.

[0100] Furthermore, the configuration of the drive circuit GD applicable to the display device DSP in Figure 2 is not limited to that shown in Figure 3(A). It is not possible. For example, the configuration of the drive circuit GD that can be applied to the display device DSP in Figure 2 is shown in Figure 3. The drive circuit GD shown in (B) may also be used.

[0101] The drive circuit GD in Figure 3(B) has circuits BF[1] to BF[m], This differs from the drive circuit GD in Figure 3(A).

[0102] In the drive circuit GD shown in Figure 3(B), the inputs of circuits BF[1] to BF[m] The terminals are electrically connected one-to-one with each terminal GT of circuits 100[1] to 100[m]. The output terminals of circuits BF[1] through BF[m] are connected to the wiring GL[1 Each of the ] or wiring GL[m] is electrically connected on a one-to-one basis.

[0103] Each of circuits BF[1] through BF[m] is, for example, a buffer circuit, an inverter. The configuration may include an amplification circuit, such as a circuit or latch circuit. Each of circuits BF[1] to BF[m] is connected to the potential of terminal GT. The system can have a function to output an amplified potential to the line GL.

[0104] Note that the drive circuit GD shown in Figures 3(A) and 3(B) has wiring CL1 and wiring CL2 , and wiring other than wiring PL may be extended. For example, circuit 100[1] to circuit Wiring may be provided to drive each of the 100m sections, supplying a constant potential.

[0105] <Configuration Example 1> Next, the circuits 100[1] to the respective drive circuits GD in Figure 3(A) and Figure 3(B) This section describes a specific example of the circuit configuration for circuit 100[m].

[0106] Figure 1(A) is a semiconductor device according to one aspect of the present invention, as shown in Figures 3(A) and 3(B). The circuit configuration can be applied to each drive circuit GD, from circuit 100[1] to circuit 100[m]. An example is shown. Circuit 100A1, as an example, uses transistor MN1 to transistor It has a capacitor MN10, capacitors C1, C2, and C3. Also, circuit 100A1 For example, terminal IT, terminal PWC, terminal CLK1, terminal CLK2, and terminal G It has terminal T and terminal OT.

[0107] For example, the transistors MN1 through MN10 are OS transistors. It is preferable to apply this. In particular, metallic acids contained in the channel formation region of OS transistors Examples of oxides include indium, element M, and zinc in In-M-Zn oxide ( Element M includes aluminum, gallium, yttrium, tin, copper, vanadium, and beryllium. Boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, Choose from cerium, neodymium, hafnium, tantalum, tungsten, or magnesium. It is preferable to use one or more types of transistors. A transistor having silicon in the channel formation region (hereinafter referred to as a Si transistor) ) may be applied. Also, as silicon, for example, single crystal silicon, amorphous silicon Con (sometimes called hydrogenated amorphous silicon), microcrystalline silicon, or polycrystalline silicon. Silicon can be used. In addition, other than OS transistors and Si transistors. For example, in transistors, germanium (Ge) is included in the channel formation region. The transistors used are zinc selenide (ZnSe), cadmium sulfide (CdS), and gallium carbonate. Indium (GaAs), indium phosphide (InP), gallium nitride (GaN), or sulfite Compound semiconductors such as recon-germanium (SiGe) are included in the channel formation region. A transistor in which carbon nanotubes are included in the channel-forming region, This allows the use of transistors in which an organic semiconductor is included in the channel formation region.

[0108] The transistors MN1 to MN10 shown in Figure 1(A) are just examples. Therefore, an n-channel transistor with a multi-gate structure having gates above and below the channel and Each of transistors MN1 through MN10 has a first gate and a second gate. It has a gate. However, in this specification, for convenience, as an example, the first gate is a gate. The first gate (sometimes referred to as the front gate), and the second gate are distinguished as the back gate. In some cases, it may be described as such. Also, in this specification, the first gate and the second gate are mutual It can be replaced with "i", and therefore the phrase "gate" can be replaced with "backgate". It can be written by substituting words. Similarly, the word "backgate" can be written as "gate It can be written by replacing the word "to" with another word. For example, "Gate is the first distribution The connection is described as "electrically connected to the wire, and the back gate is electrically connected to the second wiring." The configuration is as follows: "The back gate is electrically connected to the first wiring, and the gate is electrically connected to the second wiring." This can be replaced with the connection configuration "is connected".

[0109] Furthermore, a semiconductor device according to one aspect of the present invention may, to the extent that it solves the problem, use transistors The connection configuration of the second gate may be changed. Transistors MN1 to Transistors MN1 in Figure 1(A) Each of the ZISTA MN10 has a second gate and the connection destination of the second gate shown in the diagram. However, for example, in the same transistor, if wiring is made to both the first gate and the second gate, If terminals or circuit elements are electrically connected, which of the first gate and the second gate... Alternatively, the configuration may be changed to one side to which wiring, terminals, or circuit elements are electrically connected.

[0110] Furthermore, the semiconductor device according to one aspect of the present invention has a structure of transistors included in the semiconductor device. It does not depend on. For example, transistors MN1 to M shown in Figure 1(A) Each of the N10s has a configuration without a back gate, i.e., a single-gate structure. It may also be used as a transistor. In addition, some transistors have a back gate. Some transistors may have a configuration without a back gate.

[0111] Furthermore, this is described not only in Figure 1(A) but also in other parts of the specification. The same applies to transistors, or transistors illustrated in other drawings.

[0112] The first terminal of transistor MN1 is electrically connected to wiring VDE1, and transistor M The second terminal of N1 is connected to the first terminal of transistor MN2 and the first terminal of transistor MN5. The first terminal of transistor MN8 is electrically connected to the first terminal of transistor MN1. The terminals are the second gate of transistor MN1, the first gate of transistor MN4, and the terminals. It is electrically connected to IT.

[0113] Furthermore, the first terminal of transistor MN3 is electrically connected to wiring VDE2, and the transistor The second terminal of transistor MN3 is connected to the first gate of transistor MN2 and the first terminal of capacitor C1. The first terminal of transistor MN4, the first gate of transistor MN7, and transistor M The first gate of transistor N10 is electrically connected to the first gate of transistor MN3, It is electrically connected to the second gate of the inverter MN3 and terminal CLK2.

[0114] Furthermore, the second terminal of transistor MN5 is connected to the first gate of transistor MN6, and The second gate of the transistor MN6 and the first terminal of the capacitor C2 are electrically connected, and the transistor The first gate of transistor MN5 connects to the second gate of transistor MN5 and to wiring VDE3, and electrical They are connected precisely. Also, the first terminal of transistor MN6 is electrically connected to terminal CLK1. Connected, the second terminal of transistor MN6 is connected to the second terminal of capacitor C2, and transistor MN6 Terminal 7 is electrically connected to terminal OT.

[0115] Furthermore, the second terminal of transistor MN8 is connected to the first gate of transistor MN9, and The second gate of the zista MN9 and the first terminal of the capacitor C3 are electrically connected, and the transistor The first gate of transistor MN8 connects to the second gate of transistor MN8 and to the wiring VDE4, and electrical They are connected. Also, the first terminal of transistor MN9 is electrically connected to terminal PWC. Next, the second terminal of transistor MN9 connects to the second terminal of capacitor C3, and transistor MN1 It is electrically connected to terminal 0 (terminal 1) and terminal GT.

[0116] Furthermore, the second terminal of transistor MN2 is electrically connected to wiring VSE1, and the transistor The second gate of sta MN2 is electrically connected to wiring BG1. Also, the second gate of capacitance C1 Terminal 2 is electrically connected to wiring VSE2. Also, terminal 2 of transistor MN4 is connected. The child is electrically connected to wiring VSE3, and the second gate of transistor MN4 is connected to wiring BG It is electrically connected to 2. Also, the second terminal of transistor MN7 is connected to transistor M It is electrically connected to the second gate of N7 and the wiring VSE4. The second terminal of MN10 is connected to the second gate of transistor MN10 and to the wiring VSE5, and electrical... They are directly connected.

[0117] Note that in Figure 1(A), the second terminal of transistor MN1 and the first terminal of transistor MN2 are shown. The terminal, the first terminal of transistor MN5, and the first terminal of transistor MN8, and the electrical The connection point is shown as node N1. Also, in Figure 1(A), transistor MN The second terminal of 3, the first gate of transistor MN2, the first terminal of capacitor C1, and the transistor The first terminal of transistor MN4, the first gate of transistor MN7, and transistor MN10 The electrical connection point between the second gate and the other gate is shown as node N2.

[0118] Each of the wirings VDE1 through VDE4 is, for example, a wiring that provides a constant potential. It works. The constant potential can be, for example, a high-level potential. Note that the wiring... Each of the wires VDE1 through VDE4 may provide an equal constant potential to each other, or they may be relative to each other. Different constant potentials may be applied. Also, select from each of the wirings VDE1 to VDE4. Two or more wires are given equal constant potentials, and the remaining wires are given different constant potentials. A potential may be applied. Also, among the wirings VDE1 to VDE4, Two or more wires that provide a constant potential equal to the same value may be considered the same wire. For example, wire VDE If wiring 1 and wiring VDE2 each provide an equal constant potential to each other, then wiring VDE1 and wiring VDE2 may be connected to the same wiring.

[0119] Furthermore, one or more selected from wiring VDE1 to VDE4 are not constant potential, but variable potential. It can also be used as wiring to assign positions.

[0120] Each of the wirings VSE1 through VSE5 can be used, for example, as wiring that provides a constant potential. It functions. The constant potential can be, for example, a low-level potential, ground potential, or a negative potential. This is possible. Furthermore, each of the wirings VSE1 to VSE5 is at a constant potential equal to each other. They may be given, or they may be given different constant potentials. Also, wiring VSE1 to wiring VS Two or more wires selected from each of E5 give each other an equal constant potential, and the remaining wires The wires may be supplied with a potential different from the constant potential. Also, wiring VSE1 to wiring VSE5 Among each of these, two or more wires that give each other an equal constant potential may be considered the same wire. For example, in a case where wiring VSE1 and wiring VSE2 each provide each other with an equal constant potential. In addition, wiring VSE1 and wiring VSE2 may be the same wiring.

[0121] Furthermore, one or more selected from wiring VSE1 to VSE5 are not constant potential, but variable potential. It can also be used as wiring to assign positions.

[0122] Wiring BG1 and wiring BG2 are, for example, wires that provide a constant potential. It is possible. The constant potential can be, for example, a low-level potential, ground potential, or a negative potential. This is possible. Furthermore, wiring BG1 and wiring BG2 are each given an equal constant potential. Alternatively, they may be given different constant potentials. Also, wiring BG1 and wiring BG2 If each wire provides an equal constant potential to the other, then wire BG1 and wire BG2 are They may be the same wiring.

[0123] Furthermore, one or both of wiring BG1 and wiring BG2 are supplied with a variable potential, rather than a constant potential. It can also be used as wiring.

[0124] <<Example of operation 1>> Here, we will explain an example of the operation of circuit 100A1 shown in Figure 1(A).

[0125] Figure 4 is a timing chart showing an example of the operation of circuit 100A1. The ming chart, as an example, includes terminal IT, terminal PWC, terminal CLK1, terminal CLK2, This shows the potential fluctuations of node N1, node N2, terminal GT, and terminal OT. Note that in Figure 4, the high-level potential is V High This is written as, and the low-level potential is V Low and written They are doing it.

[0126] Note that, in the timing chart of FIG. 4, for the purpose of simply describing the operation of the circuit 100A1, the length of the input period, the length of the output period, and the like of the signals illustrated in the timing chart of FIG. 4 may differ from actual circuit operation.

[0127] In addition, in the present operation example, the constant potentials respectively supplied to the wirings VDE1 to VDE4 are equal high-level potentials (V High ). Further, the wirings VSE1 to VSE 5 have constant potentials respectively supplied thereto that are equal low-level potentials (V Low ). Further, the constant potential supplied to the wiring BG1 is a low-level potential (V LL ), and the constant potential supplied to the wiring BG2 is a low-level potential (V Low ). Note that V LL is a potential lower than V Low . In particular, it is preferable that V LL is a negative potential.

[0128] Note that for each of V High and V Low , it is preferable that the potential is such that a difference between V High and V Low is higher than the respective threshold voltages of transisto rs MN1 to MN10 .

[0129] [From time T1 to time T2] From time T1 to time T2, V Low is supplied to a terminal IT, V is supplied to a terminal PW Low C, V Low is supplied to a terminal CLK1, and V Low is supplied to a terminal CLK2. Further, as an example, V High - V​th_MN3 It is assumed that V is retained. th_MN3 is transistor M This is the threshold voltage for N3.

[0130] The first gate of transistor MN3 receives the V from terminal CLK2. Low Given, The first terminal of the ZISTA MN3 receives the V from the wiring VDE2. High Given, transistor M The potential at the second terminal (node ​​N2) of N3 is V High -V th_MN3 This is how it is. At that time, the potential of the second terminal of transistor MN3 becomes lower than the potential of the first terminal, The second terminal of transistor MN3 becomes the source. Also, the gate-source of transistor MN3. The voltage between them is V Low -(V High -V th_MN3 ) becomes V th_MN3 is appropriate When the threshold voltage is within the range, V Low -(V High -V th_MN3 ) is 0V As the voltage also decreases, transistor MN3 turns off.

[0131] The potential of the first gate (node ​​N2) of transistor MN2 is V High -V th_MN3 Therefore, the second terminal of transistor MN2 receives the V from the wiring VSE1. Low Given Therefore, transistor MN2 turns ON. This connects node N1 and wiring VSE1 Since there is a conductive state between them, the potential of node N1 is V Low This is the result.

[0132] Also, the potential of the first gate (terminal IT) of transistor MN1 is V Low And, The potential at the second terminal (node ​​N1) of the zista MN1 is VLow Therefore, transistor MN 1 will be in the off state.

[0133] Furthermore, the first gate of transistor MN5 receives the V from wiring VDE3. High Given The potential of the first terminal (node ​​N1) of transistor MN5 is V Low Therefore, The transistor MN5 is turned ON. This causes the first gate between the wiring VSE1 and transistor MN6. Since there is conduction between the terminal and the first gate, the potential of the first gate of transistor MN6 is V Low and Yes.

[0134] Additionally, the first gate of transistor MN8 receives the V from wiring VDE4. High Given The potential of the first terminal (node ​​N1) of transistor MN8 is V Low Therefore, The transistor MN8 is turned ON. This causes the first gate between the wiring VSE1 and transistor MN9. Since there is conduction between the gate and the terminal, the potential of the first gate of transistor MN9 is V Low and Yes.

[0135] The potential of the first gate (node ​​N2) of transistor MN7 is V High -V th_MN3 Therefore, the second terminal of transistor MN7 receives the V from the wiring VSE4. Low Given Therefore, transistor MN7 is turned ON. Therefore, terminal OT and wiring VSE4 Since there is conductivity between them, the potential of terminal OT is V Low This is the result.

[0136] Also, the potential of the first gate of transistor MN6 is V Low The transistor MN6 The potential of the second terminal (terminal OT) is V LowTherefore, transistor MN6 is in the off state. Yes.

[0137] The potential of the first gate (node ​​N2) of transistor MN10 is V High -V th_MN 3, and the second terminal of transistor MN10 is connected to the V from wiring VSE5. Low Given Therefore, transistor MN10 is turned ON. As a result, terminal GT and wiring VS Since there is conductivity between E5 and the terminal GT, the potential of terminal GT is V Low This is the result.

[0138] Also, the potential of the first gate of transistor MN9 is V Low Therefore, transistor MN9 The potential of the second terminal (terminal GT) is V Low Therefore, transistor MN9 is in the off state. Yes.

[0139] The potential of the first gate (terminal IT) of transistor MN4 is V Low And, transistor The second terminal of MN4 is connected to the V wire from VSE3. Low Since the transistor MN4 will be turned off.

[0140] Here, transistors MN1 and MN3 are in the OFF state. Transistor MN4, transistor MN6, or transistor MN9 is normally on. Let's consider the cases.

[0141] In this specification, normally-on means a device that does not require voltage to be applied to the gate. This refers to a state where a current flows through a transistor due to the presence of a condensate. Alternatively, it can be described as "normal." ON means that the channel exists even when the gate-source voltage is 0V, and the transistor This refers to a state where current flows through the gate. Also, normally off means that the gate has a potential difference. When no current is applied, or when the gate is given ground potential, no current flows through the transistor. It refers to the state. Also, in OS transistors, normally off refers to the state where the gate has a potential. When no voltage is applied, or when the gate is given ground potential, the channel width flowing through the transistor The current per 1 μm is 1 × 10⁻⁶ at room temperature. -20 A or less, 1 × 10 at 85℃ - 18 A or less, or 1 × 10 at 125°C -16 This means being less than or equal to A.

[0142] When transistor MN1 is normally on, the wiring from VDE1 to node N1 Current flows through it. Therefore, the potential of node N1 is V Low It may be higher than that. Furthermore, a through-current flows between wiring VDE1 and wiring VSE1, causing circuit 101A1 to shut down. Power consumption may be high. Note that transistor MN1 is normally on. However, the potential of node N1 is V Low If it does not change significantly from (for example, transistor MN The source-drain current of transistor 2 is greater than the source-drain current of transistor MN1. In the following cases, circuit 101A1 may operate normally.

[0143] In transistor MN3, the gate-source voltage of transistor MN3 is V L ow -(V High -V th_MN3 ) is the threshold voltage V th_MN3 It will be lower than Therefore, even if transistor MN3 is normally on, transistor MN3 is in the off state. To become.

[0144] If transistor MN4 is normally on, then the wiring from node N2 to VSE3 Current flows through it. Therefore, the potential of node N2 is V High -V th_MN3 Lower This can happen. As a means to prevent a drop in the potential of node N2, for example, the electrostatic capacitance C1 can be used. It is preferable to increase the capacity value. Also, for example, electrically connected to node N2. The number of capacitors may be increased. Also, for example, the second gate of transistor MN4 may be electrically connected. Lowering the potential of the connected wiring BG2 increases the threshold voltage of transistor MN4. It is preferable to do so.

[0145] The potential at the first terminal of transistor MN6 is V Low And the second terminal of transistor MN6 The potential of the child (terminal OT) is V Low Therefore, transistor MN6 is normally on. Even so, the potential of terminal OT does not change.

[0146] Similarly, the potential of the first terminal of transistor MN9 is V Low Therefore, transistor MN9 The potential of the second terminal (terminal GT) is V Low Therefore, transistor MN9 is normal Even when it's turned on, the potential of terminal GT does not change.

[0147] [From time T2 to time T3] Between time T2 and time T3, terminal CLK2 has V High It is given.

[0148] In transistor MN3, the first gate of transistor MN3 receives terminal CLK2 V Highis supplied, and V from the wiring VDE2 is supplied to the first terminal of the transistor MN3 Hi gh . At this time, for example, the potential of the second terminal (node N2 ) of the transistor MN3 is lower than V High -V th_MN3 , the transistor MN3 is turned on, so that conduction is established between the wiring VDE2 and the node N2.

[0149] When the transistor MN3 is in the on state, current flows from the wiring VDE2 to the node N2 , so that the potential of the node N2 increases. Since the threshold voltage of the transistor MN3 is V t h_MN3 , when the potential of the node N2 (the second terminal of the transistor MN3) increases to V High -V th_MN3 , the transistor MN3 is turned off.

[0150] Further, between time T2 and time T3, after V High is supplied to the terminal CLK2 , V Low is supplied to the terminal CLK2. Accordingly, the gate-source voltage of the transistor MN3 is V = V Low -(V High -V th_MN3 ), and when V th_M N3 is a threshold voltage within an appropriate range, the transistor MN3 is turned off.

[0151] Through the above operation, the circuit 100A1 can, by supplying V High to the terminal CLK2 , refresh the potential of the node N2 to V High -V th_MN3 .

[0152] ​ [From time T3 to time T4] Between time T3 and time T4, terminal IT has V Low Given, terminal PW C contains V Low Given, terminal CLK1 has V Low Given, terminal CLK2 is V Low Assume that the following is given. Between time T3 and time T4, terminal IT The potentials input to terminals PWC, CLK1, and CLK2 are, at time T Terminals IT, PWC, CLK1, and CLK between time 1 and time T2 Since the potential input to each of the two is equal, the number of times between time T3 and time T4 The operation example for path 100A1 is described as an example of operation between time T1 and time T2. We will take that into consideration.

[0153] [From time T4 to time T5] Between time T4 and time T5, terminal IT has V High It is given.

[0154] The first gate of transistor MN4 receives the V from terminal IT. High Given, Trans The second terminal of MN4 is wired from VSE3 to V Low Since the transition MN4 is turned ON. This creates a conductive state between node N2 and wiring VSE3. Therefore, the potential of node N2 is V High -V th_MN3 From V Low It changes to.

[0155] Furthermore, from the above, the potential of the first gate (node ​​N2) of transistor MN2 is V Low and Furthermore, the second terminal of transistor MN2 is connected to the V from the wired VSE1. Low Given Therefore, transistor MN2 is in the off state.

[0156] Furthermore, from the above, the potential of the first gate (node ​​N2) of transistor MN7 is V Low and Therefore, the second terminal of transistor MN7 receives the V from the wiring VSE4. Low Given Therefore, transistor MN7 is in the off state.

[0157] Furthermore, from the above, the potential of the first gate (node ​​N2) of transistor MN10 is V Low Therefore, the second terminal of transistor MN10 receives the V from the wiring VSE5. Low Given Therefore, transistor MN10 is in the off state.

[0158] The first gate of transistor MN1 receives the V from terminal IT. High Given, Trans The first terminal of st MN1 receives the V from wiring VDE1. High Given, transistor MN The potential at the second terminal (node ​​N2) of 1 is V Low This is the case. At this time, transistor M Since N1 is in the ON state, there is conductivity between wiring VDE1 and node N1.

[0159] When transistor MN1 is ON, current flows from wiring VDE1 to node N1. As a current flows, the potential at node N1 increases. The threshold voltage of transistor MN1 is V t h_MN1 Therefore, the potential of node N1 (the second terminal of transistor MN1) is V High - V th_MN1 When the voltage reaches this level, transistor MN1 turns off.

[0160] Furthermore, between time T4 and time T5, terminal IT is V High The following is entered. Therefore, the potential V of node N1 (the second terminal of transistor MN1) High -V th_MN1 If the voltage drops due to any factor, transistor MN1 will turn on again, and the wiring VD Current flows from E1 to node N1, and the current at node N1 (the second terminal of transistor MN1) V High -V th_MN1 It rises to this level. Also, the second terminal of transistor MN1 The electric potential is V High -V th_MN1 When the voltage reaches that level, transistor MN1 turns off again. This is the state it is in.

[0161] The first gate of transistor MN5 receives the V from wiring VDE3. High Given, tiger The first terminal (node ​​N1) of the inverter MN5 has V High -V th_MN1 Given, The potential at the second terminal of transistor MN5 is V Low This is the case. Because the potential of the second terminal of MN5 is lower than the potential of the first terminal, the third terminal of transistor MN5 Terminal 2 becomes the source, and transistor MN5 turns on. This causes node N1 A conductive state is established between this and the first gate of transistor MN6.

[0162] When transistor MN5 is ON, node N1 to transistor MN6 Because current flows through the first gate, the potential of the first gate of transistor MN6 increases. Here, the threshold voltage of transistor MN5 is V th_MN5 For example, V th_M N5 ga V th_MN1When the threshold voltage is above this level, the first gate of transistor MN6 The potential is V High -V th_MN5 When the voltage rises to this level, transistor MN5 is in the OFF state. It becomes a state. On the other hand, for example, V th_MN5 ga V th_MN1 The threshold voltage is less than At that time, the potential of the first gate of transistor MN6 is V High -V th_MN1 It will get that high At this time, the gate-source voltage V High -(V High -V th_MN1 ) =V th_MN1 The threshold voltage V of transistor MN5 th_MN5 Because it is higher than, Transistor MN5 is turned ON. Note that in this configuration example, time T4 of this operation example It is preferable that transistor MN5 be in the OFF state from time T5 onwards. , V th_MN5 is V th_MN1 It is preferable that the threshold voltage is as above. Furthermore, V th_MN5 It is more preferable that this is a threshold voltage value that does not result in a normally-on state. In this example, the second terminal of transistor MN5 (the first gate of transistor MN6) V High -V th_MN5 If it reaches (V th_MN5 ga V th_MN1 That's all. This explains the case where...

[0163] The potential of the first gate of transistor MN6 is V High -V th_MN5 And, The first terminal of the zista MN6 receives the V from terminal CLK1. Low Given, transistor MN The potential of the second terminal of 6 is V Low This is the case. At this time, the first terminal of transistor MN6 Alternatively, the second terminal becomes the source, and transistor MN6 turns ON. As a result, the terminal A conductive state is established between CLK1 and terminal OT. Note that from before time T4, terminal CLK1 is V Low Since V is given, the potential of the second terminal (terminal OT) of transistor MN6 is V L ow It remains unchanged.

[0164] The first gate of transistor MN8 receives the V from wiring VDE4. High Given, tiger The first terminal (node ​​N1) of the inverter MN8 has V High -V th_MN1 Given, The potential at the second terminal of transistor MN8 is V Low This is the case. Because the potential of the second terminal of MN8 is lower than the potential of the first terminal, the third terminal of transistor MN8 Terminal 2 becomes the source, and transistor MN8 turns on. This causes node N1 A conductive state is established between this and the first gate of transistor MN9.

[0165] When transistor MN8 is ON, node N1 to transistor MN9 Because current flows through the first gate, the potential of the first gate of transistor MN9 increases. Here, the threshold voltage of transistor MN8 is V th_MN8 For example, V th_M N8 ga V th_MN1 When the threshold voltage is above this level, the first gate of transistor MN9 The potential is V High -V th_MN8 When the voltage rises to this level, transistor MN8 is in the off state. It becomes a state. On the other hand, for example, V th_MN8 ga V th_MN1 The threshold voltage is less than At that time, the potential of the first gate of transistor MN9 is V High -V th_MN1 It will get that high At this time, the gate-source voltage V High -(V High -V th_MN1 ) =V th_MN1 The threshold voltage V of transistor MN8 th_MN8 Because it is higher than, Transistor MN8 is turned ON. Note that in this configuration example, the time T4 of this operation example is It is preferable that transistor MN8 be in the OFF state from time T5 onwards. , V th_MN8 is V th_MN1 It is preferable that the threshold voltage is as above. Furthermore, V th_MN8 It is more preferable that this is a threshold voltage value that does not result in a normally-on state. In this example, the second terminal of transistor MN8 (the first gate of transistor MN9) V High -V th_MN8 If it reaches (V th_MN8 ga V th_MN1 That's all. This explains the case where...

[0166] The potential of the first gate of transistor MN9 is V High -V th_MN8 And, The first terminal of the ZISTA MN9 receives the V from terminal PWC. Low Given, transistor MN9 The potential of the second terminal is V Low At this time, the first terminal of transistor MN9 or The second terminal becomes the source, and transistor MN9 turns on. As a result, terminal P WC and terminal GT become conductive. Furthermore, from before time T4, terminal PWC has V L ow Since is given, the potential of terminal OT is V LowIt remains unchanged.

[0167] Also, between time T4 and time T5, V High After For terminal IT, V Low This is given. This allows the gate-so of transistor MN1 to The voltage between the two sides is V Low -(V High -V th_MN1 ) becomes V th_MN1 is suitable When the threshold voltage is within a narrow range, transistor MN1 is in the off state.

[0168] The first gate of transistor MN4 receives the V from terminal IT. Low Given, Transis The second terminal of MN4 receives the V from the wiring VSE3. Low Since the transition Node MN4 is turned off. As a result, potential V is present at node N2. Low It is retained.

[0169] [From time T5 to time T6] Between time T5 and time T6, terminal CLK1 receives V High It is given.

[0170] The potential of the first gate of transistor MN6 is V High -V th_MN5 And, The first terminal of the zista MN6 receives the V from terminal CLK1. High Given, The potential of the second terminal of MN6 is V Low The threshold voltage of transistor MN6 is as follows. Pressure V th_MN6 The gate-source voltage V of transistor MN6 High -V L ow -V th_MN5 However, the threshold voltage of transistor MN6 is V th_MN6 twist As the voltage increases, transistor MN6 turns on. This causes terminal CLK A conductive state is established between terminal 1 and terminal OT.

[0171] When transistor MN6 is ON, current flows from terminal CLK1 to terminal OT. As current flows, the potential of the second terminal (terminal OT) of transistor MN6 increases. When the potential of the second terminal (terminal OT) of the inverter MN6 increases, the capacitance due to capacitor C2 increases. As a result, the potential of the first gate of transistor MN6 also increases. Therefore, the transistor The potential of the second terminal (terminal OT) of MN6 is V High -V th_MN6 It will be higher than In this example, the final potential V supplied by terminal CLK1 is... High It is equal to Also, the potential of the first gate of transistor MN6 at this time is (V High -V th _MN5 )+(V High -V Low ) = 2V High -V Low -V th_MN5 to It is assumed that the price will increase. In this example of operation, capacitive coupling is used in this way to create a transistor. The gate potential is increased in response to the rise in potential of the first or second terminal. It's called rap.

[0172] Here, the transistor is in the OFF state between time T5 and time T6. When MN1, transistor MN3, or transistor MN4 is normally on Let's consider the concept of combination.

[0173] In transistor MN1, the gate-source voltage of transistor MN1 is V L ow -(V High -V th_MN1 ) is the threshold voltage V th_MN1 It will be lower than Therefore, even if transistor MN1 is normally on, transistor MN1 is in the off state. To become.

[0174] If transistor MN3 is normally on, the wiring from VDE2 to node N2 Current flows through it. Therefore, the potential of node N2 is V Low It may be higher than that. Furthermore, the potential of node N2 increases, which affects the potential of the first gate of transistor MN2. The value can also increase. Furthermore, even if transistor MN3 is normally on, The potential of the N2 is V Low If it becomes slightly higher than that, the gate of transistor MN3 - When the source-to-source voltage falls below the threshold voltage, transistor MN3 turns off. Yes. Also, if the threshold voltage of transistor MN2 is sufficiently large, Due to the normally-on characteristics of MN3, even if the potential of node N2 rises, transistor M Since N2 can remain in the off state, circuit 101A1 operates normally. There are things that need to be done.

[0175] In transistor MN4, the potential of the first terminal (node ​​N2) of transistor MN4 is V Low Therefore, the potential of the second terminal (wiring VSE3) of transistor MN4 is V Low dea Therefore, even if transistor MN4 is normally on, the potential of node N2 does not change. do not.

[0176] [From time T6 to time T7] Between time T6 and time T7, terminal PWC has V High It is given.

[0177] The potential of the first gate of transistor MN9 is V High -V th_MN8 And, The first terminal of the ZISTA MN9 receives the V from terminal PWC. High Given, Transis The potential of the second terminal of MN9 is V Low This is the threshold voltage of transistor MN9. V th_MN9 The gate-source voltage V of transistor MN9 High -V Lo w -V th_MN8 However, the threshold voltage of transistor MN9 is V th_MN9 Rather As the temperature rises, transistor MN9 turns on. This causes terminal PWC and A conductive state is established between terminal GT and the terminal.

[0178] When transistor MN9 is ON, current flows from terminal PWC to terminal GT. As a result, the potential of the second terminal (terminal GT) of transistor MN9 increases. The potential of the second terminal (terminal GT) of the ZISTRA MN9 increases, resulting in capacitive coupling by capacitor C3. This also increases the potential of the first gate of transistor MN9. Therefore, the potential of the second terminal (terminal GT) of transistor MN9 is V High -V th_M N8 It becomes higher than, and in this example of operation, the final potential V provided by terminal PWC is High and equal It shall be assumed that this occurs. Also, the potential of the first gate of transistor MN9 at this time is (V High -V th_MN8 )+(V High -VLow ) = 2V High -V Low -V th_MN8 It will rise to a certain level.

[0179] Also, between time T6 and time T7, V is connected to terminal PWC. High Given Later, V is connected to terminal PWC. Low This is given. This allows the second terminal of transistor MN9 to The potential of the child (terminal GT) is V, similar to the operation example between time T5 and time T6. Low and Therefore, the gate-source voltage is V High -V th_MN8 This is the result.

[0180] By the way, between time T6 and time T7, the transistors that are in the OFF state Transistor MN1, transistor MN3, or transistor MN4 is normally on. For this case, refer to the description of the operation example between time T5 and time T6.

[0181] [From time T8 to time T9] Between time T8 and time T9, terminal CLK1 has V Low It is given.

[0182] The potential of the first gate of transistor MN6 is 2V. High -V Low -V th_MN5 in Yes, the first terminal of transistor MN6 receives the V from terminal CLK1. Low Given The potential of the second terminal of transistor MN6 is V High This is the case. Because the potential of the first terminal of transistor MN6 is lower than the potential of the second terminal, transistor MN6 The first terminal becomes the source, and transistor MN6 turns on. As a result, terminal C A conductive state is established between LK1 and terminal OT.

[0183] When transistor MN6 is ON, current flows from terminal OT to terminal CLK1. As current flows, the potential of terminal OT decreases. In this example of operation, the potential of terminal OT eventually The potential V supplied by terminal CLK1 Low Let it be equal to . Also, for this reason, The potential of the first gate of STAMN6 is V High -V th_MN5 It is expected to decrease to that extent. ru.

[0184] [From time T9 to time T10] Between time T9 and time T10, terminal CLK2 has V High is given At this time, the operation of circuit 101A1 between time T9 and time T10 is from time T2 The operation will be the same as before, up to time T3.

[0185] For example, V at terminal CLK2 High When given, transistor MN3 turns ON. In this state, the potential at node N2 is V Low From V High -V th_MN3 It changes to this. As a result, transistors MN2, MN7, and MN10 turn on. In this state, the potentials of node N1, terminal OT, and terminal GT are V Low This is the result.

[0186] Furthermore, the potential of node N1 is V Low By decreasing to this level, transistor MN5 , and transistor MN8 turns ON. As a result, the second terminal of transistor MN5 The child (first gate of transistor MN6), and the second terminal of transistor MN8 (transistor The potentials of each of the first gates of MN9 are also V Low It drops to that point. Therefore, tra The potentials of the first and second terminals of the inverter MN5 are V Low And also, As shown, the potentials of the first and second terminals of transistor MN8 are V Low This will be .

[0187] [After time T10] After time T10, for example, V is connected to terminal CLK2. Low Input a variable potential, The potential of the N1 is V Low And the potential of node N2 is V High -V th_MN3 and After that, connect terminal IT to V High Without inputting, V is sent to terminal CLK1 or terminal PWC. Hi gh This provides the necessary information. A specific example of its operation is explained below.

[0188] [From time T11 to time T12] Between time T11 and time T12, terminal CLK1 has V High Given ru.

[0189] The potential of the first gate of transistor MN6 is V Low Therefore, the first of transistor MN6 The terminal receives the V from terminal CLK1. High Given, the second terminal of transistor MN6 The potential of this child is V Low At this time, the potential of the first terminal of transistor MN6 is Also, because the potential of the second terminal becomes low, the second terminal of transistor MN6 becomes the source, The inverter MN6 is turned off. As a result, there is no conductivity between terminal CLK1 and terminal OT. This is the state it is in.

[0190] Furthermore, the potential of the first gate of transistor MN7 is V High -V th_MN3 And, The second terminal of transistor MN7 receives the V from wiring VSE4. Low Since the given information, Transistor MN7 turns ON. This creates a conductive path between terminal OT and wiring VSE4. When the system is open, the potential of terminal OT is V Low This is the result.

[0191] Also, between time T11 and time T12, V is applied to terminal CLK1. High gave After that, V is sent to terminal CLK1. Low The first gate of transistor MN6 is given. The potential is V Low Therefore, the first terminal of transistor MN6 receives the V from terminal CLK1. Lo w Given that the potential of the second terminal of transistor MN6 is V Low Therefore If the threshold voltage of transistor MN6 is within the appropriate range, transistor MN6 will turn off. This is the state it is in.

[0192] As described above, V is connected to terminal CLK2. Low Input a variable potential and set the potential of node N1 to V Low And the potential of node N2 is V High -V th_MN3 After that, terminal IT V High Without inputting, V is sent to terminal CLK1. High Even if you give it transistor MN6 It remains in the OFF state. Also, afterwards, V is applied to terminal CLK1. Low Even if you give it a transition The MN6 will remain in the off state.

[0193] [From time T12 to time T13] Between time T12 and time T13, terminal PWC has V High is given .

[0194] The potential of the first gate of transistor MN9 is V Low Therefore, the first of transistor MN9 The terminal has V from terminal PWC. High Given, the second terminal of transistor MN9 The potential is V Low At this time, the potential of the first terminal of transistor MN9 is Because the potential of the second terminal becomes low, the second terminal of transistor MN9 becomes the source, The ZISTA MN9 is turned off. As a result, there is no conductivity between terminal PWC and terminal GT. This is the result.

[0195] Furthermore, the potential of the first gate of transistor MN10 is V High -V th_MN3 and The second terminal of transistor MN10 is connected to the V from the wiring VSE5. Low Given Therefore, transistor MN10 turns ON. This connects terminal GT and wiring VSE5. The connection between them becomes conductive, and the potential at terminal GT is V Low This is the result.

[0196] Also, between time T12 and time T13, V is connected to terminal PWC. High was given After that, V is connected to terminal PWC. Low The following is given: The power of the first gate of transistor MN9 V Low Therefore, the first terminal of transistor MN9 receives the V from terminal PWC. Low is given The potential of the second terminal of transistor MN9 is V Low Therefore, The MN9 will be turned off.

[0197] As described above, V is connected to terminal CLK2. Low Input a variable potential and set the potential of node N1 to V Low And the potential of node N2 is V High -V th_MN3 After that, terminal IT V High Without inputting, V is sent to terminal PWC. High Even if you give it, transistor MN9 It remains in the off state. Also, afterwards, a V is output to terminal PWC. Low Even if you give it a transistor MN9 remains in the off state.

[0198] <<Comparison 1>> Here, we compare circuit 100A1 with circuit 101 shown in Figure 5.

[0199] The circuit 101 in Figure 5 is the same as the circuit 100A1 in Figure 1(A), and configuration examples 2 to 2 described later. This is the circuit configuration that served as the basis for the development of circuits such as those described in section 8. As an example, circuit 101 and Comparing the circuit configuration with circuit 100A1, circuit 100A1 has the following configuration for transistor MN7. Two gates are electrically connected to the second terminal of transistor MN7, and transistor MN1 The second gate of 0 is electrically connected to the second terminal of transistor MN10. In contrast, in circuit 101, the second gate of transistor MN7 is electrically connected to wiring BG1. Furthermore, the second gate of transistor MN10 is electrically connected to wiring BG1. It is complete.

[0200] Furthermore, the operation of circuit 101 can be performed by applying the operation example of circuit 100A1 described above. .

[0201] Here, between time T5 and time T6 in the above example of operation, it is in the OFF state. When transistor MN7 or transistor MN10 is normally on Let's think about it.

[0202] In circuit 101, when transistor MN7 is normally on, terminal O Current flows from T to wiring VSE4. Therefore, the potential of terminal OT is V High Lower This can happen. Also, a through-current flows between terminal CLK1 and wiring VSE4, The power consumption of circuit 101 may be high. Note that transistor MN7 is normally Even if it is set to N, the potential of terminal OT is V High If it does not change significantly from (for example, The source-drain current of transistor MN6 is equal to the source-drain current of transistor MN7. Circuit 101 may operate normally if the current is greater than the limit.

[0203] Furthermore, in circuit 101, the potential of the first terminal (terminal GT) of transistor MN10 is V Low Therefore, the potential at the second terminal (wiring VSE5) of transistor MN10 is V Low dea Therefore, even if transistor MN10 is normally on, the potential of terminal GT does not change. do not.

[0204] By the way, in circuit 101 of Figure 5, transistors MN2, MN7, and The second gates of each transistor MN10 are electrically connected to wiring BG1. Therefore, in order to normally turn off transistor MN2, for example, wiring BG1 Negative potential (V LL If ) is given, transistors MN7 and MN10 will also be no - May turn off. As described above, transistor MN7 and transistor Even if MN10 is normally on, circuit 101 may still operate normally. The second gates of transistor MN7 and transistor MN10 are connected to wiring BG1. It is not necessary to apply a negative potential to these transistors. Also, transistors MN7 and MN10 When operated in normally off mode, transistors MN7 and MN1 The amount of current flowing when each of the 0s is ON may be small, and this is the cause This can cause the drive speed of circuit 101 to slow down. Therefore, transistor MN7 and The potential applied to the second gate of transistor MN10 is applied to the second gate of transistor MN2. It is preferable that the potential is different from the potential of the eruption.

[0205] In circuit 100A1 shown in Figure 1(A), the second gate of transistor MN7 is connected to wiring VSE. Electrically connected to 4, the second gate of transistor MN10 is electrically connected to wiring VSE5. Because they are connected, the second gates of transistors MN7 and MN10 are connected This makes it possible to avoid applying a potential as low as the negative potential provided by line BG1. In the configuration of circuit 100A1, unlike circuit 101, transistor MN2, transistor Of the MN7 and MN10 transistors, only transistor MN2 is set to normally off. This is possible. For this reason, transistor MN7 in circuit 100A1, and transistor The amount of current that flows when each of the MN10 is ON is determined by the transistors in circuit 101. The amount of current flowing when transistors MN7 and MN10 are both ON is greater than It can be made larger. Therefore, the circuit of the drive circuit GD in Figure 3(A) or Figure 3(B) Apply circuit 100A1 of Figure 1(A) to each of circuits 100[1] through 100[m]. By doing so, the driving speed of the drive circuit GD can be increased compared to applying the circuit 101 in Figure 5. It is possible.

[0206] Furthermore, the semiconductor device according to one aspect of the present invention is not limited to the configuration shown in Figure 1(A). For example, The configuration of a semiconductor device according to one aspect of the invention can be modified depending on the situation, as long as it is within the scope of solving the problem. Further improvements may be made.

[0207] For example, in circuit 100A1 in Figure 1(A), the capacitance C1 controls the potential of node N2. If sufficient retention is possible, circuit 100A1 will be as shown in circuit 100A2 of Figure 1(B). Alternatively, the configuration may be changed so that the transistor MN4 does not have a second gate.

[0208] Furthermore, for example, the circuit 100A1 in Figure 1(A) is the same as the circuit 100A3 shown in Figure 6(A). The configuration may be modified. The circuit 100A3 shown in Figure 6(A) has a transistor MN The second gate of 7 is electrically connected to wiring BG2, and the second gate of transistor MN10 The two gates are electrically connected to wiring BG2, and the circuit 100A1 in Figure 1(A) They are different.

[0209] In circuit 100A3 in Figure 6(A), the second gate of transistor MN2 is connected to wiring BG1. Electrically connected to the second gates of transistors MN7 and MN10. Since the wire is electrically connected to wiring BG2, for example, a constant potential is applied to wiring BG1. Even if this is the case, the second gates of transistors MN7 and MN10 In this case, the constant potential is not provided. That is, the threshold voltage of transistor MN2 and the transistor The threshold voltages of the MN7 transistor and the MN10 transistor are controlled independently. This allows, for example, applying a negative potential to the second gate of transistor MN2. Furthermore, the second gates of transistors MN7 and MN10 are at ground potential. or by applying a low-level potential (a potential higher than the negative potential), the transistor MN7 And the amount of the off current of transistor MN10 is greater than the amount of the off current of transistor MN2. It can be heard. Therefore, the drive circuit GD in Figure 3(A) or Figure 3(B) Apply circuit 100A3 of Figure 6(A) to each of circuits 100[1] through 100[m]. By doing so, similar to circuit 100A1 in Figure 1(A), the drive speed of the drive circuit GD is increased. It is possible.

[0210] Furthermore, for example, the circuit 100A1 in Figure 1(A) is the same as the circuit 100A4 shown in Figure 6(B). The configuration may be modified. The circuit 100A4 shown in Figure 6(B) has a transistor MN 7. The second gates of transistor MN3 are electrically connected to wiring BG3. It is structured in this way.

[0211] Wiring BG3, as an example, provides a constant potential, similar to wiring BG1 and wiring BG2. It functions as a line. The constant potential can be, for example, a low-level potential, ground potential, or negative potential. This can be done. Also, wiring BG3 is wired to provide a variable potential rather than a constant potential. That's fine.

[0212] In the configuration of circuit 100A4 in Figure 6(B), the same applies as in circuit 100A3 in Figure 6(A). , the threshold voltage of transistor MN2, and transistors MN7 and MN10 Each of the threshold voltages and can be controlled independently. This allows for, for example, to A negative potential is applied to the second gate of transistor MN2 from wiring BG1, and transistor MN The second gates of transistors 7 and MN10 are connected to ground potential or low potential from wiring BG3. By applying a level potential (a potential higher than the negative potential), transistor MN7 and the transistor... Make the off-current of transistor MN10 greater than the off-current of transistor MN2. This is possible. Therefore, the drive circuit GD of Figure 3(A) or Figure 3(B) has a circuit 100[ To each of the circuits 1] through 100[m], the circuit 100A4 in Figure 6(A) is applied. Therefore, similar to the circuit 100A1 in Figure 1(A), the drive speed of the drive circuit GD can be increased. can.

[0213] <Configuration Example 2> Next, we will discuss the circuits shown in Figures 3(A) and 3(B), which are different from the circuit described in Configuration Example 1. Examples of circuit configurations applicable to circuits 100[1] to 100[m] of the drive circuit GD are as follows: I will explain.

[0214] Figure 7(A) is a semiconductor device according to one aspect of the present invention, as shown in Figures 3(A) and 3(B). The circuit configuration can be applied to each drive circuit GD, from circuit 100[1] to circuit 100[m]. An example is shown. Circuit 100B1 is a modified version of circuit 100A1 in Figure 1(A). It differs from circuit 100A1 in that it has capacitance C4.

[0215] Furthermore, circuit 100B1 is configured such that transistors MN7 and MN10 The second gate of the circuit is electrically connected to wiring BG1, but circuit 100B The connection destinations for the second gates of transistors MN7 and MN10 are: Circuit 100A1 in Figure 1(A), Circuit 100A3 in Figure 6(A), Circuit 100 in Figure 6(B) You may change it to match any one of the A4 layouts.

[0216] The first terminal of capacitor C4 is, for example, connected to the second terminal of transistor MN1, and the transistor The first terminal of MN2, the first terminal of transistor MN5, and the first terminal of transistor MN8 And, it is electrically connected to. Also, the second terminal of capacitance C4 is, for example, connected to wiring VSE. It is electrically connected to 6.

[0217] Wiring VSE6, for example, provides a constant potential, similar to wiring VSE1 to VSE5. It functions as a constant potential. The constant potential can be, for example, a low-level potential, ground potential, or negative potential. It can be set to an electric potential. Also, the constant potential provided by wiring VSE6 is set to wiring VSE1 to wiring If the potential supplied by one or more of the selected VSE5s is equal, then the wiring VSE6 and its wiring are identical. It can also be used as wiring.

[0218] Furthermore, the wiring VSE6 may be a wiring that provides a variable potential rather than a constant potential.

[0219] Furthermore, the operation of circuit 100B1 can be performed by applying the operation example of circuit 100A1 described above. Cut.

[0220] <<Comparison 2>> Here, similar to Configuration Example 1, we have the circuit 100B1 shown in Figure 7(A) and the circuit in Figure 5 mentioned above. This explains the differences in configuration and operation between 101 and [another device].

[0221] As mentioned above, the circuit 100B1 in Figure 7(A) has a configuration that includes a capacitance C4. The circuit 101 in Figure 5 does not have capacitance C4.

[0222] Between time T5 and time T6 in the above example of operation, the transistor is in the OFF state. Let's consider the case where ZISTA MN2 is normally on.

[0223] In circuit 101, when transistor MN2 is normally on, node Current flows from N1 to wiring VSE1. Therefore, the potential of node N1 is V High -V th_MN1 It may be lower than that. In particular, the potential of node N1 is V High -V th _MN1 If it becomes lower than that, either transistor MN5 or transistor MN8 or Both are turned on, and one or both of transistors MN6 and MN9 Because the potential of the first gate decreases, the bootstrap effect described above may be reduced. This may cause circuit 101 to malfunction.

[0224] On the other hand, in circuit 100B1 in Figure 7(A), the first terminal of capacitor C4 is connected to transistor MN. The second terminal of 1, the first terminal of transistor MN2, and the first terminal of transistor MN5, Because the first terminal of transistor MN8 is electrically connected to transistor MN2 When it becomes normally on, the potential of the first terminal (node ​​N1) of capacitor C4 drops. This makes it less likely to happen. As a result, circuit 100B1 will operate more stably than circuit 101. It is possible.

[0225] Therefore, the drive circuit GD in Figure 3(A) or Figure 3(B) has a circuit 100[1] to circuit By applying circuit 100B1 in Figure 7(A) to each of the 100[m], Figure 5 The drive circuit GD can be operated more stably than by applying circuit 101.

[0226] In addition, in circuit 100B1 in Figure 7(A), the potential of node N1 is controlled by capacitor C4. If sufficient holding is possible, circuit 100B1 is as shown in circuit 100B2 in Figure 7(B). Alternatively, the configuration may be changed so that the transistor MN2 does not have a second gate.

[0227] <Configuration Example 3> Figure 8 shows the circuit 100A1 in Figure 1(A), the circuit 100A2 in Figure 1(B), and the circuit in Figure 6(A). Circuit 100A3, circuit 100A4 in Figure 6(B), and circuit 100B1 in Figure 7(A) are different. The semiconductor device according to one aspect of the present invention is shown in Figures 3(A) and 3(B) respectively. An example of a circuit configuration applicable to circuits 100[1] to 100[m] of circuit GD is shown. Yes, they are.

[0228] Circuit 100C is a modified circuit configuration of circuit 100A1 in Figure 1(A), and the transient The first gate of transistor MN5 is electrically connected to wiring VME1, and transistor MN The first gate of circuit 8 is electrically connected to wiring VME2, which is different from circuit 100A1. It is.

[0229] Furthermore, circuit 100C is configured for each of transistors MN7 and MN10. The second gate is electrically connected to wiring BG1, but circuit 100C The connection destinations for the second gates of transistors MN7 and MN10 are shown in the diagram. Circuit 100A1 in Figure 1(A), Circuit 100A3 in Figure 6(A), Circuit 100A4 in Figure 6(B) You may change it to match any one of the following configurations.

[0230] Wiring VME1 and wiring VME2 are, for example, wires that provide a constant potential. It is possible. However, the constant potential is, for example, the voltage supplied by wiring VDE1 to wiring VDE4. It is preferable to set the potential lower than the given position. Note that wiring VME1 and wiring VME2 are given The constant potentials may be equal in potential or different in potential. If the constant potential supplied by wiring VDE1 and wiring VDE2 is 5V, then the wiring It is preferable that the constant potential supplied by VME1 and wiring VME2 is 4V.

[0231] Furthermore, the operation of circuit 100C can be performed by applying the operation example of circuit 100A1 described above. ru.

[0232] <<Comparison 3>> Here, similar to Configuration Example 1 and Configuration Example 2, the circuit 100C shown in Figure 8 and the previously mentioned Figure 5 This section explains the differences in configuration and operation between circuit 101 and the other circuit.

[0233] In the circuit 100C shown in Figure 8, the first gate of transistor MN5 is electrically connected to the wiring VME1. The first gate of transistor MN8 is electrically connected to wiring VME2. In this respect, it differs from circuit 101 in Figure 5.

[0234] Between time T5 and time T6 in the above example of operation, the transistor is in the OFF state. Let's consider the case where Zista MN5 is normally on.

[0235] In circuit 101, when transistor MN5 is normally on, The charge held at the second terminal of transistor MN5 (the first gate of transistor MN6) The current flows to node N1, and as a result, to the second terminal of transistor MN5 (transistor M The potential of the first gate of N6 is 2V High -V Low -V th_MN5 A place that is lower than There is a match. Therefore, the bootstrap effect described above becomes smaller, and the potential of terminal OT is V High It can sometimes be lower than that.

[0236] Furthermore, in the above example of operation, the device is in an off state between time T6 and time T7. Let's consider the case where transistor MN8 is normally-on.

[0237] In circuit 101, when transistor MN8 is normally on, The charge held at the second terminal of transistor MN8 (the first gate of transistor MN9) The current flows to node N1, and as a result, to the second terminal of transistor MN8 (transistor M The potential of the first gate of N9 is 2V High -V Low -V th_MN8 It will be lower than In some cases, this can lead to a reduction in the bootstrap effect described above, and the potential of terminal GT decreases. ga V High It can sometimes be lower than that.

[0238] On the other hand, in circuit 100C in Figure 8, transistors MN5 and MN8 The potential applied to each of the first gates (the potential applied by wiring VME1 and wiring VME2) However, by lowering the potential below that supplied by wiring VDE1, when the potential of node N1 is boosted... Then, the timing when transistors MN5 and MN8 are each turned off The process becomes faster than the configuration of circuit 101 in Figure 5. Also, transistor MN5 and transistor Even after each of the MN8 generators is turned off, the potential of node N1 is, ideally, wired The potential difference between the potential supplied by VDE1 and the threshold voltage of transistor MN1 increases. As a result, the gate-source connections of transistors MN5 and MN8 are Since the voltage will be lower than 0V, transistors MN5 and MN8 will be turned off. The current can be made lower. This allows transistors MN6 and M The potential of each first gate of N9 can be maintained for a long time.

[0239] Note that the potential of the first gate of transistor MN6 at this time is the voltage supplied by wiring VME1. This is the difference between the position and the threshold voltage of transistor MN5, and also the first position of transistor MN9. The gate potential is the difference between the potential supplied by wiring VME2 and the threshold voltage of transistor MN9. Therefore, in circuit 100C in Figure 8, transistor MN6 and transistor The potential of each first gate of MN9 is the same as that of transistor MN6 in circuit 101 in Figure 5. The potentials of the first gates of transistors MN9 and the circuit shown in Figure 8 are lower than those of the first gates of each transistor. The first gates of transistors MN6 and MN9 at 100C The potential can be boosted by bootstrapping using capacitors C2 and C3. Cut.

[0240] Therefore, the drive circuit GD in Figure 3(A) or Figure 3(B) has a circuit 100[1] to circuit By applying circuit 100C in Figure 8 to each of the 100[m], circuit 1 in Figure 5 is obtained. This allows the drive circuit GD to operate more stably than applying 01.

[0241] <Configuration Example 4> Figure 9(A) shows a half of one aspect of the present invention, which differs from the circuit described in Configuration Examples 1 to 3. The circuit 100 of the drive circuit GD in Figures 3(A) and 3(B), which are conductive devices [ 1] An example of a circuit configuration applicable to a circuit of up to 100[m] is shown.

[0242] Circuit 100D1 is a modified circuit configuration of circuit 100A1 in Figure 1(A), and The second gate of transistor MN5 is electrically connected to wiring VSE7, and transistor M The difference from circuit 100A1 is that the second gate of N8 is electrically connected to wiring VSE8. It is.

[0243] Furthermore, circuit 100D1 is configured such that transistors MN7 and MN10 The second gate of circuit 100D is electrically connected to wiring BG1, but circuit 100D The connection destinations for the second gates of transistors MN7 and MN10 are: Circuit 100A1 in Figure 1(A), Circuit 100A3 in Figure 6(A), Circuit 100 in Figure 6(B) You may change it to match any one of the A4 layouts.

[0244] Wiring VSE7 and wiring VSE8 are, for example, wiring VSE1 to wiring V Similar to each of the SE5s, it functions, for example, as wiring that provides a constant potential. The potential can be, for example, a low-level potential, ground potential, or negative potential. The constant potential supplied by wiring VSE7 is supplied by wiring VSE1 through VSE5 and wiring VSE8. If the potential supplied by one or more selected points is equal, then wiring VSE7 and that wiring are considered the same wiring. Also, the constant potential provided by wiring VSE8 is also good. If one or more selected from line VSE7 give the same potential, then wiring VSE8 and its wiring are the same It can also be used as a single wire.

[0245] Furthermore, one or both of the wires selected from wiring VSE7 and wiring VSE8 are not at a constant potential. Alternatively, it may be used as wiring that provides a variable potential.

[0246] Furthermore, the operation of circuit 100D1 can be performed by applying the operation example of circuit 100A1 described above. Cut.

[0247] <<Comparison 4>> Here, similar to Configuration Examples 1 to 3, the circuit 100D1 shown in Figure 9(A) and the previously mentioned The differences in configuration and operation between the circuit 101 in Figure 5 and the other circuit will be explained.

[0248] As described above, in the circuit 100D1 of Figure 9(A), the second gate of transistor MN5 is Electrically connected to wiring VSE7, the second gate of transistor MN8 is electrically connected to wiring VSE8. The configuration is electrically connected. Also, circuit 101 in Figure 5 has transistor MN The second gate of transistor 5 is electrically connected to the first gate of transistor MN5, and transistor M The second gate of N8 is electrically connected to the first gate of transistor MN8. It is.

[0249] Between time T5 and time T6 in the above example of operation, the transistor is in the OFF state. Let's consider the case where Zista MN5 is normally on.

[0250] In circuit 101, when transistor MN5 is normally on, the above As shown in Comparison 3, the second terminal of transistor MN5 (the first gate of transistor MN6) The potential is 2V High -V Low -V th_MN5 It becomes lower than the bootstra mentioned above. The effect of the pin decreases, and the potential of terminal OT becomes V High It can sometimes be lower than that.

[0251] Furthermore, in the above example of operation, the device is in an off state between time T6 and time T7. Let's consider the case where transistor MN8 is normally-on.

[0252] In circuit 101, when transistor MN8 is normally on, the above As shown in Comparison 3, the second terminal of transistor MN8 (the first gate of transistor MN9) The potential is 2V High -V Low -V th_MN8 It becomes lower than the bootstra mentioned above. The effect of the wrap decreases, and the potential of terminal GT becomes V High It can sometimes be lower than that.

[0253] On the other hand, transistors MN5 and MN8 in circuit 100D1 of Figure 9(A) The respective threshold voltages are those of transistor MN5 and transistor MN5 in circuit 101 of Figure 5. Unlike MN8, the potential is fluctuated by the potential applied to wiring VSE7 and wiring VSE8. This can be done. For example, the potential applied to wiring VSE7 and wiring VSE8 can be reduced. By setting the potential to Bell potential, ground potential, or negative potential, transistor MN5 and transistor The threshold voltages of each of the transistors MN8 can be increased, as can the transistors MN5 and Each of the MN8 transistors can be switched from normally on to normally off. This will cause transistors MN5 and MN8 of circuit 100D1 to be affected respectively. The amount of this off-current is that of transistors MN5 and MN8 in circuit 101. It can be made smaller than the amount of their off-currents. That is, transistor MN6, and The potential of each first gate of transistor MN9 can be maintained for a long time.

[0254] Furthermore, the circuit configuration of circuit 100D1 is changed to the circuit configuration of circuit 100D2 shown in Figure 9(B). It may be modified. Circuit 100D2, as an example, has the second gate of transistor MN5 wired The point where it is electrically connected to BG2, and the second gate of transistor MN8 is connected to wiring BG2. It differs from circuit 100D1 in that it is electrically connected.

[0255] By applying ground potential, low level potential, or negative potential to wiring BG2, circuit 100 In the configuration of D2, as with circuit 100D1, transistor MN5 and transistor Each of the MN8 can be set to normally off.

[0256] Furthermore, the circuit configuration of circuit 100D1 is as shown in Figure 10(A), except for circuit 100D2. The circuit configuration of circuit 100D3 may be changed. Circuit 100D3 is, as an example, a transistor The second gates of transistors MN5 and MN8 are electrically connected to wiring BG3. It differs from circuit 100D1 in that it is configured in a certain way.

[0257] Regarding wiring BG3, the explanation of wiring BG3 applied to circuit 100A4 as described in Configuration Example 1 is as follows: We will drink from the Ming Dynasty.

[0258] By applying ground potential, low level potential, or negative potential to wiring BG3, circuit 100 In the configuration of D3, as with circuit 100D1, transistor MN5 and transistor Each of the MN8 can be set to normally off.

[0259] Furthermore, the circuit configuration of circuit 100D1 is the same as the circuit configuration of circuit 100D4 shown in Figure 10(B). It may be changed. Circuit 100D4, as an example, uses transistor MN5 and transistor Each of the second gates of transistor MN8 connects to the first gate of transistor MN2 and the second gate of capacitor C1. Terminal 1, the first terminal of transistor MN4, the first gate of transistor MN7, and It differs from circuit 100D1 in that it is electrically connected to the first gate of the inverter MN10. It is.

[0260] In circuit 100D4 of Figure 10(B), for example, when a low-level potential is input to terminal IT Furthermore, when a high-level potential is input to terminal CLK2, transistor MN1 is in the off state. In this state, transistor MN3 is ON and transistor MN4 is OFF, The first gate of transistor MN2, the first terminal of capacitor C1, and the first terminal of transistor MN4 The potential difference between the first gate of transistor MN7 and the first gate of transistor MN10 is It becomes higher. At this time, transistors MN5 and MN8 are no It becomes a marion and turns on. Also, the first gate of transistor MN2 is at a high level. As the potential increases, transistor MN2 turns ON, and transistors MN6 and MN2 turn ON. Each of the first gates of the MN9 transistor will be at a low potential.

[0261] Furthermore, for example, if a high-level potential is input to terminal IT and a low-level potential is input to terminal CLK2, When this input is present, transistor MN3 is in the off state and transistor MN4 is in the on state. Therefore, the first gate of transistor MN2 and the first terminal of capacitor C1, and the transistor The first terminal of MN4, the first gate of transistor MN7, and the first terminal of transistor MN10 The potential between the gate and the transistor becomes a low-level potential. At this time, transistor MN5 and the transistor Each of the MN8 transistors is normally off. Also, at this time, the MN 1 is ON, transistor MN2 is OFF, transistor MN5 is ON, Since transistor MN8 is ON, transistors MN6 and MN The potential of the first gate of each of the 8 transistors increases. Then, transistor MN5 and transistor When the potential of each first terminal (node ​​N1) of the MN8 reaches a predetermined level, The transistor MN5 and transistor MN8 are both turned off.

[0262] As described above, by configuring circuit 100D4, when circuit 100D4 is operating... Then, at the necessary timing, temporarily switch transistors MN5 and MN8 It can be turned off normally. Therefore, transistor MN6 and transistor The potential of each first gate of the MN9 can be maintained for a long time.

[0263] Based on the above, the drive circuit GD in Figure 3(A) or Figure 3(B) has circuits 100[1] to 1 For each of 00[m], there is circuit 100D1 in Figure 9(A) and circuit 100D2 in Figure 9(B). By applying circuit 100D3 in Figure 10(A) or circuit 100D4 in Figure 10(B), Therefore, it is possible to make the drive circuit GD operate more stably than by applying circuit 101 in Figure 5. Cut.

[0264] <Configuration Example 5> Figure 11 shows a semiconductor according to one aspect of the present invention, which differs from the circuits described in Configuration Examples 1 to 4. The device consists of the drive circuits GD shown in Figures 3(A) and 3(B), respectively, and the circuits 100[1] An example of a circuit configuration applicable to a circuit of up to 100 [m] is shown.

[0265] Circuit 100E is a modified circuit configuration of circuit 100A1 in Figure 1(A), and the transient The second gate of transistor MN5 is electrically connected to the first terminal of transistor MN5, The second gate of transistor MN8 is electrically connected to the first terminal of transistor MN8. In this respect, it differs from circuit 100A1.

[0266] Furthermore, circuit 100E is configured for each of transistors MN7 and MN10. The second gate is electrically connected to wiring BG1, but circuit 100E The connection destinations for the second gates of transistors MN7 and MN10 are shown in the diagram. Circuit 100A1 in Figure 1(A), Circuit 100A3 in Figure 6(A), Circuit 100A4 in Figure 6(B) You may change it to match any one of the following configurations.

[0267] Furthermore, the operation of circuit 100E can be performed by applying the operation example of circuit 100A1 described above. ru.

[0268] <<Comparison 5>> Here, similar to Configuration Examples 1 to 4, the circuit 100E shown in Figure 11 and the previously mentioned Figure 5 This section explains the differences in configuration and operation between circuit 101 and the other circuit.

[0269] As described above, in the circuit 100E in Figure 11, the second gate of transistor MN5 is The first terminal of transistor MN5 is electrically connected, and the second gate of transistor MN8 is connected to the transistor The configuration is electrically connected to the first terminal of the ZISTA MN8. Also, see the circuit in Figure 5. 101 is the electrical signal from the second gate of transistor MN5 to the first gate of transistor MN5. It is connected, and the second gate of transistor MN8 electrically connects to the first gate of transistor MN8. The configuration is such that they are connected in a specific way.

[0270] When the operation example of the timing chart in Figure 4 is applied to the operation of circuit 101, During the period when a high-level potential is input to terminal IT (between time T4 and time T5), Node N1 (the second terminal of transistor MN1, the first terminal of transistor MN2, and The electrical connection point between the first terminal of transistor MN5 and the first terminal of transistor MN8. As the potential increases, the gates of transistors MN5 and MN8 -When the source-to-source voltage falls below the respective threshold voltage, the transistor MN 5. Transistor MN8 is turned off.

[0271] At this time, when the configuration of circuit 101 is changed to the configuration of circuit 100E, transistor M The potentials of the second gates of N5 and transistor MN8 are equal to the potential of node N1. That is, the transistors MN5 and MN8 in circuit 100E. The potential of its second gate (node ​​N1) is the same as that of transistor MN in the operation example described above. 5. And the potential of the second gate of each transistor MN8 is lower, so circuit 1 The threshold voltages of transistors MN5 and MN8 at 00E The respective configurations of transistors MN5 and MN8 in circuit 101 The voltage will be higher than the specified value. Therefore, change the configuration of circuit 101 to that of circuit 100E. Then, a high-level potential is input to terminal IT, and the potential of node N1 rises during the period (time T4 or During the period from [time] to time T5, transistors MN5 and MN8 respectively This makes it easier for transistors MN5 and MN8 to turn off, respectively. The amount of off-current can be reduced. That is, transistor MN6, and transistor The potential of each first gate of the MN9 can be maintained for a long time.

[0272] Therefore, the drive circuit GD in Figure 3(A) or Figure 3(B) has a circuit 100[1] to circuit By applying circuit 100E in Figure 11 to each of the 100[m], the circuit in Figure 5 is obtained. This allows the drive circuit GD to operate more stably than applying 101.

[0273] <Configuration Example 6> Figure 12(A) shows a circuit different from the one described in Configuration Examples 1 to 5, representing one aspect of the present invention. The semiconductor device is the drive circuit GD shown in Figures 3(A) and 3(B), and the circuit 100 is the respective drive circuit GD. [1] An example of a circuit configuration that can be applied to a circuit of 100[m] is shown.

[0274] Circuit 100F1 is a modified circuit configuration of circuit 100A1 in Figure 1(A), and It differs from circuit 100A1 in that it has a diode MN11 and a capacitor C5. Specifically, In circuit 100F1, the first terminal of transistor MN11 is electrically connected to terminal IT. The second terminal of transistor MN11 connects with the first gate of transistor MN1, and the transistor The second gate of transistor M1 and the first terminal of capacitor C5 are electrically connected, The first gate of N11 connects to the second gate of transistor MN11 and to wiring VDE5. The configuration is such that they are connected precisely. Also, the second terminal of capacitor C5 is connected to transistor MN. The second terminal of 1, the first terminal of transistor MN2, and the first terminal of transistor MN5, It is electrically connected to the first terminal of transistor MN8.

[0275] Furthermore, circuit 100F1 is configured such that transistors MN7 and MN10 The second gate of the circuit is electrically connected to wiring BG1, but circuit 100F The connection destinations for the second gates of transistors MN7 and MN10 are: Circuit 100A1 in Figure 1(A), Circuit 100A3 in Figure 6(A), Circuit 100 in Figure 6(B) You may change it to match any one of the A4 layouts.

[0276] Wiring VDE5 is, for example, similar to each of the wirings VDE1 to VDE4. For example, it functions as wiring that provides a constant potential. This constant potential can be, for instance, a high-level wire. It can be an electric potential, etc. Also, the constant potential provided by wiring VDE5 is determined by wiring VDE1 to If the potential given by one or more selected wires from wiring VDE4 is equal, then wiring VDE5 and its wires They may be the same wiring.

[0277] Furthermore, wiring VDE5 may be wired to provide a variable potential rather than a constant potential.

[0278] Furthermore, the operation of circuit 100F1 can be performed by applying the operation example of circuit 100A1 described above. Cut.

[0279] <<Comparison 6>> Here, similar to Configuration Examples 1 to 5, the circuit 100F1 shown in Figure 12(A) and the aforementioned The differences in configuration and operation between circuit 101 in Figure 5 and the other circuit will be explained.

[0280] As described above, circuit 100F1 in Figure 12(A) consists of transistor MN11 and a capacitor. The configuration includes C5. On the other hand, the circuit 101 in Figure 5 has transistor MN 11 and the configuration does not have capacity C5.

[0281] When the operation example of the timing chart in Figure 4 is applied to the operation of circuit 101, During the period when a high-level potential is input to terminal IT (between time T4 and time T5), Node N1 (the second terminal of transistor MN1, the first terminal of transistor MN2, and The electrical connection point between the first terminal of transistor MN5 and the first terminal of transistor MN8. As the potential increases, the gates of transistors MN5 and MN8 -When the source-to-source voltage falls below the respective threshold voltage, the transistor MN 5. Transistor MN8 is turned off.

[0282] On the other hand, the operation example of the timing chart in Figure 4 is applied to the operation of circuit 100F1. When this is happening, a high-level potential is input to terminal IT during the period from time T4 to time T5. Between these points, the first terminal of transistor MN11 and the second terminal of transistor MN11 ( The potential of the first gate of transistor MN1 increases. Also, the potential of the gate of transistor MN11 increases. When the source-source voltage falls below the threshold voltage of transistor MN11, The transistor MN11 turns off. Also, the gate-source voltage of transistor MN1 Because the voltage becomes greater than the threshold voltage of transistor MN1, transistor MN1 is This creates an "off" state, and the potential at node N1 increases. At this time, transistor MN11 is in the "off" state. Because of this state, the bootstrap by capacitance C5 causes the transistor MN1 to The potential of the first gate increases further. This results in a higher gate-source voltage across transistor MN1. Because the voltage becomes sufficiently greater than the threshold voltage, the potential at node N1 is such that the wiring VDE1 The voltage is increased to the desired potential.

[0283] In other words, the voltage increase at node N1 by applying a high-level potential to terminal IT is shown in Figure 5. The circuit 100F1 in Figure 12(A) is higher than the circuit 101.

[0284] As a result, in circuit 100F1, transistors MN5 and MN8 The potential of each of the first terminals rises to the potential supplied by wiring VDE1, so the transient The gate-source current when both transistor MN5 and transistor MN8 are in the off state. The difference between the voltage and the threshold voltage is greater than in the case of the circuit configuration 101. Therefore, the circuit The amount of off-current for transistors MN5 and MN8 of the 100F1 is The amount of off-current of transistors MN5 and MN8 in circuit 101. It can be made smaller than that. That is, transistors MN6 and MN9 The potential of each of the first gates can be maintained for a long time.

[0285] Furthermore, the circuit configuration of circuit 100F1 is the same as the circuit configuration of circuit 100F2 shown in Figure 12(B). It may be changed. Circuit 100F2 has a connection configuration for transistor MN11 and the transistor It differs from circuit 100F1 in that it has a component MN12.

[0286] Specifically, the first gate of transistor MN11 is electrically connected to wiring VDE5. Furthermore, it is electrically connected to the second gate of transistor MN11. The first terminal of transistor MN12 is connected to the first gate of transistor MN1, and the terminal of transistor MN1 The second gate is electrically connected to the second terminal of transistor MN11, The second terminal of MN12 is connected to terminal IT, the first terminal of transistor MN11, and transistor The first gate of transistor MN4 is electrically connected to the terminal, and the first gate of transistor MN12 is connected to the terminal. Electrically connected to child CLK1, the second gate of transistor MN12 is electrically connected to wiring BG1. They are connected by energy.

[0287] When a low-level potential is input to terminal CLK1, transistor MN12 is turned off. When this happens, a high-level potential is input to terminal IT, causing the first gate of transistor MN1 to malfunction. The potential is the threshold voltage of transistor MN11, from the high-level potential applied to terminal IT. The potential is reduced by this. Also, transistor MN11 has a diode connection configuration. Therefore, the potential of the second terminal of transistor MN11 is the high-level potential applied to terminal IT. When the potential becomes the threshold voltage of transistor MN11 minus the threshold voltage of transistor MN1 1 is in the OFF state. Then, transistor MN1 turns ON, and the power of node N1 For the operation in which the position increases due to bootstrap at capacitance C5, see circuit 100. Refer to the explanation of how F1 works.

[0288] Furthermore, if you want to lower the potential of the first gate of transistor MN1 to a low level, for example, Simply input a low-level potential to terminal IT and a high-level potential to terminal CLK1. This refers to the operation of the circuit 100A in Embodiment 1 between time T5 and time T9. This corresponds to the operation in which transistor MN12 turns on, and terminal IT and the transistor Because a conductive state is established between the first gate of transistor MN1, the first gate of transistor MN1 The potential of transistor MN1 can be reduced to a low level potential. Because the source-source voltage becomes lower than the threshold voltage of transistor MN1, the transistor Node MN1 is in the off state, node N1 is in the floating state, and capacity C5 This maintains the high-level potential supplied from wiring VDE1.

[0289] By applying the configuration of circuit 100F2, circuit 100F2 can be used in the same way as circuit 100F1. The amount of off-current for transistors MN5 and MN8 is as follows: The amount of off-current of transistor MN5 and transistor MN8 is smaller than the amount of off-current of each transistor. This allows the first gates of transistors MN6 and MN9 to be made It can maintain the potential for a long time.

[0290] Based on the above, the drive circuit GD in Figure 3(A) or Figure 3(B) has circuits 100[1] to 1 Each of the 00[m] is either circuit 100F1 in Figure 12(A) or circuit 10 in Figure 12(B). By applying 0F2, the drive circuit GD is safer than applying circuit 101 in Figure 5. It can be operated at a fixed rate.

[0291] <Configuration Example 7> Figure 13 shows a semiconductor according to one embodiment of the present invention, which differs from the circuits described in Configuration Examples 1 to 6. The device consists of the drive circuits GD shown in Figures 3(A) and 3(B), respectively, and the circuits 100[1] An example of a circuit configuration applicable to a circuit of up to 100 [m] is shown.

[0292] Circuit 100G is a circuit configuration that is a modified version of circuit 100A1 in Figure 1(A), and the transient This circuit differs from circuit 100A1 in that it does not include transistors MN5 and MN8. .

[0293] Furthermore, circuit 100G is configured for each of transistors MN7 and MN10. The second gate is electrically connected to wiring BG1, but the circuit 100G The connection destinations for the second gates of transistors MN7 and MN10 are shown in the diagram. Circuit 100A1 in Figure 1(A), Circuit 100A3 in Figure 6(A), Circuit 100A4 in Figure 6(B) You may change it to match any one of the following configurations.

[0294] By omitting the transistor MN5, the first gate of transistor MN6 is Parasitic capacitance around the meter can be reduced. Similarly, by providing transistor MN8, By eliminating this configuration, the parasitic capacitance around the first gate of transistor MN8 is reduced. It is possible.

[0295] Furthermore, the circuit configuration of circuit 100G is such that transistors MN6 and MN9 Designed to minimize parasitic capacitance around each first gate (node ​​N1). It is preferable that this is done. Specifically, for example, transistor MN6 and transistor The first gate of transistor MN9, the second terminal of transistor MN1, and the terminal of transistor MN2 It is preferable to shorten the wiring that electrically connects one terminal to the other.

[0296] The first gate (node ​​N1) of transistors MN6 and MN9 By reducing the parasitic capacity around it, boots in capacity C2 and capacity C3 The traps in the first gates of transistors MN6 and MN9 The voltage can be increased more significantly. This allows for a greater boost in transistor MN6, and The drive capability of the inverter MN9 can be increased, and the potential from terminal CLK1 is transmitted to terminal OT. However, the output voltage drops almost completely, and the potential at terminal GT from terminal PWC drops almost completely. It will be output without being output.

[0297] Based on the above, the drive circuit GD in Figure 3(A) or Figure 3(B) has circuits 100[1] to 1 By applying circuit 100G in Figure 13 to each of 00[m], circuit 1 in Figure 5 is obtained. This allows the drive circuit GD to operate more stably than applying 01.

[0298] <Configuration Example 8> Circuit 100AA1 in Figure 14(A), Circuit 100AA2 in Figure 14(B), and Circuit 100AA2 in Figure 15(A) Circuit 100AA3, circuit 100AA4 in Figure 15(B), and circuit 100AA5 in Figure 16 Each of these is a modified example of circuit 100A1 as described in Configuration Example 1, and circuit 100AA1, Circuits 100AA2, 100AA3, 100AA4, and 100AA5 These are semiconductor devices according to one aspect of the present invention, as shown in Figures 3(A) and 3(B). It can be applied to circuits 100[1] to 100[m] of the drive circuit GD.

[0299] Circuit 100AA1 in Figure 14(A) is, as an example, a trace of circuit 100A1 in Figure 1(A). Transistor MN2 and transistor MN4 are each multi-gate transistors This is the structure.

[0300] Specifically, for example, transistor MN2 is composed of transistor MN2a and transistor M It has N2b and the first terminal of transistor MN2a and the first terminal of transistor MN2b They are electrically connected to each other, and each of transistors MN2a and MN2b The first gates are electrically connected to each other, and transistors MN2a and MN2b Each of the second gates is electrically connected to the others. Therefore, transistor MN2 The first gate of transistor a and transistor MN2b is the first gate of transistor MN2. It functions as such, and the second gates of transistors MN2a and MN2b are It functions as the second gate of transistor MN2. Also, the second gate of transistor MN2a. The terminal corresponds to the first terminal of transistor MN2, and the second terminal of transistor MN2b is, This corresponds to the second terminal of transistor MN2.

[0301] Also, for example, transistor MN4 is composed of transistor MN4a and transistor MN4b The first terminal of transistor MN4a and the first terminal of transistor MN4b are mutually connected. Electrically connected, the first gates of transistors MN4a and MN4b The transistors are electrically connected to each other, and transistors MN4a and MN4b are each The second gates of these are electrically connected to each other. Therefore, transistor MN4a and Each first gate of transistor MN4b is the first gate of transistor MN4 It functions, and the second gates of transistors MN4a and MN4b respectively are It functions as the second gate of transistor MN4. Also, the second terminal of transistor MN4a is , corresponds to the first terminal of transistor MN4, and the second terminal of transistor MN4b is, This corresponds to the second terminal of the ZISTA MN4.

[0302] By making transistor MN2 a multi-gate transistor, When transistor MN2 is in the off state, current flows between the first and second terminals of transistor MN2. The off-current can be reduced. Similarly, the transistor MN4 has a multi-gate structure. By using this transistor, when transistor MN4 is in the off state, The off-current flowing between the first and second terminals of the transistor MN4 can be reduced.

[0303] Note that the transistor MN2 and transistor in circuit 100AA1 shown in Figure 14(A) MN4 is a multi-gate transistor with two transistors each. However, transistors MN2 and MN4 have three or more transistors. It may also be used as a multi-gate transistor.

[0304] Furthermore, the circuit 100AA1 shown in Figure 14(A) includes transistor MN2 and transistor Although MN4 was made into a multi-gate transistor, the configuration of circuit 100AA1 is as follows: One or more transistors selected from transistors MN1 to MN10 form a multi-gate structure. It can also be used as a generator.

[0305] Also, transistor MN2 and transistor in circuit 100AA1 shown in Figure 14(A) This applies not only to MN4, but also to the transistors illustrated in other drawings in this specification. A multi-gate transistor structure can be applied.

[0306] Note that in circuit 100AA1, the second gate of transistor MN7 is The second terminal is electrically connected, and the second gate of transistor MN10 is connected to transistor MN1 Although it is configured to be electrically connected to the second terminal of 0, the transistor of circuit 100AA1 The second gates of transistors MN7 and MN10 are connected to wiring BG1. They may be connected in a specific manner. Alternatively, transistor MN7 of circuit 100AA1 and transistor The connection destinations for each of the second gates of the ZISTA MN10 are circuit 100A3 in Figure 6(A) and Figure 6 (B) The circuit 100A4 may be modified to match any one of its configurations.

[0307] Circuit 100AA2 in Figure 14(B) is, as an example, a trace of circuit 100A1 in Figure 1(A). Transistor MN2, Transistor MN4, Transistor MN7, and Transistor MN10 The configuration involves swapping the connections between the first and second gates of each device.

[0308] Specifically, in circuit 100AA2 in Figure 14(B), for example, transistor MN2 The first gate of transistor MN2 is electrically connected to wiring BG1, and the second gate of transistor MN2 is connected to The first terminal of capacitor C1, the second terminal of transistor MN3, and the first terminal of transistor MN4 And, the second gate of transistor MN7 and the second gate of transistor MN10, They are connected precisely. Also, for example, the first gate of transistor MN4 is connected to wiring BG2. They are electrically connected. Also, for example, the first gate of transistor MN7 is The second terminal of MN7 is electrically connected to the wiring VSE4. Also, for example, The first gate of transistor MN10 is connected to the second terminal of transistor MN10 and to wiring VSE It is electrically connected to 5.

[0309] As shown in circuit 100AA2 in Figure 14(B), transistors MN2 and M The first and second gates of transistors N4, MN7, and MN10 respectively Even if the connections to the terminals are swapped, circuit 100AA2 will function similarly to circuit 100A1. In some cases, the desired operation can be performed.

[0310] Note that in circuit 100AA2 shown in Figure 14(B), transistor MN2, transistor The first gate and second gate of transistors MN4, MN7, and MN10 respectively The connections to the gates were swapped, but in circuit 100AA2, other than those mentioned above, Regarding the transistors, the connection destinations of the first and second gates may also be swapped.

[0311] Also, transistors MN2 and MN of circuit 100AA2 shown in Figure 14(B) 4. Transistors MN7 and MN10, as well as other transistors in this specification Regarding the transistors shown in the diagram, the connection points of the first and second gates are also specified. You may make a replacement.

[0312] Note that in circuit 100AA2, the second gate of transistor MN7 is The second terminal is electrically connected, and the second gate of transistor MN10 is connected to transistor MN1 Although it is configured to be electrically connected to the second terminal of 0, the transistor of circuit 100AA2 The second gates of transistors MN7 and MN10 are connected to wiring BG1. They may be connected in a specific way. Alternatively, transistor MN7 of circuit 100AA2 and transistor The connection destinations for each of the second gates of the ZISTA MN10 are circuit 100A3 in Figure 6(A) and Figure 6 (B) The circuit 100A4 may be modified to match any one of its configurations.

[0313] The circuit 100AA3 in Figure 15(A) is, as an example, a transistor MN1, a transistor MN3, transistor MN5, transistor MN6, transistor MN8, and transistor In each of the MN9 stadiums, there is no second gate.

[0314] In the same transistor, the first gate and the second gate are electrically connected to each other. This allows the on-current of the transistor to be increased. On the other hand, the transistor If there is no need to increase the on-current of the transistor, the second gate of the transistor is omitted. This is also possible. Specifically, for example, in circuit 100A1 of Figure 1(A), transistor M N1, transistor MN3, transistor MN5, transistor MN6, transistor M If the on-current of N8 and transistor MN9 is sufficiently high, then circuit 10 in Figure 15(A) As shown in 0AA3, the above-mentioned transistor does not need to have a second gate. stomach.

[0315] Note that in circuit 100AA3, the second gate of transistor MN7 is The second terminal is electrically connected, and the second gate of transistor MN10 is connected to transistor MN1 Although it is configured to be electrically connected to the second terminal of 0, the transistor of circuit 100AA3 The second gates of transistors MN7 and MN10 are connected to wiring BG1. They may be connected in a specific way. Alternatively, transistor MN7 of circuit 100AA3 and transistor The connection destinations for each of the second gates of the ZISTA MN10 are circuit 100A3 in Figure 6(A) and Figure 6 (B) The circuit 100A4 may be modified to match any one of its configurations.

[0316] Circuit 100AA4 in Figure 15(B) is, as an example, the n-th element of circuit 100A1 in Figure 1(A). Each of the channel-type transistors, transistors MN1 through MN10, , changed to p-channel type transistors, specifically transistors MP1 to MP10. This is the configuration.

[0317] For example, transistors MP1 through MP10 can be SOI(Si By applying a p-channel transistor with a licon-on-insulator structure... It is possible.

[0318] Specifically, the first terminal of transistor MP1 is electrically connected to wiring VSE11. The second terminal of transistor MP1 connects to the first terminal of transistor MP2, and transistor MP The first terminal of 5 is electrically connected to the first terminal of transistor MP8, The first gate of MP1 is connected to the second gate of transistor MP1, terminal IT, and transistor It is electrically connected to the first gate of the MP4.

[0319] Furthermore, the first terminal of transistor MP3 is electrically connected to wiring VSE12, The second terminal of transistor MP3 is connected to the first gate of transistor MP2 and the first terminal of capacitor C1. , the first terminal of transistor MP4, the first gate of transistor MP7, and transistor The first gate of transistor MP10 is electrically connected to the first gate of transistor MP3. It is electrically connected to the second gate of the transistor MP3 and terminal CLK2.

[0320] Furthermore, the second terminal of transistor MP5 is connected to the first gate of transistor MP6, and The second gate of the zista MP6 and the first terminal of the capacitor C2 are electrically connected, and the transistor The first gate of transistor MP5 connects to the second gate of transistor MP5 and to wiring VSE13. They are electrically connected. The first terminal of transistor MP6 is electrically connected to terminal CLK1. The second terminal of transistor MP6 is connected to the second terminal of capacitor C2, and the second terminal of transistor MP7 The first terminal and the terminal OT are electrically connected.

[0321] Furthermore, the second terminal of transistor MP8 is connected to the first gate of transistor MP9, and The second gate of the ZISTA MP9 and the first terminal of the capacitor C3 are electrically connected, and the transistor The first gate of transistor MP8 connects to the second gate of transistor MP8 and to wiring VSE14. They are electrically connected. The first terminal of transistor MP9 is electrically connected to terminal PWC. The second terminal of transistor MP9 is connected to the second terminal of capacitor C3, and the second terminal of transistor MP10 is connected to the second terminal of capacitor C3. The first terminal and terminal GT are electrically connected.

[0322] Furthermore, the second terminal of transistor MP2 is electrically connected to wiring VDE11, The second gate of the ZISTA MP2 is electrically connected to wiring BG11. Also, capacitance C1 The second terminal is electrically connected to wiring VDE12. Also, transistor MP4 The second terminal is electrically connected to wiring VDE13, and the second gate of transistor MP4 is It is electrically connected to wiring BG12. Also, the second terminal of transistor MP7 is connected to the transistor It is electrically connected to the second gate of the converter MP7 and wiring VDE14. The second terminal of transistor MP10 is connected to the second gate of transistor MP10 and to wiring VDE It is electrically connected to 15.

[0323] Each of the wirings VDE11 to VDE15 is, as an example, the wiring described in Configuration Example 1. Similar to lines VDE1 to wiring VDE4, it functions as wiring that provides a constant potential. As a constant potential, for example, a high-level potential can be used. Note that the wiring VDE11 to Each of the wires VDE15 may be given the same constant potential, or different constant potentials. You may assign a position to each of the following: The above wiring provides each other with an equal constant potential, while the remaining wiring provides a different potential from that constant potential. You may assign a position to each of the wirings VDE11 to VDE15. Two or more wires that provide the same constant potential may be considered the same wire. For example, wire VDE1 If both 1 and wiring VDE12 give each other equal constant potentials, then wiring VDE11 and Wiring VDE12 may be the same wiring.

[0324] Furthermore, one or more selected from wiring VDE1 to VDE15 are variable, not constant potential. It can also be used as wiring to supply potential.

[0325] Each of the wirings VSE11 to VSE14 is, as an example, the wiring described in Configuration Example 1. Similar to wires VSE1 to VSE5, it functions as wiring that provides a constant potential. For example, this could be a low-level potential or ground potential. Each of the wirings 11 through VSE14 may be given an equal constant potential, or different potentials. A constant potential may be applied. Alternatively, a selection may be made from each of the wirings VSE11 to VSE14. Two or more wires that have been identified give each other an equal constant potential, and the remaining wires are not related to that constant potential. A different potential may be applied. Also, among the wirings VSE11 to VSE14 Two or more wires that give each other an equal constant potential may be considered the same wire. For example, wiring If VSE11 and wiring VSE12 each provide an equal constant potential to each other, then wiring VS E11 and wiring VSE12 may be the same wiring.

[0326] Furthermore, one or more selected from wiring VSE11 to wiring VSE14 are not constant potential, but are flexible. It can also be used as wiring to provide a voltage change.

[0327] Wiring BG11 and wiring BG12 are, for example, the same as the wiring described in Configuration Example 1. Similar to BG1 and wiring BG2, it functions as wiring that provides a constant potential. For example, it can be set to a high-level potential. Note that wiring BG11 and wiring B Each of the G12s may give each other equal constant potentials, or different constant potentials. It is also possible that wiring BG11 and wiring BG12 each provide each other with an equal constant potential. If the wiring is as described, wiring BG11 and wiring BG12 may be the same wiring.

[0328] Furthermore, one or both of wiring BG11 and wiring BG12 are not at a constant potential, but at a variable potential. It can also be used as wiring to assign positions.

[0329] As shown in circuit 100AA4 in Figure 15(B), the transistor configuration of circuit 100A1 Change transistors MN1 through MN10 to transistors MP1 through MP10. Change the wiring VDE1 to VDE4 to wiring VSE11 to VSE14, and By changing wires VSE1 through VSE5 to wires VDE11 through VDE15, Circuit 100AA4, like circuit 100A1, may be able to perform the desired operation. ru.

[0330] Note that circuit 100AA4 in Figure 15(B) is the same as the transistor in circuit 100A1 in Figure 1(A). Transistors MN1 through MN10 to transistors MP1 through MP10 The modified configuration is shown, but is not included in the circuitry illustrated in other drawings in this specification. Similarly, for transistors, n-channel transistors and p-channel transistors The polarity of the transistor may be changed. Also, if the polarity of the transistor is changed, the wiring VD E1 to wiring VDE4, wiring VSE1 to wiring VSE5, wiring BG1, wiring BG2 etc. The height of the applied constant potential may be changed.

[0331] Note that in circuit 100AA4, the second gate of transistor MP7 is The second terminal is electrically connected, and the second gate of transistor MP10 is connected to transistor MP1 Although it is configured to be electrically connected to the second terminal of 0, the transistor of circuit 100AA4 The second gates of transistor MP7 and transistor MP10 are connected to wiring BG11. They may be electrically connected. Alternatively, transistor MP7 of circuit 100AA4, and transistor Each second gate of the inverter MP10 is connected in the same way as circuit 100A3 in Figure 6(A). It may be electrically connected to wire BG12. Or, transistor M of circuit 100AA4. The second gates of P7 and transistor MP10 are connected to circuit 100A in Figure 6(B). Similar to 4, it may be electrically connected to the new wiring. The new wiring may be: The wiring can be configured to provide a constant potential, such as a high-level potential, or a variable potential.

[0332] Circuit 100AA5 in Figure 16 is, as an example, in circuit 100A1 in Figure 1(A), Transistors MN8 to MN10, capacitor C3, and terminal GT are not provided. It has a complex structure.

[0333] In the circuit 100AA5 in Figure 16, terminal GT is not provided, therefore, instead of terminal GT, The configuration outputs a signal only to terminal OT. For example, circuit 100A1 in Figure 1(A) By combining this with the circuit 100AA5 in Figure 16, the shift rate shown in Figures 3(A) and 3(B) is obtained. By configuring the zista, the shift register is configured to use circuit 100AA5. It is possible to configure the circuit 100 so that no signal is output from terminal GT. The shift register receives a clock signal input to the shift register and terminal OT, This is used to adjust the timing of signals output from terminals such as GT. There is a compatibility issue. Furthermore, the adjustment of the timing can be performed during the design phase of the shift register. can.

[0334] Furthermore, circuit 100AA5 in Figure 16 is a transient in circuit 100A1 in Figure 1(A). Configuration without transistors MN8 to MN10, capacitor C3, and terminal GT. However, instead of transistor MN5, transistor MN7, capacitor C2, and terminal The configuration may be changed to one without a child OT (not shown in the diagram).

[0335] The shift register of the drive circuit GD in Figures 3(A) and 3(B) is configured as described in Configuration Example 1 above. By using the circuit 100A1 described in Configuration Example 8, an n-channel type transient can be generated. A unipolar circuit consisting only of a transistor (in the case of circuit 100AA4 in Figure 15(B), a p-channel type transistor) A shift register (a unipolar circuit consisting only of a star) can be constructed. In particular, Configuration Examples 1 to One of the circuit configurations in Configuration Example 8, or two or more circuits selected from Configuration Examples 1 to 8. By applying the combined circuit configuration to a shift register, a circuit with stable operation can be created. It can be achieved.

[0336] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0337] (Embodiment 2) In this embodiment, the specific circuit configuration of the circuit 100A1 described in the above embodiment is as follows: I will explain.

[0338] Figure 17 is a layout diagram (plan view) showing an example of the circuit configuration of circuit 100A1 in Figure 1(A). (Figure). Also, in Figure 17, circuit 100A1 is, as an example, a conductive GEM and It comprises a conductive BGM, a conductive PLG, a conductive SDM, and a semiconductor SMC. Figure 17 does not show the insulator included in circuit 100A1.

[0339] The conductive background music (BGM) is located beneath the semiconductor SMC, as an example. For example, C is located below the conductive GEM. Also, for example, the conductive GEM is And it is located below the conductive SDM. In other words, in Figure 17, circuit 100A1 is From the bottom, the components are formed in the following order: conductive BGM, semiconductor SMC, conductive GEM, and conductive SDM. It is.

[0340] A portion of the conductive BGM is, for example, transistors MN1 to MN10. Each functions as a second gate. Also, some of the conductive GEMs are, for example, tra It functions as the first gate of transistors MN1 through MN10.

[0341] Conductive BGM, semiconductor SMC, conductive GEM, and conductive SDM are, for example, It can be formed using photolithography. Specifically, for example, conductor B When forming a GM, the conductive material that will become the conductive BGM is cut using the sputtering method, CVD (C) hemical vapor deposition) method, PLD (Pulsed La (Atomic Layer Deposition) method, or ALD (Atomic Layer Deposition) method The film is formed using a film deposition method such as the sition method, and then photolithography is applied. Therefore, the desired pattern can be formed. Also, semiconductor SMC, conductive GEM, and conductive Body SDM can also be formed using the same method as described above.

[0342] Furthermore, between the conductive BGM and the semiconductor SMC, and between the semiconductor SMC and the conductive GEM, An insulator may be provided between the GEM body and the SDM conductor. In particular, the BGM conductor The insulator provided between the semiconductor SMC is the first gate insulating film (back gate insulating film). It functions as (sometimes referred to as) and is placed between the semiconductor SMC and the conductive GEM. The insulator is the second gate insulating film (sometimes called the gate insulating film or front gate insulating film). It may function as a certain function.

[0343] Furthermore, the conductor PLG is between the conductor BGM and the conductor GEM, and between the conductor BGM and the conductor S Between DM, between conductive GEM and conductive SDM, or between semiconductor SMC and conductive SDM A conductive PLG (Plug-Linked Gem) is positioned between them and functions as a wire or plug to electrically connect them. For example, an opening is formed in the above-mentioned insulator, and a conductive material that will become a conductive PLG is placed in the opening. It is formed by filling in the conductor PLG. After the formation of the conductive PLG, the conductive PLG and To align the height of each film surface of the surrounding insulator, a flattening method such as chemical mechanical polishing is used. The flattening process may be performed by chemical treatment.

[0344] The transistors MN1 through MN10 are included in the circuit 100A1 shown in Figure 17. Each of these, as an example, is a conductor BGM, a semiconductor SMC, a conductor GEM, and an insulator. It has a part of each of the following. In other words, it has a part of conductive BGM and a part of semiconductor SM. C, along with some conductive GEM and some insulators, forms transistor MN1 to The transistor MN10 is formed.

[0345] Furthermore, the capacitance C1 included in circuit 100A1 in Figure 17 is due to the conductor BGM and the conductor GEM. It has a part of and. Also, the capacitance C2 and included in circuit 100A1 in Figure 17 Each of capacitance C3 has a portion of the conductor BGM and the conductor SDM, respectively. Furthermore, between the conductor BGM and conductor GEM contained in capacitance C1, there is a high dielectric constant insulating material. It is preferable that a body is provided. Similarly, conductors included in capacitance C2 and capacitance C3 It is preferable that an insulator with a high dielectric constant is provided between the BGM and the conductor SDM. .

[0346] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0347] (Embodiment 3) In this embodiment, a display device is provided that combines a semiconductor device according to one aspect of the present invention with a display unit. This section describes an example of a configuration.

[0348] Figure 18 is a schematic cross-sectional view of a display device according to one embodiment of the present invention. The display device 10 has a pixel layer P It has XAL, a wiring layer LINL, and a circuit layer SICL.

[0349] The wiring layer LINL is provided on the circuit layer SICL, and the pixel layer PXAL is located on the wiring layer LINL It is located above.

[0350] The circuit layer SICL consists of the substrate BS, the drive circuit area DRV, and the functional circuit area MFNC. To possess.

[0351] The substrate BS may include, for example, a semiconductor substrate made of silicon or germanium (for example, A single-crystal substrate can be used. In addition, the substrate BS can be, for example, a semiconductor substrate. For example, SOI (Silicon On Insulator) substrates, glass substrates, quartz substrates Plates, plastic substrates, sapphire glass substrates, metal substrates, stainless steel substrates, Substrates with stainless steel foil, tungsten substrates, and tungsten foil Substrates, flexible substrates, laminated films, paper containing fibrous materials, or base film A glass substrate can be used. For example, barium borosilicate glass. Examples include aluminoborosilicate glass or soda-lime glass. Flexible substrate, bonded Examples of laminated films and base films include, for example, polyethylene terephthalate. PET, polyethylene naphthalate (PEN), polyethersulfone (PES) Examples include plastics, such as polytetrafluoroethylene (PTFE). Alternatively, as an example, synthetic resins such as acrylic resin can be cited. Alternatively, as an example, Examples include polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Alternatively, as an example, polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition. Examples include films or papers. Note that the manufacturing process of the display device 10 includes heat treatment. If this is the case, it is preferable to use a material with high heat resistance for the substrate BS.

[0352] For example, if the substrate BS is a semiconductor substrate having silicon as its material, the drive circuit area The transistors included in the DRV region and the MFNC functional circuit region are Si transistors. It is possible.

[0353] Furthermore, for example, if the substrate BS is a glass substrate, the drive circuit area DRV and the functional circuit The transistors included in region MFNC can be OS transistors.

[0354] The drive circuit area DRV and the function circuit area MFNC are located on the substrate BS.

[0355] The drive circuit region DRV, as an example, drives pixels included in the pixel layer PXAL, which will be described later. It has a drive circuit for this purpose. For specific configuration examples of the drive circuit region DRV, see below. More details will follow.

[0356] One example of a functional circuit area (MFNC) is a GPU (Graphics Processor). The display device 10 may also include a touch panel. If so, the functional circuit area MFNC contains the touch sensor included in the touch panel. A sensor controller that controls the display elements of the display device 10 may also be included. When an EL material is used in a light-emitting device, the functional circuit area MFNC It may include an EL correction circuit. Also, liquid crystal elements may be used as the display elements of the display device 10. If this is applied, the functional circuit region MFNC may include a gamma correction circuit. stomach.

[0357] The wiring layer LINL is located on top of the circuit layer SICL.

[0358] The wiring layer LINL has wiring. Furthermore, the wiring included in the wiring layer LINL is, for example, The drive circuit included in the drive circuit region DRV located below the wiring layer LINL, and the wiring layer Wiring that electrically connects the circuitry included in the pixel layer PXAL, which is located above LINL. It functions as such.

[0359] The pixel layer PXAL has, for example, multiple pixels. Furthermore, the multiple pixels are located in the pixel layer P In XAL, they may be arranged in a matrix.

[0360] Furthermore, each of multiple pixels can represent one or more colors. In particular, multiple For example, the colors could be red (R), green (G), and blue (B). To make it. Or, as multiple colors, for example, red (R), green (G), and blue (B), Furthermore, two or more colors selected from cyan, magenta, yellow, and white may also be used. Each pixel that represents a color is called a subpixel, and white is represented by multiple subpixels of different colors. When representing them, multiple subpixels are sometimes collectively referred to as pixels. In this specification, for convenience, For the purposes of this explanation, we will refer to subpixels simply as pixels.

[0361] Figure 19 is a block diagram showing an example configuration of the display device 10 shown in Figure 18. The display device 10 shown, as an example, includes a display unit DIS and a circuit unit SIC. Figure 19 shows the sensor PDA, which is located inside the display device 10. It may be placed inside, or it may be located outside.

[0362] In Figure 19, thick solid lines represent multiple wires or bus wiring.

[0363] In Figure 19, the display unit DIS has, as an example, multiple pixel circuits PX arranged in a matrix. It is arranged. The pixel circuit PX includes, for example, a liquid crystal display device and an organic EL material. Selected from light-emitting devices, including light-emitting diodes such as microLEDs. A pixel circuit to which one or more are applied can be used. In this embodiment, the display unit DI It is explained that the pixel circuit PX of S is fitted with a light-emitting device containing organic EL material. To clarify. Furthermore, regarding the pixel circuits that can be applied to the display unit DIS, pixel circuit PX, etc., implementation This will be explained in detail in Form 4.

[0364] Furthermore, in Figure 19, the circuit section SIC consists of a drive circuit area (DRV) and a function circuit area (MFN). It has C and

[0365] The drive circuit area DRV is, for example, a peripheral circuit for driving the display unit DIS. It works. Specifically, the drive circuit area DRV is, for example, the source driver circuit 11, digital It includes a cascading analog conversion circuit 12, a gate driver circuit 13, and a level shifter 14. The source driver circuit 11 corresponds, for example, to the drive circuit SD in Figure 2, and also, The gate driver circuit 13 corresponds, for example, to the drive circuit GD in Figure 2.

[0366] Furthermore, the functional circuit area MFNC is used, for example, to display image data on the display unit DIS. A storage device where the data is stored, and a decoder for restoring the encoded image data. , GPU (Graphics Processing Unit) for processing image data It) can be provided with circuits such as a power supply circuit, a correction circuit, or a CPU. Figure 19 shows In this context, the functional circuit area MFNC includes, as an example, a memory device 21 and a GPU (AI-accelerated Data 22, EL correction circuit 23, timing controller 24, CPU (NoffCPU) It has (registered trademark) 25, a sensor controller 26, and a power supply circuit 27.

[0367] Furthermore, the display device 10 in Figure 19 includes circuits included in the drive circuit area DRV, and the functional circuit area Each of the circuits included in the MFNC region is electrically connected to a bus wiring BSL, for example. It is configured in this way.

[0368] As an example, the source driver circuit 11 controls the pixel circuit PX included in the display unit DIS. It has the function of transmitting image data. Therefore, the source driver circuit 11 has wiring S It is electrically connected to the pixel circuit PX via L.

[0369] The digital-to-analog conversion circuit 12, for example, uses a GPU, correction circuit, etc., as described later. It has the function of converting digitally processed image data into analog data. The converted image data is transmitted to the display unit DIS via the source driver circuit 11. The digital-to-analog conversion circuit 12 is included in the source driver circuit 11. Alternatively, the source driver circuit 11, the digital-to-analog conversion circuit 12, and the display unit DIS may be The system may also be configured so that image data is transmitted sequentially.

[0370] The gate driver circuit 13, as an example, determines the destination of image data transmission in the display unit DIS. It has the function of selecting the pixel circuit PX which is such that the gate driver circuit 13 is It is electrically connected to the pixel circuit PX via line GL.

[0371] The level shifter 14 is, for example, a source driver circuit 11, a digital-to-analog conversion circuit Converts the signals input to the path 12, gate driver circuit 13, etc., to an appropriate level. It has a function.

[0372] The storage device 21, for example, has a function to store image data to be displayed on the display unit DIS. It has. The storage device 21 stores the image data as digital data or analog data. It can be configured to save data.

[0373] Furthermore, when saving image data to the storage device 21, the storage device 21 is a non-volatile memory device. It is preferable to use a NAND type memory. In this case, the storage device 21 may be, for example, a NAND type memory. These can be applied.

[0374] Furthermore, temporary data generated by the GPU 22, EL correction circuit 23, CPU 25, etc., is stored in the memory device 21. When saving data, it is preferable to use volatile memory as the storage device 21. In total, the storage device 21 is, for example, SRAM (Static Random Accelerator). ss Memory), DRAM (Dynamic Random Access Me You can apply mory, etc.

[0375] As an example, the GPU22 processes the image data read from the storage device 21 into the display unit DI. It has the functionality to perform processing for drawing to S. In particular, GPU22 performs parallel pipeline Because it is configured to perform processing, it processes image data to be displayed on the display unit DIS at high speed. It can do this. Also, GPU22 is a decoder for restoring encoded images. It can also function as such.

[0376] Furthermore, the functional circuit area MFNC includes a circuit that can improve the display quality of the display unit DIS. Multiple such elements may be included. For example, the circuit may include an image displayed on the display unit DIS. A correction circuit (color adjustment or brightness adjustment) detects color unevenness and corrects it to produce an optimal image. A circuit for correcting the error may be provided. In addition, an organic EL display may be used for the pixels of the display unit DIS. Even if an optical device is applied, an EL correction circuit may be provided in the functional circuit region (MFNC). Good. The brightness emitted by a light-emitting device using organic EL material is determined by the flow of light into the light-emitting device. It is determined by the amount of current drawn. Therefore, the light-emitting device depends on the transistor characteristics, etc. When the amount of current flowing through it changes, the brightness of the light-emitting device also changes unintentionally. The L correction circuit measures the amount of current flowing through the light-emitting device and compares it with the desired amount of current. Furthermore, it has a function to adjust the amount of current flowing to the light-emitting device when necessary. This allows the brightness emitted by the light-emitting device to be adjusted appropriately. In this embodiment, the table The pixel circuit PX of the display unit DIS is fitted with a light-emitting device containing organic EL material. As explained above, the functional circuit area MFNC includes, for example, the EL correction circuit 23. It includes it.

[0377] Furthermore, artificial intelligence may be used for the image correction described above. For example, if pixels are equipped with The current flowing through the display device (or the voltage applied to the display device) is monitored. The image is acquired by an image sensor or similar device, and the current (or The voltage and the image are input data for artificial intelligence calculations (e.g., artificial neural networks). It may be treated as data, and the output result may be used to determine whether or not the image has been corrected.

[0378] Furthermore, artificial intelligence calculations are used not only for image correction but also for upconversion processing of image data. This can also be applied to the resolution of the display unit DIS for low-resolution image data. By performing upconversion according to the degree, high-quality images are displayed on the DIS display unit. It can be demonstrated. Furthermore, artificial intelligence calculations can be used for down-converting image data. This can also be applied.

[0379] Furthermore, the GPU22 included in the functional circuit area MFNC is used for the calculations of the artificial intelligence described above. This can be done by using GPU22 to perform various correction calculations (such as correcting color unevenness). Circuits 22a and upconversion processing circuits 22b can be performed.

[0380] In this specification, a GPU that performs artificial intelligence calculations is referred to as an AI accelerator. In other words, in this specification, the GPU provided in the functional circuit area MFNC is referred to as an AI A It is sometimes explained by substituting "accelerator".

[0381] The timing controller 24, as an example, displays an image on the display unit DIS. It has a function to vary the display rate. For example, when displaying a still image on the display unit DIS, The display device 10 is driven by the timing controller 24, which reduces the frame rate. It is possible to do so, and for example, when displaying a video on the display unit DIS, the display device 10 can The timing controller 24 can be used to increase the frame rate. Furthermore, by providing a timing controller 24 to the display device 10, still images, or The frame rate can be changed depending on the video. In particular, still images can be displayed on the DIS display unit. When displaying, the frame rate can be reduced, so the display device 1 It is possible to reduce power consumption to zero.

[0382] CPU25, for example, is used for running the operating system, controlling data, and various other tasks. It has functions for general-purpose processing such as calculations and program execution. The CPU 25 performs, for example, write or read image data from the storage device 21. This function is responsible for issuing commands such as outputting data, correcting image data, or controlling sensors (as described later). It has a memory device, a GPU, a correction circuit, and a timing controller. Selected from circuits included in the functional circuit area (MFNC), such as tracers and high-frequency circuits. It may also have a function to transmit one or more control signals.

[0383] Furthermore, CPU25 has a circuit that temporarily backs up data (hereinafter referred to as the backup circuit). It may have a backup circuit (referred to as a path). The backup circuit may, for example, when the power supply voltage is stopped. Even if so, it is preferable that the data can be retained. For example, the display unit DIS When a still image is displayed, CPU25 will continue to operate until it displays an image different from the current still image. The function can be stopped. Therefore, the data being processed by CPU25 is backed up by a backup circuit. It is temporarily moved to a remote location, and then the power supply voltage to CPU25 is stopped, and CPU25 By stopping it, the dynamic power consumption of CPU25 can be reduced. Furthermore, in this specification, a CPU having a backup circuit will be referred to as a NoffCPU.

[0384] The sensor controller 26, for example, has the function of controlling the sensor PDA. Figure 19 shows the wiring for electrically connecting the sensor PDA and the sensor controller 26. The wiring SNCL is shown in the diagram.

[0385] As a sensor PDA, for example, it could be located above, below, or inside the display unit DIS. It can be used as a touch sensor that can be equipped with [something].

[0386] Alternatively, the sensor PDA can be, for example, an illuminance sensor. In particular, the display unit By acquiring the intensity of ambient light illuminating the DIS using an illuminance sensor, the display adjusts according to the ambient light. The brightness (luminance) of the image displayed on the DIS can be changed. For example, the ambient light is bright. In such cases, the brightness of the image displayed on the display unit DIS is increased to improve the visibility of the image. This is possible. Conversely, if the ambient light is dim, the brightness of the image displayed on the DIS display unit will be lowered, and the image will disappear. It can reduce power consumption.

[0387] Alternatively, the sensor PDA could be, for example, an image sensor. For example, By acquiring images using the image sensor, the display unit DIS displays the images. It can be shown.

[0388] The power supply circuit 27 is, for example, a circuit included in the drive circuit area DRV, and a functional circuit area. Power supplied to circuits included in MFNC, pixels included in the display unit DIS, etc. It has the function of generating pressure. Furthermore, the power supply circuit 27 has the function of selecting the circuit to supply voltage. It may have a power supply circuit 27 during the period when a still image is displayed on the display unit DIS. So, by stopping the voltage supply to CPU25, GPU22, etc., the display... The overall power consumption of the device can be reduced.

[0389] <Example of image sensor configuration> This section describes an image sensor that can be used in the sensor PDA of the display device 10. explain.

[0390] An example of an image sensor applicable to a sensor PDA is the imaging device I shown in Figure 20. You can use M.

[0391] Figure 20 is a block diagram showing an example of the circuit configuration of the imaging device IM. The imaging device IM is Imaging unit 31, first drive circuit unit 33, second drive circuit unit 34, readout circuit unit 35, and control It is equipped with a control circuit section 36. Furthermore, it includes a first drive circuit section 33, a second drive circuit section 34, and a readout circuit. The term "functional circuit" is sometimes used to refer collectively to section 35 and the control circuit section 36. This includes shift registers, level shifters, inverters, latches, analog switches, or logic Various circuits, such as logic circuits, can be used.

[0392] The transistors used in the imaging unit 31 and functional circuit of the imaging device IM are n-channel. It may be a type transistor or a p-channel transistor. Both p-channel transistors and p-channel transistors may be used. Imaging unit 31 and The functional circuit combines n-channel and p-channel transistors. An OS structure configuration may also be used.

[0393] The imaging unit 31 is arranged in a matrix of m rows and n columns (where m and n are integers of 1 or more). It is equipped with arranged imaging pixels 32. The imaging unit 31 is connected to a first drive circuit via a plurality of wires 41. It is electrically connected to part 33. In addition, the imaging unit 31 reads out via multiple wires 42. It is electrically connected to the track section 35. The readout circuit section 35 is connected to the second drive via a plurality of wires 43. It is electrically connected to the dynamic circuit section 34. For example, row i (where i is an integer between 1 and m) The imaging pixel 32 located in (a number) is driven by the i-th wiring 41 in the first drive cycle. It is electrically connected to the circuit section 33. Also, the j-th column (where j is an integer between 1 and n, inclusive) The imaging pixel 32 located in ( ) is read out via the j-th wiring 42 to the readout circuit 35 It is electrically connected to it.

[0394] In Figure 20, the imaging pixel 32 located in the first row and first column is shown as imaging pixel 32[1,1]. The image pixel 32 located at the mth row and nth column is denoted as image pixel 32[m,n]. Also, i The image pixel 32 located in the jth row and jth column is denoted as image pixel 32[i,j].

[0395] Note that the wiring connected to a single image sensor 32 is not limited to wiring 41 and wiring 42. Other wiring besides wiring 41 and wiring 42 may be connected to the image pixel 32.

[0396] Furthermore, the pixel density (also called "resolution") of the imaging unit 31 is 100 ppi or more and 1000 ppi. A value of 0 ppi or less is preferred, and a value of 1000 ppi or more and 10000 ppi or less is more preferred. Example For example, the resolution could be between 2000ppi and 6000ppi, or 3000ppi. It may be between pi and 5000ppi.

[0397] There are no particular limitations on the aspect ratio of the imaging unit 31. Imaging device I The imaging unit 31 of M can handle various aspect ratios, such as 1:1 (square), 4:3, 16:9, 16:10, etc. It can handle various aspect ratios.

[0398] The diagonal size of the imaging unit 31 may be between 0.1 inches and 100 inches. Or, Depending on the situation, a screen size of 100 inches or larger may be acceptable.

[0399] The control circuit unit 36 ​​has the function of controlling the operation of the circuits provided by the imaging device IM. The drive circuit unit 33 has a function to select the image pixel 32 for each row. The selected row's imaging pixel 32 reads the imaging data via wiring 42 to the readout circuit 3 Output to 5.

[0400] The readout circuit 35 holds the imaging data supplied from the imaging pixels 32 for each column, Noise reduction processing is performed. For example, CDS (Correlat) is used as a noise reduction process. Even if you perform processes such as double sampling (correlated double sampling), Good. Also, the readout circuit 35 has a function to amplify the imaging data, or an analog function for the imaging data. It may also be equipped with a digital conversion function.

[0401] The second drive circuit 34 sequentially selects the imaging data held in the readout circuit 35. It also has a function to output the image data to an external device via the OUT output terminal.

[0402] First drive circuit section 33, second drive circuit section 34, readout circuit section 35, and control circuit section 36 One or more selected from these include, for example, Figure 3(A) or Figure 3(B) described in Embodiment 1. A shift register may be provided. In addition, the circuit 100[1] to the shift register may be provided. As for the path 100 [m], for example, the circuit described in Configuration Examples 1 to 8 of Embodiment 1. You may also apply 100A1 or similar.

[0403] <Example of circuit configuration for imaging pixels> Figure 21(A) is a circuit diagram illustrating an example of the circuit configuration of the imaging pixel 32. The imaging pixel 32 is , photoelectric conversion device PHD (also called "photoelectric conversion element" or "image sensor") and tra Transistor Tr1, Transistor Tr2, Transistor Tr3, Transistor Tr4 And, it is equipped with a capacity CA. However, a configuration without a capacity CA is also possible. In this case, the configuration excluding the photoelectric conversion device (PHD) from the above elements is called the "imaging pixel circuit." There are cases where this is the case.

[0404] One electrode (cathode) of the photoelectric conversion device PHD is connected to the source of transistor Tr1. It is electrically connected to one of the drains or source of transistor Tr1. The other end is electrically connected to either the source or the drain of transistor Tr2. Either the source or drain of the transistor Tr2 is electrically connected to one electrode of the capacitor CA. The process continues. One electrode of capacitance CA is electrically connected to the gate of transistor Tr3. Either the source or drain of transistor Tr3 is connected to the source of transistor Tr4. It is electrically connected to one of the drains.

[0405] Here, the source or drain of transistor Tr1, and one electrode of capacitance CA, Let node FD be the electrical connection point with the gate of transistor Tr3. Node FD is a charge It can function as a detection unit.

[0406] The other electrode (anode) of the photoelectric conversion device PHD is electrically connected to the wiring POW1. The gate of transistor Tr1 is electrically connected to wiring SEL2. The source or drain of Tr2 is electrically connected to wiring POW2. The source or drain of Tr3 is electrically connected to wiring POW3. The gate of transistor Tr2 is electrically connected to wiring SEL1. Transistor Tr4 The gate of the capacitor is electrically connected to wiring SEL3. The other electrode of the capacitor CA is connected, for example, GN It is electrically connected to a reference potential line such as a D wiring. Source or drain of transistor Tr4 The other end of the input is electrically connected to the wiring output transformer (OPT).

[0407] Wiring SEL2, SEL1, and SEL3 control the on / off state of each transistor. It functions as a control signal line. The wiring OPT functions as an output line.

[0408] Wires POW1, POW2, and POW3 function as power lines. (Figure 21) The imaging pixel 32 shown in (A) has the cathode of the photoelectric conversion device PHD connected to transistor Tr1 The configuration involves an electrical connection, and the imaging operation can be performed by resetting the node FD to a high potential. This configuration allows for high potential. Therefore, wiring POW2 is at a high potential (higher potential than wiring POW1). Let's assume that.

[0409] In Figure 21(A), the cathode of the photoelectric conversion device PHD is electrically connected to node FD. The connection configuration is shown, but the anode of the photoelectric conversion device PHD is connected to the base of transistor Tr1. The configuration may also involve an electrical connection to either the drain or the socket. In this case, node F The configuration allows imaging to be performed by resetting D to a low potential, so wiring POW2 It should be at a low potential (lower than the potential of wiring POW1).

[0410] Transistor Tr1 has the function of controlling the potential of node FD. Transistor 1 is also called a "transfer transistor". Transistor Tr2 resets the potential of node FD. It has the function of resetting. Transistor Tr2 is also called the "reset transistor". Zistar Tr3 functions as a source follower circuit, taking the potential of node FD as imaging data. The output can be routed to the OPT. Transistor Tr4 outputs the image data to the pixel. It has a selection function. Transistor Tr3 is also called an "amplifying transistor". The 4-tube transistor is also called a "selection transistor."

[0411] Furthermore, as shown in Figure 21(B), the photoelectric conversion device PHD and transistor Tr1 are connected. As a set, multiple sets of photoelectric conversion devices PHD and transistor Tr1 are connected to node FD. This may also be the case. According to the circuit configuration shown in Figure 21(B), the occupied area per image pixel 32 This can reduce the amount of data. Therefore, the mounting density of the imaging pixels 32 can be increased.

[0412] In Figure 21(B), the first pair of photoelectric conversion devices PHD and transistor Tr1 are shown as photoelectric conversion The replacement device is shown as PHD_1, and the transistor as Tr1_1. The gate is electrically connected to wiring SEL2_1. Also, the second set of photoelectric conversion devices P HD and transistor Tr1, photoelectric conversion device PHD_2, transistor Tr1_2 and This shows that the gate of transistor Tr1_2 is electrically connected to wiring SEL2_2. Furthermore, the kth set (where k is an integer greater than or equal to 1) of photoelectric conversion devices PHD and transistor Tr1 This indicates the photoelectric conversion device PHD_k and the transistor Tr1_k. The gate of r1_k is electrically connected to the wiring SEL2_k.

[0413] For example, all transistors included in an imaging device (IM) can be manufactured using the same process.

[0414] Furthermore, the functional circuits included in the imaging device IM are equipped with all the configurations shown in this embodiment. It is not necessary, and other configurations are also acceptable.

[0415] <Example configuration of display device and imaging device> Next, the configuration of the display device 10, in which the display device and the imaging device are integrated, will be described.

[0416] Figure 22 shows the pixel array PA, source driver circuit 11, and gate driver shown in Figure 19. A display device including circuit 13 (hereinafter referred to as display device DS) and the imaging device shown in Figure 21 This shows the configuration of the display device 10, which is a combination of an IM and a device.

[0417] In Figure 22, multiple wires 41 are referred to as wires 41[1] to 41[m], and multiple A single wire 42 is denoted as wire 42[1] to wire 42[n], and multiple wires 43 are denoted as wire 43 [1] Or it is written as wiring 43[n].

[0418] In Figure 22, as an example, the second drive circuit section 34 and the source driver circuit 11 are connected by wiring 4. They are electrically connected by wiring 4[1] to 44[n].

[0419] The imaging data read out by the readout circuit 35 is, for example, read out by wiring 43[1] via wiring 43[n], second drive circuit section 34, and wiring 44[1] to wiring 44[n] The data is then sent to the source driver circuit 11.

[0420] Therefore, the source driver circuit 11 receives the voltage of the imaging data supplied from the imaging device IM. It may also have functions for adjustment, polarity conversion, and power amplification. In other words, source drivers The IBA circuit 11 may also have a function to convert the imaging data into an image signal. - The driver circuit 11 outputs the image signal converted from the imaging data to the pixel array PA. It is possible.

[0421] With this configuration, the imaging data acquired by the imaging unit 31 is transmitted by the source driver circuit 11. This allows for the conversion of the image signal into one more suitable for display on a pixel array PA. For example, it is possible to realize a display device that is less susceptible to noise and has good display quality.

[0422] Furthermore, the display device 10 described above has a pixel array PA and an imaging unit 31 on the same array. The arrangement may also be as follows. For example, as shown in Figure 23, the display device 10 is the same A configuration in which pixel circuits and imaging circuits are arranged in the array may also be used.

[0423] The display device 10 shown in Figure 23 has a cell array AY, and the circuit CE[1,1] to the circuit This shows a configuration in which CE[m,n] is arranged in an m x n matrix. Also, i When I is an integer between 1 and m and j is an integer between 1 and n, the circuit CE[i,j] is For example, it has a pixel circuit PX[i,j] and an imaging pixel 32[i,j]. In Figure 23, only circuits CE[1,1] and CE[m,n] are marked in the cell array AY. This is illustrated as a number.

[0424] As shown in Figure 23, the display device 10 has a pixel circuit PX and an imaging pixel 32 which are the same By arranging them in a ray configuration, the entire display area can be used as a sensor area. For example, if imaging pixels 32[1,1] to 32[m,n] capture the user's finger... By doing so, the display device 10 can be equipped with a fingerprint authentication function. Pixels 32[1,1] to imaging pixels 32[m,n] continuously capture images of the user's finger. Therefore, the display device 10 or the electronic device equipped with the display device 10 recognizes the user's finger movements. It is possible to do so. In addition, the display device 10 or the electronic device equipped with the display device 10 can use the user's finger Depending on the movement, various actions will be performed (for example, zooming in or zooming out of the image, the display of the image, etc.). It may also have a function to perform actions such as rolling. In other words, the display device 10 has a touch panel and It may also have the following functions.

[0425] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0426] (Embodiment 4) In this embodiment, the present invention relates to a display device that can be provided in an electronic device according to one aspect of the present invention. Let me explain. The display unit DIS described in the above embodiment is as described in this embodiment. A display device can be applied.

[0427] <Example of display device configuration> Figure 24 is a cross-sectional view showing an example of a display device according to one aspect of the present invention. The device 1000, as an example, has a configuration in which a pixel circuit and a drive circuit are provided on a substrate 310. The above-described embodiment includes the display device DSP, the display device 10, etc. The configuration can be that of the display device 1000 shown in Figure 24.

[0428] Specifically, for example, the circuit layer SICL, the wiring layer LINL, and the pixels shown in the display device 10. The PXAL layer can be configured as shown in the display device 1000 in Figure 24. SICL, as an example, has a substrate 310, on which a transistor 300 is located. It is formed. Furthermore, a wiring layer LINL is provided above the transistor 300. The wiring layer LINL contains transistor 300, transistor 200 (described later), and (described later) Wiring is provided for electrically connecting light-emitting devices 150a, 150b, etc. Furthermore, above the wiring layer LINL, the pixel layer PXAL is provided, and the pixel layer PX AL, as an example, consists of a transistor 200 and a light-emitting device 150 (in Figure 24, the light-emitting device...). It includes a vice 150a and a light-emitting device 150b, etc.

[0429] For example, the substrate 310 can be a substrate that can be applied to the substrate BS described above. This is possible. Furthermore, if heat treatment is included in the manufacturing process of the display device 1000, the substrate For 310, it is preferable to select a material with high heat resistance.

[0430] In this embodiment, the substrate 310 is a semiconductor substrate having silicon as its material. I will explain.

[0431] The transistor 300 is provided on the substrate 310, and includes an element isolation layer 312, a conductor 316, Insulator 315, insulator 317, semiconductor region 313 consisting of a part of the substrate 310, source region Alternatively, it has a low-resistance region 314a and a low-resistance region 314b that function as drain regions. Therefore, transistor 300 is a Si transistor. Note that in Figure 24... The source or drain of transistor 300 is connected via the conductor 328, which will be described later. A configuration in which the conductors 330, 356, and 366 described later are electrically connected. While this is shown, the electrical connection configuration of a semiconductor device according to one aspect of the present invention is not limited thereto. i. A semiconductor device according to one aspect of the present invention, for example, the gate of transistor 300 is a conductor 3 The conductors 330, 356, and 366 are electrically connected via 28. This configuration is also acceptable.

[0432] For example, the transistor 300 has a top surface and a side surface in the channel width direction of the semiconductor region 313. The configuration is such that the conductor 316 is covered via an insulator 315 that functions as a gate insulating film. This allows for a Fin-type configuration. Making transistor 300 a Fin-type configuration. This allows for an increase in the effective channel width and improves the on-characteristics of transistor 300. This can be increased. Also, the contribution of the electric field of the gate electrode can be increased, This can improve the off-road characteristics of the Rangista 300.

[0433] Note that transistor 300 can be either a p-channel or n-channel type. Alternatively, multiple transistors 300 can be provided, and both p-channel and n-channel types can be used. That's fine.

[0434] The region in which the channel of the semiconductor region 313 is formed, the region near it, the source region, or The low-resistance regions 314a and 314b, which constitute the rain region, are, for example, silicon-based It is preferable that it contains semiconductors, and more preferably that it contains single-crystal silicon. These are germanium (Ge), silicon germanium (SiGe), and gallium arsenide (GaA). s), containing aluminum gallium arsenide (GaAlAs), or gallium nitride (GaN) It may be formed from a material. Also, the transistor 300 is connected to each of the above-mentioned regions. This silicon uses a structure in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, the transistor 300 may be composed of gallium arsenide and aluminum arsenide. A HEMT (High Electron Mobility Tr) using lium. You can also use "ansistor."

[0435] The conductor 316, which functions as a gate electrode, is made of n-type materials such as arsenic or phosphorus. Silicon containing elements that impart conductivity, or elements that impart p-type conductivity such as boron Semiconductor materials such as CON can be used. In addition, metal materials and alloys can be used for the conductor 316. Conductive materials such as materials or metal oxide materials can be used.

[0436] Furthermore, since the work function is determined by the material of the conductor, the material of the conductor must be selected accordingly. This allows you to adjust the threshold voltage of the transistor. Specifically, by using nitride in the conductor... It is preferable to use materials such as tan or tantalum nitride. Furthermore, conductivity and embedding are also important. To achieve both properties, the aforementioned conductor is made of metal material such as tungsten or aluminum. It is preferable to use the material in a laminated form, and in particular, using tungsten is preferable in terms of heat resistance. It seems so.

[0437] The element isolation layer 312 separates multiple transistors formed on the substrate 310. It is provided for this purpose. The element isolation layer is, for example, LOCOS (Local Oxide). tion of Silicon) method, STI (Shallow Trench Iso It can be formed using methods such as the lation method and the mesa separation method.

[0438] Note that the transistor 300 shown in Figure 24 is just one example, and its structure is not limited to that example. A suitable transistor can be used depending on the configuration and driving method. For example, transistor 3 00 may have a planar structure instead of a fin structure.

[0439] The transistor 300 shown in Figure 24 has insulators 320, 322, and 324. The insulators 326 are arranged in layers starting from the substrate 310 side.

[0440] As insulators 320, 322, 324, and 326, for example, oxidative Silicon, silicon oxide nitride, silicon nitride, silicon nitride, aluminum oxide, acid Aluminum nitride, aluminum nitride oxide, or aluminum nitride may be used.

[0441] The insulator 322 is located on the transistor 300, which is covered by the insulators 320 and 322. It may also function as a planarizing film that flattens the resulting step. For example, insulation. The upper surface of body 322 is chemically mechanically polished (CMP) to improve flatness. The surface is flattened by a planar treatment using methods such as mechanical polishing. It's okay to be there.

[0442] Furthermore, the insulator 324 is made from the substrate 310 or the transistor 300, etc. Region above 4 (for example, transistor 200, light-emitting device 150a, light-emitting device) To prevent the diffusion of impurities such as water and hydrogen into areas such as 150b It is preferable to use a barrier insulating film. Therefore, the insulator 324 is composed of hydrogen atoms, hydrogen It has the function of suppressing the diffusion of impurities such as molecules and water molecules (the above impurities do not easily permeate). It is preferable to use an insulating material. Also, depending on the situation, the insulator 324 may be nitrogen source The atoms include nitrogen molecules, nitrogen oxide molecules (e.g., N2O, NO, and NO2), and copper atoms. An insulating material is used that has the function of suppressing the diffusion of impurities (i.e., the above oxygen does not easily permeate it). This is preferable. Alternatively, the oxygen (e.g., oxygen atoms and / or oxygen molecules) may be expanded. It is preferable that the material has a function to suppress dispersion.

[0443] As an example of a film with hydrogen barrier properties, silicon nitride formed by CVD is used. It is possible to be there.

[0444] The amount of hydrogen desorbed can be analyzed, for example, using a thermal desorption gas analysis method (TDS). For example, the amount of hydrogen desorption from insulator 324 is determined in TDS analysis when the film surface temperature is 5 In the range of 0°C to 500°C, the amount of desorption converted to hydrogen atoms is per unit area of ​​insulator 324. Convert to units, 10 x 10 15 atoms / cm 2 The following is preferably 5 × 10 15 at oms / cm 2 The following is acceptable.

[0445] Furthermore, it is preferable that the dielectric constant of the insulator 326 is lower than that of the insulator 324. For example, The relative permittivity of the edge material 326 is preferably less than 4, and more preferably less than 3. Also, for example, an insulator... The relative permittivity of 326 is preferably 0.7 times or less, and preferably 0.6 times or less, than the relative permittivity of the insulator 324. This is more preferable. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between the wiring is reduced. It can be reduced.

[0446] Furthermore, insulators 320, 322, 324, and 326 are insulator 3 A conductor 328 connected to a light-emitting device or circuit element located above 26, and Conductors 328 and 330 are embedded. Or it functions as wiring. Also, a conductive material that functions as a plug or wiring is In some cases, multiple structures may be grouped together and assigned the same reference numeral. Also, in this specification, etc., The wire and the plug that connects to the wiring may be a single unit. That is, a part of the conductor may be the wiring. In some cases, it functions as a plug, and in other cases, part of the conductor functions as a plug.

[0447] The material for each plug and wiring (for example, conductor 328 and conductor 330) is gold. Conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials are applied in a single layer or It can be used in a stacked configuration. Materials such as tungsten and molybdenum offer both heat resistance and conductivity. It is preferable to use a high melting point material, and it is preferable to use tungsten. Alternatively, A It is preferable to form it with a low-resistance conductive material such as aluminum or copper. By using it, wiring resistance can be reduced.

[0448] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, as shown in Figure 24. And insulator 350, insulator 352, and insulator 354 are insulator 326, and conductor 3 They are arranged in a sequential stack above 30. Also, insulator 350, insulator 352, and A conductor 356 is formed on the insulator 354. The conductor 356 is connected to the transistor 30 It functions as a plug or wiring that connects to 0. Note that conductor 356 is conductor 32 8. It can be provided using the same material as the conductor 330.

[0449] For example, insulator 350, like insulator 324, is resistant to hydrogen, oxygen, and water. It is preferable to use an insulator having barrier properties. Also, insulator 352 and insulator 35 4. Similar to the insulator 326, the relative dielectric is used to reduce parasitic capacitance between the wires. It is preferable to use an insulator with a relatively low ratio. Also, insulator 362 and insulator 364 It functions as an interlayer insulating film and a planarizing film. In addition, the conductor 356 is hydrogen, acid It is preferable that the material contains a conductor that has barrier properties against water.

[0450] For example, tantalum nitride can be used as a conductor that has barrier properties against hydrogen. This is good. Also, by laminating tantalum nitride and highly conductive tungsten, the wiring can be This allows for the suppression of hydrogen diffusion from transistor 300 while maintaining conductivity. In this case, the tantalum nitride layer having barrier properties against hydrogen provides a barrier against hydrogen. It is preferable that the structure is in contact with the insulator 350.

[0451] Furthermore, on the insulator 354 and the conductor 356, there is an insulator 360, an insulator 362, and an insulating layer. The edge units 364 are stacked in order.

[0452] Insulator 360, like insulator 324, is resistant to impurities such as water and hydrogen. It is preferable to use an insulator that has rear properties. Therefore, as the insulator 360, for example If so, materials applicable to insulator 324 and the like can be used.

[0453] Insulators 362 and 364 have functions as an interlayer insulating film and a planarizing film. Furthermore, insulators 362 and 364, like insulator 324, are insoluble in water and hydrogen. It is preferable to use an insulator that has barrier properties against impurities. One or both of the insulators 362 and 364 may be made of a material applicable to the insulator 324. It is possible to be there.

[0454] Furthermore, the conductive material 356 of each of the insulators 360, 362, and 364 An opening is formed in the region that overlaps with a part of it, and a conductor 366 is provided to fill the opening. It is also formed on the insulator 362. Conductor 36 6, for example, functions as a plug or wire for connecting to transistor 300. Furthermore, the conductor 366 is provided using the same material as the conductors 328 and 330. It is possible.

[0455] Insulator 364 and conductor 366 are stacked in order on insulator 370 and insulator 372. It is layered.

[0456] Insulator 370, like insulator 324, is resistant to impurities such as water or hydrogen. It is preferable to use an insulator that has rear properties. Therefore, as the insulator 370, for example If so, materials applicable to insulator 324 and the like can be used.

[0457] The insulator 372 has the function of an interlayer insulating film and a planarizing film. 2, like insulator 324, has barrier properties against impurities such as water and hydrogen. It is preferable to use an edge material. For this reason, the insulator 372 is applicable to the insulator 324. Materials that can be cut can be used.

[0458] Furthermore, the insulators 370 and 372 are superimposed on a portion of the conductor 366. An opening is formed in the region, and a conductor 376 is provided to fill the opening. Furthermore, the conductor 376 is also formed on the insulator 372. After that, etching treatment Depending on the method, the conductive material 376 is patterned into the shapes of wires, terminals, pads, etc.

[0459] The conductive material 376 may be, for example, copper, aluminum, tin, zinc, tungsten, silver, platinum, Alternatively, gold can be used. Note that the conductor 376 is included in the pixel layer PXAL, which will be described later. It is preferable that the material used in the conductive material 216 is composed of the same components as the material used in the conductive material 216. .

[0460] Next, an insulator 380 is formed to cover the insulator 372 and the conductor 376, and then, Planarization treatment using chemical mechanical polishing (CMP) or the like is performed until the conductor 376 is exposed. This allows the conductive material 376 to be formed on the substrate 310 as wiring, terminals, or pads. It is possible.

[0461] Insulator 380, for example, like insulator 324, can contain impurities such as water and hydrogen. It is preferable to use a film that has barrier properties to prevent dispersion. In other words, the insulator 380 It is preferable to use a material that can be applied to the insulator 324. Alternatively, for the insulator 380, for example, For example, similar to insulator 326, in order to reduce parasitic capacitance between wiring, the relative permittivity is relative A relatively low-grade insulator may be used. In other words, insulator 380 can be the same as insulator 326. Materials may be used.

[0462] The pixel layer PXAL, for example, consists of a substrate 210, a transistor 200, and a light-emitting device. The 150 (light-emitting device 150a and light-emitting device 150b in Figure 24), and the substrate 102 and , is provided. Also, the pixel layer PXAL includes, as an example, an insulator 220 and an insulator 222, insulator 226, insulator 250, insulator 111a, insulator 111b, An edge body 112, an insulator 113, an insulator 162, and a resin layer 163 are provided. The pixel layer PXAL includes, for example, conductor 216, conductor 228, and conductor 230. , Conductor 121 (Conductor 121a and Conductor 121b in Figure 24) and Conductor 122 (Figure 2 In section 4, conductors 122a and 122b, and conductor 123 are provided.

[0463] In Figure 24, for example, the insulator 202, together with the insulator 380, forms a bonding layer. It has the function of being the same as the material used in the insulator 380, for example. It is preferable that it is composed of these components.

[0464] A substrate 210 is provided above the insulator 202. In other words, below the substrate 210 An insulator 202 is formed on the surface. The substrate 210 is, for example, suitable for substrate 310. It is preferable to use a substrate that can be used. Note that in the display device 1000 of Figure 24, substrate 31 0 is described as a semiconductor substrate made of silicon.

[0465] A transistor 200, for example, is formed on the substrate 210. Since 0 is formed on a substrate 210 which is a semiconductor substrate made of silicon, Si It functions as a transistor. Note that the configuration of transistor 200 is as follows: Please refer to the explanation for Ta300.

[0466] An insulator 220 and an insulator 222 are provided above the transistor 200. The insulator 220, for example, similar to the insulator 320, functions as an interlayer insulating film and a planarizing film. It has the ability to do so. Also, the insulator 222, for example, is similar to the insulator 322, and is an interlayer insulating film and It functions as a planarization film.

[0467] Furthermore, the insulator 220 and the insulator 222 are provided with multiple openings. Multiple openings are located in the region superimposed on the source and drain of transistor 200, and the conductor It is formed in regions that overlap with 376, etc. Also, among the multiple apertures, transistor 20 In the opening formed in the region superimposed on the source and drain of 0, the conductor 228 is formed This is achieved. In addition, among the remaining openings, the openings formed in the region superimposed on the conductor 376 are An insulator 214 is formed on the side of the opening, and a conductor 216 is formed in the remaining opening. In particular, conductor 216 is called TSV (Through Silicon Via). There are cases where this is the case.

[0468] For example, the conductor 216 or conductor 228 may be made of a material applicable to the conductor 328. This is possible. In particular, the conductor 216 is formed of the same material as the conductor 376. This is preferable.

[0469] The insulator 214 has the function of insulating the substrate 210 from the conductor 216. For example, the insulator 214 may be made of a material applicable to the insulator 320 or the insulator 324. It is preferable to do so.

[0470] An insulator 380 and a conductor 376 formed on the substrate 310, and formed on the substrate 210 The insulator 202 and the conductor 216 are bonded together, for example, by a bonding process. They are joined together.

[0471] As a pre-process before the bonding process, for example, on the substrate 310 side, an insulator 380 A planarization process is performed to make the heights of the surfaces of the conductive material 376 the same. Similarly, on the substrate 210 side, the respective surfaces of the insulator 202 and the conductor 216 A flattening process is performed to make the heights the same.

[0472] In the bonding process, the insulator 380 and the insulator 202 are joined together, that is, the insulators are joined together. When performing this process, high flatness is achieved through polishing, etc., followed by hydrophilic treatment with oxygen plasma, etc. Hydrophilic bonding methods, such as those that involve bringing surfaces into contact for temporary bonding and then performing permanent bonding through dehydration by heat treatment, are also used. It can be used. Hydrophilic bonding also involves bonding at the atomic level, resulting in superior mechanical properties. A joint can be formed.

[0473] Furthermore, when joining conductor 376 and conductor 216, that is, joining conductors together, The oxide film and impurity adsorption layer on the surface are removed by sputtering or other processes, followed by cleaning and A surface activation bonding method can be used, which involves bringing activated surfaces into contact and joining them together. This can utilize methods such as diffusion bonding, which uses both temperature and pressure to join surfaces together. In both cases, bonding occurs at the atomic level, resulting in a joint that is excellent not only electrically but also mechanically. It is possible.

[0474] By performing the bonding process described above, the conductive material 376 on the substrate 310 side is attached to the substrate It can be electrically connected to the conductor 216 on the 210 side. Also, the insulator on the substrate 310 side A connection with mechanical strength can be obtained between 380 and the insulator 202 on the substrate 210 side. Cut.

[0475] When substrate 310 and substrate 210 are bonded together, an insulating layer and a metal layer are provided on each bonding surface. Since they coexist, for example, a combination of surface activation bonding and hydrophilic bonding methods can be used. For example, after polishing, the surface is cleaned, and an anti-oxidation treatment is applied to the surface of the metal layer, followed by hydrophilicity. Methods such as processing and joining can be used. In addition, the surface of the metal layer can be treated with gold or other difficult materials. It may be an oxidizing metal and subjected to hydrophilic treatment.

[0476] In addition, other bonding methods besides the one described above may be used to bond substrate 310 and substrate 210. You may also use a flip. For example, as a method of bonding substrate 310 and substrate 210, The flip-chip bonding method may also be used. When using this, the conductor 376 on the substrate 310 side is placed above the conductor 216 on the substrate 210 side. A bump or other connection terminal may be provided below it. As for flip-chip bonding, For example, a resin containing anisotropic conductive particles is placed between the insulator 380 and the insulator 202, and the conductor 3 A method of joining by injecting the material between 76 and the conductor 216, and a method of joining using silver-tin solder. The law is cited. Alternatively, if the bump and the conductor connected to the bump are both made of gold. In addition, ultrasonic bonding can be used. Furthermore, physical stress such as impact and thermal stress can be reduced. In order to mitigate the effects of the above flip-chip bonding method, under The filler material is placed between insulator 380 and insulator 202, and between conductor 376 and conductor 216. It may also be injected into it. Also, for example, as a bonding between substrate 310 and substrate 210, Bonding film may also be used.

[0477] Insulator 224 is placed on insulator 222, insulator 214, conductor 216, and conductor 228. The insulator 226 and the other are stacked in that order.

[0478] Insulator 224, like insulator 324, contains water and hydrogen in the region above insulator 224. It is preferable to have a barrier insulating film that prevents the diffusion of such impurities. For the body 224, it is preferable to use a material that can be applied to the insulator 324, for example.

[0479] The insulator 226 is preferably an interlayer film with a low dielectric constant, similar to the insulator 326. Therefore, it is preferable to use a material for the insulator 226 that can be used for, for example, the insulator 326. It's nice.

[0480] Furthermore, insulators 224 and 226 contain transistors 200 and light-emitting devices 15 A conductor 230, etc., which is electrically connected to 0, is embedded. Note that the conductor 230 is It functions as a plug or wiring. For example, the conductor 230 is conductor 3 28, or a material applicable to the conductor 330 can be used.

[0481] On insulator 224 and insulator 226 are insulator 250, insulator 111a, and insulator 111b and are stacked in that order.

[0482] Insulator 250, like insulator 324, acts as a barrier against impurities such as water or hydrogen. It is preferable to use an insulator having insulating properties. For this reason, the insulator 250 may be, for example, an insulating material. Materials applicable to body 324 and other components can be used.

[0483] Insulator 111a and insulator 111b each have an oxide insulating film, a nitride insulating film, and an oxide Various inorganic insulating films, such as nitride insulating films and nitride oxide insulating films, can be suitably used. The edge 111a has a silicon oxide film, a silicon oxide nitride film, or an aluminum oxide film. It is preferable to use an oxide insulating film or an oxide-nitriding insulating film. The insulator 111b is A silicon nitride film or silicon nitride oxide film, which is a nitride insulating film or a nitride oxide insulating film. It is preferable to use a silicon oxide film for the insulator 111a. It is preferable to use a silicon nitride film for the edge body 111b. The insulator 111b is etched It is preferable that it has the function of a protective film. Alternatively, the insulator 111a has nitride insulation. A film or nitride-oxide insulating film is used, and the insulator 111b is an oxide insulating film or an oxide-nitride insulating film. This may also be used. In this embodiment, an example is shown in which a recess is provided in the insulator 111b. However, the insulator 111b does not necessarily need to have a recess.

[0484] Furthermore, the conductive material 23 of each of the insulators 250, 111a, and 111b An opening is formed in the region that overlaps with a part of 0, and a conductor 121 fills the opening. A conductor 121a, shown in Figure 24, is provided. The electric element 121b is collectively referred to as conductor 121. Note that conductor 121 is conductor 328 , and can be provided using the same material as the conductor 330.

[0485] Furthermore, the pixel electrode described in this embodiment includes, as an example, a material that reflects visible light. The counter electrode contains a material that transmits visible light.

[0486] The display device 1000 is a top-emission type. The light emitted by the light-emitting device is directed onto the substrate. It is ejected towards the 102 side. The substrate 102 is made of a material with high transmittance to visible light. It is preferable.

[0487] Light-emitting devices 150a and 150b are provided above the conductor 121. ru.

[0488] Here, we will describe the light-emitting device 150a and the light-emitting device 150b.

[0489] The light-emitting device described in this embodiment is an organic EL element (OLED). Self-emitting light-emitting devices such as Light Emitting Diodes This refers to the light-emitting device electrically connected to the pixel circuit, which is an LED (Light Emulator). (Itting Diode), Micro LED, QLED (Quantum-dot LED) Self-luminescent light emission, such as a light-emitting diode (light-emitting diode) or a semiconductor laser. It can be used as a device.

[0490] Conductors 122a and 122b are, for example, on the insulator 111b, and conductor 121a A conductive film is formed on the upper and conductor 121b, and the conductive film is subjected to a patterning process and E It can be formed by performing a chipping process.

[0491] Each of the conductors 122a and 122b is, for example, connected to the display device 1000. The light-emitting devices 150a and 150b function as anodes. .

[0492] Examples of conductors 122a and 122b include indium tin oxide (ITO (Sometimes referred to as) and other methods can be applied.

[0493] Furthermore, the conductive material 122a and conductive material 122b are each made of two layers, not one layer. The above layered structure may also be used. For example, the first layer of conductor may have a reflectance to visible light. By applying a highly conductive material, and as the top layer of conductive material, a highly light-transmitting conductive material is applied. Yes, it is possible. Examples of conductors with high reflectivity to visible light include silver, aluminum, or A silver (Ag), palladium (Pd), and copper (Cu) alloy film (Ag-Pd-Cu(APC) film) Examples include the above-mentioned indium stinic acid. Furthermore, a conductor with high light transmittance is, for example, the above-mentioned indium stinic acid. Examples include cycloids. Also, as conductors 122a and conductors 122b, for example, a pair A multilayer film of aluminum sandwiched between titanium (a multilayer film in the order of Ti, Al, Ti), or a pair A layered film of silver sandwiched between indium tin oxide (layered film in the order of ITO, Ag, ITO) It is possible.

[0494] An EL layer 141a is provided on the conductive material 122a. Also, on the conductive material 122b An EL layer 141b is provided.

[0495] By the way, EL layer 141a and EL layer 141b each exhibit light emission of different colors. It is preferable to have a light-emitting layer. For example, the EL layer 141a is red (R) and green (G) The EL layer 141b has an emissive layer that emits either blue (B) light, and the remaining two layers It can have a light-emitting layer that exhibits one type of light emission. Also, although not shown in Figure 24, However, if an EL layer different from EL layer 141a and EL layer 141b is provided, The EL layer may have a light-emitting layer that exhibits the remaining light emission. The device 1000 has multiple pixel electrodes (for example, conductors 121a and 121b) with color It may have a structure (SBS structure) that forms a different light-emitting layer for each individual unit.

[0496] The colors emitted by the light-emitting layers contained in EL layer 141a and EL layer 141b, respectively, are also described. The combinations are not limited to those listed above; for example, colors such as cyan, magenta, or yellow can also be used. It is also acceptable. Furthermore, although the above example shows three colors, the light-emitting data included in the display device 1000 may vary. The Vice 150 may emit light in two colors, or it may emit four or more colors.

[0497] EL layer 141a and EL layer 141b are layers containing a light-emitting organic compound (light emission In addition to the layers, one or more of the following are included: electron injection layer, electron transport layer, hole injection layer, and hole transport layer. It is acceptable to have it.

[0498] Furthermore, the EL layer 141a and EL layer 141b are coated, for example, by a vapor deposition method (such as vacuum deposition) or by coating. Fabric coating methods (dip coating, die coating, bar coating, spin coating, spray coating) Printing methods (inkjet, screen printing, offset printing) Methods such as printing, flexographic printing, gravure printing, microcontact printing, etc. It can be formed by [this method].

[0499] Furthermore, when applying the above coating method or printing method, polymer compounds (for example, Ori) (Gomers, dendrimers, or polymers), medium-molecular-weight compounds (compounds in the intermediate region between low and high molecular weights) Compounds (molecular weight 400-4000), or inorganic compounds (e.g., quantum dot materials) are used. This is possible. Furthermore, quantum dot materials include colloidal quantum dot materials and alloy-type quantum dot materials. A core-shell type quantum dot material, or a core-type quantum dot material can be used. ru.

[0500] For example, the light-emitting devices 150a and 150b in Figure 24 are: As shown in Figure 25(A), the light-emitting device 150 has a light-emitting layer 4411 and a layer 4430. It can be composed of multiple layers.

[0501] Layer 4420 is, for example, a layer containing a material with high electron injection potential (electron injection layer) and an electron transport layer. It can have a layer containing a highly efficient material (electron transport layer), etc. The light-emitting layer 4411 is, for example, For example, it contains a luminescent compound. Layer 4430 is a layer containing a material with high hole injection potential ( It can have a hole injection layer and a layer containing a material with high hole transport properties (hole transport layer).

[0502] A layer 4420 is provided between a pair of electrodes (conductor 121 and conductor 122, which will be described later), and light emission The configuration having layers 4411 and 4430 can function as a single light-emitting unit. In this specification, the configuration shown in Figure 25(A) is referred to as a single structure.

[0503] Furthermore, Figure 25(B) shows the EL layer 141 of the light-emitting device 150 shown in Figure 25(A). This is a modified version. Specifically, the light-emitting device 150 shown in Figure 25(B) is made of a conductor 121 The upper layer 4430-1, the layer 4430-2 on top of layer 4430-1, and the light emission on layer 4430-2. Layer 4411, layer 4420-1 on the light-emitting layer 4411, and layer 4420- on layer 4420- It has 2 and a conductor 122 on layer 4420-2. For example, the conductor 121 is the anode. When conductor 122 is used as the cathode, layer 4430-1 functions as a hole injection layer, and layer 443 Layer 0-2 functions as a hole transport layer, layer 4420-1 functions as an electron transport layer, and layer 442 O-2 functions as an electron injection layer. Alternatively, conductor 121 is used as the cathode and conductor 122 is used When used as an anode, layer 4430-1 functions as an electron injection layer, and layer 4430-2 functions as an electron transport layer. It functions as a layer, with layer 4420-1 acting as a hole transport layer and layer 4420-2 acting as a hole injection layer. It functions as a layer. This layer structure allows for efficient carrier emission to occur in the light-emitting layer 4411. Injecting this makes it possible to increase the efficiency of carrier recombination within the light-emitting layer 4411. .

[0504] Furthermore, as shown in Figure 25(C), multiple light-emitting layers (for example) are placed between layer 4420 and layer 4430. In addition, a configuration in which a light-emitting layer 4411, a light-emitting layer 4412, and a light-emitting layer 4413 are provided is also a single This is a variation of the structure.

[0505] Furthermore, a laminate having multiple layers such as layer 4420, light-emitting layer 4411, and layer 4430 This is sometimes referred to as a light-emitting unit. Furthermore, multiple light-emitting units are connected by an intermediate layer (charge generation). They can be connected in series via layers. Specifically, as shown in Figure 25(D), multiple The light-emitting units, light-emitting unit 4400a and light-emitting unit 4400b, are intermediate. It can be connected in series via the layer (charge generation layer) 4440. Note that in this specification, Such a structure is called a tandem structure. Furthermore, in this specification, a tandem structure is sometimes referred to as an example. In some cases, this is referred to as a stacked structure. Furthermore, the light-emitting devices are arranged in a tandem structure. This makes it possible to create a light-emitting device capable of high-brightness light emission. In addition, the light-emitting device can be turned on. By adopting a DEM structure, for example, the luminous efficiency of the light-emitting device and the lifespan of the light-emitting device can be improved. An improvement in life expectancy can be expected. The light-emitting device 150 of the display device 1000 in Figure 24 is in a tandem structure. In this case, the EL layer 141 is, for example, the light-emitting layer 4420 of the light-emitting unit 4400a. Layers 4411 and 4430, intermediate layer 4440, and layer 4420 of light-emitting unit 4400b The configuration can include a light-emitting layer 4412 and a layer 4430.

[0506] Furthermore, when displaying white, the SBS structure described earlier is the same as the single structure mentioned above. It can consume less power than a tandem structure. Therefore, power consumption is kept low. In such cases, an SBS structure is preferable. On the other hand, a single structure and a tandem structure Because the manufacturing process is simpler than that of the SBS structure, manufacturing costs can be lowered. This is preferable because it allows for or increases the manufacturing yield.

[0507] The light-emitting color of the light-emitting device 150 depends on the material that makes up the EL layer 141, and can be red, green, blue, It can be cyan, magenta, yellow, or white. Also, a microphone is connected to the light-emitting device 150. By adding a cavity structure, color purity can be further enhanced.

[0508] A light-emitting device that emits white light has a configuration that includes two or more types of light-emitting materials in the light-emitting layer. This is preferable. In order to obtain white light emission, the light emitted by each of the two light-emitting materials should be in a complementary color relationship. You just need to select a suitable light-emitting material. For example, the light-emitting color of the first light-emitting layer and the light-emitting color of the second light-emitting layer By arranging them to be complementary colors, a configuration can be obtained in which the entire light-emitting device emits white light. This can be done. Also, when obtaining white light emission using three or more light-emitting layers, the three or more light-emitting layers The combination of these light-emitting colors allows the entire light-emitting device to emit white light. That's all you need to do.

[0509] The light-emitting layer exhibits emission of red (R), green (G), blue (B), yellow (Y), and orange (O). It is preferable to have two or more photoluminescent substances. Alternatively, it may have two or more light-emitting substances, each of which emits light The luminescence of the material preferably includes spectral components of two or more colors from R, G, and B.

[0510] Furthermore, as shown in Figure 24, there is a gap between the two EL layers in adjacent light-emitting devices. A gap is provided. Specifically, in Figure 24, a recess is provided between adjacent light-emitting devices. A recess is formed, and the side surface of the recess (conductor 121a, conductor 122a, and EL layer 141a) The sides, the sides of the conductor 121b, the conductor 122b, and the EL layer 141b, and the bottom surface (insulator) A portion of 111b is covered by an insulator 112. An insulator 162 is formed on 112 so as to fill the recess. In this way, E It is preferable that the L layer 141a and the EL layer 141b are arranged so as not to be in contact with each other. This allows current (lateral leakage current, side leakage current) to pass through two adjacent EL layers. (Also known as crosstalk) is preferable to prevent the flow of (and other similar) signals that cause unintended light emission. This can be prevented. Therefore, contrast can be increased, resulting in a display with high display quality. This enables the realization of a configuration with extremely low lateral leakage current between light-emitting devices. Therefore, the black display performed by the display device is a display with as little light leakage as possible (also called a true black display) It is possible.

[0511] For example, a photolithography can be used to form the EL layer 141a and the EL layer 141b. One example is a method using the i method. For example, E which becomes EL layer 141a and EL layer 141b The L film is deposited on the conductive material 122, and then the EL film is processed by photolithography. By patterning, EL layer 141a and EL layer 141b are formed. This makes it possible to create a gap between the two EL layers in adjacent light-emitting devices. A gap can be created.

[0512] The insulator 112 can be an insulating layer having an inorganic material. For example, inorganic insulating films such as oxide insulating films, nitride insulating films, oxide-nitrided insulating films, or nitride-oxide insulating films. A film can be used. The insulator 112 may be a single-layer structure or a multilayer structure. Examples of oxide insulating films include silicon oxide films, aluminum oxide films, and magnesium oxide films. Indium gallium zinc oxide film, gallium oxide film, germanium oxide film, oxide Yttrium film, zirconium oxide film, lanthanum oxide film, neodymium oxide film, hafny oxide film Examples include silicon nitride films and tantalum oxide films. Examples of nitride insulating films include silicon nitride films. Examples include aluminum nitride films. Examples of oxidative nitride insulating films include aluminum nitride films. Examples include ricon films and aluminum oxide nitride films. Examples of nitride oxide insulating films include, for example, Examples include silicon nitride film and aluminum nitride film. In particular, aluminum nitride The um film has a high selectivity ratio with the EL layer during etching, and is used in the formation of the insulator 162 described later. In this regard, it is preferable because it has the function of protecting the EL layer. In particular, when formed by the ALD method The inorganic insulating films of aluminum oxide film, hafnium oxide film, and silicon oxide film are used as insulators 11 By applying it to 2, an insulator 112 is obtained that has fewer pinholes and excellent function in protecting the EL layer. It is possible to form this.

[0513] In this specification, an oxidized nitride is defined as a compound whose composition contains more oxygen than nitrogen. This refers to materials with a high concentration of nitrogen, and nitride oxides, in terms of their composition, have a higher nitrogen content than oxygen. It refers to a material that contains more nitrogen than other materials. For example, if it is written as silicon oxidnitride, then its composition is more than nitrogen. When referring to a material with a high oxygen content, and it is written as silicon nitride oxide, its composition is as follows: This indicates materials with a higher nitrogen content than oxygen content.

[0514] For the formation of the insulator 112, for example, sputtering, CVD, PLD, or AL A film deposition method such as method D can be used. In particular, the insulator 112 has good coverage A It is preferable to form it using the LD method.

[0515] The insulator 162 provided on the insulator 112 is an insulating material formed between adjacent light-emitting devices. It has the function of flattening the recess of the edge 112. In other words, by having an insulator 162 This has the effect of improving the flatness of the surface on which the conductor 123 is formed, as will be described later. The insulator 162 has the effect of An insulating layer having an organic material can be suitably used. For example, the insulator 162 may contain an organic material. Polyamide resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimide resin Mido resins, silicone resins, siloxane resins, benzocyclobutene resins, phenolic resins Lipids or precursors of these resins can be applied. Also, for example, the insulator 162 can be... Polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, poly Ethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol Organic materials such as soluble polyamide resin may also be used. Furthermore, the insulator 162 may be, for example... For example, a photosensitive resin can be used. Alternatively, the photosensitive resin can be, for example, a positive-type material or a negative-type material. ru.

[0516] The height of the upper surface of the insulator 162 and the height of the upper surface of the EL layer 141a or EL layer 141b The difference is preferably 0.5 times or less the thickness of the insulator 162, and more preferably 0.3 times or less. For example, the upper surface of the EL layer 141a or the EL layer 141b is the upper surface of the insulator 162. An insulator 162 may be provided to further increase the temperature. Also, for example, the upper surface of the insulator 162 However, it is such that it is higher than the upper surface of the light-emitting layer of the EL layer 141a or the EL layer 141b. An insulator 162 may be provided.

[0517] On the EL layer 141a, on the EL layer 141b, on the insulator 112, and on the insulator 162, An electric body 123 is provided. In addition, light-emitting devices 150a and 150b are provided. Each of the above is provided with an insulator 113.

[0518] The conductor 123 is, for example, the respective light-emitting devices 150a and 150b. It functions as a common electrode. Furthermore, it transmits light emitted from the light-emitting device 150 to the display device 1000. To be ejected upwards, it is preferable that the conductor 123 has a light-transmitting conductive material. It's nice.

[0519] The conductor 123 is a material that has high conductivity and also has light transmission and light reflectivity (semi-transparent and semi-reflective). It is preferable that the conductor 123 is, for example, silver and Magnesium alloys and indium tin oxide can be used.

[0520] The insulator 113 may be referred to as a protective layer, and the light-emitting device 150a and the light-emitting d By providing an insulator 113 above each of the vises 150b, the reliability of the light-emitting device is improved. This can be enhanced. In other words, the insulator 113 is connected to the light-emitting device 150a and the light-emitting device It functions as a passivation membrane to protect chair 150b. Therefore, the insulator 113 Preferably, the insulator is made of a material that prevents the ingress of water, etc. For example, the insulator 113 may be made of an insulator 1 Materials applicable to 11a or insulator 111b can be used. Specifically, oxidation Aluminum, silicon nitride, or silicon nitride oxide can be used.

[0521] A resin layer 163 is provided on the insulator 113. Also, a base is provided on the resin layer 163. A plate 102 is provided.

[0522] For example, it is preferable to use a translucent substrate for the substrate 102. By using a light-transmitting substrate, the light-emitting device 150a and light-emitting device 15 The light emitted at 0b can be projected upwards onto the substrate 102.

[0523] Note that the display device according to one aspect of the present invention is not limited to the configuration of the display device 1000 shown in Figure 24. No. The configuration of the display device according to one aspect of the present invention may be modified as appropriate, as long as it is within the scope of solving the problem. It may be done.

[0524] For example, transistor 20 is included in the pixel layer PXAL of the display device 1000 in Figure 24 0 is a transistor having a metal oxide in the channel formation region (hereafter referred to as an OS transistor and It may also be referred to as (name). The display device 1000 shown in Figure 26 is the same as the display device 1000 in Figure 24. Above the circuit layer SICL and the wiring layer LINL, a replacement for transistor 200 is provided. The configuration includes a transistor 500 (OS transistor) and a light-emitting device 150. That's how it is.

[0525] In Figure 26, the transistor 500 is mounted on the insulator 512. 12 is provided above the insulator 364 and the conductor 366, and the insulator 512 is For example, it is preferable to use a material that has barrier properties against oxygen and hydrogen. Specifically For example, silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, oxide Aluminum, aluminum oxide nitride, aluminum oxide nitride, aluminum nitride, etc. Use it.

[0526] As an example of a film with hydrogen barrier properties, silicon nitride formed by CVD is used. It is possible to have a semiconductor device having an oxide semiconductor such as transistor 500. Furthermore, hydrogen diffusion can degrade the properties of the semiconductor device. Therefore, A film that suppresses hydrogen diffusion is used between the transistor 500 and the transistor 300. This is preferable. Specifically, a membrane that suppresses hydrogen diffusion is a membrane that has a low rate of hydrogen desorption. ru.

[0527] Furthermore, for example, the same material as the insulator 320 can be used for the insulator 512. Furthermore, by applying materials with relatively low dielectric constants to these insulators, the gaps between the wires can be reduced. Raw capacitance can be reduced. For example, the insulator 512 has a silicon oxide film, or an oxide film. A silicon nitride film can be used.

[0528] Furthermore, an insulator 514 is provided on the insulator 512, and a transient is provided on the insulator 514. A transistor 500 is provided. Also, on the insulator 512, the transistor 500 is covered. Furthermore, an insulator 576 is formed above the insulator 576. An insulator 581 is provided to cover it.

[0529] The insulator 514 is provided with circuit elements, etc., located below the substrate 310 or the insulator 512. From the region where the transistor 500 is located, hydrogen and water are present in the region where the transistor 500 is located. It is preferable to use a film that has barrier properties to prevent the diffusion of pure substances. Therefore, insulation For body 514, for example, silicon nitride formed by the CVD method can be used.

[0530] As described above, the transistor 500 shown in Figure 26 has a metal oxide channel formation region This is an OS transistor. Examples of the metal oxide include indium, element M. and In-M-Zn oxide containing zinc (element M is aluminum, gallium, yt Rium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium Zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum Metal oxides such as one or more selected from tungsten or magnesium. These can be used. Specifically, for example, as metal oxides, indium, gallium You may use an oxide containing um and zinc (sometimes referred to as IGZO). Also, for example, Metal oxides include indium, aluminum, and zinc oxides (referred to as IAZO). (In some cases) may be used. Also, as metal oxides, for example, indium, aluminum Even when using oxides containing zinc, gallium, and zinc (sometimes referred to as IAGZO) Good. In addition to the above, metal oxides include In-Ga oxide, In-Zn oxide, Indium oxide may also be used.

[0531] In particular, metal oxides that function as semiconductors have a band gap of 2 eV or more, preferably It is preferable to use gold with a band gap of 2.5 eV or higher. By using a specific oxide, the transistor's off-current (sometimes called leakage current) can be reduced. This can be reduced.

[0532] In particular, the drive transistors included in the pixel circuit have a large source-drain voltage. Even in this case, a transistor whose off-current is sufficiently small, such as an OS transistor, It is preferable to apply this. By using an OS transistor as the drive transistor, the drive To reduce the amount of off-current flowing to the light-emitting device when the transistor is in the off state. Therefore, it is possible to sufficiently reduce the brightness of the light emitted by a light-emitting device through which an off-current flows. This is possible. Therefore, a drive transistor with a large off-current and a drive transistor with a small off-current are used. When comparing a turntable and a drive tube, the drive tube has a larger off-current when displaying black in the pixel circuit. A pixel circuit that includes a drive transistor has a lower off-current than a pixel circuit that includes a transistor. The luminescence brightness can be reduced. In other words, by using an OS transistor, the pixel circuit This can suppress black distortion when displaying black.

[0533] Furthermore, the off-current value of an OS transistor per 1 μm channel width at room temperature is: 1aA(1×10 -18 A) Below, 1zA(1×10 -21 A) Below, or 1yA(1 ×10 -24 A) The following is possible. Note that at room temperature, channel width 1 μm The off-current value of each Si transistor is 1 fA (1 × 10⁻¹⁰). -15 A) More than 1pA (1× 10 -12 A) is less than or equal to the value below. Therefore, the off-current of the OS transistor is the Si transistor It could be said that it is about 10 orders of magnitude lower than the off-current of a standard transistor.

[0534] Furthermore, when increasing the luminescence brightness of the light-emitting device included in the pixel circuit, the current flow to the light-emitting device is reduced. The current needs to be increased. Also, to do this, the drive motor included in the pixel circuit The source-drain voltage of the transistor needs to be increased. OS transistors are made of Si Compared to transistors, OS transistors have higher voltage resistance between source and drain. A high voltage can be applied between the source and drain of the sta. This allows the pixel circuit By using an OS transistor as the driving transistor included in the OS transistor, the soaring of the OS transistor Because a high voltage can be applied between the current and drain, the amount of current flowing through the light-emitting device can be increased. By increasing the size, the luminescence brightness of the light-emitting device can be increased.

[0535] Furthermore, when a transistor operates in the saturation region, the OS transistor is Si Compared to a transistor, the change in source-drain current in response to a change in gate-source voltage is greater. This allows for a reduction in size. Therefore, the drive transistor included in the pixel circuit is O By applying an S transistor, the change in the gate-source voltage affects the source - Because the current flowing between the drains can be precisely controlled, the current flowing through the light-emitting device The amount can be precisely controlled. Therefore, the brightness of the light emitted by the light-emitting device can be precisely controlled. This allows for (the gradation in the pixel circuit to be increased).

[0536] Furthermore, in the saturation characteristics of the current that flows when a transistor operates in the saturation region, OS Even when the source-drain voltage gradually increases, the transistor performs better than a Si transistor. It can also supply a stable constant current (saturation current). Therefore, it drives OS transistors. By using it as a transistor, for example, current-electric current in light-emitting devices containing EL materials. Even if there are variations in the pressure characteristics, a stable constant current can be supplied to the light-emitting device. Furthermore, when operating in the saturation region, the source-drain voltage of the OS transistor is Even if the current is increased, the source-drain current remains almost unchanged, thus increasing the luminescence of the light-emitting device. It can be made stable.

[0537] As described above, OS transistors are used as the drive transistors included in the pixel circuit. And, "suppression of black level distortion," "increase in luminous brightness," "multi-gradation," and "increase in the brightness of the light-emitting device." This allows for the suppression of glitches and other issues. Therefore, the display device, including the pixel circuit, is designed to produce clear images. Moreover, it can display smooth images, and as a result, the image sharpness (image clarity), And a high contrast ratio, or both, can be observed. Furthermore, the image quality ( Image sharpness refers to the suppression of motion blur and the suppression of black level distortion. It may refer to one or both of the following: the act of doing so. Also, the drive transistor included in the pixel circuit. By creating a configuration with extremely low off-current, the black display performed by the display device is made possible without light leakage. It is possible to display with as little or no color as possible (completely black display).

[0538] Insulator 576 and insulator 581, or one or both, contain impurities such as water or hydrogen. A barrier insulating film that suppresses diffusion from above to transistor 500. It is preferable that it functions as such. Therefore, one of the insulators 576 and 581 or Both sides contain hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (for example) It has the function of suppressing the diffusion of impurities such as N2O, NO, and NO2, and copper atoms. It is preferable to use an insulating material that (does not easily allow the above impurities to permeate) or an oxygen (e.g.) For example, it has the function of suppressing the diffusion of oxygen atoms and / or oxygen molecules (the above acid It is preferable to use an insulating material (which is not easily permeable to elements).

[0539] Insulator 576 and insulator 581, or one or both, contain impurities such as water and hydrogen. It is preferable to use an insulator that has the function of suppressing the diffusion of oxygen, for example, oxidation Aluminum, magnesium oxide, hafnium oxide, gallium oxide, indium gallium You can use zinc oxide, silicon nitride, or silicon nitride oxide.

[0540] Also, insulator 581, insulator 576, and the source or drain of transistor 500 The electrode is provided with an opening for forming a plug or wiring. A conductor 540, which functions as a plug or wiring, is formed in the opening.

[0541] Furthermore, the insulator 581 may function, for example, as one or both of an interlayer film and a planarization film. It is preferable to use an insulating material.

[0542] Above the insulator 581 and the conductor 540 are insulators 224 and 226. This has been done. Furthermore, the insulator located above the insulator 224, including the insulator 224, For descriptions of conductors, circuit elements, etc., please refer to the explanation of the display device 1000 in Figure 24.

[0543] Figure 24 shows the semiconductor substrate on which the light-emitting device 150, pixel circuit, etc., are formed, and the drive Figure 2 shows a display device constructed by bonding together semiconductor substrates on which circuits and other components are formed. In 6, a light-emitting device 15 is placed on a semiconductor substrate on which a drive circuit is formed. Figure 2 shows a display device in which pixel circuits and the like are formed, but a display device according to one aspect of the present invention is shown in Figure 2. 4. Not limited to Figure 26. A display device according to one aspect of the present invention includes, for example, a transistor A table having a structure in which only one transistor layer is formed, rather than a layered structure with two or more layers stacked on top of each other. It may also be used as a display device.

[0544] Specifically, for example, a display device according to one aspect of the present invention is the display device 10 shown in Figure 27(A) As shown in 00, a circuit including a transistor 200 formed on the substrate 210, and the transistor The configuration may also include a light-emitting device 150 provided above the 200. For example, as shown in the display device 1000 in Figure 27(B), an insulator 5 A transistor 500 is provided on the insulator 512, and the transistor 500 The substrate may also have a configuration that includes a light-emitting device 150 located above it. For example, 501 can be a substrate that can be applied to substrate 310, and in particular, glass It is preferable to use a stainless steel substrate.

[0545] A display device according to one aspect of the present invention is shown in Figure 27(A) and Figure 27(B), respectively. As shown in the apparatus 1000, only one layer of transistors is formed, and above the transistor A configuration in which a light-emitting device 150 is provided may also be used. In addition, although not shown in the figures, one of the present invention The display device of the embodiment may have a layer structure in which three or more transistors are formed. .

[0546] <Example of sealing structure for display device> Next, regarding the sealing structure of the light-emitting device 150 that can be applied to the display device 1000 in Figure 24, I will explain.

[0547] Figure 28(A) is a cross-sectional view showing an example of a sealing structure applicable to the display device 1000 in Figure 24. Specifically, Figure 28(A) shows the end of the display device 1000 in Figure 24, and the end The components provided around it are illustrated. Also, Figure 28(A) shows the display device 100 Only a portion of the 0 pixel layer PXAL is shown in the diagram. Specifically, Figure 28(A) is: Insulator 250, and insulators, conductors, and light-emitting devices located above insulator 250. Figure S150a is shown.

[0548] Furthermore, an opening is provided in the region 123CM shown in Figure 28(A). Furthermore, a conductor 121CM is provided in the opening, as an example. 123 is connected to the wiring located below the insulator 250 via the conductor 121CM. They are connected by gas. This allows the conductor 123, which functions as a common electrode, to have a potential (for example) If the anode potential and cathode potential of the light-emitting device 150a are supplied, Yes, it is possible. Furthermore, selection can be made from the conductors included in region 123CM and the conductors surrounding region 123CM. The number of electrodes that have been exposed is sometimes referred to as a connecting electrode.

[0549] Furthermore, as the conductor 121CM, for example, a material applicable to the conductor 121 can be used. It is possible.

[0550] In the display device 1000 shown in Figure 28(A), the end of the resin layer 163 or the area around the end An adhesive layer 164 is provided. Specifically, the insulator 113 and the substrate 102 are bonded together by the adhesive layer. The display device 1000 is configured to be accessed via 164.

[0551] The adhesive layer 164 is, for example, a material that suppresses the permeation of impurities such as moisture. This is preferable. By using this material in the adhesive layer 164, the reliability of the display device 1000 is improved. It is possible.

[0552] The insulator 113 and the substrate 102 are bonded together using the adhesive layer 164, with the resin layer 163 in between. The combined structure is sometimes called a solid-sealed structure. Also, in a solid-sealed structure, The grease layer 163, like the adhesive layer 164, has the function of bonding the insulator 113 and the substrate 102 together. If the above is present, the adhesive layer 164 does not necessarily need to be provided.

[0553] On the other hand, the adhesive layer 164 is used to separate the insulator 113 and the substrate 102, instead of the resin layer 163. A structure formed by filling it with an inert gas and bonding the parts together is sometimes called a hollow-sealed structure (Figure) (Not shown). Examples of inert gases include nitrogen and argon.

[0554] Furthermore, in the sealing structure of the display device 1000 shown in Figure 28(A), there are two or more adhesive layers. They can be used in layers. For example, as shown in Figure 28(B), the adhesive layer 164 can be used on the inside (adhesion). An adhesive layer 165 may be provided between layer 164 and resin layer 163. By layering these materials, the permeation of impurities such as water can be further suppressed. The reliability of the display device 1000 can be further improved.

[0555] Furthermore, a desiccant may be mixed into the adhesive layer 165. This will allow the adhesive layer 164 and the bonding to adhere. The resin layer 163 formed inside layer 165, the insulator, the conductor, the EL layer, etc. Since the moisture present is adsorbed by the desiccant, the reliability of the display device 1000 is enhanced. It is possible.

[0556] Furthermore, although the display device 1000 in Figure 28(B) shows a solid encapsulation structure, a hollow encapsulation structure is also shown. That is also acceptable.

[0557] Furthermore, in the sealing structure of the display device 1000 shown in Figures 28(A) and 28(B), resin Layer 163 may be filled with an inert liquid. Examples of inert liquids include fluorine. Examples include inert liquid systems.

[0558] By the way, one aspect of the present invention is not limited to the above-described configuration, and depending on the situation, the above-described configuration may be used. The configuration can be changed as appropriate. Below, an example of changing the display device 1000 in Figure 24 is shown in Figure 29. This will be explained using Figures (A) to 30(B). Note that Figures 29(A) to 30(B) contain: The diagram shows only a portion of the pixel layer PXAL of the display device 1000. Specifically, Figure Figures 29(A) to 30(B) each represent insulator 250, insulator 111a, and insulator Insulator, conductor, light-emitting device 150a, and light-emitting device located above 111a Figure 150b is shown. In particular, Figures 29(A) to 30(B) show the light-emitting device 1 50c, conductor 121c, conductor 122c, and EL layer 141c are also shown in the diagram.

[0559] For example, the color of light emitted by EL layer 141c is determined by EL layer 141a and EL layer 141 The color of the light exhibited by b may be different. Also, for example, the configuration of the display device 1000 is as follows: The number of colors emitted by the light-emitting devices 150a to 150c may be two. Furthermore, for example, the configuration of the display device 1000 can be improved by increasing the number of light-emitting devices 150. Multiple light-emitting devices may emit four or more colors (not shown in the diagram).

[0560] Furthermore, for example, the configuration of the display device 1000 is as shown in Figure 29(A), EL layer A configuration in which the EL layer 142 is formed on 141a or on the EL layer 141c is also possible. For example, in Figure 25(A), EL layers 141a to EL layers 141c are layer 4430 When the configuration includes the luminescent layer 4411, the EL layer 142 has a configuration that includes layer 4420. In this case, the layer 4420 included in the EL layer 142 is the light-emitting device 150a or It functions as a common layer in each of the light-emitting devices 150c. Similarly, for example, Figure In 25(C), EL layer 141a to EL layer 141c are layer 4430 and light-emitting layer 4411 When the configuration includes a light-emitting layer 4412 and a light-emitting layer 4413, the EL layer 142 is layer 442 By including 0 in the configuration, layer 4420 included in EL layer 142 becomes light-emitting device 150 It functions as a common layer in each of the light-emitting devices a to 150c. Also, for example, In Figure 25(D), the EL layers 141a to 141c form the light-emitting unit 4400b Layer 4430, light-emitting layer 4412, and layer 4420, intermediate layer 4440, and light-emitting unit 4 When the configuration includes a 400a layer 4430 and an emissive layer 4411, the EL layer 142 By including the layer 4420 of the light-emitting unit 4400b, the EL layer 142 is included Layer 4420 of light-emitting unit 4400a is a light-emitting device 150a to light-emitting device 150 It functions as a common layer in each of c.

[0561] Furthermore, for example, in the configuration of the display device 1000, the insulator 113 is not one layer but two layers. The above laminated structure may also be used. The insulator 113 may, for example, be an inorganic material insulator as the first layer. Apply the first layer, then apply an organic insulating layer as the second layer, and an inorganic insulating layer as the third layer. A three-layer laminated structure may also be used. Figure 29(B) shows an insulator 113a made of an inorganic material. The insulator is made of an organic material, and the insulator 113b is made of an inorganic material. The structure includes an insulator 113 containing insulators 113a, 113b, and 113c. This diagram shows a cross-sectional view of a part of the multi-layered display device 1000.

[0562] Furthermore, for example, the configuration of the display device 1000 may include EL layers 141a to EL layers 141c A microcavity structure (micro-resonator structure) may be provided in each of these. A Vity structure, for example, is a conductor 122 that is the upper electrode (common electrode) and has light-transmitting and light-emitting properties. A reflective conductive material is used, and the conductor 121, which is the lower electrode (pixel electrode), reflects light. Using a conductive material with properties, the distance between the lower surface of the light-emitting layer and the upper surface of the lower electrode, i.e., Figure 25 ( The thickness of layer 4430 in A) corresponds to the color wave of light emitted by the light-emitting layer contained in EL layer 141. This refers to a structure where the thickness is adjusted according to the length.

[0563] For example, light reflected by the lower electrode (reflected light) returns from the light-emitting layer to the upper electrode Because it causes significant interference with light directly incident on it (incident light), the optical distance between the lower electrode and the light-emitting layer Adjust to (2n-1)λ / 4 (where n is a natural number greater than or equal to 1, and λ is the wavelength of light to be amplified). It is preferable to do so. By adjusting the optical distance, the reflection of each wavelength λ can be adjusted. By aligning the phase of light with the incident light, the emission from the light-emitting layer can be further amplified. On the other hand, If the reflected light and the incident light have wavelengths other than λ, their phases will not match, and therefore they will not resonate and will attenuate. ru.

[0564] In the above configuration, the EL layer has a structure having multiple light-emitting layers, or a structure having a single light-emitting layer. It may also be a structure that is such as the above-mentioned tandem type light-emitting device configuration. In combination, multiple EL layers are provided in a single light-emitting device with a charge generation layer in between, and each This may also be applied to configurations in which one or more light-emitting layers are formed on the EL layer.

[0565] The microcavity structure enhances the emission intensity in the front direction at specific wavelengths. This makes it possible to reduce power consumption. In particular, X such as VR or AR For devices designed for R (Radio Wave), the light emitted from the front of the light-emitting device reaches the eyes of the user wearing the device. Because light is often incident on the device, a microcavity structure is provided in the display device for XR applications. It can be said that this is preferable. Furthermore, the image is displayed using four sub-pixels of red, yellow, green, and blue. In the case of a display device, in addition to the brightness enhancement effect of yellow light emission, all sub-pixels emit wavelengths of each color. Because a combined microcavity structure can be applied, a display device with good characteristics can be created. Cut.

[0566] Figure 30(A) shows, as an example, the display device 10 when a microcavity structure is provided. A cross-sectional view of part of 00 is shown. Also, the light-emitting device 150a emits blue (B) light. The light-emitting device 150b has a light-emitting layer that emits green (G) light, and When the optical device 150c has an emissive layer that emits red (R) light, as shown in Figure 30(A) As described above, the film thickness is increased in the order of EL layer 141a, EL layer 141b, and EL layer 141c. Preferably, the EL layer 141a, EL layer 141b, and EL layer 141c The film thickness of layer 4430 contained in each is determined according to the color of light emitted by each light-emitting layer. You can decide that. In this case, layer 4430, which is included in EL layer 141a, will be the thinnest. Layer 4430, which is included in EL layer 141c, is the thickest layer.

[0567] Furthermore, for example, the configuration of the display device 1000 may include a coloring layer (color filter), etc. It may be included. Figure 30(B) shows, as an example, between the resin layer 163 and the substrate 102. This shows a configuration that includes colored layer 166a, colored layer 166b, and colored layer 166c. The colored layers 166a to 166c can be formed, for example, on the substrate 102. It is possible. In addition, the light-emitting device 150a has a light-emitting layer that emits blue (B) light, and the light-emitting device Chair 150b has a light-emitting layer that emits green (G) light, and light-emitting device 150c emits red ( When there is an emissive layer that exhibits the emission of R), the colored layer 166a is made blue and the colored layer 166b is The base color is green, and the colored layer 166c is red.

[0568] The display device 1000 shown in Figure 30(B) is provided with a colored layer 166a to a colored layer 166c. The substrate 102 is connected to the light-emitting device 150a to light-emitting device 15 via the resin layer 163. It can be constructed by bonding it to a substrate 310 that has been formed up to 0c. The light-emitting device 150a and the colored layer 166a are superimposed, and the light-emitting device 150b and the colored layer 1 66b is superimposed, and the light-emitting device 150c and the colored layer 166c are bonded together so that they are superimposed. It is preferable to provide the display device 1000 with a colored layer 166a to a colored layer 166c. For example, the light emitted by the light-emitting device 150b is used to color the colored layer 166a, or color It is not injected onto the substrate 102 via layer 166c, and via the colored layer 166b, onto the substrate 1 It is ejected upwards from 02. That is, diagonally from the light-emitting device 150 of the display device 1000. It is possible to block light in the direction of elevation (when the upper surface of the substrate 102 is considered a horizontal plane). Therefore, the dependence of the display device 1000 on the viewing angle can be reduced, and the display device 1000 This prevents a decrease in the display quality of the image when it is viewed from an oblique angle. .

[0569] Furthermore, the colored layers 166a to 166c formed on the substrate 102 have over It may be covered with a resin or other material called a coating layer. Specifically, the display device 1000 is Resin layer 163, the overcoat layer, colored layers 166a to 166c, substrate 102 The layers may be stacked in the following order (not shown). Note that the resin used for the overcoat layer For example, a translucent material that is based on acrylic resin or epoxy resin. Examples include thermosetting materials.

[0570] Furthermore, for example, the configuration of the display device 1000 includes, in addition to the colored layer, a black matrix S may also be included (not shown). Between colored layer 166a and colored layer 166b, colored layer Between 166b and colored layer 166c, and between colored layer 166c and colored layer 166a, black matrix By providing a space, the light-emitting device 150 of the display device 1000 is directed diagonally (substrate) Because it can better block light in the direction of the elevation angle when the upper surface of 102 is considered a horizontal plane, When the image displayed on the display device 1000 is viewed from an oblique angle, the quality of the display of the image deteriorates. It can be prevented more effectively.

[0571] Furthermore, as shown in Figure 30(B), if the display device has a colored layer, the display device is equipped Light-emitting devices 150a to 150c are all light-emitting devices that emit white light. I...

Claims

1. It has a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a first capacitor, a second capacitor, and a third capacitor. The first gate of the first transistor is electrically connected to the first gate of the fourth transistor. Either the source or drain of the first transistor is electrically connected to either the source or drain of the second transistor, either the source or drain of the fifth transistor, and either the source or drain of the eighth transistor. The source or drain of the fifth transistor is electrically connected to the first gate of the sixth transistor and the first terminal of the second capacitor. The source or drain of the eighth transistor is electrically connected to the first gate of the ninth transistor and the first terminal of the third capacitor. The first gate of the second transistor is electrically connected to the first terminal of the first capacitor, to either the source or drain of the third transistor, to either the source or drain of the fourth transistor, to the second gate of the fifth transistor, to the first gate of the seventh transistor, to the second gate of the eighth transistor, and to the first gate of the tenth transistor. The source or drain of the seventh transistor is electrically connected to the source or drain of the sixth transistor and to the second terminal of the second capacitor. Either the source or drain of the 10th transistor is electrically connected to either the source or drain of the 9th transistor and to the second terminal of the 3rd capacitor. Semiconductor equipment.

2. A gate driver circuit having a shift register including the semiconductor device of claim 1, a source driver circuit, and a pixel array, Display device.

3. An electronic device comprising a display device according to claim 2 and a housing.

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