Image sensor

Abstract

To provide an image sensor with improved aperture ratio. [Solution] The image sensor 3 comprises a first semiconductor substrate 7 including a first photoelectric conversion unit, a second photoelectric conversion unit arranged in the row direction, a first transfer unit for transferring the charge converted by the first photoelectric conversion unit, and a second transfer unit for transferring the charge converted by the second photoelectric conversion unit; a second semiconductor substrate 8 stacked together with the first semiconductor substrate and including a first transfer signal supply unit that supplies a first transfer signal having a voltage lower than the ground voltage of the first semiconductor substrate to the first transfer unit, and a second transfer signal supply unit that supplies a second transfer signal having a voltage lower than the ground voltage of the first semiconductor substrate to the second transfer unit; and a plurality of connection parts that electrically connect the first semiconductor substrate and the second semiconductor substrate, each having conductive members arranged to face each other in the stacking direction in which the first semiconductor substrate and the second semiconductor substrate are stacked, the plurality of connection parts are arranged between the first semiconductor unit and the second semiconductor unit in the stacking direction.

Description

[[Technical Field]]

[0001] The present invention relates to an image sensor. [[Background Art]]

[0002] Conventionally, an image sensor capable of controlling an exposure time for each frame has been known (e.g., Patent Document 1). In order to control the exposure time for each pixel in a conventional image sensor, a power supply that supplies a negative voltage and a power supply that supplies a positive voltage must be arranged for each pixel, which causes a problem that the aperture ratio is reduced. [[Prior Art Literature]] [[Patent Literature]]

[0003] [[Patent Document 1]] Japanese Unexamined Patent Publication No. 2006-180111 [[Summary of the Invention]]

[0004] According to a first aspect, the image sensor comprises: a first semiconductor substrate having a first semiconductor portion including a first photoelectric conversion portion that converts light into electric charge, a second photoelectric conversion portion that converts light into electric charge and is arranged side by side with the first photoelectric conversion portion in a row direction, a first transfer portion that transfers electric charge converted by the first photoelectric conversion portion, and a second transfer portion that transfers electric charge converted by the second photoelectric conversion portion; a second semiconductor substrate stacked together with the first semiconductor substrate, the second semiconductor substrate having a second semiconductor portion including a first transfer signal supply portion that supplies a first transfer signal having a voltage lower than the ground voltage of the first semiconductor substrate to the first transfer portion, and a second transfer signal supply portion that supplies a second transfer signal having a voltage lower than the ground voltage of the first semiconductor substrate to the second transfer portion; and a plurality of connection portions each having conductive members arranged to face each other in the stacking direction where the first semiconductor substrate and the second semiconductor substrate are stacked, the plurality of connection portions electrically connecting the first semiconductor substrate and the second semiconductor substrate, wherein the plurality of connection portions are arranged between the first semiconductor portion and the second semiconductor portion in the stacking direction. [[Brief Description of the Drawings]]

[0005] [Figure 1] A schematic cross-sectional view showing the configuration of the imaging device. [Figure 2] Cross-sectional view of the image sensor [Figure 3] A block diagram schematically showing the structure of a pixel. [Figure 4] Circuit diagrams of the analog circuit section and the pixel drive section. [Figure 5] Timing chart showing imaging sequence using an image sensor [Figure 6] Cross-sectional view of the image sensor [Figure 7] A block diagram schematically showing the configuration of the image sensor. [Modes for carrying out the invention]

[0006] (First Embodiment) Figure 1 is a schematic cross-sectional view showing the configuration of an imaging device using an image sensor according to the first embodiment. The imaging device 1 comprises an imaging optical system 2, an image sensor 3, a control unit 4, a lens drive unit 5, and a display unit 6.

[0007] The imaging optical system 2 forms an image of the subject on the imaging surface of the image sensor 3. The imaging optical system 2 consists of lens 2a, focusing lens 2b, and lens 2c. Focusing lens 2b is a lens used to adjust the focus of the imaging optical system 2. Focusing lens 2b is configured to be drivable in the optical axis O direction.

[0008] The lens drive unit 5 has an actuator (not shown). The lens drive unit 5 drives the focusing lens 2b by a desired amount in the optical axis O direction using this actuator. The image sensor 3 captures an image of the subject and outputs the image. The control unit 4 controls each part, including the image sensor 3. The control unit 4 performs image processing on the image signal output by the image sensor 3 and records it on a recording medium (not shown) or displays the image on the display unit 6. The display unit 6 is a display device having a display element such as a liquid crystal panel.

[0009] Figure 2 is a cross-sectional view of the image sensor 3. Note that Figure 2 shows only a portion of the image sensor 3 as a whole. The image sensor 3 is a so-called back-illuminated image sensor. The image sensor 3 converts incident light from the plane of the paper into photoelectric energy. The image sensor 3 comprises a first semiconductor substrate 7 and a second semiconductor substrate 8.

[0010] The first semiconductor substrate 7 comprises a PD layer 71 and a wiring layer 72. The PD layer 71 is located on the back side of the wiring layer 72. Multiple embedded photodiodes 31 are arranged in a two-dimensional manner on the PD layer 71. Therefore, the surface of the PD layer 71 on the wiring layer 72 side (i.e., the side opposite to the incident light side) has the opposite conductivity to that of the PD layer 71. For example, if the PD layer 71 is an N-type semiconductor layer, then a P-type semiconductor layer with high density and thin thickness is arranged on the surface on the wiring layer 72 side. A ground voltage (GND) is applied to the first semiconductor substrate 7 as the substrate voltage. Various circuits for reading signals from the photodiodes 31 are arranged on the second semiconductor substrate 8. Specifically, the A / D conversion unit 302, sampling unit 303, pixel value holding unit 304, and calculation unit 305, which will be described later, and a part of the pixel driving unit 307 (the transfer signal supply unit 307a and the second reset signal supply unit 307c, which handle the voltage Vneg, will be described later) are arranged on the second semiconductor substrate 8.

[0011] The image sensor 3 includes a power supply unit 94, which is a first voltage source, that supplies a first voltage, Vneg, to each pixel 30. The voltage Vneg is lower than the substrate voltage of the first semiconductor substrate 7. In this embodiment, the substrate voltage of the first semiconductor substrate 7 is the ground voltage. Therefore, the voltage Vneg is a negative voltage lower than the ground voltage. The power supply unit 94 is not provided individually for each pixel 30, but rather one unit is provided in common for multiple pixels 30.

[0012] If a power supply unit is individually provided for each pixel 30 to supply a voltage Vneg lower than the substrate voltage of the first semiconductor substrate 7, the image sensor would require a complex circuit. This could potentially worsen the yield of the image sensor. The image sensor 3 according to this embodiment, as described later, can supply voltage Vneg to each pixel 30 from outside the pixel 30 with a simple configuration, thus eliminating this concern.

[0013] As will be explained in more detail later, a voltage Vneg lower than the substrate voltage of the first semiconductor substrate 7 is required to prevent charge from being transferred from the photodiode 31 to the floating diffusion FD when the transfer transistor Tx is off.

[0014] In this embodiment, the power supply unit 94 that supplies the voltage Vneg is provided on the first semiconductor substrate 7. However, the power supply unit 94 may be provided in a location other than the first semiconductor substrate 7. For example, the power supply unit 94 may be provided on the second semiconductor substrate 8, and the voltage Vneg may be supplied to the first semiconductor substrate 7 via bumps, and each pixel 30 may be electrically connected to it.

[0015] Multiple color filters 73, corresponding to each of the multiple photodiodes 31, are provided on the incident light side of the PD layer 71. There are multiple types of color filters 73 that transmit wavelengths corresponding to, for example, red (R), green (G), and blue (B). For example, three types of color filters 73 corresponding to red (R), green (G), and blue (B) are arranged to form a Bayer array.

[0016] Multiple microlenses 74, corresponding to each of the multiple color filters 73, are provided on the incident light side of the color filter 73. The microlenses 74 focus the incident light toward the corresponding photodiode 31. The incident light that has passed through the microlenses 74 is filtered by the color filter 73 to filter only a portion of the wavelength range before being incident on the photodiode 31. The photodiode 31 converts the incident light into electricity to generate an electric charge.

[0017] A plurality of bumps 75 are arranged on the surface of the wiring layer 72. A plurality of bumps 76 corresponding to the plurality of bumps 75 are arranged on a surface of the second semiconductor substrate 8 facing the wiring layer 72. The plurality of bumps 75 and the plurality of bumps 76 are bonded to each other. The first semiconductor substrate 7 and the second semiconductor substrate 8 are electrically connected to each other via the plurality of bumps 75 and the plurality of bumps 76.

[0018] As will be described in detail later, the image sensor 3 has a plurality of pixels 30. One pixel 30 includes a first pixel 30x provided on the first semiconductor substrate 7 and a second pixel 30y provided on the second semiconductor substrate 8. One first pixel 30x includes one microlens 74, one color filter 73, one photodiode 31, and the like. The first pixel 30x further includes various circuits (described later) provided on the first semiconductor substrate 7, such as an individual power supply unit 341 which is a second voltage source that supplies a voltage V1 which is a second voltage. The second pixel 30y includes various circuits (described later) provided on the second semiconductor substrate 8.

[0019] FIG. 3 is a block diagram schematically showing the configuration of the pixel 30. The pixel 30 includes an analog circuit unit 301, an A / D conversion unit 302, a sampling unit 303, a pixel value holding unit 304, a pixel driving unit 307, an individual pixel control unit 306, and an arithmetic unit 305.

[0020] The analog circuit unit 301 photoelectrically converts incident light and outputs the result as an analog signal to the A / D conversion unit 302. The A / D conversion unit 302 samples the analog signal output from the analog circuit unit 301, and outputs a digital signal multiplied by a predetermined gain. The A / D conversion unit 302 repeatedly samples the pixel reset signal and the pixel signal, and individually outputs the sampling result of the pixel reset signal and the sampling result of the pixel signal as digital signals, respectively.

[0021] The sampling unit 303 calculates and holds an integral value of the sampling result of the pixel reset signal and the sampling result of the pixel signal. The sampling unit 303 includes a first adder 308 and a first memory 309 for pixel reset signals, and a second adder 310 and a second memory 311 for pixel signals.

[0022] The sampling unit 303 causes the first adder 308 to add the sampling result of the pixel reset signal output by the A / D conversion unit 302 and the integral value of past sampling results held in the first memory 309. The sampling unit 303 stores this addition result in the first memory 309. The sampling unit 309 updates the value stored in the first memory 309 every time the A / D conversion unit 302 outputs a sampling result of the pixel reset signal.

[0023] The sampling unit 303 causes the second adder 310 to add the sampling result of the pixel signal output by the A / D conversion unit 302 and the integral value of past sampling results held in the second memory 311. The sampling unit 303 stores this addition result in the second memory 311. The sampling unit 303 updates the value stored in the second memory 311 every time the A / D conversion unit 302 outputs a sampling result of the pixel signal.

[0024] As described above, the A / D conversion unit 302 and the sampling unit 303 execute a process of repeatedly sampling the pixel reset signal and the pixel signal, and integrating the sampling results. This process is a so-called correlated multiple sampling process.

[0025] When the individual pixel control unit 306 completes a predetermined number of samplings, the sampling unit 303 outputs a digital value based on the value stored in the first memory 309 and the value stored in the second memory 311 to the pixel value holding unit 304. The pixel value holding unit 304 stores this digital value as the result of photoelectric conversion by the pixel 30. The pixel value holding unit 304 is connected to the signal line 340. The digital value stored in the pixel value holding unit 304 can be read out from the outside via the signal line 340.

[0026] The calculation unit 305 calculates the number of repetitions, exposure time, gain, etc., in the correlated multiplexing process based on the exposure time instructed from the outside and the previous photoelectric conversion result held in the pixel value holding unit 304. The individual pixel control unit 306 outputs the number of repetitions and gain calculated by the calculation unit 305 to the A / D conversion unit 302. The individual pixel control unit 306 outputs the exposure time and gain calculated by the calculation unit 305 to the pixel drive unit 307. The pixel drive unit 307 outputs various drive signals (described later) to drive each part of the analog circuit unit 301 to the analog circuit unit 301.

[0027] Figure 4 is a circuit diagram of the analog circuit section 301, the individual pixel control section 306, and the pixel drive section 307. For convenience, only parts of the individual pixel control section 306 and the pixel drive section 307 are shown in Figure 4. Parts of the individual pixel control section 306 are denoted as 306a, 306b, etc., and parts of the pixel drive section 307 are denoted as 307a, 307b, etc.

[0028] The analog circuit section 301 includes a photodiode 31, a transfer transistor Tx, a floating diffusion transistor FD, a first reset transistor RST1, a second reset transistor RST2, an amplification transistor AMI, a selection transistor SEL, a capacitance expansion transistor FDS, and a capacitance C1.

[0029] The photodiode 31 is a photoelectric conversion unit that converts incident light into photoelectric energy and generates an amount of charge corresponding to the amount of incident light. The transfer transistor Tx is a transfer unit that transfers the charge generated by the photodiode 31 to the floating diffusion FD based on a transfer signal supplied from the transfer signal supply unit 307a, which will be described later. The floating diffusion FD is a storage unit that stores the charge transferred by the transfer transistor Tx. The amplification transistor AMI outputs a signal corresponding to the amount of charge stored in the floating diffusion FD. When the selection transistor SEL is turned on, the signal output by the amplification transistor AMI is input to the A / D conversion unit 302.

[0030] The analog circuit section 301 has two reset transistors: a first reset transistor RST1 and a second reset transistor RST2. When resetting the floating diffusion FD, the first reset transistor RST1 receives a first reset signal from the first reset signal supply unit 307b, which will be described later. The first reset signal supply unit 307b, which will be described later, supplies a voltage VDD signal as the first reset signal. Based on this first reset signal, the first reset transistor RST1 resets the floating diffusion FD. When resetting the photodiode 31, the second reset transistor RST2 receives a second reset signal from the second reset signal supply unit 307c, which will be described later. The second reset signal supply unit 307c, which will be described later, supplies a voltage VDD signal as the second reset signal. Based on this second reset signal, the second reset transistor RST2 resets the photodiode 31.

[0031] The capacitance expansion transistor FDS switches the connection between the floating diffusion FD and the capacitor C1 based on the capacitance expansion signal supplied from the capacitance expansion signal supply unit 307d, which will be described later. For example, if the amount of incident light on the photodiode 31 is large and the floating diffusion FD becomes saturated, the capacitance expansion transistor FDS is turned on to connect the floating diffusion FD and the capacitor C1. As a result, the capacitance of the floating diffusion FD is effectively increased by the amount of capacitor C1, allowing it to handle larger light intensities.

[0032] The first reset signal supply unit 307b is a CMOS circuit consisting of a pMOS transistor Tr7 and an nMOS transistor Tr8. Based on the output signal of the first reset control unit 306b, the first reset signal supply unit 307b supplies either a voltage VDD (a predetermined power supply voltage; the same applies hereinafter) or a ground voltage (GND) as the first reset signal to the gate of the first reset transistor RST1. As described above, the first reset control unit 306b is part of the individual pixel control unit 306, and the first reset signal supply unit 307b is part of the pixel drive unit 307. When overdrive is performed, the first reset control unit 306b should supply a voltage VRST1H, which is higher than the voltage VDD, to the gate of the first reset transistor RST1 instead of the voltage VDD.

[0033] The capacitance expansion signal supply unit 307d is a CMOS circuit consisting of a pMOS transistor Tr11 and an nMOS transistor Tr12. Based on the output signal of the capacitance expansion control unit 306d, the capacitance expansion signal supply unit 307d supplies either the voltage VDD or the ground voltage (GND) as a capacitance expansion signal to the gate of the capacitance expansion transistor FDS. As described above, the capacitance expansion control unit 306d is part of the individual pixel control unit 306, and the capacitance expansion signal supply unit 307d is part of the pixel drive unit 307.

[0034] The transfer signal supply unit 307a includes a buffer 340, a resistor R1, and a resistor R2. The transfer control signal is supplied to the buffer 340 by the transfer control unit 306a. The transfer control unit 306a outputs either a predetermined high-level voltage (e.g., voltage VDD) or a low-level voltage (e.g., the ground voltage, which is the substrate voltage of the first semiconductor substrate 7) as the transfer control signal to the buffer 340. If the transfer control signal is a high-level voltage, the buffer 340 outputs a voltage V1 supplied from the individual power supply unit 341 in the pixel 30, and if it is a low-level voltage, it outputs the ground voltage, which is the substrate voltage of the first semiconductor substrate 7. Voltage V1 is a voltage higher than the substrate voltage of the first semiconductor substrate 7. In this embodiment, the substrate voltage of the first semiconductor substrate 7 is the ground voltage. Therefore, voltage V1 is a positive voltage higher than the ground voltage.

[0035] The output terminal of buffer 340 is connected to the gate of transfer transistor Tx via resistor R2. Power supply unit 94 supplies voltage Vneg between resistor R2 and transfer transistor Tx via resistor R1. In other words, from the perspective of transfer transistor Tx, the wiring from the gate electrode branches into two: power supply unit 94 is connected to one via resistor R1, and buffer 340 is connected to the other via resistor R2.

[0036] When buffer 340 is outputting voltage V1, a voltage Vg1 determined by equation (1) is applied to the gate of transfer transistor Tx. In equation (1), r1 is the resistance value of resistor R1, and r2 is the resistance value of resistor R2. Vg1=(Vneg×r2+V1×r1) / (r1+r2) ···(1)

[0037] For example, if Vneg is -2V, V1 is 8V, and r1 is equal to r2, then the voltage Vg1 will be 3V. In other words, when buffer 340 outputs voltage V1, a positive voltage of 3V is applied to the gate of transfer transistor Tx, and transfer transistor Tx turns on. In other words, when the transfer control signal is a high-level voltage, transfer transistor Tx transfers the charge generated by photodiode 31 to floating diffusion FD.

[0038] On the other hand, when buffer 340 is outputting a ground voltage, a voltage Vg2 determined by equation (2) is applied to the gate of transfer transistor Tx. Vg2=(Vneg×r2) / (r1+r2) ···(2)

[0039] For example, if Vneg is -2V and r1 is equal to r2, then the voltage Vg2 will be -1V. In other words, when buffer 340 outputs the ground voltage, which is the substrate voltage of the first semiconductor substrate 7, a negative voltage of -1V, which is lower than the substrate voltage of the first semiconductor substrate 7, is applied to the gate of the transfer transistor Tx, and the transfer transistor Tx is turned off. In other words, when the transfer control signal is a low-level voltage, the transfer transistor Tx does not transfer the charge generated by the photodiode 31 to the floating diffusion FD.

[0040] The transfer signal supply unit 307a, configured as described above, supplies either a positive voltage or a voltage lower than the substrate voltage of the first semiconductor substrate 7 (a negative voltage in this embodiment) as a transfer signal to the gate of the transfer transistor Tx based on the output signal of the transfer control unit 306a. As previously mentioned, the transfer control unit 306a is part of the individual pixel control unit 306, and the transfer signal supply unit 307a is part of the pixel driving unit 307. The reason for applying a voltage lower than the substrate voltage of the first semiconductor substrate 7 to the gate of the transfer transistor Tx is to prevent charge from being transferred from the photodiode 31 to the floating diffusion FD when the transfer transistor Tx is off.

[0041] The second reset signal supply unit 307c has a buffer 350, a resistor R3, and a resistor R4. Based on the output signal of the second reset control unit 306c, the second reset signal supply unit 307c supplies either a positive voltage or a voltage lower than the substrate voltage of the first semiconductor substrate 7 (a negative voltage in this embodiment) as a second reset signal to the gate of the second reset transistor RST2. The configuration of the second reset signal supply unit 307c is the same as that of the transfer signal supply unit 307a, so its description is omitted. As mentioned above, the second reset control unit 306c is part of the individual pixel control unit 306, and the second reset signal supply unit 307c is part of the pixel drive unit 307.

[0042] Next, the layout of each component shown in Figures 3 and 4 on the semiconductor substrate will be described. The first semiconductor substrate 7 will contain the analog circuit section 301, the transfer drive section 307a, and the individual power supply section 341 (Figure 4) from the components shown in Figures 3 and 4. The second semiconductor substrate 8 will contain the remaining components from the components shown in Figures 3 and 4.

[0043] This approach was taken to make the photodiode 31 as large as possible. In this embodiment, since the parts of the pixel 30 are arranged on the second semiconductor substrate 8 as much as possible, the area of ​​the photodiode 31 can be increased, which is expected to improve the efficiency of incident light utilization and increase the saturation electron number.

[0044] Figure 5 is a timing chart showing the imaging sequence using the image sensor 3. The image sensor 3 can selectively perform multiple exposure and correlated multiple sampling. First, we will explain the multiple exposure control using Figure 5(a).

[0045] Figure 5(a) is a timing chart for multiple exposures of each of the 30 pixels. The horizontal axis in Figure 5(a) represents time, with time progressing to the right. The rectangle labeled "Dark" in Figure 5(a) indicates the timing at which the A / D conversion unit 302 samples the pixel reset signal. The rectangle labeled "Sig" in Figure 5(a) indicates the timing at which the A / D conversion unit 302 samples the pixel signal. The rectangle labeled "Out" in Figure 5(a) indicates the timing at which the pixel value holding unit 304 outputs the stored digital value (photoelectric conversion result) to the peripheral circuit via the signal line 340. In Figure 5(a), the pixels 30 are classified into four categories, pixels 30a to 30d, based on the amount of incident light, and multiple exposures are performed.

[0046] The operation of resetting the photodiode 31 and the floating diffusion FD at the start time t0 of the exposure period T1 is the same for all pixels 30. Subsequently, for pixels 30a with extremely low incident light levels, the floating diffusion FD is reset at time t3, and the pixel reset signal is sampled. Time t3 is the time obtained by subtracting the time required for resetting the floating diffusion FD and sampling the pixel reset signal from the end time t4 of the exposure period T1. At the end time t4 of the exposure period T1, the charge accumulated in the photodiode 31 generated from time t0 to t4 is transferred to the floating diffusion FD, and the pixel signal is sampled. Subsequently, at time t5, the photoelectric conversion result is stored in the pixel value holding unit 304.

[0047] For pixel 30b, where the amount of incident light is slightly less, the externally specified exposure period T1 is divided equally into two periods, T2 and T3, and the above operation is performed twice. Specifically, at times t1 and t3, the floating diffusion FD is reset and the pixel reset signal is sampled. Time t1 is the time obtained by subtracting the time required for resetting the floating diffusion FD and sampling the pixel reset signal from the end time t2 of period T2. Then, at time t2, the charge accumulated in the photodiode 31 is transferred to the floating diffusion FD and the pixel signal is sampled. The operation at times 3 to t5 is the same as in the case of pixel 30a.

[0048] For pixel 30c, where the amount of incident light is slightly high, the externally specified exposure period T1 is divided into four equal parts, and the above operation is performed four times. For pixel 30d, where the amount of incident light is extremely high, the externally specified exposure period T1 is divided into eight equal parts, and the above operation is performed eight times.

[0049] As described above, with multiple exposure control, imaging can be performed by individually changing the exposure time for pixels 30 with a high amount of incident light and pixels 30 with a low amount of incident light. Even when the amount of incident light is so high that the floating diffusion FD would saturate in normal imaging, the dynamic range can be expanded by dividing the exposure time into small segments and repeatedly performing imaging.

[0050] Next, correlated multiplexing control will be explained using Figure 5(b). Figure 5(b) is a timing chart for when correlated multiplexing control is performed for each pixel 30. The horizontal axis in Figure 5(b) is time, and time progresses to the right. The rectangle labeled "Dark" in Figure 5(b) indicates the timing when the A / D conversion unit 302 samples the pixel reset signal. The rectangle labeled "Sig" in Figure 5(b) indicates the timing when the A / D conversion unit 302 samples the pixel signal. The rectangle labeled "Out" in Figure 5(b) indicates the timing when the A / D conversion unit 302 outputs the sampling result to the sampling unit 303. In Figure 5(b), the pixels 30 are classified into four types, pixels 30a to 30d, based on the amount of incident light, and correlated multiplexing is performed.

[0051] Pixel 30a has the longest exposure time, and pixel 30d has the shortest exposure time. In correlated multiplexing control, the longer the exposure time of a pixel 30, the earlier the floating diffusion FD is reset. The longer the exposure time of a pixel 30, the longer the time between resetting the floating diffusion FD and sampling the pixel signal. During that period, the pixel reset signal is repeatedly sampled.

[0052] For example, in Figure 5(b), pixel 30a has the longest exposure time. The floating diffusion FD is reset at time t7, which is 5 units before the end time t6 of exposure time T4 for pixel 30a. As a result, the pixel reset signal is sampled 4 times by time t6. After exposure time T4 ends, the pixel signal is repeatedly sampled until the end of the next exposure time T6.

[0053] A longer exposure time means a lower amount of incident light, which in turn means that the noise from the amplification transistor AMI, the selection transistor SEL, and the A / D conversion unit 302 has a greater impact on the pixel signal. In other words, pixels 30 that are more affected by the aforementioned noise will have their pixel reset signal and pixel signal sampled more times, allowing for higher sensitivity imaging.

[0054] The image sensor 3 performs the above operations in parallel for each of its pixels 30. That is, each pixel 30 performs the operations in parallel, from photoelectric conversion by the photodiode 31 to the storage of the digital value in the pixel value holding unit 304. The imaging results are read out from the pixel value holding unit 304 sequentially for each pixel 30.

[0055] As described above, the image sensor 3 of this embodiment can control the exposure time for each pixel. In order to control the exposure time for each pixel, the on / off timing of the transfer transistor Tx must be controllable for each pixel. That is, the voltage supplied to the gate of the transfer transistor Tx (voltages V1 and Vg1 and Vg2 based on voltage Vneg in this embodiment) must be controllable for each pixel. In other words, a first power supply unit that supplies voltage Vneg and a second power supply unit that supplies voltage V1 must be provided for each pixel. Since the voltage handled by the first semiconductor substrate 7 is different from voltages Vneg and V1, if the first and second power supply units are to be placed within the pixel 30, the first and second power supply units will occupy a large area. In particular, since the first power supply unit handles voltage Vneg which is lower than the substrate voltage, a triple-well structure is required so as not to be forward-biased with respect to the substrate. Therefore, the first power supply unit requires a particularly large area. As a result, the area of ​​the photodiode 31 in the pixel 30 becomes significantly smaller. In other words, the aperture ratio of the photodiode 31 is significantly reduced, making it difficult to miniaturize the image sensor. In this embodiment, by providing the first power supply unit, power supply unit 94, as a common power supply for all pixels and located outside the pixels, the exposure time can be controlled for each pixel without individually providing the first power supply unit and the second power supply unit near the photodiode 31 on the first semiconductor substrate 7 (without reducing the aperture ratio of the photodiode 31). Furthermore, the image sensor can be miniaturized.

[0056] According to the above-described embodiment, the following effects and advantages can be obtained. (1) The image sensor 3 comprises a power supply unit 94 that supplies a negative voltage and a plurality of pixels 30. Each of the plurality of pixels 30 includes a photodiode 31 that converts incident light into photoelectricity, a floating diffusion FD that stores the charge converted into photoelectricity by the photodiode 31, a transfer transistor Tx that transfers the charge converted into photoelectricity by the photodiode 31 to the floating diffusion FD based on a transfer signal, an individual power supply unit 341 that supplies a positive voltage, and a transfer signal supply unit 307a that supplies either a first voltage lower than the ground voltage or a second voltage higher than the ground voltage as a transfer signal to the transfer transistor Tx based on the negative voltage supplied by the power supply unit 94 and the positive voltage supplied by the individual power supply unit 341. In this way, parallel readout of each pixel can be performed without providing a power supply to supply a negative voltage to each pixel 30.

[0057] (2) The first semiconductor substrate 7 is provided with a photodiode 31, a transfer transistor Tx, a floating diffusion FD, a transfer signal supply unit 307a, and an individual power supply unit 341. The second semiconductor substrate 8 is provided with an A / D conversion unit 302 and a sampling unit 303. In this way, the circuit for handling the negative power supply is provided on the second semiconductor substrate 8 and not present on the first semiconductor substrate 7, so there is no need to provide a diffusion layer or the like for handling the negative power supply on the first semiconductor substrate 7, and the aperture ratio of the photodiode 31 can be improved.

[0058] (3) A transfer control signal consisting of a ground voltage and a positive voltage is input to the transfer signal supply unit 307a. The transfer signal supply unit 307a converts the transfer control signal into a transfer signal consisting of a negative voltage and a positive voltage and outputs it. In this way, a transfer signal including a negative voltage can be supplied without introducing any special circuit elements for handling negative voltages.

[0059] (4) Each of the multiple pixels 30 has a resistor R1 connected to the power supply unit 94 at one end and the transfer transistor Tx at the other end, and a resistor R2 to which a transfer signal is input at one end and which is connected to the transfer transistor Tx at the other end. In this way, the magnitude of the voltage supplied to the transfer transistor Tx can be easily controlled by a potential division circuit using the combination of resistance values ​​of resistors R1 and R2.

[0060] (Second Embodiment) Unlike the image sensor 3 of the first embodiment, the image sensor 3 of the second embodiment does not have a second semiconductor substrate 8, but only a single semiconductor substrate 70. The following description will focus on the differences between the image sensor 3 of the second embodiment and the image sensor 3 of the first embodiment. Parts identical to those of the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0061] Figure 6 is a cross-sectional view of the image sensor 3. Note that Figure 6 shows only a portion of the image sensor 3 as a whole. The image sensor 3 is a so-called back-illuminated image sensor. The image sensor 3 converts incident light from the direction of the paper plane into photoelectric light.

[0062] The image sensor 3 has multiple pixels 30. Each pixel 30 includes a microlens 74 and a color filter 73 as shown in Figure 6. In addition to these, the pixel 30 also includes an analog circuit section 301, an A / D conversion section 302, a sampling section 303, a pixel value holding section 304, a calculation section 305, an individual pixel control section 306, and a pixel driving section 307 as shown in Figure 4. These areas are located in area 710. Reference numeral 720 denotes a wiring layer.

[0063] Figure 7 is a schematic block diagram showing the configuration of the image sensor 3. The semiconductor substrate 70 is provided with a plurality of pixels 30 arranged in a two-dimensional manner. In Figure 7, only a total of nine pixels 30 arranged in 3 rows and 3 columns are shown among the plurality of pixels 30 provided on the semiconductor substrate 70.

[0064] The semiconductor substrate 70 includes a power supply unit 94, which is a first voltage source, that supplies a first voltage, Vneg, to each pixel 30. The voltage Vneg is lower than the substrate voltage of the first semiconductor substrate 7. In this embodiment, the substrate voltage of the first semiconductor substrate 7 is the ground voltage. Therefore, the voltage Vneg is a negative voltage lower than the ground voltage. The power supply unit 94 is not provided individually for each pixel 30, but rather one unit is provided in common for multiple pixels 30.

[0065] Each of the multiple pixels 30 is provided with an individual power supply unit 341 that supplies a predetermined voltage V1. An individual power supply unit 341 is provided for each pixel 30. The voltage V1 supplied by the individual power supply unit 341 is a voltage higher than the substrate voltage of the first semiconductor substrate 7. In this embodiment, the substrate voltage of the first semiconductor substrate 7 is the ground voltage. Therefore, the voltage V1 is a positive voltage higher than the ground voltage.

[0066] According to the above-described embodiment, in addition to the effects and advantages described in the first embodiment, the following further effects and advantages can be obtained. (5) All parts constituting the pixels 30 are provided on a single semiconductor substrate 70. This reduces the manufacturing cost of the image sensor 3. In addition, the process of stacking multiple semiconductor substrates can be omitted, simplifying the manufacturing process.

[0067] The following modifications are also within the scope of the present invention, and it is possible to combine one or more of these modifications with the embodiments described above.

[0068] (Variation 1) A switch may be provided between the power supply unit 94 and the multiple pixels 30 to turn the electrical connection between the power supply unit 94 and the multiple pixels 30 on and off. When this switch is turned off, the current flowing from the multiple pixels 30 to the power supply unit 94 is interrupted. By providing this switch, when imaging is not being performed, no current flows between the power supply unit 94 and the transfer signal supply unit 307a, thereby reducing power consumption. If the electrical connection with the power supply unit 94 is to be turned on and off at the same timing for all pixels 30, only one switch needs to be provided before the power supply unit 94. Alternatively, the power supply unit 94 may have the above-mentioned switch built into it.

[0069] (Modification 2) In each of the embodiments described above, a capacitor, coil, or the like may be used instead of the resistor R1. The signal output from buffer 340 is a signal with a constant frequency, and a potential division circuit can be constructed by combining any impedance of capacitors, coils, etc.

[0070] (Variation 3) In the first embodiment, resistor R1 may be a silicon through-electrode connecting the first semiconductor substrate 7 and the second semiconductor substrate. This makes it easy to set the resistance value of resistor R1 to a desired value.

[0071] Although various embodiments and modifications have been described above, the present invention is not limited to these. Other embodiments conceivable within the scope of the technical idea of ​​the present invention are also included within the scope of the present invention. The embodiments and modifications described above also include the following image sensors and electronic cameras. (1) An image sensor comprising a first voltage source that supplies a first voltage and a plurality of pixels to which the first voltage is supplied, wherein each pixel includes a photoelectric conversion unit that converts incident light into photoelectric energy, a storage unit to which the charge converted into photoelectric energy by the photoelectric conversion unit is transferred and stored, a transfer unit that transfers the charge from the photoelectric conversion unit to the storage unit, a second voltage source that supplies a second voltage, and a supply unit that supplies a transfer signal to the transfer unit, which is either the first voltage from the first voltage source or the second voltage from the second voltage source. (2) In an image sensor as described in (1), the supply unit includes a first resistor disposed between the first voltage source and the transfer unit, and a second resistor disposed between the second voltage source and the transfer unit. (3) In an image sensor as described in (2), a substrate voltage is applied to the image sensor, the first voltage source supplies a voltage lower than the substrate voltage, and the second voltage source supplies a voltage higher than the substrate voltage. (4)(3) In an image sensor as described above, the transfer unit electrically conducts between the photoelectric conversion unit and the storage unit to transfer the charge generated by the photoelectric conversion unit to the storage unit, and the supply unit supplies a transfer signal to the transfer unit to electrically conduct or deconduct between the photoelectric conversion unit and the storage unit. (5) An image sensor as described in (3) or (4) comprises a first semiconductor substrate on which the above-mentioned plurality of pixels are provided, and a second semiconductor substrate on which an A / D conversion unit is provided for each of the plurality of pixels, which outputs a digital signal based on the amount of charge stored in the storage unit. In an image sensor as described in (6)(5), the first voltage source is provided on the second semiconductor substrate, and the first resistor includes at least an electrode connecting the first semiconductor substrate and the second semiconductor substrate. In an image sensor as described in (7)(3)~(5), the supply unit has a capacitor that is placed between the first voltage source and the transfer unit. (8) In an image sensor as described in (3) to (7), some of the multiple supply units transfer the charge generated by the photoelectric conversion unit during a first period to the storage unit, and some of the other supply units transfer the charge generated by the photoelectric conversion unit during a second period of a different length from the first period to the storage unit. (9)(3)~(8) In an image sensor as described above, the photoelectric conversion unit is an embedded photodiode, and the transfer unit transfers the charge photoelectrically converted by the photoelectric conversion unit to the storage unit when the transfer signal is a first voltage based on the voltage supplied by the first voltage source, and does not transfer the charge photoelectrically converted by the photoelectric conversion unit to the storage unit when the transfer signal is a second voltage based on the voltage supplied by the first voltage source. In an image sensor as described in (10)(3)~(9), the supply unit receives either a third voltage greater than or equal to the substrate voltage or a fourth voltage greater than or equal to the substrate voltage and higher than the third voltage. When the third voltage is received, the supply unit outputs the transfer signal which is the first voltage, and when the fourth voltage is received, it supplies the transfer signal which is the second voltage. (11) In an image sensor as described in (1) to (10), each of the plurality of pixels has a switching unit that electrically conducts or deconducts between the supply unit and the first voltage source. (12) An electronic camera having an image sensor like those in (1) to (11).

[0072] Furthermore, the embodiments and modifications described above also include the following image sensors. (1) An image sensor comprising a plurality of pixels, each having a negative voltage power supply unit that supplies a negative voltage, a photoelectric conversion unit that converts incident light into photoelectric energy, a storage unit that stores the charge converted into photoelectric energy by the photoelectric conversion unit, a transfer unit that transfers the charge converted into photoelectric energy by the photoelectric conversion unit to the storage unit based on a transfer signal, a positive voltage power supply unit that supplies a positive voltage, and a transfer signal supply unit that supplies either a first voltage lower than the ground voltage or a second voltage higher than the ground voltage to the transfer unit as a transfer signal based on the negative voltage supplied by the negative voltage power supply unit and the positive voltage supplied by the positive voltage power supply unit. (2) An image sensor as described in (1) comprises a first semiconductor substrate on which the plurality of pixels are provided, and a second semiconductor substrate on which an A / D conversion unit is provided for each of the plurality of pixels, which outputs a digital signal based on the amount of charge stored in the storage unit. (3) In an image sensor as described in (2), the transfer signal supply unit includes a first resistor with one end connected to the negative voltage power supply unit and the other end connected to the transfer unit, and a second resistor with the transfer signal input from one end and the other end connected to the transfer unit. (4) In an image sensor as described in (3), the negative voltage power supply unit is provided on the second semiconductor substrate, and the first resistor includes at least an electrode connecting the first semiconductor substrate and the second semiconductor substrate. (5) In an image sensor as described in (1) or (2), the transfer signal supply unit has a capacitor with one end connected to the negative voltage power supply unit and the other end connected to the transfer unit. (6) In an image sensor as described in (1) to (5), some of the transfer signal supply units transfer the charge generated by the photoelectric conversion unit during a first period to the storage unit, and some of the transfer signal supply units transfer the charge generated by the photoelectric conversion unit during a second period of a different length from the first period to the storage unit. (7) In an image sensor as described in (1) to (6), the photoelectric conversion unit is an embedded photodiode, and the transfer unit transfers the charge photoelectrically converted by the photoelectric conversion unit to the storage unit when the transfer signal is the first voltage, and does not transfer the charge photoelectrically converted by the photoelectric conversion unit to the storage unit when the transfer signal is the second voltage. (8) In an image sensor as described in (1) to (7), the transfer signal supply unit receives either a third voltage which is greater than or equal to the ground voltage or a fourth voltage which is greater than or equal to the ground voltage and higher than the third voltage as a drive signal. The transfer signal supply unit outputs the transfer signal which is the first voltage when the drive signal is the third voltage, and outputs the transfer signal which is the second voltage when the drive signal is the fourth voltage. (9) In an image sensor as described in (1) to (8), each of the plurality of pixels has a switching unit that turns on and off the electrical connection between the transfer signal supply unit and the negative voltage power supply unit.

[0073] The disclosures of the following priority application are incorporated herein by reference. Japanese Patent Application No. 195283 of 2015 (filed September 30, 2015) [Explanation of Symbols]

[0074] 3…Image sensor, 7…First semiconductor substrate, 8…Second semiconductor substrate, 30…Pixel, 31…Photodiode, 70…Semiconductor substrate, 301…Analog circuit section, 302…A / D conversion section, 303…Sampling section, 306…Individual pixel control section, 307…Pixel driving section

Claims

[Claim 1] A first semiconductor substrate having a first semiconductor section including a first photoelectric conversion unit that converts light into electric charge, a second photoelectric conversion unit that converts light into electric charge and is arranged in the row direction alongside the first photoelectric conversion unit, a first transfer unit that transfers the charge converted by the first photoelectric conversion unit, and a second transfer unit that transfers the charge converted by the second photoelectric conversion unit, A second semiconductor substrate laminated together with the first semiconductor substrate, the second semiconductor substrate having a second semiconductor section including a first transfer signal supply section that supplies a first transfer signal having a voltage lower than the ground voltage of the first semiconductor substrate to the first transfer section, and a second transfer signal supply section that supplies a second transfer signal having a voltage lower than the ground voltage of the first semiconductor substrate to the second transfer section, Each of the first semiconductor substrate and the second semiconductor substrate has conductive members arranged to face each other in the stacking direction in which they are stacked, and a plurality of connection parts that electrically connect the first semiconductor substrate and the second semiconductor substrate. Equipped with, The plurality of connecting portions are arranged between the first semiconductor portion and the second semiconductor portion in the stacking direction. Image sensor.

Images