Chip binning system and method
Patent Information
- Application Number
- JP2025100698
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-02-24
- Filing Date
- 2025-06-17
- Publication Date
- 2026-09-03
Smart Images
Figure 2026140769000001_ABST
Abstract
Description
[Technical Field]
[0001] The present disclosure relates to a chip binning system and method, and in particular to a multiple-time chip binning system and method. [Background Art]
[0002] When binning chips, a clustering algorithm, such as the K-means algorithm, is often used to perform clustering based on chip feature data, which is achieved by minimizing intra-cluster variation. However, when processing chip feature data, the influence of power changes cannot be efficiently controlled and taken into consideration. If it is assumed that all clusters are the same, minute differences and abnormalities between chips cannot be identified. Therefore, a chip binning method that takes into account influences such as chip binning efficiency and can identify minute differences is necessary to improve the efficiency and accuracy of chip binning. [Summary of Invention]
[0003] The present disclosure provides a chip binning system, comprising: a chip analysis database for storing a plurality of pieces of chip analysis data corresponding to a plurality of chips; and a chip binning server communicatively connected to the chip analysis database to receive the plurality of pieces of chip analysis data. The chip binning server includes: a feature generation module for generating a plurality of corresponding pieces of chip feature data based on the plurality of pieces of chip analysis data; a first binning module for generating a plurality of corresponding chip performances based on the plurality of corresponding pieces of chip feature data, and performing first binning on the plurality of chips based on the plurality of chip performances to generate first binning data; a second binning module for performing second binning on the plurality of chips in each bin in the first binning data based on a plurality of corresponding chip powers in the plurality of pieces of chip analysis data to generate second binning data; and a bin number reduction module for reducing the number of bins in the second binning data to generate third binning data.
[0004] In one embodiment, the first binning module repeatedly binns multiple chips that have not been binned in the first and second binning processes.
[0005] In one embodiment, the chip binning system is connected to a chip binning server for communication and receives third binning data and chip analysis data corresponding to multiple chips in the third binning data, and further includes a binning analysis server for establishing a chip binning model based on these, the chip binning model is used to bin multiple chips different from multiple other chips based on the corresponding multiple chip analysis data and generate fourth binning data.
[0006] In one embodiment, the first binning process generates first binning data by binning multiple chips in a predetermined proportion of chips with good performance based on the corresponding performance of multiple chips.
[0007] In one embodiment, the first binning process selects at least one binning center chip from a plurality of chips based on the corresponding chip performances, and binns the plurality of chips to generate first binning data based on whether the plurality of chip performance distances between the plurality of chips and at least one binning center chip are smaller than a preset performance distance.
[0008] In one embodiment, the first binning module repeatedly binns multiple chips that have not been binned in the first and second binning processes, and the preset performance distance in each repeated binning process is greater than that of the previous binning process.
[0009] In one embodiment, the power standard deviation of multiple chips in each bin of the second binning data generated by the second binning is less than or equal to a preset standard deviation.
[0010] This disclosure further proposes a chip binning method that includes: generating a plurality of corresponding chip feature data based on a plurality of chip analysis data corresponding to a plurality of chips; generating a plurality of corresponding chip performances based on the plurality of corresponding chip feature data; generating first binning data by performing first binning on the plurality of chips based on the plurality of chip performances; generating second binning data by performing second binning on the plurality of chips in each bin of the first binning data based on the plurality of corresponding chip powers in the plurality of chip analysis data; and generating third binning data by reducing the number of bins in the second binning data.
[0011] In one embodiment, the chip binning method further includes repeatedly binning multiple chips that have not been binned in the first binning and second binning, starting from the first binning.
[0012] In one embodiment, the chip binning method further includes establishing a chip binning model based on third binning data and chip analysis data corresponding to multiple chips in the third binning data, and the chip binning model is used to bin multiple different chips based on the corresponding multiple chip analysis data and generate fourth binning data. [Brief explanation of the drawing]
[0013] To fully understand the examples and their advantages, please refer to the following description in conjunction with the drawings. [Figure 1] This is a schematic diagram of a chip binning system according to an embodiment of the present disclosure. [Figure 2] This is a flowchart of the chip binning method in the embodiments of this disclosure. [Figure 3] This is a schematic diagram comparing the chip binning method in the embodiments of this disclosure with the binning efficiency using the K-means algorithm. [Modes for carrying out the invention]
[0014] The embodiments of this disclosure will be discussed in detail below. However, as can be understood, the embodiments provide many applicable concepts that can be implemented in various specific contexts. The embodiments discussed and disclosed are for illustrative purposes only and are not intended to limit the scope of this disclosure.
[0015] Figure 1 is a schematic diagram of a chip binning system 100 according to an embodiment of the present disclosure. As shown in Figure 1, the chip binning system 100 includes a chip binning server 110, a binning analysis server 120, and a chip analysis database 130 that are interconnected. The chip binning server 110 includes a feature generation module 111, a first binning module 112, a second binning module 113, and a bin count reduction module 114. Figure 2 is a flowchart of the chip binning method 200 according to an embodiment of the present disclosure. The operation of the chip binning system 100 according to the present disclosure will be described in detail below with reference to Figures 1 and 2.
[0016] First, the chip binning server 110 receives chip analysis data from the chip analysis database 130 and performs step S201. The feature generation module 111 of the chip binning server 110 generates corresponding chip feature data based on the chip analysis data. The chip analysis data is one-dimensional or multi-dimensional data in which the production line or chip detection unit is used or measured, and is stored in the chip analysis database 130. The feature generation module 111 then performs data augmentation on this chip analysis data, calculating based on the relationships between different dimensions in the original chip analysis data and their importance to chip performance evaluation, to generate new chip feature data corresponding to each chip. After generating the new chip feature data, the subsequent binning process can be performed based on the chip feature data.
[0017] In detail, the chip analysis data may include manufacturing parameters of the production line corresponding to each chip, sensing parameters (e.g., preset and actual temperatures, production speed of the production line, etc.), and voltage, current, power, maximum frequency, speed, accuracy, etc., measured by the chip probe on the chip, and any parameters related to chip production and / or chip performance may be used as chip analysis data, and a subsequent binning process can be performed based on this, and the disclosure is not particularly limited thereto. In one embodiment, the chip analysis data may be preprocessed before performing step S201, for example, by screening to remove outliers in order to make binning more accurate, or by preprocessing with other data, and the disclosure is not particularly limited thereto.
[0018] After acquiring chip feature data, step S202 is performed, and the first binning module 112 generates corresponding chip performance based on the corresponding chip feature data, and then performs first binning based on the chip performance corresponding to each chip. Data other than chip performance may be generated based on chip analysis data and / or chip feature data based on other grounds that you wish to use for binning, and this disclosure is not particularly limited thereto.
[0019] Chip performance may be calculated from chip feature data corresponding to each chip. For example, a performance analysis model may comprehensively calculate features of different dimensions in the chip feature data to provide an evaluation score or vector for each chip's performance. Compared to directly obtaining chip performance from chip analysis data, the chip feature data obtained via step S201 can bring the analysis of chip performance and subsequent binning results closer to the quality targets to be achieved in production. As long as chip performance can be obtained based on chip analysis data and / or chip feature data, this disclosure does not particularly limit the specific types of chip analysis data and chip feature data used, or the algorithms or models used to calculate chip performance.
[0020] After obtaining the chip performance of each chip, step S203 is performed, and the first binning module 112 performs first binning, that is, bins the chips based on the chip performance corresponding to each chip. In one embodiment, the chips may be ranked according to their chip performance, and chips with good chip performance and within a predetermined percentage, for example, chips ranked in the top 5% in chip performance, may be placed in the same bin. In another embodiment, the chip performance distance of each chip, for example, the difference between numerical values or the distance between vectors, may be calculated to determine whether or not to place these chips in the same bin.
[0021] In detail, based on chip performance, one or more representative chips may be selected from the chips. For example, a chip with good performance may be designated as the binning center chip, and the chip performance of other chips and their corresponding chip performance distances may be calculated based on the chip performance of this binning center chip, and a preset performance distance may be set. Chips whose chip performance distance from the binning center chip is smaller than the preset performance distance are placed in the same bin. The preset performance distance may be estimated by referring to the preliminary binning results of other machine learning-based chips, or it may be estimated by referring to these preliminary binning results, and as long as these chips can be reasonably classified based on chip performance, there are no particular restrictions in this disclosure on the method for obtaining the preset chip distance.
[0022] In one embodiment, in the first binning, the chips are first ranked according to their performance as described above, and after separating the chips with good performance within a predetermined percentage, the remaining chips are subjected to the first binning according to the chip performance distance using the method described above. For example, chips ranked in the top 5% in terms of chip performance may be placed in the same bin, and a binning center chip may be selected from the remaining 95% of chips and binned based on the chip performance distance. In step S204, the first binning module 112 generates first binning data by performing step S205 using binning information (e.g., chip number and label indicating the binning result) corresponding to the binned chips, based on whether or not the chips have been binned. Chips that have not been binned, i.e., chips that cannot be binned into an appropriate bin in this first binning, are subjected to the first binning again in step S203 in a subsequent step S207 along with other chips that have not been binned.
[0023] Then, after acquiring the first binning data, step S206 is performed, and the second binning module 113 performs the second binning on the chips in each bin of the first binning data. Since chip power has good discriminability for chip binning and is related to the last chip specification, in one embodiment, the second binning is based on the chip power in the chip analysis data corresponding to the chip, but any data or features necessary for chip differences or specifications can be used as the basis for binning in the second binning, and this disclosure is not particularly limited thereto.
[0024] In the second binning, binning is performed based on chip power. Specifically, chips in each bin are divided into a plurality of segments according to chip power, for example, equally divided into 100 or more segments, which is determined according to the required precision. After the segment covering the largest number of chips is extracted as a binning segment, the chip power corresponding to the binning segment is expanded outward. For example, the chip power corresponding to half a segment to 1 segment is increased or decreased, so that more chips are included in the binning segment. Every time the chip power corresponding to the binning segment is changed, the power standard deviation of the chip power of the chips included in the binning segment is calculated, and the expansion of the binning segment and the calculation of the power standard deviation are repeatedly performed. When the power standard deviation is greater than or equal to a preset standard deviation, for example, greater than or equal to the preset standard deviation of 0.25, it means that the second binning of this binning is completed, and chips in the binning segment that has the largest number of chips and whose power standard deviation is less than or equal to the preset standard deviation are taken as the binning result of the second binning of this binning. That is, the second binning is performed on each bin in the first binning data respectively to obtain the second binning result of each bin.
[0025] Since the same standard deviation is loose or strict for data with different degrees of dispersion, it is necessary to set the preset standard deviation according to the data characteristics. For the setting of the preset standard deviation, estimation may be performed with reference to the preliminary binning results of chips obtained by other clustering models. For example, the K-means algorithm is used to perform preliminary binning on chips first to determine the preset standard deviation. As long as the reasonable chip power range of these chip binning results can be obtained, the present disclosure has no particular limitation on the determination method of the preset standard deviation.
[0026] Then, step S207 is performed. The second binning module 113 performs step S208 to generate second binning data based on whether the chips were binned in step S206, using binning information corresponding to the binned chips (e.g., chip numbers and labels indicating binning results). Chips that have not been binned, that is, chips not covered by the final binning segment, are subjected to the first binning in step S203 again together with chips that were similarly not binned during the aforementioned first binning. The first binning data and the second binning data may be stored in the chip analysis database 130 so as to be available when there is a subsequent analysis demand.
[0027] After chips are processed in steps S203 to S208, the second binning data includes relevant binning information of the binned chips, and repeated binning is performed on chips that have not been binned in step S204 and step S207, so that the first binning and the second binning are performed again starting from step S203. In the repeated binning stage, chips may be binned directly based on chip performance distance, and the preset performance for the first binning may be set larger than that of the previous binning, that is, in the first binning of repeated binning, the condition for dividing chips into the same bin can be made looser than that of the previous binning, so that remaining chips can be successfully binned in repeated binning and the number of chips that cannot be binned is reduced. In one embodiment, the preset standard deviation in the second binning may be increased to increase the number of chips in the same bin. It should be noted that the degree of loosening in the repeated binning stage of the first binning and the second binning may be adjusted according to the number or proportion of chips to be retained and eliminated, and the present disclosure is not particularly limited thereto.
[0028] After the completion of the second binning, the number of bins obtained after the second binning may be enormous because the first and second binning processes binned as many chips as possible. In one embodiment, after obtaining the second binning data, step S209 may be performed, and the bin count reduction module 114 reduces the number of bins of chips in the second binning data.
[0029] In detail, for chips in the second binning data, an unsupervised learning algorithm, such as the K-means algorithm, is used to reduce the number of binnings in the second binning to satisfy a predetermined number of binnings, such as the number of binnings requested by the client, based on corresponding chip analysis data and / or chip feature data such as chip performance and power. Specifically, for example, the top 5 bins with the best average chip performance are merged into one bin, and the next top 5 bins are merged into one bin. The number of binnings may be reduced based on, for example, the maximum power of the chip, average chip performance, or cumulative chip performance, and this disclosure does not particularly limit the reduction method, the number of binnings to be reduced, and the underlying chip analysis data or chip feature data.
[0030] The bin reduction module 114 reduces the number of bins for the chips in the second binning data, then performs step S210 to generate third binning data. The third binning data includes binning information corresponding to the chips being binned (e.g., chip number and label indicating the binning result), and the number of bins in the third binning data is smaller than that of the first and second binning data. The third binning data may also be stored in the chip analysis database 130 for use in subsequent analysis needs.
[0031] Figure 3 is a schematic diagram comparing the binning efficiency of the chip binning method 200 and the K-means algorithm in an embodiment of this disclosure. Here, using 30 binning as an example, the solid line L1 represents the cumulative binning efficiency from multiple simulations in which the chip is binned into 30 bins using steps S201 to S210 of the chip binning method 200, i.e., the reduction in the number of bins is completed and the chip is divided into 30 bins. The dashed line L2 represents the binning efficiency from multiple simulations in which the chip is binned into 30 bins using the K-means algorithm based on chip performance data and chip power, directly based on chip analysis data. As shown in Figure 3, the binning efficiency of the chip binning method 200 is higher as the number of simulations increases. Note that the number of bins in the chip binning method 200 applied to this disclosure is not limited to this, meaning that the chip binning method 200 can obtain good binning efficiency at different numbers of bins compared to the K-means algorithm.
[0032] In one embodiment, since chips may have the same binning demand for each lot in multiple production runs, in order to accelerate binning efficiency, the third binning data, the chip analysis data and / or chip feature data corresponding to the chips included, and the labels of the binning results are analyzed to obtain a binning policy, which can then be reused for subsequent lots of chips to quickly perform binning. For this reason, as shown in Figure 2, step S211 may be performed, and the binning analysis server 120 may directly obtain the third binning data and the corresponding chip analysis data and / or chip feature data from the chip binning server 110 or the chip analysis database 130, and then use a supervised learning model, such as a random forest, support vector machine, or artificial neural network, to search for the binning policy hidden in the third binning data and establish a chip binning model. The trained chip binning model may then be used to quickly bin subsequent lots of chips. Specifically, the chip binning model rapidly binns chips from subsequent lots to generate fourth binning data, which includes the correspondence between each chip in this lot and each bin in the third binning data. This allows us to determine which bin in the corresponding third binning data each chip can be binned into and to label each chip in this lot with the corresponding bin number.
[0033] The chip binning system and method of this disclosure screens chip analysis data, increases chip feature data for binning using a data augmentation method, performs two-stage binning based on chip performance and chip power in the first and second binning stages, and finally reduces the number of binnings, resulting in a more refined binning result that matches the demand for the number of binnings, and can fully consider the impact of chip power and distinguish chips with minute differences compared to using only a clustering algorithm, such as the K-means algorithm, thereby obtaining more accurate binning results.
[0034] Although the present disclosure has been disclosed in the examples described above, the examples described above are not intended to limit the present disclosure, and any one of the parties may make certain changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the claims that are subsequently attached. [Explanation of symbols]
[0035] 100: Chip binning system 110: Chip binning server 111: Feature generation module 112: First Binning Module 113: Second Binning Module 114: Bin count reduction module 120: Binning Analysis Server 130: Chip Analysis Database 200: Chip binning method L1: Solid line L2: Dashed line S201~S211: Step
Claims
1. A chip binning system, A chip analysis database for storing multiple chip analysis data corresponding to multiple chips, A chip binning server that communicates with the chip analysis database and receives the multiple chip analysis data, Equipped with, The aforementioned chip binning server is A feature generation module for generating corresponding multiple chip feature data based on the aforementioned multiple chip analysis data, A first binning module for generating corresponding multiple chip performances based on the corresponding multiple chip feature data, and generating first binning data by performing first binning on the multiple chips based on the multiple chip performances, A second binning module for generating second binning data by performing second binning on the plurality of chips in each bin of the first binning data based on the corresponding plurality of chip powers in the plurality of chip analysis data, A bin count reduction module for reducing the number of bins in the second binning data to generate third binning data, A chip binning system including a chip binning system.
2. The chip binning system according to claim 1, wherein the first binning module repeatedly binns the plurality of chips that have not been binned by the first binning and the second binning.
3. The system further includes a binning analysis server that is connected to the chip binning server for communication, receives the third binning data and the chip analysis data corresponding to the plurality of chips in the third binning data, and establishes a chip binning model based on these, The chip binning system according to claim 1, wherein the chip binning model is used to bin a plurality of other chips different from the plurality of chips based on the corresponding plurality of chip analysis data, and to generate a fourth binning data.
4. The chip binning system according to claim 1, wherein the first binning binns the plurality of chips in a preset ratio of the plurality of chips with good chip performance based on the corresponding plurality of chip performances, and generates the first binning data.
5. The chip binning system according to claim 1, wherein the first binning selects at least one binning center chip from the plurality of chips based on the corresponding plurality of chip performances, binns the plurality of chips based on whether the plurality of chip performance distances between the plurality of chips and the at least one binning center chip are smaller than a preset performance distance, and generates the first binning data.
6. The chip binning system according to claim 5, wherein the first binning module repeatedly binns the plurality of chips that have not been binned in the first binning and the second binning, and the preset performance distance in the repeated binning is greater than that of the previous binning.
7. The chip binning system according to claim 1, wherein the power standard deviation of the plurality of chips in each bin in the second binning data generated by the second binning is less than or equal to a preset standard deviation.
8. A chip binning method, Based on multiple chip analysis data corresponding to multiple chips, it generates corresponding multiple chip feature data, Based on the corresponding plurality of chip feature data, a corresponding plurality of chip performances are generated, and based on the plurality of chip performances, a first binning is performed on the plurality of chips to generate first binning data, Based on the corresponding chip powers in the aforementioned plurality of chip analysis data, a second binning is performed on the plurality of chips in each bin of the first binning data to generate second binning data. The process involves reducing the number of binning operations in the second binning data to generate the third binning data, A chip binning method that includes this.
9. The chip binning method according to claim 8, further comprising repeatedly binning the plurality of chips that have not been binned in the first binning and the second binning, starting from the first binning.
10. The method further includes establishing a chip binning model based on the third binning data and the chip analysis data corresponding to the plurality of chips in the third binning data, The chip binning method according to claim 8, wherein the chip binning model is used to bin a plurality of other chips different from the plurality of chips based on the corresponding plurality of chip analysis data, and to generate a fourth binning data.