Printed circuit board and method for manufacturing the same

Abstract

The present invention provides a printed circuit board and a method for manufacturing the same that can form a surface treatment layer without the need for plating wires. [Solution] The printed circuit board according to the present invention comprises an insulating layer, a first circuit pattern embedded in the insulating layer such that one side is exposed on one side of the insulating layer, a second circuit pattern arranged to protrude onto the other side of the insulating layer opposite to the one side of the insulating layer, a surface conductive layer arranged on at least a portion of the first circuit pattern and made of a different material from the first circuit pattern, a surface treatment layer arranged on the surface conductive layer, and a solder resist layer arranged on one side so as to expose the surface treatment layer.

Description

[Technical Field]

[0001] The present invention relates to a printed circuit board and a method for manufacturing the same, and in particular, to a printed circuit board capable of forming a surface treatment layer without a plating line and a method for manufacturing the same. [Background Art]

[0002] Demand for high-performance logic semiconductors is increasing in technical fields such as artificial intelligence and autonomous vehicles, and packaging technology is also changing. Pads for electrical connection with a semiconductor chip are disposed on the outermost layer of a printed circuit board on which the semiconductor chip is mounted, and a surface treatment layer for preventing oxidation of the pads and improving bonding properties with solder is disposed on the pads.

[0003] A plating line is required to form a surface treatment layer through electrolytic plating, and there is a problem that the area occupied by the plating line may become a constraint on circuit design. [Summary of the Invention] [Problem to be Solved by the Invention]

[0004] The present invention has been made in view of the above problems in conventional printed circuit boards, and an object of the present invention is to provide a printed circuit board capable of forming a surface treatment layer without a plating line and a method for manufacturing the same. Another object of the present invention is to provide a printed circuit board manufactured by a simplified process that does not include a plating line forming step, and a method for manufacturing the same. [Means for Solving the Problem]

[0005] To achieve the above objective, the printed circuit board according to the present invention comprises: an insulating layer; a first circuit pattern embedded in the insulating layer such that one side is exposed on one side of the insulating layer; a second circuit pattern arranged to protrude onto the other side of the insulating layer facing the one side of the insulating layer; a surface conductive layer arranged on at least a portion of the first circuit pattern and made of a different material from the first circuit pattern; a surface treatment layer arranged on the surface conductive layer; and a solder resist layer arranged on the one side such that the surface treatment layer is exposed.

[0006] Preferably, the surface conductive layer protrudes from one surface of the insulating layer. The surface conductive layer is preferably a metal having an etching selectivity ratio with respect to the first circuit pattern. Preferably, the surface conductive layer is made of nickel, and the first circuit pattern is made of copper. The surface conductive layer is preferably made of a nonmetallic conductive material. The nonmetallic conductive material is preferably graphite or a conductive organic polymer. The aforementioned surface treatment layer is preferably made of gold (Au).

[0007] A method for manufacturing a printed circuit board according to the present invention, made to achieve the above objective, is characterized by comprising the steps of: forming a surface seed layer on a carrier; forming a first circuit pattern on the surface seed layer; forming an insulating layer on the surface seed layer that covers the first circuit pattern; forming a second circuit pattern on the insulating layer; removing the carrier; forming a surface treatment layer on the surface seed layer that overlaps with at least a portion of the first circuit pattern; removing the portion of the surface seed layer exposed by the surface treatment layer to form a surface conductive layer interposed between the first circuit pattern and the surface treatment layer; and forming a solder resist layer on the insulating layer that exposes the surface treatment layer.

[0008] The surface seed layer is preferably a metal having an etching selectivity ratio with respect to the first circuit pattern. Preferably, the surface seed layer is made of nickel, and the first circuit pattern is made of copper. The surface seed layer is preferably a non-metallic conductive material. The nonmetallic conductive material is preferably graphite or a conductive organic polymer. The step of forming the surface treatment layer preferably includes the steps of forming a mask pattern having an opening that overlaps with at least a portion of the first circuit pattern on the surface seed layer, and forming an electroplating layer on the portion of the surface seed layer exposed through the opening. The electrolytic plating layer is preferably made of gold (Au). [Effects of the Invention]

[0009] According to the printed circuit board and its manufacturing method according to the present invention, a surface treatment layer is formed on the outermost pad without the need for separate plating wires. Therefore, the overall manufacturing process of printed circuit boards can be simplified, and the constraints on circuit design due to the area occupied by plated wires can be avoided. [Brief explanation of the drawing]

[0010] [Figure 1] This is a cross-sectional view showing a schematic configuration of a printed circuit board according to an embodiment of the present invention. [Figure 2] This is a cross-sectional view illustrating a method for manufacturing a printed circuit board according to an embodiment of the present invention. [Figure 3] This is a cross-sectional view illustrating a method for manufacturing a printed circuit board according to an embodiment of the present invention. [Figure 4] This is a cross-sectional view illustrating a method for manufacturing a printed circuit board according to an embodiment of the present invention. [Figure 5] This is a cross-sectional view illustrating a method for manufacturing a printed circuit board according to an embodiment of the present invention. [Figure 6]This is a cross-sectional view illustrating a method for manufacturing a printed circuit board according to an embodiment of the present invention. [Figure 7] This is a cross-sectional view illustrating a method for manufacturing a printed circuit board according to an embodiment of the present invention. [Modes for carrying out the invention]

[0011] Next, specific examples of embodiments for carrying out the printed circuit board and its manufacturing method according to the present invention will be described with reference to the drawings.

[0012] The present invention can be implemented in various different forms and is not limited to the embodiments described herein. To clearly illustrate the present invention, irrelevant parts have been omitted, and the same or similar reference numerals are used throughout the specification for identical or similar components. Furthermore, the drawings are provided to facilitate understanding of the embodiments disclosed herein, and the drawings are not intended to limit the technical ideas disclosed herein, and should be understood to include all modifications, equivalents, or substitutions that fall within the concept and technical scope of the present invention. Furthermore, the dimensions and thicknesses of each component shown in the drawings are arbitrarily indicated for the sake of explanation, and the present invention is not necessarily limited to those shown. In the drawings, the thickness is shown enlarged to clearly represent various layers and regions. Furthermore, in the drawings, the thickness of some layers and areas was exaggerated for the sake of explanation.

[0013] Furthermore, when we say that a layer, membrane, region, plate, or other part is "on top of" another part, this includes not only cases where it is "directly on top" of the other part, but also cases where there is yet another part in between. Conversely, if one part is "directly above" another part, it means that there is no other part in between. Furthermore, being "above" the reference point means being located either above or below the reference point, and does not necessarily mean being located "above" in the opposite direction of gravity. Further, throughout the entire specification, when a certain component is stated to be "included" in a part, this means that, unless specifically stated to the contrary, other components are not excluded, and additional other components may be included. Further, throughout the entire specification, when the expression "coupled (connected)" is used, this does not only mean that two or more components are directly coupled (connected), but also includes that two or more components are indirectly coupled (connected) via another component, as well as being electrically coupled (connected) in addition to being physically coupled (connected); and although referred to by different names depending on position and function, this means that they are integrated. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0014] FIG. 1 is a cross-sectional view showing a schematic configuration of a printed circuit board according to an embodiment of the present invention. Referring to FIG. 1, the printed circuit board according to an embodiment of the present invention includes an insulating layer 106. The insulating layer 106 is ABF (Ajinomoto Build-up Film (registered trademark)).

[0015] In FIG. 1, the insulating layer 106 is illustrated as a single layer, but in other embodiments, the insulating layer 106 may include a plurality of insulating layers. When the insulating layer 106 includes a plurality of insulating layers, a part of the insulating layers may be a prepreg manufactured by impregnating glass cloth with a thermosetting resin or a thermoplastic resin. In some cases, at least a part of the insulating layers may be PID (Photo-Imageable Dielectric).

[0016] A first circuit pattern 104 is disposed on one surface of the insulating layer 106. One surface of the first circuit pattern 104 is exposed from the insulating layer 106, and the other surface is embedded in the insulating layer 106. For example, if the cross-section of the first circuit pattern 104 has four faces, as shown in Figure 1, one face is exposed from the insulating layer 106, and the other three faces are embedded within the insulating layer 106. The first circuit pattern 104 is made of copper (Cu).

[0017] A second circuit pattern 108 is placed on the other side of the insulating layer 106 that is opposite to the aforementioned one side. The second circuit pattern 108 is positioned to protrude from the other side of the insulating layer 106. A portion of the second circuit pattern 108 is connected to a portion of the first circuit pattern 104 by vias 110 that penetrate the insulating layer 106. The second circuit pattern 108 and via 110 are made of copper (Cu).

[0018] The via 110 has a cross-sectional area that decreases along the height direction toward one side on the other side of the insulating layer 106. In other words, the cross-sectional area of ​​the via 110 that is closest to one surface of the insulating layer 106, in relation to the height and vertical directions, is smaller than the cross-sectional area that is closest to the other surface of the insulating layer 106. In other embodiments, if the insulating layer 106 includes multiple insulating layers, a circuit pattern is arranged on each insulating layer, and some of the circuit patterns are connected to each other by vias that penetrate each insulating layer. In this case, the via has a cross-sectional area that decreases along the height direction, as shown in via 110 in Figure 1.

[0019] A solder resist layer 118 is placed on one and the other surface of the insulating layer 106. The solder resist layer 118 partially exposes the second circuit pattern 108. Furthermore, the solder resist layer 118 exposes a portion of the first circuit pattern 104. The surface conductive layer 116 and the surface treatment layer 114 are sequentially placed on the first circuit pattern 104 exposed by the solder resist layer 118.

[0020] The surface conductive layer 116 protrudes from one surface of the insulating layer 106. The surface conductive layer 116 is a metal having an etching selectivity ratio with respect to the first circuit pattern 104. In other words, the surface conductive layer 116 is etched by a specific etching solution, while the first circuit pattern 104 is not etched or is etched at a very low rate. Conversely, the first circuit pattern 104 is etched by other etching solutions, while the surface conductive layer 116 is not etched or is etched at a very low rate. When the first circuit pattern 104 is made of copper (Cu), the surface conductive layer 116 is made of nickel (Ni).

[0021] In other embodiments, the surface conductive layer 116 may be graphite or a nonmetallic conductive material such as a conductive organic polymer. The conductive organic polymer may be polyacetylene, polyphenylenevinylene, polypyrrole, or polythiophene. The surface treatment layer 114 is gold (Au).

[0022] By arranging the surface conductive layer 116 and the surface treatment layer 114 on the first circuit pattern 104 according to this embodiment, the first circuit pattern 104 can be effectively protected even if it is exposed by the solder resist layer 118. Furthermore, a separate plating wire is not required for forming the surface treatment layer 114, thus avoiding constraints on circuit design.

[0023] Figures 2 to 7 are cross-sectional views illustrating a method for manufacturing a printed circuit board according to an embodiment of the present invention. Referring to Figure 2, a surface seed layer 100 is formed on carrier C. The carrier C includes a first copper foil layer CF1 and a second copper foil layer CF2 that are sequentially laminated on both sides of the carrier insulating layer CI.

[0024] The surface seed layer 100 is formed on the second copper foil layer CF2 by electroplating. The surface seed layer 100 is a metal that has an etching selectivity ratio with respect to the second copper foil layer CF2 and the first circuit pattern 104, which will be described later. In other words, with respect to a specific etching solution, the surface seed layer 100 is etched, while the second copper foil layer CF2 and the first circuit pattern 104 are not etched or are etched at a very low rate. Conversely, with respect to other etching solutions, the second copper foil layer CF2 and the first circuit pattern 104 are etched, while the surface seed layer 100 is not etched or is etched at a very low rate.

[0025] When the second copper foil layer CF2 and the first circuit pattern 104 are made of copper (Cu), the surface seed layer 100 is made of nickel (Ni). In other embodiments, the surface seed layer 100 may be graphite or a nonmetallic conductive material such as a conductive organic polymer. In this case, the surface seed layer 100 is formed by a printing or coating process. The conductive organic polymer may be polyacetylene, polyphenylenevinylene, polypyrrole, or polythiophene.

[0026] Referring to Figure 3, a first mask 102 is formed on the surface seed layer 100. The first mask 102 is formed by laminating a photosensitive resin film onto the surface seed layer 100 and then performing photolithography. Subsequently, the surface seed layer 100 is used as a plating seed, and the first circuit pattern 104 is electroplated onto the surface seed layer 100 exposed by the first mask 102. The first circuit pattern 104 is formed from copper (Cu).

[0027] Referring to Figure 4, an insulating layer 106 is formed on the surface seed layer 100, covering the first circuit pattern 104. The insulating layer 106 is formed by laminating ABF (Ajinomoto Build-up Film®) onto the surface seed layer 100 and applying heat and pressure. After this, the insulating layer 106 is processed with a laser or drill to form via holes that expose a portion of the first circuit pattern 104. An electroless plating process is performed to form a circuit seed layer 107 on the insulating layer 106 in which via holes are formed and on the first circuit pattern 104 exposed by the via holes. Using the circuit seed layer 107 as a plating seed, vias 110 that fill via holes and a second circuit pattern 108 on the insulating layer 106 are formed in the electroplating process. A plating mask is formed on the circuit seed layer 107, exposing the region where the second circuit pattern 108 will be formed before the electroplating process. The circuit seed layer 107 and the second circuit pattern 108 are formed of copper (Cu).

[0028] Referring to Figure 5, the first copper foil layer CF1 and the second copper foil layer CF2 are separated, and the remaining portion of carrier C, excluding the second copper foil layer CF2, is removed. As a result, two coreless laminates are formed, but in the following explanation, only one of them will be shown in the diagram. After removing the remaining portion of carrier C, the second copper foil layer CF2 is etched and removed. Since the surface seed layer 100 has an etching selectivity ratio with respect to the second copper foil layer CF2, the surface seed layer 100 is not etched or is etched at a very low rate while the second copper foil layer CF2 is etched. Meanwhile, while the second copper foil layer CF2 is etched, the circuit seed layer 107 exposed by the second circuit pattern 108 is also etched.

[0029] As shown in Figure 5, the first conductive pattern 104 is embedded in the insulating layer 106 such that one side of it is exposed on one side of the insulating layer 106. The second conductive pattern 108 is formed so as to protrude from one surface of the insulating layer 106 and the other surface of the insulating layer 106 facing it. A circuit seed layer 107, which remains after etching, is interposed between the second conductive pattern 108 and the insulating layer 106.

[0030] Referring to Figure 6, the second mask 112 is formed on one and the other surface of the insulating layer 106. Specifically, the second mask 112 is formed on a surface seed layer 100 on one surface of the insulating layer 106, having an opening that at least partially overlaps with a portion of the first circuit pattern 104. Furthermore, the second mask 112 is formed to completely cover the other side of the insulating layer 106. The second mask 112 is formed by laminating a photosensitive resin film onto the surface seed layer 100 and then performing photolithography. Subsequently, a surface treatment layer 114 is formed on the surface seed layer 100 exposed by the second mask 112. The surface treatment layer 114 is formed by electroplating gold (A) using the surface seed layer 100 as a plating seed.

[0031] Referring to Figure 7, after removing the second mask 112, the surface seed layer 100 exposed by the surface treatment layer 114 is etched and removed. As a result, a surface conductive layer 116 is formed between the surface treatment layer 114 and the first circuit pattern 104. The surface treatment layer 114 is used as an etching mask while the surface seed layer 100 is etched. Furthermore, since the surface seed layer 100 is a metal that has an etching selectivity ratio with respect to the first circuit pattern 104, while the surface seed layer 100 is etched, the first circuit pattern 104 is either not etched or etched at a very low rate.

[0032] In another embodiment, when the surface seed layer 100 is formed of graphite or a conductive organic polymer, the portion exposed by the surface treatment layer 114 is removed by dry etching such as plasma etching. In one embodiment, the surface seed layer 100 used as a plating seed for electroplating the first circuit pattern 104 can be used as a plating seed for electroplating the surface treatment layer 114. Therefore, the entire process can be simplified by performing electroplating twice on a single plating seed. Furthermore, by forming the surface treatment layer 114 without separate plating wires, the constraints on circuit design due to the area occupied by the plating wires can be avoided.

[0033] Furthermore, the present invention is not limited to the embodiments described above. It can be modified and implemented in various ways without departing from the technical scope of the present invention. [Explanation of Symbols]

[0034] 104 First Circuit Pattern 106 Insulating layer 108 Second Circuit Pattern 110 Beer 114 Surface treatment layer 116 Surface conductive layer 118 Solder Resist Layer

Claims

1. Insulating layer and, A first circuit pattern is embedded in the insulating layer such that one side is exposed on one side of the insulating layer, A second circuit pattern is arranged so as to protrude from the other surface of the insulating layer that is opposite to one surface of the insulating layer, A surface conductive layer, which is made of a material different from the first circuit pattern, is disposed on at least a portion of the first circuit pattern. A surface treatment layer disposed on the surface conductive layer, A printed circuit board characterized by comprising: a solder resist layer disposed on one surface such as to expose the surface treatment layer.

2. The printed circuit board according to claim 1, characterized in that the surface conductive layer protrudes from one surface of the insulating layer.

3. The printed circuit board according to claim 1, characterized in that the surface conductive layer is a metal having an etching selectivity ratio with respect to the first circuit pattern.

4. The printed circuit board according to claim 3, characterized in that the surface conductive layer is nickel and the first circuit pattern is copper.

5. The printed circuit board according to claim 1, characterized in that the surface conductive layer is a nonmetallic conductive material.

6. The printed circuit board according to claim 5, characterized in that the nonmetallic conductive material is graphite or a conductive organic polymer.

7. The printed circuit board according to claim 1, characterized in that the surface treatment layer is gold (Au).

8. The steps include forming a surface seed layer on the carrier, The steps include forming a first circuit pattern on the surface seed layer, The steps include forming an insulating layer on the surface seed layer to cover the first circuit pattern, The steps include forming a second circuit pattern on the insulating layer, The step of removing the carrier, The steps include forming a surface treatment layer on the surface seed layer that overlaps with at least a portion of the first circuit pattern, The steps include removing the surface seed layer from the portion exposed by the surface treatment layer to form a surface conductive layer interposed between the first circuit pattern and the surface treatment layer, A method for manufacturing a printed circuit board, comprising the step of forming a solder resist layer on the insulating layer that exposes the surface treatment layer.

9. The method for manufacturing a printed circuit board according to claim 8, characterized in that the surface seed layer is a metal having an etching selectivity ratio with respect to the first circuit pattern.

10. The method for manufacturing a printed circuit board according to claim 9, characterized in that the surface seed layer is nickel and the first circuit pattern is copper.

11. The method for manufacturing a printed circuit board according to claim 8, characterized in that the surface seed layer is a nonmetallic conductive material.

12. The method for manufacturing a printed circuit board according to claim 11, characterized in that the nonmetallic conductive material is graphite or a conductive organic polymer.

13. The step of forming the surface treatment layer is: The steps include forming a mask pattern on the surface seed layer having an opening that overlaps with at least a portion of the first circuit pattern, The method for manufacturing a printed circuit board according to claim 8, comprising the step of forming an electrolytic plating layer on the surface seed layer of the portion exposed through the opening.

14. The method for manufacturing a printed circuit board according to claim 13, characterized in that the electrolytic plating layer is gold (Au).

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