Printed circuit board

Abstract

One of the several objectives of the present invention is to provide a printed circuit board with a structure that can be applied to large-area products, allows for miniaturization and high performance, and is advantageous in terms of pitch reduction and warpage control. [Solution] The present invention relates to a printed circuit board comprising: a core layer; a first wiring section disposed above the core layer and including one or more first insulating layers and one or more first wiring layers disposed within one or more first insulating layers; a second wiring section disposed above the first wiring section and including one or more second insulating layers and one or more second wiring layers disposed within one or more second insulating layers; a glass layer disposed above the second wiring section; and a third wiring layer disposed on the upper surface of the glass layer, wherein the thickness of the third wiring layer is thinner than the thickness of at least one of the one or more first wiring layers.

Description

Technical Field

[0001] The present invention relates to a printed circuit board. Background Art

[0002] In recent years, with the rapid surge in demand for high-performance computing and large-scale data processing, the server-centric semiconductor application market has been expanding rapidly. In response to this, demand for large-area substrates for realizing high integration and processing high bandwidth has been increasing, and as a result, miniaturization and performance improvement of substrates and packages have been continuously progressing. For example, as demand for chiplets and heterogeneous integrated packages, which integrate a plurality of chips in a single package to implement functions in a distributed manner, increases, the importance of narrowing the spacing of fine wiring, ensuring the overall flatness of packages and substrates, and warpage suppression technology has emerged. Summary of the Invention Problem to be Solved by the Invention

[0003] One of several objects of the present invention is to provide a printed circuit board having a structure that can be applied to large-area products, can achieve miniaturization and performance improvement, and is advantageous in terms of pitch reduction and warpage control. Means for Solving the Problem

[0004] One of the various solutions proposed through the present invention is to provide a printed circuit board by forming wiring sections on both sides of a core layer in a build-up process, placing a glass layer with excellent flatness on the upper wiring section, and forming a fine wiring layer on the glass layer. For example, the printed circuit board of the present invention includes a core layer, a first wiring section disposed above the core layer and including one or more first insulating layers and one or more first wiring layers disposed within one or more first insulating layers, a second wiring section disposed above the first wiring section and including one or more second insulating layers and one or more second wiring layers disposed within one or more second insulating layers, a glass layer disposed above the second wiring section, and a third wiring layer disposed on the upper surface of the glass layer, wherein the thickness of the third wiring layer may be thinner than the thickness of at least one of the one or more first wiring layers.

[0005] Another of the various solutions proposed through the present invention is to provide a printed circuit board by forming build-up wiring sections on both sides of a glass core in a build-up process, and further forming a build-up wiring section including a fine wiring layer on the upper build-up wiring section. For example, the printed circuit board of the present invention includes a glass core, a first build-up wiring section including a first insulating body disposed above the glass core, a plurality of first build-up wiring layers disposed on or inside the first insulating body, and a plurality of first build-up wiring vias disposed inside the first insulating body, a second build-up wiring section including a second insulating body disposed above the first insulating body, a plurality of second build-up wiring layers disposed on or inside the second insulating body, and a plurality of second build-up wiring vias disposed inside the second insulating body, a third insulating body disposed below the glass core, a plurality of third build-up wiring layers disposed on or inside the third insulating body, and a plurality of third build-up wiring vias disposed inside the third insulating body, and a plurality of through-vias each surrounded by the glass core, wherein the minimum line width of the wiring included in at least one of the plurality of second build-up wiring layers may be smaller than the minimum line width of the wiring included in at least one of the plurality of first build-up wiring layers and at least one of the plurality of third build-up wiring layers. [Effects of the Invention]

[0006] As one of the various effects of the present invention, it is possible to provide a printed circuit board with a structure that is applicable to large-area products, enables miniaturization and high performance, and is advantageous in terms of pitch reduction and warpage control. [Brief explanation of the drawing]

[0007] [Figure 1] This is a schematic cross-sectional view showing an example of a printed circuit board. [Figure 2] This is a schematic cross-sectional view showing a modified example of a printed circuit board. [Figure 3a]This is a schematic cross-sectional view illustrating an example of the manufacturing process of a printed circuit board. [Figure 3b] This is a schematic cross-sectional view illustrating an example of the manufacturing process of a printed circuit board. [Figure 3c] This is a schematic cross-sectional view illustrating an example of the manufacturing process of a printed circuit board. [Figure 3d] This is a schematic cross-sectional view illustrating an example of the manufacturing process of a printed circuit board. [Figure 4] This is a schematic cross-sectional view showing another example of a printed circuit board. [Figure 5] This is a schematic cross-sectional view showing a modified example of a printed circuit board. [Figure 6] This is a schematic cross-sectional view showing yet another example of a printed circuit board. [Figure 7] This is a cross-sectional view illustrating a modified example of a printed circuit board, which is yet another example. [Modes for carrying out the invention]

[0008] The present invention will be described below with reference to the attached drawings. The shapes and sizes of the elements in the drawings may be exaggerated or reduced for clearer explanation.

[0009] Figure 1 is a schematic cross-sectional view showing an example of a printed circuit board.

[0010] Referring to the drawings, an example printed circuit board 100A may include a core layer 101, a first wiring section 110 disposed above the core layer 101 and including one or more first insulating layers 111 and one or more first wiring layers 112 disposed on or within the one or more first insulating layers 111, a second wiring section 120 disposed above the first wiring section 110 and including one or more second insulating layers 121 and one or more second wiring layers 122 disposed on or within the one or more second insulating layers 121, a glass layer 131 disposed above the second wiring section 120, and a third wiring layer 132 disposed on the upper surface of the glass layer 131. In this case, the third wiring layer 132 may include wiring that is relatively denser than at least one of the one or more first wiring layers 112, for example, wiring that is denser than each of the one or more first wiring layers 112. Furthermore, at least one of the one or more second wiring layers 122, for example, each of the one or more second wiring layers 122, may contain wiring that is relatively denser than at least one of the one or more first wiring layers 112, for example, each of the one or more first wiring layers 112.

[0011] As described above, the printed circuit board 100A according to one example can include a core layer 101, and first and second wiring sections 110 and 120 with different wiring densities can be sequentially formed on the upper side of the core layer 101. In this case, it can be applied to large-area products, may be effective in controlling warpage during the process, allows for various wiring designs, and may enable the design of fine wiring in the outer region of the substrate. Furthermore, a glass layer 131 with excellent flatness and advantageous for warpage control can be further placed on the second wiring section 120, and a third wiring layer 132 can be formed on the surface of such a glass layer 131. In this case, a better warpage control effect can be obtained via the glass layer 131, and the flatness characteristics of the glass layer 131 can be utilized to form the third wiring layer 132 with finer wiring. Therefore, the laminated structure of the second wiring section 120, the glass layer 131, and the third wiring layer 132 can be used as a silicon interposer or interconnect bridge for die-to-die signal transmission, and such a laminated structure can also play the role of other high-density wiring sections.

[0012] On the other hand, the thickness of the third wiring layer 132 may be thinner than the thickness of at least one of the one or more first wiring layers 112, for example, the thickness of each of the one or more first wiring layers 112. Also, the thickness of at least one of the one or more second wiring layers 122, for example, the thickness of each of the one or more second wiring layers 122 may be thinner than the thickness of at least one of the one or more first wiring layers 112, for example, the thickness of each of the one or more first wiring layers 112. For example, the minimum line width, minimum thickness, and minimum spacing of the wiring included in the third wiring layer 132 may be smaller than the minimum line width, minimum thickness, and minimum spacing of the wiring included in at least one of the one or more first wiring layers 112, for example, the minimum line width, minimum thickness, and minimum spacing of the wiring included in each. Also, the minimum line width, minimum thickness, and minimum spacing of the wiring included in one or more second wiring layers 122 may be smaller than the minimum line width, minimum thickness, and minimum spacing of the wiring included in at least one of the one or more first wiring layers 112, for example, the minimum line width, minimum thickness, and minimum spacing of the wiring included in each. In this case, as described above, the laminated structure of the second wiring section 120, the glass layer 131, and the third wiring layer 132 can easily fulfill the role of a high-density wiring section for various applications.

[0013] Furthermore, the first wiring section 110 may further include one or more first wiring vias 113 that penetrate at least a portion of at least one of the one or more first insulating layers 111. Similarly, the second wiring section 120 may further include one or more second wiring vias 123 that penetrate at least a portion of at least one of the one or more second insulating layers 121. Thus, electrical paths can be formed in the first and second wiring sections 110 and 120. For example, one or more first and second wiring layers 112 and 122 may be electrically connected to each other via one or more first and second wiring vias 113 and 123. In addition, one or more third wiring vias 133 may be formed in the glass layer 131 and the uppermost second insulating layer 121 of the one or more second insulating layers 121, each penetrating at least a portion of the glass layer 131 and the uppermost second insulating layer 121 collectively. Therefore, the second wiring section 120 and the third wiring layer 132, which is arranged on the glass layer 131, can be electrically connected to each other. For example, one or more second wiring layers 122 and the third wiring layer 132 can be electrically connected to each other via one or more third wiring vias 133. In this case, various electrical connection paths can be provided on the upper side of the core layer 101.

[0014] Referring to the drawings, an example printed circuit board 100A may further include one or more through-vias 103 that each penetrate at least a portion of the core layer 101. It may also further include a third wiring section 140 located below the core layer 101, which includes one or more third insulating layers 141, one or more fourth wiring layers 142 each located on or within the one or more third insulating layers 141, and one or more fourth wiring vias 143 that each penetrate at least a portion of at least one of the one or more third insulating layers 141. The second and third wiring sections 130 and 140 may have a symmetrical number of layers, but are not limited to this, and may be asymmetrical. Here, the number of layers may be the number of layers of the first and third insulating layers 111, 141 and / or the first and fourth wiring layers 112, 142.

[0015] For example, the first and second wiring sections 110, 120 and the third wiring section 140 may be arranged above and below the core layer 111, respectively, which may enable a wider variety of wiring designs. Furthermore, warping control may become easier. The first and third wiring sections 110, 140 may be electrically connected to each other via one or more through-vias 103. For example, one or more first and fourth wiring layers 112, 142 may be electrically connected to each other via one or more first and fourth wiring vias 113, 143 and one or more through-vias 103. In this case, the printed circuit board 100A can be easily utilized, for example, as a 2.nD structure FCB (Flip-Chip Board).

[0016] On the other hand, between the upper surface of the core layer 101 and the lowest first wiring layer 112 of one or more first wiring layers 112, the lowest first insulating layer 111 of one or more first insulating layers 111 can be placed. Also, between the lower surface of the core layer 101 and the uppermost fourth wiring layer 142 of one or more fourth wiring layers 142, the uppermost third insulating layer 141 of one or more third insulating layers 141 can be placed. In this case, the upper surface of one or more through-vias 103 can contact at least one first wiring via 113 that penetrates at least a portion of the lowest first insulating layer 111 of one or more first wiring vias 113. Also, the lower surface of one or more through-vias 103 can contact at least one fourth wiring via 143 that penetrates at least a portion of the uppermost third insulating layer 141 of one or more fourth wiring vias 143. In this case, the adhesion between the bottommost first wiring layer 112 and the topmost third insulating layer 141 can be ensured, thereby further improving reliability.

[0017] Referring to the drawings, a printed circuit board 100A according to an example may include one or more first insulating layers 111, one or more second insulating layers 121, and one or more third insulating layers 141, which may each include a plurality of first insulating layers 111, a plurality of second insulating layers 121, and a plurality of third insulating layers 141, respectively; one or more first wiring layers 112, one or more second wiring layers 122, and one or more fourth wiring layers 142 may each include a plurality of first wiring layers 112, a plurality of second wiring layers 122, and a plurality of fourth wiring layers 142, respectively; one or more first wiring vias 113, one or more second wiring vias 123, one or more third wiring vias 133, and one or more fourth wiring vias 143 may each include a plurality of first wiring vias 113, a plurality of second wiring vias 123, a plurality of third wiring vias 133, and a plurality of fourth wiring vias 143, respectively.

[0018] For example, each of the first to third wiring portions 110, 120, 140 may be formed of multiple layers. Accordingly, more diverse wiring designs are possible, which may increase the degree of design freedom. However, the relationship between the number of layers of the first to third wiring portions 110, 120, and 140 is not necessarily limited thereto. For example, the first insulating layer 111, the second insulating layer 121, the third insulating layer 141, the first wiring layer 112, the second wiring layer 122, the fourth wiring layer 142, the first wiring via 113, the second wiring via 123, and the fourth wiring via 143 do not necessarily need to be a plurality of layers. For example, the first insulating layer 111, the second insulating layer 121, the third insulating layer 141, the first wiring layer 112, the second wiring layer 122, the fourth wiring layer 142, the first wiring via 113, the second wiring via 123, and / or the fourth wiring via 143 may each be a single layer as needed. For example, in the present invention, one or more layers may be a single layer or a plurality of layers. In the case of a single layer, the topmost layer or the bottommost layer may be the same. In the case of a plurality of layers, the topmost layer and the bottommost layer may be distinguished from each other.

[0019] On the other hand, the first wiring section 110, the second wiring section 120, and the third wiring section 140 can be referred to as the first build-up wiring section 110, the second build-up wiring section 120, and the third build-up wiring section 140, respectively. Also, the first insulating layer 111, the second insulating layer 121, and the third insulating layer 141 can be referred to as the first insulating body 111, the second insulating body 121, and the third insulating body 141, respectively. Furthermore, the first wiring layer 112, the second wiring layer 122, and the fourth wiring layer 142 can be referred to as the first build-up wiring layer 112, the second build-up wiring layer 122, and the third build-up wiring layer 142, respectively. Also, the first wiring via 113, the second wiring via 123, and the fourth wiring via 143 can be referred to as the first build-up wiring via 113, the second build-up wiring via 123, and the third build-up wiring via 143, respectively. Furthermore, the third wiring layer 132 may be referred to as the fourth build-up wiring layer 132. Similarly, the third wiring via 133 may be referred to as the fourth build-up wiring via 133. Of course, the terms used in this invention may be substituted for each other according to the structure, function, or common understanding in the general art of the components, and this should not be interpreted as limiting the scope of protection of the invention.

[0020] In this case, at least one of the plurality of second build-up wiring layers 122, for example, the minimum line width, minimum thickness, and minimum spacing of the wiring included in each may be smaller than the minimum line width, minimum thickness, and minimum spacing of the wiring included in at least one of the plurality of first build-up wiring layers 112, for example, each, and the minimum line width, minimum thickness, and minimum spacing of the wiring included in at least one of the plurality of third build-up wiring layers 142, for example, each. Further, the minimum line width, minimum thickness, and minimum spacing of the wiring included in at least one of the fourth build-up wiring layers 132, for example, each may be smaller than the minimum line width, minimum thickness, and minimum spacing of the wiring included in at least one of the plurality of first build-up wiring layers 112, for example, each, and the minimum line width, minimum thickness, and minimum spacing of the wiring included in at least one of the plurality of third build-up wiring layers 142, for example, each. For example, the plurality of second build-up wiring layers 122 and the fourth build-up wiring layers 132 may include relatively higher-density wiring and / or finer wiring than the plurality of first build-up wiring layers 112 and the plurality of third build-up wiring layers 142.

[0021] Referring to the drawings, a printed circuit board 100A according to an example may further include a plurality of conductive bumps 135 respectively disposed on the third wiring layer 132 and respectively connected to at least a part of the third wiring layer 132. A plurality of semiconductor chips 151 and 152 may be respectively disposed on the glass layer 131, and the plurality of semiconductor chips 151 and 152 may be respectively connected to one or more of the plurality of conductive bumps 135. Further, the printed circuit board may further include a solder resist layer 160 disposed below the third wiring portion 140. The solder resist layer 160 may have a plurality of openings h each exposing at least a part of the lowermost fourth wiring layer 142 among the one or more fourth wiring layers 142. A plurality of second electrical connection metals 165 may be disposed on the plurality of openings h of the solder resist layer 160. The plurality of second electrical connection metals 165 may be respectively connected to the lowermost fourth wiring layer 142.

[0022] For example, a plurality of conductive bumps 135 may be formed on the outermost surface of the printed circuit board 100A, which are electrically connected to a third wiring layer 132 containing high-density wiring. Therefore, a plurality of semiconductor chips 151, 152 can be more easily mounted on the glass layer 131 via the plurality of conductive bumps 135 and more easily electrically connected to the third wiring layer 132. On the other hand, a surface treatment layer P may be formed on the upper surface of each of the plurality of conductive bumps 135. In addition, the plurality of semiconductor chips 151, 152 may each be connected to the plurality of conductive bumps 135 via a plurality of first electrically connecting metals 155. In this case, the connection reliability between the plurality of semiconductor chips 151, 152 and the plurality of conductive bumps 135 can be further improved. If necessary, the plurality of semiconductor chips 151, 152 may be fixed with underfill and / or molding material, but are not limited thereto. Furthermore, an electrical connection path may be provided below the third wiring section 140 for mounting to another board, such as a main board. For example, the printed circuit board 100A may be a ball grid array (BGA) package board, but is not limited to this.

[0023] Referring to the drawings, one example of a printed circuit board 100A may further include a frame 105 having a through-hole H and an insulating material 107 filling at least a portion of the through-hole H. The core layer 101 may be at least partially located within the through-hole H, and the insulating material 107 may be located between the frame 105 and the core layer 101. One or more first insulating layers 111 may cover the upper surface of the core layer 101, the upper surface of the frame 105, and the upper surface of the insulating material 107, respectively. One or more third insulating layers 141 may cover the lower surface of the core layer 101, the lower surface of the frame 105, and the lower surface of the insulating material 107, respectively.

[0024] For example, the core layer 101 can be arranged using a frame 105 having through-holes H and an insulating material 107. The frame 105 can be used as a jig in the manufacturing process. Therefore, this may be advantageous in controlling warpage during the process. In addition, multiple through-holes H can be formed in a large-area frame 105, and by utilizing this, multiple printed circuit boards 100A can be manufactured in the same process and then separated by a cutting process, thereby increasing productivity. The insulating material 107 may be formed in a separate filling process. Therefore, the first insulating layer 111, which is the lowest layer among one or more first insulating layers 111, and the third insulating layer 141, which is the uppermost layer among one or more third insulating layers 141, can each have an interlayer boundary with the insulating material 107.

[0025] The components of the printed circuit board 100A will be described in more detail below with reference to the drawings.

[0026] The core layer 101 can contain a variety of materials. For example, the core layer 101 can contain a glass core layer containing glass, a ceramic core layer containing ceramic, a silicon core layer containing silicon, a metal core layer containing metal, and / or a copper foil laminate (CCL). The glass core layer can contain a glass component that is an amorphous solid. In this case, the glass can include, for example, pure silicon dioxide (about 100% SiO2), soda-lime glass, borosilicate glass, aluminosilicate glass, etc. However, it is not limited to these, and alternative glass materials such as fluorine glass, phosphoric acid glass, and chalcogen glass can also be used as materials. In addition, other additives may be further included to form a glass with specific physical properties. Additives can include magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and / or antimony. Carbonates and / or oxides of such elements and other elements may also be included. For example, calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda) may be included. On the other hand, the glass core layer may be a layer distinct from organic insulating materials such as glass fibers (glass fiber, glass cloth, glass fabric), for example, CCL (copper clad laminate), PPG (prepreg), etc. For example, the glass core layer may be a glass core including a glass plate. The ceramic core layer may include ceramic materials having high thermal conductivity and electrical insulation properties such as alumina, aluminum nitride, silicon nitride, boron nitride, and zirconium oxide. As the silicon core layer, a high-purity silicon wafer or a doped silicon substrate can be used. The metal core layer may include metals or metal alloys with excellent thermal conductivity such as aluminum (Al), copper (Cu), molybdenum (Mo), tungsten (W), and stainless steel. The core layer 101 may be a panel substrate that can be made to a large area, but is not limited thereto. The core layer 101 may be substantially square or rectangular in shape on a plane, but is not limited thereto.The thickness of the core layer 101 may be greater than the thickness of each of the first insulating layer 111, each of the second insulating layer 121, the thickness of the glass layer 131, and / or each of the third insulating layer 141. On the other hand, when a glass core layer, for example a glass core, is used as the core layer 101, it can have a low coefficient of thermal expansion and excellent dimensional stability in response to temperature changes, low dielectric loss and can provide electrical properties advantageous for high-speed signal transmission, it may have high mechanical strength and be resistant to bending and distortion, can be easily made larger in area, and may be able to be made lighter.

[0027] The through via 103 may contain metals. These metals may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The through via 103 can perform various functions depending on the design. For example, it may include ground vias, power vias, signal vias, etc. The through via 103 may have a substantially circular or elliptical shape in plan and a substantially columnar or hourglass shape in cross-section, but is not limited thereto. The through via 103 may be formed in a through hole penetrating between the upper and lower surfaces of the core layer 101. For example, the through via 103 may be a TGV (Through Glass Via), TCV (Through Ceramic Via), TSV (Through Silicon Via), etc., depending on the material of the core layer 101, but is not limited thereto. If the core layer 101 is a metal core layer, an insulating film or the like may be placed between the core layer 101 and the through via 103. The through via 103 may include a sputtered layer (e.g., sputtered titanium / copper) as a seed layer and an electroplated layer (e.g., electroplated copper) as a fill plating layer. However, it is not limited to this, and may also include an electroless plating layer (e.g., chemical copper) as a seed layer, or may include both a sputtered layer and an electroless plating layer. If necessary, the fill plating layer of the through via 103 may be conformally formed, or filler material may be filled between the fill plating layers. The upper and lower surfaces of the through via 103 may be substantially coplane with the upper and lower surfaces of the glass layer 110, respectively, but is not limited to this. For example, recess steps may be formed between the upper and lower surfaces of the glass layer 110 and the upper and lower surfaces of the through via 115, respectively. For example, the upper surface of the through via 115 may be positioned below the upper surface of the glass layer 110, or the lower surface of the through via 115 may be positioned above the lower surface of the glass layer 110. There may be multiple through vias 103, and the above-described provisions can be applied independently to each through via 103.

[0028] The frame 105 can be made of various materials. For example, it can be made of substantially the same material as the core layer 101. However, it is not limited to this, and may be made of different materials. For example, the core layer 101 can be made of organic insulating materials such as copper foil laminate (CCL), inorganic insulating materials such as silicon or ceramic, or metals such as copper (Cu). However, it is not limited to these. The frame 105 can be used as a jig in the manufacturing process. Therefore, in this case, it may be more advantageous in controlling warpage in the process. In addition, multiple through-holes H can be formed in a large-area frame 105. By utilizing this, multiple printed circuit boards 100A can be manufactured in the same process and then separated by a cutting process, thereby increasing productivity. The through-holes H can penetrate between the upper and lower surfaces of the frame 105. The through-holes H can have a shape corresponding to the shape of the core layer 101 and can have a larger space on a plane than the planar area of ​​the core layer 101. As an example that is not limited to this, the frame 105 may include a copper foil laminate (CCL), the through-hole H may be a cavity formed therein, and the core layer 101 may be a glass core placed in such a cavity.

[0029] The insulating material 107 can include a variety of materials. For example, the insulating material 107 can include an organic insulating material, which can include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material containing an inorganic filler and / or organic filler together with the resin. However, it is not limited to these, and other types of materials may also be included, such as ceramic composites, epoxy-ceramic hybrid resins, and silicon-based materials. The insulating material 107 may also be formed in a separate filling process. Therefore, the bottommost first insulating layer 111 and the topmost third insulating layer 141 may each have interlayer boundaries with the insulating material 107. However, it is not limited to these, and for example, if the materials of the bottommost first insulating layer 111 and / or the topmost third insulating layer 141 and the insulating material 107 are substantially the same, the interlayer boundaries between them may not be defined.

[0030] The first insulating layer 111 may include an organic insulating material. The organic insulating material may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material containing an inorganic filler, an organic filler, and / or glass fiber (glass cloth, glass fabric) together with the resin. For example, the organic insulating material may be a non-photosensitive insulating material such as ABF (Ajinomoto Build-up Film) or PPG (Prepreg), but is not limited to this, and other polymer materials may also be used. The organic insulating material may also be a photosensitive insulating material such as PID (Photo Imageable Dielectric), and may include an adhesive sheet such as BS (Bonding Sheet). The first insulating layer 111 may be one layer or multiple layers, and if there are multiple layers, the above-described contents can be applied independently to each layer. When multiple first insulating layers 111 contain substantially the same organic insulating material to each other, and the interlayer boundaries between them are unclear, the layers can be separated via first wiring layers 112 formed on different layers. The first insulating layer 111 can provide the first insulating body 111 to the first wiring section 110. For example, one or more first insulating layers 111, i.e., multiple first insulating layers 111, can collectively provide a single first insulating body 111.

[0031] The first wiring layer 112 may include metals. These metals may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The first wiring layer 112 can perform various functions depending on the design. For example, it may include signal patterns, power patterns, ground patterns, etc. These patterns can each have various forms such as lines, planes, and pads. The first wiring layer 112 may primarily include patterns other than signal patterns, but is not limited to these. The first wiring layer 112 may include an electroless plating layer (e.g., chemical copper) as a seed layer and an electroplating layer (e.g., electroplated copper) as a pattern layer. However, it is not limited to this, and may also include a sputtered layer (e.g., sputtered titanium / copper) as a seed layer, or may include both a sputtered layer and an electroless plating layer. The first wiring layer 112 can provide relatively low-density wiring to the first insulating body 111. It can also provide conductive patterns with various functions. The first wiring layer 112 may consist of one layer or multiple layers, and if it consists of multiple layers, the above-described provisions can be applied independently to each layer.

[0032] The first wiring via 113 may contain metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The first wiring via 113 may include filled vias that fill via holes, or conformal vias positioned along the walls of via holes. The first wiring via 113 can perform various functions depending on the design. For example, it may include ground vias, power vias, signal vias, etc. The first wiring via 113 may primarily include other vias besides signal vias, but is not limited to these. The first wiring via 113 may include an electroless plating layer (e.g., chemical copper) as a seed layer and an electroplating layer (e.g., electroplated copper) as a pattern layer. However, it may also include a sputtered layer (e.g., sputtered titanium / copper) as a seed layer, or both a sputtered layer and an electroless plating layer. The first wiring via 113 may have a substantially tapered shape in cross-section, where the width of the upper end is wider than the width of the lower end. The first wiring via 113 can provide an electrical connection path to the first insulating body 111. For example, the first wiring layer 112 may consist of multiple layers, and the first wiring via 113 and through via 103 may each consist of multiple first wiring vias 113, in which case some of the multiple first wiring vias 113 can electrically connect the multiple first wiring layers 112 to the multiple through vias 103, and other parts of the multiple first wiring vias 113 can electrically connect the multiple first wiring layers 112 to each other.

[0033] The second insulating layer 121 may include an organic insulating material. The organic insulating material may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material containing an inorganic filler and / or an organic filler together with the resin. For example, the organic insulating material may include a non-photosensitive insulating material such as ABF (Ajinomoto Build-up Film), or a photosensitive insulating material such as PID (Photo Imageable Dielectric). For example, the second insulating layer 121 can be formed as a thin film, and may include an organic insulating material that facilitates the formation of high-density wiring. The second insulating layer 121 may be one layer or multiple layers, and if there are multiple layers, the above-described provisions can be applied independently to each. When multiple second insulating layers 121 contain substantially the same organic insulating material, and the interlayer boundaries between them are unclear, the layers can be separated via second wiring layers 122 formed on different layers. The second insulating layer 121 can provide a second insulating body 121 to the second wiring section 120. For example, one or more second insulating layers 121, i.e., multiple second insulating layers 121, can collectively provide a single second insulating body 121.

[0034] The second wiring layer 122 may contain metals. These metals may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The second wiring layer 122 can perform various functions depending on the design. For example, it may include signal patterns, power patterns, ground patterns, etc. These patterns can each have various forms such as lines, planes, and pads. The second wiring layer 122 may primarily contain signal patterns, but is not limited to this. The second wiring layer 122 may include an electroless plating layer (e.g., chemical copper) as a seed layer and an electroplating layer (e.g., electroplated copper) as a pattern layer. However, it is not limited to this, and may also include a sputtered layer (e.g., sputtered titanium / copper) as a seed layer, or both a sputtered layer and an electroless plating layer. The second wiring layer 122 can provide relatively high-density wiring to the second insulating body 121. The second wiring layer 122 may be one layer or multiple layers, and if there are multiple layers, the above-described provisions can be applied independently to each layer. The bottommost second wiring layer 122 may have a boundary with the topmost first wiring via 113, but they can also be integrated without a boundary.

[0035] The second wiring via 123 may contain metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The second wiring via 123 may include filled vias that fill via holes, or conformal vias positioned along the walls of via holes. The second wiring via 123 can perform various functions depending on the design. For example, it may include ground vias, power vias, signal vias, etc. The second wiring via 123 may primarily consist of signal vias, but is not limited to this. The second wiring via 123 may include an electroless plating layer (e.g., chemical copper) as a seed layer and an electroplating layer (e.g., electroplated copper) as a pattern layer. However, it is not limited to this, and may also include a sputtered layer (e.g., sputtered titanium / copper) as a seed layer, or both a sputtered layer and an electroless plating layer. The first wiring via 113 may have a substantially tapered shape in cross-section, where the width of the upper end is wider than the width of the lower end. The second wiring via 123 can provide an electrical connection path to the second insulating body 121. For example, the second wiring layer 122 may consist of multiple layers, and there may be multiple second wiring vias 123, in which case the multiple second wiring vias 123 may electrically connect the multiple second wiring layers 122 to each other. When there are multiple second wiring vias 123, the above-described provisions can be applied independently to each of them.

[0036] The glass layer 131 may include glass, which is an amorphous solid. The glass may include, for example, pure silicon dioxide (about 100% SiO2), soda-lime glass, borosilicate glass, aluminosilicate glass, etc. However, it is not limited to these, and alternative glass materials such as fluorine glass, phosphoric acid glass, chalcogen glass, etc. may also be used as materials. In addition, other additives may be further included to form glass having specific physical properties. Additives may include magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and / or antimony. They may also include carbonates and / or oxides of such elements and other elements. For example, calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda) may be included. The glass layer 131 may be a layer distinct from organic insulating materials containing glass fibers (glass fiber, glass cloth, glass fabric), such as CCL (copper clad laminate) and PPG (prepreg). For example, the glass layer 131 may include a glass plate.

[0037] The third wiring layer 132 may contain metals. These metals may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The third wiring layer 132 can perform various functions depending on the design. For example, it may include signal patterns, power patterns, ground patterns, etc. These patterns can each have various forms such as lines, planes, and pads. The third wiring layer 132 can mainly consist of signal patterns, but is not limited to this. The third wiring layer 132 may include a sputtered layer (e.g., sputtered titanium / copper) as a seed layer and an electroplated layer (e.g., electroplated copper) as a pattern layer. However, it is not limited to this, and may also include an electroless plating layer (e.g., chemical copper) as a seed layer, or both a sputtered layer and an electroless plating layer. The third wiring layer 132 can provide high-density wiring.

[0038] The third wiring via 133 may contain metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The third wiring via 133 may include filled vias that fill via holes, or conformal vias that are positioned along the walls of via holes. The third wiring via 133 can perform various functions depending on the design. For example, it may include ground vias, power vias, signal vias, etc. The third wiring via 133 may primarily consist of signal vias, but is not limited thereto. The third wiring via 133 may include a sputtered layer (e.g., sputtered titanium / copper) as a seed layer and an electroplated layer (e.g., electroplated copper) as a pattern layer. However, it is not limited thereto; it may also include an electroless plating layer (e.g., chemical copper) as a seed layer, or both a sputtered layer and an electroless plating layer. The third wiring via 133 may have a substantially tapered shape in cross-section, where the width of its upper end is wider than the width of its lower end. The third wiring via 133 can provide an electrical connection path between the third wiring layer 132 and the second wiring section 120. For example, there may be multiple third wiring vias 133, in which case the multiple third wiring vias 133 may electrically connect the second and third wiring layers 122 and 132 to each other. When there are multiple third wiring vias 133, the above-described provisions can be applied independently to each of them.

[0039] The conductive bump 135 may include metals. These metals may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The conductive bump 135 may also be a metal post, for example, a copper post, but is not limited thereto. The conductive bump 135 may include signal bumps, power bumps, ground bumps, etc., and may include mostly signal bumps, but is not limited thereto. The conductive bump 135 may include an electroless plating layer (e.g., chemical copper) as a seed layer and an electroplating layer (e.g., electroplated copper) as a pattern layer. However, it may also include a sputtered layer (e.g., sputtered titanium / copper) as a seed layer, or it may include both a sputtered layer and an electroless plating layer. The conductive bump 135 may be electrically and physically connected to the third wiring layer 132. There may be multiple conductive bumps 135, and the above-described provisions can be applied independently to each of them.

[0040] The surface treatment layer P can be placed on the upper surface of the conductive bump 135. The surface treatment layer P can consist of a single metal or a combination thereof, such as copper (Cu), nickel (Ni), palladium (Pd), gold (Au), or tin (Sn), which can be formed by methods such as plating, sputtering, vapor deposition, or reflow. Such a surface treatment layer P can provide functions such as regulating the formation of intermetallic compounds, minimizing electrical contact resistance, preventing oxidation, and improving wettability during the reflow process, thereby contributing to improved reliability of the entire packaging process. For example, if the conductive bump 135 includes a copper post, the surface treatment layer P can have a multilayer structure including a nickel layer, a copper layer, and a tin layer. For example, the metal post 135 on which the surface treatment layer P is formed may, but is not limited to, have a CNCS(Cu / Ni / Cu / Sn) bump structure, and may have other combination bump structures such as a CS(Cu / Sn) bump structure.

[0041] The third insulating layer 141 may include an organic insulating material. The organic insulating material may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material containing an inorganic filler, an organic filler, and / or glass fiber (glass cloth, glass fabric) together with the resin. For example, the organic insulating material may be a non-photosensitive insulating material such as ABF (Ajinomoto Build-up Film) or PPG (Prepreg), but is not limited to this, and other polymer materials may also be used. The organic insulating material may also be a photosensitive insulating material such as PID (Photo Imageable Dielectric), and may include an adhesive sheet such as BS (Bonding Sheet). The third insulating layer 141 may be one layer or multiple layers, and if there are multiple layers, the above-described contents can be applied independently to each layer. When multiple third insulating layers 141 contain substantially the same organic insulating material to each other, and the interlayer boundaries between them are unclear, the layers can be separated via a fourth wiring layer 142 formed on different layers. The third insulating layer 141 can provide a third insulating body 141 to the third wiring section 140. For example, one or more third insulating layers 141, i.e., multiple third insulating layers 141, can collectively provide a single third insulating body 141.

[0042] The fourth wiring layer 142 may include metals. These metals may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The fourth wiring layer 142 can perform various functions depending on the design. For example, it may include signal patterns, power patterns, ground patterns, etc. These patterns can each have various forms such as lines, planes, and pads. The fourth wiring layer 142 may, but is not limited to, include patterns other than signal patterns. The fourth wiring layer 142 may include an electroless plating layer (e.g., chemical copper) as a seed layer and an electroplating layer (e.g., electroplated copper) as a pattern layer. However, it is not limited to this, and may also include a sputtered layer (e.g., sputtered titanium / copper) as a seed layer, or may include both a sputtered layer and an electroless plating layer. The fourth wiring layer 142 can provide relatively low-density wiring to the third insulating body 141. It can also provide conductive patterns with various functions. The fourth wiring layer 142 may be one layer or multiple layers, and if there are multiple layers, the above-described provisions can be applied independently to each layer.

[0043] The fourth wiring via 143 may contain metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The fourth wiring via 143 may include a filled via that fills a via hole, or a conformal via that is positioned along the wall of the via hole. The fourth wiring via 143 can perform various functions depending on the design. For example, it may include a ground via, power via, signal via, etc. The fourth wiring via 143 may primarily include other vias other than signal vias, but is not limited to these. The fourth wiring via 143 may include an electroless plating layer (e.g., chemical copper) as a seed layer and an electroplating layer (e.g., electroplated copper) as a pattern layer. However, it may also include a sputtered layer (e.g., sputtered titanium / copper) as a seed layer, or both a sputtered layer and an electroless plating layer. The fourth wiring via 143 may have a substantially tapered shape in cross-section, where the width of the upper end is wider than the width of the lower end. The fourth wiring via 143 can provide an electrical connection path to the third insulating body 141. For example, the fourth wiring layer 142 may consist of multiple layers, and there may be multiple fourth wiring vias 143 and multiple through vias 103. In this case, some of the multiple fourth wiring vias 143 can electrically connect the multiple fourth wiring layers 142 to the multiple through vias 103, and other parts of the multiple fourth wiring vias 143 can electrically connect the multiple fourth wiring layers 142 to each other. When there are multiple fourth wiring vias 143, the above-described provisions can be applied independently to each of them.

[0044] The semiconductor chips 151 and 152 may include integrated circuit (IC) dies in which hundreds to millions or more elements are integrated within a single chip. The integrated circuit may be a logic chip such as a central processor (CPU), graphics processor (GPU), field-programmable gate array (FPGA), digital signal processor (DSP), cryptographic processor, microprocessor, microcontroller, application processor (AP), analog-to-digital converter, or ASIC (Application-Specific IC). However, it is not limited to these, and may also be a memory chip such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, or HBM (High Bandwidth Memory), or it may be a form in which various functions are integrated into a single chip, such as a System on Chip (SoC). For example, the first semiconductor chip 151 may be a logic chip such as a CPU or GPU, and the second semiconductor chip 152 may be a memory chip such as HBM, in which case a large number of second semiconductor chips 152 may be arranged around the first semiconductor chip 151. Alternatively, the first semiconductor chip 151 may be an input / output die, and the second semiconductor chip 152 may be a chiplet of a logic chip such as a CPU or GPU and / or a memory chip such as HBM. In this case as well, multiple second semiconductor chips 152 may be arranged around the first semiconductor chip 151. For example, a highly integrated package configuration may be possible. There may be multiple first and second semiconductor chips 151 and 152, and the above-described content can be applied independently to each of them.

[0045] The first electrical coupling metal 155 may include metals such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the first electrical coupling metal 155 may include copper bumps. Alternatively, the first electrical coupling metal 155 may include solder bumps. Alternatively, the first electrical coupling metal 155 may include a combination of copper bumps and solder bumps. There may be multiple first electrical coupling metals 155, and the above-described features can be applied independently to each. Multiple first electrical coupling metals 155 can each be coupled to multiple conductive bumps 135. For example, multiple first electrical coupling metals 155 may each be bonded to a surface treatment layer P formed on each of the multiple conductive bumps 135.

[0046] The solder resist layer 160 may include a liquid or film-type solder resist, but is not limited thereto; other types of insulating materials such as ABF may be used. A surface treatment layer and / or metal bumps may be formed on each pattern exposed to the multiple openings h, as needed. Each pattern exposed to the multiple openings h may be in the form of SMD (Solder Mask Defined) and / or NSMD (Non Solder Mask Defined), but is not limited thereto. The solder resist layer 160 can protect internal components of the printed circuit board 100A, such as the third wiring section 140.

[0047] The second electrical connecting metal 165 can be formed from a low-melting-point metal, such as a solder of tin (Sn)-aluminum (Al)-copper (Cu), but this is merely an example and the material is not particularly limited thereto. The second electrical connecting metal 165 may also be a ball, a pin, etc. The second electrical connecting metal 165 may be formed in multiple layers or a single layer. When formed in multiple layers, it may include copper columns and solder, and when formed in a single layer, it may include tin-silver solder, but is not limited thereto. The second electrical connecting metal 165 can be used to mount the printed circuit board 100A to another board such as a main board. There may be multiple second electrical connecting metals 165, and the above-described contents can be applied independently to each of them.

[0048] Figure 2 is a schematic cross-sectional view showing a modified example of a printed circuit board.

[0049] Referring to the drawings, the modified printed circuit board 100B, in the printed circuit board 100A of the above example, may further include a fourth wiring section 170 disposed above the glass layer 131 and comprising one or more fourth insulating layers 171, one or more fifth wiring layers 172 disposed on or within the one or more fourth insulating layers 171, and one or more fifth wiring vias 173 that penetrate at least a portion of at least one of the one or more fourth insulating layers 171. Furthermore, one or more first insulating layers 111, one or more second insulating layers 121, and one or more third insulating layers 141 may each contain an organic insulating material, while one or more fourth insulating layers 171 may each contain an inorganic insulating material. The third wiring layer 132 and one or more fifth wiring layers 172 can be electrically connected to each other via one or more fifth wiring vias 173. The uppermost fifth wiring layer 172 may, if necessary, be electrically connected to the fifth wiring layers 172 of other layers via fifth wiring vias not specifically shown in the drawings.

[0050] For example, high-density wiring can be further formed on the upper side of the glass layer 131 using an inorganic insulating material as a base. In this case, by utilizing the flatness characteristics of the glass layer 131 and the thin-film characteristics of one or more fourth insulating layers 171 containing the inorganic insulating material, one or more fifth wiring layers 172 and one or more fifth wiring vias 173 can be formed as fine wiring and fine vias, respectively. Therefore, the outer configuration of the substrate including the fourth wiring section 170 can be easily utilized as a silicon interposer or interconnect bridge for die-to-die signal transmission, and can also easily perform other roles of high-density wiring sections.

[0051] On the other hand, each of the four fourth insulating layers 171 may include one or more silicon oxide films and silicon nitride films. However, it is not limited to these, and various other inorganic insulating materials used as materials for inorganic insulating films in semiconductor processes can also be used. When one or more of the four fourth insulating layers 171 include such inorganic insulating materials, the four fourth insulating layers 171 can be formed as thinner films. For example, the thickness of at least one of the four fourth insulating layers 171 may be thinner than the thickness of at least one of the four first insulating layers 111, at least one of the four second insulating layers 121, at least one of the four third insulating layers 141, and the glass layer 131. For example, the thickness of one or more fourth insulating layers 171, that is, the height from the bottom surface to the top surface of each, may be 5 μm or less, but is not limited to this.

[0052] Furthermore, at least one of the five fifth wiring layers 172 may include wiring that is relatively denser than at least one of the one or more first wiring layers 112 and at least one of the one or more fourth wiring layers 142. For example, each of the five fifth wiring layers 172 may include wiring that is relatively denser than each of the one or more first wiring layers 112 and each of the one or more fourth wiring layers 142. For example, the thickness of at least one of the five fifth wiring layers 172 may be thinner than the thickness of at least one of the one or more first wiring layers 112 and at least one of the one or more fourth wiring layers 142. For example, the thickness of each of the five fifth wiring layers 172 may be thinner than the thickness of each of the one or more first wiring layers 112 and each of the one or more fourth wiring layers 142. For example, each of the five fifth wiring layers 172 may include multiple line patterns, in which case the minimum line width, minimum spacing, and minimum thickness of the multiple line patterns may be 3 μm or less, but are not limited thereto.

[0053] Furthermore, at least one of the five vias 173 may be of a relatively higher density than at least one of the first vias 113 and at least one of the fourth vias 143. For example, each of the five vias 173 may be of a relatively higher density than each of the first vias 113 and each of the fourth vias 143. For example, the thickness of at least one of the five vias 173 may be thinner than the thickness of at least one of the first vias 113 and at least one of the fourth vias 143. For example, the thickness of each of the five vias 173 may be thinner than the thickness of each of the first vias 113 and each of the fourth vias 143.

[0054] On the other hand, the fourth wiring section 170 can be called the fourth build-up wiring section 170. Also, the fourth insulating layer 171 as a whole can be called the fourth insulating body 171. Also, the fifth wiring layer 172 can be called the fifth build-up wiring layer 172. Also, the fifth wiring via 173 can be called the fifth build-up wiring via 173. For example, the terms used in this invention can, of course, be substituted for each other according to the structure, function, or common understanding in the general art of the components, as described above, and this should not be interpreted as limiting the scope of protection of this invention.

[0055] In this case, the minimum line width, minimum thickness, and minimum spacing of the wiring contained in at least one of the plurality of fifth build-up wiring layers 172 may be smaller than the minimum line width, minimum thickness, and minimum spacing of the wiring contained in at least one of the plurality of first build-up wiring layers 112, and at least one of the plurality of third build-up wiring layers 142, for example, the minimum line width, minimum thickness, and minimum spacing of the wiring contained in at least one of the plurality of third build-up wiring layers 142. For example, the plurality of fifth build-up wiring layers 172 may include wiring and / or fine wiring that are relatively denser than the plurality of first build-up wiring layers 112 and the plurality of third build-up wiring layers 142.

[0056] On the other hand, the multiple conductive bumps 135 can be positioned above the fourth wiring section 170, which is positioned above the glass layer 131. For example, the multiple conductive bumps 135 may each be positioned above at least one of the one or more fifth wiring layers 172, rather than above the third wiring layer 132, and may each be connected to at least a portion of at least one of the one or more fifth wiring layers 172. For example, the multiple conductive bumps 135 may each be connected to at least one of the multiple pad patterns of the one or more fifth wiring layers 172. A portion of each of the multiple conductive bumps 135, for example, at least a portion of their lower ends, may be covered with one or more fourth insulating layers 171. Multiple semiconductor chips 151, 152 can be electrically connected to one or more fifth wiring layers 172 via the multiple conductive bumps 135.

[0057] In the following section, the components of the modified printed circuit board 100B will be described in more detail with reference to the drawings.

[0058] The fourth insulating layer 171 may include an inorganic insulating material. The inorganic insulating material may be, for example, silicon oxide or silicon nitride. For example, the fourth insulating layer 171 may include one or more silicon oxide films and silicon nitride films. However, it is not limited thereto, and other inorganic insulating materials used as materials for inorganic insulating films in semiconductor processes may also be used. For example, the fourth insulating layer 171 may include, but is not limited to, silicon dioxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), boron nitride (BN), and / or silicon carbide (SiC). The fourth insulating layer 171 may be one layer or multiple layers, and if there are multiple layers, the above-described contents may be applied independently to each layer. When multiple fourth insulating layers 171 contain substantially the same inorganic insulating material, and the interlayer boundaries between them are unclear, the layers can be separated via fifth wiring layers 172 formed on different layers. The fourth insulating layer 171 can provide a fourth insulating body 171 to the fourth wiring section 170. For example, one or more fourth insulating layers 171, i.e., multiple fourth insulating layers 171, can collectively provide a single fourth insulating body 171.

[0059] The fifth wiring layer 172 may contain metals. These metals may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The fifth wiring layer 172 can perform various functions depending on the design. For example, it may include signal patterns, power patterns, ground patterns, etc. These patterns can each have various forms such as lines, planes, and pads. The fifth wiring layer 172 may primarily contain signal patterns, but is not limited to this. The fifth wiring layer 172 may include a sputtered layer (e.g., sputtered titanium / copper) as a seed layer and an electroplated layer (e.g., electroplated copper) as a pattern layer. However, it is not limited to this, and may also include an electroless plating layer (e.g., chemical copper) as a seed layer, or both a sputtered layer and an electroless plating layer. The third wiring layer 132 can provide high-density wiring. The fifth wiring layer 172 can provide relatively high-density wiring to the fourth insulating body 171. The fifth wiring layer 172 may be one layer or multiple layers, and if there are multiple layers, the above-described provisions can be applied independently to each layer.

[0060] The fifth wiring via 173 may contain metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The fifth wiring via 173 may include a filled via that fills a via hole, or a conformal via that is positioned along the wall of the via hole. The fifth wiring via 173 can perform various functions depending on the design. For example, it may include a ground via, power via, signal via, etc. The fifth wiring via 173 may primarily consist of signal vias, but is not limited to this. The fifth wiring via 173 may include a sputtered layer (e.g., sputtered titanium / copper) as a seed layer and an electroplated layer (e.g., electroplated copper) as a pattern layer. However, it is not limited to this, and may also include an electroless plating layer (e.g., chemical copper) as a seed layer, or both a sputtered layer and an electroless plating layer. The fifth wiring via 173 may have a substantially tapered shape in cross-section, where the width of the upper end is wider than the width of the lower end. The fifth wiring via 173 can provide an electrical connection path to the fourth insulating body 171. For example, the fifth wiring layer 172 may consist of multiple layers, and there may be multiple fifth wiring vias 173, in which case the multiple fifth wiring vias 173 may electrically connect the multiple fifth wiring layers 172 to each other. When there are multiple fifth wiring vias 173, the above-described provisions can be applied independently to each of them.

[0061] Other explanations may be substantially the same as those described for printed circuit board 100A in the example described above. For example, the contents described for printed circuit board 100A in the example described above can be applied substantially similarly to printed circuit board 100B in the modified example, as long as they do not contradict each other.

[0062] Figures 3a to 3d are schematic cross-sectional views illustrating an example of the manufacturing process of a printed circuit board.

[0063] Referring to Figure 3a, a frame 105 having through-holes H can be prepared. A core layer 101 with through-vias 103 formed in the through-holes H can be placed there. The remaining space of the through-holes 105 can be filled with insulating material 107. The frame 105 can be used as a jig in the manufacturing process. Multiple through-holes H may be formed in a large-area frame 105, and core layers 101 with through-vias 103 formed in each through-hole H can be placed in unit units. In this case, after manufacturing the substrate in panel units, it can be cut into numerous unit substrates. Next, a build-up process can be performed on the upper and lower sides of the core layer 101, frame 105, and insulating material 107, respectively, to form the first and third insulating layers 111, 141, the first and fourth wiring layers 112, 142, and the first and fourth wiring vias 113, 143. For example, all or part of the first wiring section 110 and / or the third wiring section 140 described above can be formed. The build-up process may include laminating organic insulating layers, forming via holes in the organic insulating layers, and forming wiring vias and wiring layers on the via holes and the organic insulating layers, respectively. The lamination of the organic insulating layers may, for example, involve laminating non-photosensitive or photosensitive insulating materials. Via holes can be formed, for example, by laser processing. Alternatively, a photoprocessing and etching process may be used. Wiring vias can be formed by a plating process including electroless plating and electrolytic plating. Wiring layers can be formed by a photoprocessing using a dry film, and a plating process including electroless plating and electrolytic plating. Such a build-up process can be repeated. For example, the build-up process can be repeated until a desired target number of layers is reached.

[0064] Referring to Figure 3b, a build-up process can be further performed on the upper side of the first wiring section 110 to form a second wiring section 120 including a second insulating layer 121, a second wiring layer 122, and a second wiring via 123. Before forming the second wiring section 120, a first wiring via 113 can be further formed on the uppermost first insulating layer 111, thereby forming the second wiring section 120. Before forming the second wiring section 120, if necessary, the upper surface of the first wiring section 110, for example, the upper surface of the uppermost first insulating layer 111, can be flattened by a polishing process or the like. The build-up process may be the same as described above. However, an organic insulating layer that facilitates the formation of fine wiring may be laminated. Alternatively, fine via holes may be formed in such an organic insulating layer, and fine wiring vias and fine wiring layers may be formed in the fine via holes and the organic insulating layer, respectively. Such a build-up process can be repeated. For example, the build-up process can be repeated until a desired target number of layers is reached.

[0065] Referring to Figure 3c, the glass layer 131 can be placed above the second wiring section 120. For example, the upper surface of the second wiring section 120, for example, the upper surface of the uppermost second insulating layer 121, can be flattened by a polishing process, and then the glass layer 131 can be attached to the flattened upper surface of the second wiring section 120, for example, the upper surface of the uppermost second insulating layer 121, in a lamination process. If necessary, the glass layer 131 can be attached using an adhesive such as an adhesion promoter or adhesive film. For example, the glass layer 131 can be attached to the flattened upper surface of the second wiring section 120, for example, the upper surface of the uppermost second insulating layer 121, using such an adhesive. Next, via holes can be formed that penetrate both the glass layer 131 and the uppermost second insulating layer 121, and a third wiring layer 132 and a third wiring via 133 can be formed on the upper surface of the glass layer 131 and in the via holes, respectively. Via holes that penetrate both the glass layer 131 and the uppermost second insulating layer 121 can be formed by laser processing or etching. Furthermore, via holes can be formed in the bottommost third insulating layer 141, and a fourth wiring layer 142 and fourth wiring vias 143 can be further formed by photoprocessing and plating processes, thereby forming the third wiring section 140. A solder resist layer 160 can also be formed below the third wiring section 140. The solder resist layer 160 can be formed by a solder resist film lamination process or a solder resist material coating process.

[0066] Referring to Figure 3d, multiple conductive bumps 135 can be formed on the third wiring layer 132. Furthermore, a surface treatment layer P can be formed on each of the multiple conductive bumps 135, and multiple semiconductor chips 151 and 152 can be mounted using multiple first electrically connecting metals 155. The multiple conductive bumps 135 can be formed using a photoprocessing step and a plating step using a dry film. The surface treatment layer P can be formed using methods such as plating, sputtering, vapor deposition, or reflow, depending on the material used. Additionally, multiple openings h can be formed in the solder resist layer 160, and multiple second electrically connecting metals 165 can be formed on each of the multiple openings h. The multiple second electrically connecting metals 165 can be formed by solder ball adhesion and a reflow step, respectively. Through this series of processes, the printed circuit board 100A according to the above example can be manufactured. On the other hand, before forming the multiple conductive bumps 135, a fourth wiring section 170 including a fourth insulating layer 171, a fifth wiring layer 172, and a fifth wiring via 173 can be formed on the glass layer 131, in which case the printed circuit board 100B according to the above-described modified example can be manufactured. The fourth wiring section 170 can be formed, for example, by a process similar to the build-up process in semiconductor manufacturing. For example, an inorganic insulating film can be formed, fine via holes can be formed in the inorganic insulating film, and fine wiring vias and a fine wiring layer can be formed on the fine via holes and the inorganic insulating film, respectively. The inorganic insulating film can be formed using CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), ALD (Atomic Layer Deposition), etc. Fine via holes can be formed by an etching process. Fine wiring vias and fine wiring layers can be formed by a plating process including a metal sputtering process and electroplating.

[0067] Other explanations may be substantially the same as those described for printed circuit board 100A in the example and printed circuit board 100B in the modified example described above. For example, the contents described for printed circuit board 100A in the example and printed circuit board 100B in the modified example described above can be applied substantially similarly to the example of manufacture and its modified examples, insofar as they do not contradict each other.

[0068] Figure 4 is a schematic cross-sectional view showing another example of a printed circuit board, and Figure 5 is a schematic cross-sectional view showing a modified example of the printed circuit board according to the other example.

[0069] Referring to the drawings, in the printed circuit board 100C according to another example and the printed circuit board 100D according to a modified example thereof, the bottommost first insulating layer 111 and / or the topmost third insulating layer 141 can be integrated with the insulating material 107 without interlayer boundaries, as in the printed circuit board 100A according to the above example and the printed circuit board 100B according to a modified example thereof. For example, the first insulating body 111 and / or the third insulating body 141 may be integrated with the insulating material 107 without interlayer boundaries. For example, the insulating material 107 may be formed by filling at least a portion of the through-hole H when laminating the bottommost first insulating layer 111 and / or the topmost third insulating layer 141. Alternatively, the insulating material 107 may contain substantially the same insulating material as the bottommost first insulating layer 111 and / or the topmost third insulating layer 141, in which case the layers containing substantially the same insulating material can be integrated with each other without interlayer boundaries. For example, the insulating material 107 may be integrated with at least a part of the first insulating body 111, or with at least a part of the third insulating body 141, or with at least a part of each of the first and third insulating bodies 111 and 141.

[0070] Other explanations may be substantially the same as those described for printed circuit board 100A relating to the above example and printed circuit board 100B relating to a modified example. For example, the contents described for printed circuit board 100A relating to the above example and printed circuit board 100B relating to a modified example can be substantially applied to printed circuit board 100C relating to another example and printed circuit board 100D relating to a modified example thereof, insofar as they do not contradict each other.

[0071] Figure 6 is a schematic cross-sectional view showing yet another example of a printed circuit board, and Figure 7 is a schematic cross-sectional view showing a modified example of a printed circuit board according to yet another example.

[0072] Referring to the drawings, in the printed circuit board 100E according to yet another example and the printed circuit board 100F according to a modified example thereof, the frame 105 and insulating material 107 may be omitted, and the core layer 101 may be arranged over a larger area, in the printed circuit board 100A according to the above example and the printed circuit board 100B according to a modified example thereof. In this case, the process may be simplified. In this case as well, the core layer 101 may include a glass core layer containing glass, a ceramic core layer containing ceramic, a silicon core layer containing silicon, a metal core layer containing metal, and / or a copper foil laminate (CCL), as described above.

[0073] Other explanations may be substantially the same as those described for printed circuit board 100A relating to the above example and printed circuit board 100B relating to a modified example. For example, the contents described for printed circuit board 100A relating to the above example and printed circuit board 100B relating to a modified example can be substantially applied to printed circuit board 100E relating to another example and printed circuit board 100F relating to a modified example thereof, insofar as they do not contradict each other.

[0074] In this invention, line width, spacing, thickness, width, length, pitch, depth, etc., can be measured using a scanning microscope or optical microscope based on a cross-section obtained by polishing or cutting the printed circuit board. The cut cross-section can be a vertical or horizontal cross-section, and each value can be measured based on the required cut cross-section. If the values ​​are not constant, the values ​​can be determined by the average value of the values ​​measured at any five points. The width of the upper and / or lower ends of the vias can be measured on a cross-section obtained by cutting the substrate along the central axis of the vias in the thickness direction. The depth of the vias can be measured as the distance from the upper end to the lower end of the vias on a cross-section obtained by cutting the substrate along the central axis of the vias in the thickness direction.

[0075] In this invention, the expression "cover" can include not only cases of covering the entire surface but also cases of covering at least a part of it, and can include cases of covering not only directly but also indirectly. Furthermore, the expression "fill" can include not only cases of completely filling but also cases of generally filling, and can include cases where, for example, some voids or air pockets exist.

[0076] In this invention, "substantially" can be determined to include process errors, positional deviations, and measurement errors that occur during the manufacturing process. For example, "substantially the same line width, spacing, thickness, height, etc." can include not only cases where the numerical values ​​are exactly the same, but also cases where they are approximately similar. Furthermore, "substantially having a certain shape" can include not only cases where the shape is exactly the same, but also cases where it is approximately the same. In addition, "substantially coplane" can include not only cases where they are exactly on the same plane, but also cases where they are approximately on the same plane.

[0077] In this invention, "substantially identical materials" can mean not only completely identical materials, but also materials of the same type. Therefore, while the composition of the materials may be substantially the same, their specific compositional ratios may differ slightly.

[0078] In this invention, "on a cross-section" can mean the cross-sectional shape when the object is cut vertically, or the cross-sectional shape when the object is viewed from the side. Furthermore, "on a plane" can mean the planar shape when the object is cut horizontally, or the planar shape when the object is viewed from the top or bottom.

[0079] In this invention, terms such as "lower side," "lower part," and "bottom surface" are used for convenience to mean the downward direction relative to the cross-section in the drawing, while terms such as "upper side," "upper part," and "top surface" are used to mean the opposite direction. Furthermore, terms such as "side" and "side" are used to mean the direction perpendicular to the top and bottom surfaces. However, these definitions of direction are for illustrative purposes only, and the scope of rights in the patent claims is not specifically limited by such descriptions of direction; the concepts of "up" and "down" can change at any time.

[0080] In this invention, "connected" is a concept that includes not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, "electrically connected" is a concept that includes both cases where they are physically connected and cases where they are not connected. In addition, expressions such as "first," "second," etc., are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, within the scope of the rights, the first component may be named the second component, and similarly, the second component may be named the first component.

[0081] The expression "example" as used in this invention does not mean that each embodiment is the same as another, but is provided to highlight and illustrate the unique and distinct features of each. However, the examples presented above do not preclude their realization in combination with features of other examples. For example, even if a matter described in a particular example is not described in another example, it can be understood as a description related to that other example, unless there is a contradictory or contrary description of that matter in the other example.

[0082] The terms used in this invention are used merely to illustrate an example and are not intended to limit the invention. In this context, singular expressions include plural expressions unless the context clearly indicates a different meaning. [Explanation of Symbols]

[0083] 100A, 100B, 100C, 100D, 100E, 100F: Printed circuit board 101: Core Layer 103: Through-beam 105: Frame 107: Insulating material H: Penetration part 110: First wiring section (first build-up wiring section) 111: First insulating layer (first insulating body) 112: First wiring layer (first build-up wiring layer) 113: First wiring via (first build-up wiring via) 120: Second wiring section (second build-up wiring section) 121: Second insulating layer (second insulating body) 122: Second wiring layer (second build-up wiring layer) 123: Second wiring via (second build-up wiring via) 131: Glass layer 132: Third wiring layer (fourth build-up wiring layer) 133: Third wiring via (fourth build-up wiring via) 135: Conductive bump P: Surface treatment layer 140: Third wiring section (Third build-up wiring section) 141: Third insulating layer (third insulating body) 142: Fourth wiring layer (third build-up wiring layer) 143: 4th wiring via (3rd build-up wiring via) 151, 152: Semiconductor chips 155: Electrically connected metal 160: Solder resist layer 165: Electrically connected metal h: opening 170: Fourth wiring section (Fourth build-up wiring section) 171: Fourth insulating layer (fourth insulating body) 172: Fifth wiring layer (Fifth build-up wiring layer) 173: Fifth wiring via (Fifth build-up wiring via)

Claims

1. The core layer, A first wiring section is disposed above the core layer and includes one or more first insulating layers and one or more first wiring layers each disposed within the one or more first insulating layers, A second wiring section is located above the first wiring section and includes one or more second insulating layers and one or more second wiring layers each located within the one or more second insulating layers, A glass layer positioned above the second wiring section, It includes a third wiring layer disposed on the upper surface of the glass layer, A printed circuit board in which the thickness of the third wiring layer is thinner than the thickness of at least one of the one or more first wiring layers.

2. The printed circuit board according to claim 1, wherein the thickness of at least one of the one or more second wiring layers is thinner than the thickness of at least one of the one or more first wiring layers.

3. The printed circuit board according to claim 2, wherein the thickness of the glass layer and the thickness of at least one of the one or more second insulating layers are each thinner than the thickness of at least one of the one or more first insulating layers.

4. The first wiring section further includes one or more first wiring vias that penetrate at least a portion of at least one of the one or more first insulating layers, The printed circuit board according to claim 1, wherein the second wiring portion further includes one or more second wiring vias that each penetrate at least a portion of at least one of the one or more second insulating layers.

5. The printed circuit board according to claim 4, further comprising one or more third wiring vias that collectively penetrate at least a portion of the glass layer and the uppermost second insulating layer among the one or more second insulating layers.

6. One or more through vias that penetrate at least a portion of the core layer, The printed circuit board according to claim 5, further comprising: disposed below the core layer; one or more third insulating layers; one or more fourth wiring layers disposed on or within the one or more third insulating layers; and a third wiring portion including one or more fourth wiring vias that penetrate at least a portion of at least one of the one or more third insulating layers.

7. Between the upper surface of the core layer and the lowest first wiring layer among the one or more first wiring layers, the lowest first insulating layer among the one or more first insulating layers is arranged. Between the lower surface of the core layer and the uppermost of the one or more fourth wiring layers, the uppermost of the one or more third insulating layers is arranged. The upper surface of each of the one or more through vias is in contact with at least one of the one or more first wiring vias that penetrates at least a portion of the bottommost first insulating layer. The printed circuit board according to claim 6, wherein the lower surface of each of the one or more through vias is in contact with at least one of the one or more fourth wiring vias that penetrates at least a portion of the uppermost third insulating layer.

8. The one or more first insulating layers, the one or more second insulating layers, and the one or more third insulating layers each include a plurality of first insulating layers, a plurality of second insulating layers, and a plurality of third insulating layers. The one or more first wiring layers, the one or more second wiring layers, and the one or more fourth wiring layers each include a plurality of first wiring layers, a plurality of second wiring layers, and a plurality of fourth wiring layers. The printed circuit board according to claim 6, wherein the one or more first wiring vias, the one or more second wiring vias, the one or more third wiring vias, and the one or more fourth wiring vias each include a plurality of first wiring vias, a plurality of second wiring vias, a plurality of third wiring vias, and a plurality of fourth wiring vias.

9. A plurality of conductive bumps, each arranged on the third wiring layer and connected to at least a portion of the third wiring layer, The printed circuit board according to claim 6, further comprising a plurality of semiconductor chips, each disposed on the glass layer and each connected to one or more of the plurality of conductive bumps.

10. The fourth wiring section is disposed above the glass layer and further includes one or more fourth insulating layers, one or more fifth wiring layers disposed on or within the one or more fourth insulating layers, and one or more fifth wiring vias that penetrate at least a portion of at least one of the one or more fourth insulating layers. The one or more first insulating layers, the one or more second insulating layers, and the one or more third insulating layers each contain an organic insulating material. The printed circuit board according to claim 6, wherein each of the one or more fourth insulating layers comprises an inorganic insulating material.

11. The printed circuit board according to claim 10, wherein each of the one or more fourth insulating layers comprises one or more of a silicon oxide film and a silicon nitride film.

12. The printed circuit board according to claim 10, wherein the thickness of at least one of the one or more fourth insulating layers is thinner than the thickness of at least one of the one or more first insulating layers, the thickness of at least one of the one or more second insulating layers, the thickness of at least one of the one or more third insulating layers, and the thickness of the glass layer.

13. The printed circuit board according to claim 10, wherein each of the multiple line patterns included in one or more fifth wiring layers has a minimum line width, minimum spacing, and minimum thickness of 3 μm or less.

14. A plurality of conductive bumps, each disposed on at least one of the one or more fifth wiring layers, and each connected to at least a portion of at least one of the one or more fifth wiring layers, The printed circuit board according to claim 10, further comprising: a plurality of semiconductor chips, each arranged on the fourth wiring section and each connected to one or more of the plurality of conductive bumps.

15. A frame having a through-hole, The present invention further includes an insulating material that fills at least a portion of the aforementioned penetration, At least a portion of the core layer is disposed within the penetration portion, The insulating material is placed between the frame and the core layer. The one or more first insulating layers cover the upper surface of the core layer, the upper surface of the frame, and the upper surface of the insulating material, respectively. The printed circuit board according to claim 6, wherein one or more third insulating layers cover the lower surface of the core layer, the lower surface of the frame, and the lower surface of the insulating material, respectively.

16. The printed circuit board according to claim 15, wherein the lowest first insulating layer among the one or more first insulating layers, and the uppermost third insulating layer among the one or more third insulating layers, each have an interlayer boundary with the insulating material.

17. The printed circuit board according to claim 15, wherein the lowest first insulating layer among the one or more first insulating layers, the uppermost third insulating layer among the one or more third insulating layers, or each of the lowest first insulating layer and the uppermost third insulating layer are integrated with the insulating material without interlayer boundaries.

18. The printed circuit board according to claim 1, wherein the core layer includes one or more of the following: a glass core layer, a ceramic core layer, a silicon core layer, a metal core layer, and a copper foil laminate (CCL).

19. Glass core and A first build-up wiring section comprising a first insulating body disposed above the glass core, a plurality of first build-up wiring layers disposed on or within the first insulating body, and a plurality of first build-up wiring vias disposed within the first insulating body, A second build-up wiring section comprising a second insulating body positioned above the first insulating body, a plurality of second build-up wiring layers positioned on or within the second insulating body, and a plurality of second build-up wiring vias positioned within the second insulating body, A third build-up wiring section comprising a third insulating body disposed below the glass core, a plurality of third build-up wiring layers disposed on or within the third insulating body, and a plurality of third build-up wiring vias disposed within the third insulating body, It includes a plurality of through vias, each surrounded by the aforementioned glass core, A printed circuit board in which the minimum line width of a wiring included in at least one of the plurality of second build-up wiring layers is smaller than the minimum line width of a wiring included in at least one of the plurality of first build-up wiring layers and at least one of the plurality of third build-up wiring layers, respectively.

20. The printed circuit board according to claim 19, wherein the minimum thickness of the wiring included in at least one of the plurality of second build-up wiring layers is thinner than the minimum thickness of the wiring included in at least one of the plurality of first build-up wiring layers and at least one of the plurality of third build-up wiring layers, respectively.

21. A frame having a through-hole, The present invention further includes an insulating material that fills at least a portion of the aforementioned penetration, At least a portion of the glass core is disposed within the through-hole, The insulating material is placed between the frame and the glass core. The first insulating body covers the upper surface of the glass core, the upper surface of the frame, and the upper surface of the insulating material, respectively. The printed circuit board according to claim 19, wherein the third insulating body covers the lower surface of the glass core, the lower surface of the frame, and the lower surface of the insulating material, respectively.

22. The printed circuit board according to claim 21, wherein the first insulating body and the third insulating body each have an interlayer boundary with the insulating material.

23. The printed circuit board according to claim 21, wherein the first insulating body, the third insulating body, or each of the first insulating body and the third insulating body are integrated with the insulating material without interlayer boundaries.

24. A glass layer positioned above the second build-up wiring section, A fourth build-up wiring layer is disposed on the glass layer, The present invention further includes a plurality of fourth build-up wiring vias that collectively penetrate the glass layer and a portion of the second insulating body, The minimum line width of the wiring included in the fourth build-up wiring layer is smaller than the minimum line width of the wiring included in at least one of the plurality of first build-up wiring layers and at least one of the plurality of third build-up wiring layers, The printed circuit board according to claim 19, wherein the minimum thickness of the wiring included in the fourth build-up wiring layer is thinner than the minimum thickness of the wiring included in at least one of the plurality of first build-up wiring layers and at least one of the plurality of third build-up wiring layers, respectively.

25. The fourth build-up wiring section further includes a fourth insulating body disposed above the glass layer, a plurality of fifth build-up wiring layers disposed on or within the fourth insulating body, and a plurality of fifth build-up wiring vias disposed within the fourth insulating body, Each of the first to third insulating bodies contains an organic insulating material. The fourth insulating body includes an inorganic insulating material. The minimum line width of the wiring included in the plurality of fifth build-up wiring layers is smaller than the minimum line width of the wiring included in at least one of the plurality of first build-up wiring layers and at least one of the plurality of third build-up wiring layers. The printed circuit board according to claim 24, wherein the minimum thickness of the wiring included in the plurality of fifth build-up wiring layers is thinner than the minimum thickness of the wiring included in at least one of the plurality of first build-up wiring layers and at least one of the plurality of third build-up wiring layers, respectively.

Images