Printed circuit board

Abstract

This invention provides a printed circuit board that eliminates the need for separate cavity processing and embedding processes by directly printing capacitors. [Solution] A printed circuit board 100 according to one embodiment of the present invention may include a plurality of insulating layers 111, a dielectric via 120 disposed inside at least one of the plurality of insulating layers, a first electrode layer and a second electrode layer disposed opposite each other with the dielectric via in between, a first through-via that penetrates at least one of the plurality of insulating layers and is connected to the first electrode layer, and a second through-via that penetrates at least one of the plurality of insulating layers and is connected to the second electrode layer.

Description

[Technical Field]

[0001] The present invention relates to a printed circuit board. [Background Art]

[0002] Recently, in order to improve the power characteristics of package substrates, a structure has been adopted in which passive elements such as chip capacitors and silicon capacitors are mounted on the outside of the substrate, or after a cavity is formed in the core of the substrate, passive elements such as chip capacitors and silicon capacitors are embedded. However, in this case, it is necessary to add a mounting or embedding process for the passive element, and a cavity must be formed according to the size of the passive element, so there is a disadvantage that a separate cavitation processing space must be secured. [Summary of the Invention] [Problem to be Solved by the Invention]

[0003] One of several objects of the present invention is to provide a printed circuit board that can omit separate cavity processing and embedding steps by directly printing a capacitor.

[0004] However, the object of the present invention is not limited to the above description, and can be more easily understood in the process of describing specific embodiments of the present invention. [Means for Solving the Problem]

[0005] A printed circuit board according to one embodiment of the present invention can include: a plurality of insulating layers; a dielectric via disposed inside at least one of the plurality of insulating layers; a first electrode layer and a second electrode layer disposed to face each other with the dielectric via interposed therebetween; a first through via penetrating at least one of the plurality of insulating layers and connected to the first electrode layer; and a second through via penetrating at least one of the plurality of insulating layers and connected to the second electrode layer.

[0006] A printed circuit board according to one embodiment of the present invention may include a plurality of insulating layers having dielectric vias, a first electrode layer and a second electrode layer arranged alternately with respect to the dielectric vias, a first via layer that penetrates at least a portion of one of the plurality of insulating layers and is connected to the first electrode layer, and a second via layer that penetrates at least a portion of one of the plurality of insulating layers and is connected to the second electrode layer. [Effects of the Invention]

[0007] One of the various effects of the present invention is that by directly printing capacitors, it is possible to provide a printed circuit board that eliminates the need for separate cavity processing and filling processes. [Brief explanation of the drawing]

[0008] [Figure 1] This is a block diagram illustrating a schematic example of an electronic equipment system. [Figure 2] This is a perspective view illustrating a typical example of an electronic device. [Figure 3] This is a schematic cross-sectional view showing a printed circuit board according to one embodiment of the present invention. [Figure 4] This is a schematic cross-sectional view showing a modified example of the printed circuit board shown in Figure 3. [Figure 5] This is a schematic cross-sectional view showing a modified example of the printed circuit board shown in Figure 3. [Figure 6] This is a schematic cross-sectional view showing a printed circuit board according to another embodiment of the present invention. [Figure 7a] Figure 3 is a schematic cross-sectional view showing an example of a manufacturing method for a printed circuit board. [Figure 7b] Figure 3 is a schematic cross-sectional view showing an example of a manufacturing method for a printed circuit board. [Figure 7c] Figure 3 is a schematic cross-sectional view showing an example of a manufacturing method for a printed circuit board. [Figure 7d] Figure 3 is a schematic cross-sectional view showing an example of a manufacturing method for a printed circuit board. [Figure 7e]Figure 3 is a schematic cross-sectional view showing an example of a manufacturing method for a printed circuit board. [Figure 7f] Figure 3 is a schematic cross-sectional view showing an example of a manufacturing method for a printed circuit board. [Figure 7g] Figure 3 is a schematic cross-sectional view showing an example of a manufacturing method for a printed circuit board. [Figure 7h] Figure 3 is a schematic cross-sectional view showing an example of a manufacturing method for a printed circuit board. [Figure 8a] Figure 6 is a schematic cross-sectional view showing an example of a method for manufacturing a printed circuit board. [Figure 8b] Figure 6 is a schematic cross-sectional view showing an example of a method for manufacturing a printed circuit board. [Figure 8c] Figure 6 is a schematic cross-sectional view showing an example of a method for manufacturing a printed circuit board. [Figure 8d] Figure 6 is a schematic cross-sectional view showing an example of a method for manufacturing a printed circuit board. [Figure 8e] Figure 6 is a schematic cross-sectional view showing an example of a method for manufacturing a printed circuit board. [Figure 8f] Figure 6 is a schematic cross-sectional view showing an example of a method for manufacturing a printed circuit board. [Modes for carrying out the invention]

[0009] Embodiments of the present invention will be described below with reference to specific embodiments and accompanying drawings. However, embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. Furthermore, embodiments of the present invention are provided to give a more complete explanation of the present invention to a person of the ordinary skill. Accordingly, the shapes and sizes of elements in the drawings may be exaggerated for clearer explanation, and elements indicated by the same reference numerals in the drawings are the same elements.

[0010] Furthermore, in order to clearly explain the present invention in the drawings, portions unrelated to the description are omitted, and the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of description. Therefore, the present invention is not necessarily limited to what is illustrated. Constituent elements having the same function within the scope of the same idea will be described using the same reference numerals. Furthermore, throughout the specification, when a certain portion is described as "comprising" a certain constituent element, this means that, unless specifically stated to the contrary, it does not exclude other constituent elements, but may further include other constituent elements.

[0011] Electronic device FIG. 1 is a block diagram schematically showing an example of an electronic device system.

[0012] Referring to FIG. 1, an electronic device 1000 accommodates a main board 1010. Chip-related components 1020, network-related components 1030, other components 1040, and the like are physically and / or electrically connected to the main board 1010. These are also coupled to other electronic components described later to form various signal lines 1090.

[0013] Examples of the chip-related components 1020 include, but are not limited to: memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPU), graphic processors (e.g., GPU), digital signal processors, encryption processors, microprocessors, and microcontrollers; logic chips such as analog-to-digital converters and application-specific ICs (ASICs). It goes without saying that chip-related electronic components of other different forms may also be included in addition to the above. It is a matter of course that these chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in a package form including the aforementioned chips and electronic components.

[0014] Network-related component 1030 includes, but is not limited to, any other wireless and wired protocols designated as Wi-Fi® (IEEE 802.11 family, etc.), WiMAX® (IEEE 802.16 family, etc.), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM®, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth®, 3G, 4G, 5G, and later. It also includes any other diverse wireless or wired standards and protocols. Furthermore, it goes without saying that network-related component 1030 may be combined with chip-related component 1020.

[0015] Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCCs (low-temperature co-firing ceramics), EMI (electromagnetic interference) filters, MLCCs (multi-layer ceramic condensers), etc. However, they are not limited to these, and may also include other passive elements in chip component form used for various other applications. It goes without saying that other components 1040 may be combined with chip-related components 1020 and / or network-related components 1030.

[0016] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that are or may not be physically and / or electrically connected to the main board 1010. Examples of other electronic components include a camera module 1050, an antenna module 1060, a display 1070, a battery 1080, etc. However, it is not limited to these, and may also include audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage devices (e.g., hard disk drives), CDs (compact disks), DVDs (digital versatile disks), etc. Needless to say, it may also include other electronic components used for various purposes depending on the type of electronic device 1000.

[0017] The electronic device 1000 may be a smartphone, personal digital assistant, digital video camera, digital still camera, network system, computer, monitor, tablet, laptop, netbook, television, video game, smartwatch, or automobile. However, it is not limited to these, and it goes without saying that it may be any other electronic device that processes data.

[0018] Figure 2 is a schematic perspective view showing an example of an electronic device.

[0019] Referring to Figure 2, the electronic device may be, for example, a smartphone 1100. Inside the smartphone 1100 is a motherboard 1110, to which various components 1120 are physically and / or electrically connected. In addition, other components, such as a camera module 1130 and / or a speaker 1140, may or may not be physically and / or electrically connected to the motherboard 1110. Some of the components 1120 may be the chip-related components described above, and may, for example, be a component package 1121, but are not limited thereto. The component package 1121 may be in the form of a printed circuit board on which electronic components, including active and / or passive components, are surface-mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board with built-in active and / or passive components. It goes without saying that the electronic device is not necessarily limited to a smartphone 1100, but may be other electronic devices as described above.

[0020] Printed circuit board Figure 3 is a schematic cross-sectional view showing a printed circuit board according to one embodiment of the present invention.

[0021] Referring to Figure 3, the printed circuit board 100 may include a plurality of insulating layers 111, dielectric vias 120, a first electrode layer 121 and a second electrode layer 122, and a first through-via 131 and a second through-via 132.

[0022] The dielectric via 120 can be placed inside at least one of the multiple insulating layers 111. That is, multiple insulating layers 111 can each have a dielectric via 120. For example, the dielectric via 120 may be placed inside each of the multiple insulating layers 111. For example, the dielectric via 120 can penetrate at least a portion of the insulating layer 111.

[0023] The first electrode layer 121 and the second electrode layer 122 can be arranged facing each other with a dielectric via 120 in between. For example, the first electrode layer 121 and the second electrode layer 122 may be arranged alternately with the dielectric via 120 in between. The printed circuit board 100 can include a capacitor section CP which includes the dielectric via 120 and the first electrode layer 121 and the second electrode layer 122.

[0024] The first through via 131 can penetrate at least one of the plurality of insulating layers 111 and be connected to the first electrode layer 121. The second through via 132 can penetrate at least one of the plurality of insulating layers 111 and be connected to the second electrode layer 122. The first through via 131 may, for example, penetrate each of the plurality of insulating layers 111 and be connected to the plurality of first electrode layers 121. The second through via 132 may, for example, penetrate each of the plurality of insulating layers 111 and be connected to the plurality of second electrode layers 122. The printed circuit board 100 may include a first via hole VH1 and a second via hole VH2 that penetrate the plurality of insulating layers 111, and the first through via 131 and the second through via 132 may be placed in the first via hole VH1 and the second via hole VH2, respectively. The through vias 131 and 132 can serve to electrically connect the capacitor section CP to the wiring layers 141, 142, 143, and 144, but the present invention is not limited thereto.

[0025] The capacitor section CP of the printed circuit board 100 can form capacitance and function as an electronic element that generates voltage and outputs current by utilizing its characteristic of repeated charging and discharging. This can stabilize an unstable power supply and eliminate noise. It can also block DC and allow AC to pass through. Furthermore, it can be used for the stable operation of semiconductor chips.

[0026] A printed circuit board 100 according to one embodiment of the present invention includes dielectric vias 120 and electrode layers 121 and 122 formed directly on or inside an insulating layer 111, thereby easily forming a capacitor portion CP of a desired size and capacitance inside the printed circuit board 100. This eliminates the need for cavity processing and embedding processes for capacitor embedding, and by eliminating the cavity, a superior effect can be obtained in terms of the distribution of insulating thickness.

[0027] The following describes in more detail each component included in the printed circuit board 100.

[0028] The insulating layer 111 may contain an insulating material. This insulating material may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or an inorganic filler, an organic filler, and / or glass fiber (glass cloth, and / or glass fabric) together with such a resin. The insulating material may also contain a photosensitive material and / or a non-photosensitive material. For example, the insulating material of the insulating layer 111 may be PPG (Prepreg), RCC (Resin Coated Copper), etc., but is not limited to these; ABF (Ajinomoto Build-up Film), PID (Photo Imageable Dielectric), FR-4, BT (Bismaleimide Triazine), etc., can also be used. In addition, other polymer materials with excellent rigidity can also be used as the insulating material of the insulating layer 111.

[0029] The dielectric via 120 may contain dielectric materials different from the insulating materials contained in the plurality of insulating layers 111. The dielectric via 120 can be formed by filling the interior of the insulating layer 111 with a separate dielectric material. The dielectric constant of the dielectric material contained in the dielectric via 120 may be higher than the dielectric constant of the insulating material contained in the insulating layer 111.

[0030] The dielectric via 120 may, for example, include a mixture of dielectric particles and a resin. The dielectric via 120 may have a form in which the dielectric particles are dispersed in the resin, but the present invention is not limited thereto. The dielectric particles may include one or more of alumina, silica, silicon nitride, tantalum oxide, titanium oxide, calcium titanate, barium titanate, and stronmium titanate particles from the viewpoint of insulating properties and dielectric constant. The resin contained in the dielectric via 120 may contain the same substance as the insulating material contained in the insulating layer 111, or it may contain a substance different from the insulating material contained in the insulating layer 111. The resin contained in the dielectric via 120 may include an organic polymer insulating material, but the present invention is not limited thereto.

[0031] The first electrode layer 121 and the second electrode layer 122 may each contain a metallic substance. The metallic substance contained in the first electrode layer 121 and the second electrode layer 122 may include, for example, one or more of Cu, Al, Ag, Sn, Au, Ni, Pb, Ti, and alloys thereof. The first electrode layer 121 and the second electrode layer 122 may each include an electroless plating layer (or chemical copper) as a seed layer and an electroplating layer (or electrolytic copper) as a plating layer, but the present invention is not limited thereto. A sputtering layer may be formed instead of an electroless plating layer as a seed layer. Copper foil may be further included as needed.

[0032] The first electrode layer 121 may include a first overlapping region that overlaps with the second electrode layer 122 and the plurality of insulating layers 111 in the stacking direction, and a first extension region that extends from the first overlapping region in a horizontal direction perpendicular to the stacking direction. The second electrode layer 122 may include a second overlapping region that overlaps with the first electrode layer 121 in the stacking direction, and a second extension region that extends from the second overlapping region in the horizontal direction.

[0033] The first through via 131 and the second through via 132 may each contain a metallic material. The metallic material contained in the first through via 131 and the second through via 132 may include, for example, one or more of Cu, Al, Ag, Sn, Au, Ni, Pb, Ti, and alloys thereof. The first through via 131 and the second through via 132 may each contain an electroless plating layer (or chemical copper) as a seed layer and an electroplating layer (or electrolytic copper) as a plating layer, but the present invention is not limited thereto. A sputtering layer may be included as a seed layer instead of an electroless plating layer, and both may be included as needed.

[0034] On the other hand, the first electrode layer 121 and the second electrode layer 122 and the first through via 131 and the second through via 132 may each contain the same metallic substance. For example, the first electrode layer 121 and the second electrode layer 122 and the first through via 131 and the second through via 132 may each contain Cu, but the present invention is not limited thereto.

[0035] The first through via 131 and the second through via 132 can each contain a metallic material that fills the first via hole VH1 and the second via hole VH2, respectively. That is, the first through via 131 and the second through via 132 can each contain a filled via that fills the first via hole VH1 and the second via hole VH2, respectively.

[0036] The first through via 131 can penetrate the first extension region of the first electrode layer 121, and the second through via 132 can penetrate the second extension region of the second electrode layer 122.

[0037] Referring to Figure 3, at least one of the first through via 131 and the second through via 132 can have a columnar shape with substantially constant width. As will be described later, the first through via 131 and the second through via 132 can be formed by filling the first via hole VH1 and the second via hole VH2 formed in a single hole-making operation in a plurality of laminated insulating layers 111, so that at least one of the first through via 131 and the second through via 132 can have a columnar shape and its width can be effectively constant.

[0038] Furthermore, the dielectric via 120 can have a columnar shape with substantially constant width. Since the dielectric via 120 can be formed by filling a hole formed in a single hole-making operation in the insulating layer 111, the dielectric via 120 can have a columnar shape and substantially constant width.

[0039] In the present invention, the concept of a substantially constant width is a general one that includes most factors, such as process errors, positional deviations, and measurement errors that occur during the manufacturing process. Here, width can mean the size of the multiple insulating layers 111 in the horizontal direction perpendicular to the stacking direction.

[0040] The printed circuit board 100 may further include a first resist layer 112 disposed on the uppermost insulating layer 111 of the plurality of insulating layers 111, and a second resist layer 113 disposed on the lowermost insulating layer 111 of the plurality of insulating layers 111. The first resist layer 112 and the second resist layer 113 may include liquid or film-type solder resist, but the present invention is not limited thereto, and other types of insulating materials may be used.

[0041] The printed circuit board 100 may include first wiring layers 141, 143 arranged on a first resist layer 112 or a second resist layer 113 and connected to a first through-via 131, and second wiring layers 142, 144 arranged on the first resist layer 112 or the second resist layer 113 and connected to a second through-via 132. The first wiring layers 141, 143 may be in direct contact with the first through-via 131, and the second wiring layers 142, 144 may be in direct contact with the second through-via 132. The first wiring layers 141, 143 may be arranged on the first resist layer 112 and the second resist layer 113, respectively, and the second wiring layers 142, 144 may be arranged on the first resist layer 112 and the second resist layer 113, respectively.

[0042] The first wiring layers 141, 143 and the second wiring layers 142, 144 may each contain a metallic substance. The metallic substance contained in the first wiring layers 141, 143 and the second wiring layers 142, 144 may include, for example, one or more of Cu, Al, Ag, Sn, Au, Ni, Pb, Ti, and alloys thereof. The first wiring layers 141, 143 and the second wiring layers 142, 144 may each contain an electroless plating layer (or chemical copper) as a seed layer and an electroplating layer (or electrolytic copper) as a plating layer, but the present invention is not limited thereto. A sputtering layer may be formed as a seed layer instead of an electroless plating layer. Copper foil may be further included as needed.

[0043] The first wiring layers 141, 143 and the second wiring layers 142, 144 can each perform various functions depending on the design. The first wiring layers 141, 143 and the second wiring layers 142, 144 can each include, for example, signal patterns, power patterns, ground patterns, etc., and these patterns can each have various forms such as lines (or traces), planes (or plates), pads (or lands), etc.

[0044] Figures 4 and 5 are schematic cross-sectional views showing modified examples of the printed circuit board of Figure 3. Hereinafter, printed circuit boards 100a and 100b according to another embodiment of the present invention will be described with reference to Figures 4 and 5. For components identical or similar to those of the printed circuit board 100 described in Figure 3, the same or similar reference numerals will be used, and redundant explanations will be omitted.

[0045] Referring to Figure 4, the printed circuit board 100a can include a first through via and a second through via 131a, 132a. The first through via 131a can include a first insulating core IC1 placed in a first via hole VH1 and a first conductive layer CL1 placed on the side surface of the first insulating core IC1, and the second through via 132a can include a second insulating core IC2 placed in a second via hole VH2 and a second conductive layer CL2 placed on the side surface of the second insulating core IC2. That is, the first through via and the second through vias 131a, 132a can each include conformal vias placed along the walls of the first via hole VH1 and the second via hole VH2, respectively. The first conductive layer CL1 and the second conductive layer CL2 can contain metallic materials, such as Cu, Al, Ag, Sn, Au, Ni, Pb, Ti and their alloys. The first insulating core IC1 and the second insulating core IC2 may contain an insulating material, for example, the same insulating material as the insulating layer 111, but the present invention is not limited thereto.

[0046] Referring to Figure 5, the printed circuit board 100b may include a first through-via 131b and a second through-via 132b. The first through-via 131b may be positioned at a distance from the upper surface S1 of the first resist layer 112 and the lower surface S2 of the second resist layer 113, and the second through-via 132b may also be positioned at a distance from the upper surface S1 of the first resist layer 112 and the lower surface S2 of the second resist layer 113. In this case, the mounted components and the capacitor portion are not directly connected via the through-vias 131b and 132b, but the capacitor portion can be connected to the mounted components via separate vias and / or wiring.

[0047] Figure 6 is a schematic cross-sectional view of a printed circuit board 100c according to another embodiment of the present invention. The printed circuit board 100c according to another embodiment of the present invention will be described with reference to Figure 6, and for components that are the same or similar as those of the printed circuit board 100 described in Figure 3, the same or similar reference numerals will be used, and redundant explanations will be omitted.

[0048] The printed circuit board 100c may include a plurality of insulating layers 111, dielectric vias 120c, a first electrode layer 121c and a second electrode layer 122c, and a first through-via 131c and a second through-via 132c.

[0049] Referring to Figure 6, the width of the upper surface of the dielectric via 120c may be greater than the width of the lower surface of the dielectric via 120c. The width of the dielectric via 120c may gradually decrease from the upper surface to the lower surface of the dielectric via 120c, for example. The dielectric via 120c may have a tapered shape, for example, such that the width of the upper end is greater than the width of the lower end in cross-section. As will be described later, when the insulating layer 111 is processed by laser drilling to fill the dielectric via 120c, the holes formed in the insulating layer 111 and the dielectric via 120c that fill the holes can have a tapered shape.

[0050] The first through via 131c may include a plurality of first via layers 131c1 that penetrate at least a portion of each of the plurality of insulating layers 111. The first via layer 131c1 may, for example, penetrate at least a portion of one of the plurality of insulating layers 111 and be connected to the first electrode layer 121c. The second through via 132c may include a plurality of second via layers 132c1 that penetrate at least a portion of each of the plurality of insulating layers 111. The second via layer 132c1 may, for example, penetrate at least a portion of one of the plurality of insulating layers 111 and be connected to the second electrode layer 122c.

[0051] Each of the multiple first via layers 131c1 and second via layers 132c1 may contain microvias. The microvias may be filled vias that fill via holes, or conformal vias that are arranged along the walls of via holes. The microvias can be arranged in a stacked type and / or staggered type. Each of the first via layers 131c1 and second via layers 132c1 may contain a metallic material. Examples of metallic materials that can be used include Cu, Al, Ag, Sn, Au, Ni, Pb, Ti, and alloys thereof.

[0052] The width of at least one upper surface of the plurality of first via layers 131c1 may be greater than the width of at least one lower surface of the plurality of first via layers 131c1. The width of the first via layer 131c1 may gradually decrease from the upper surface of the first via layer 131c1 toward the lower surface of the first via layer 131c1. The first via layer 131c1 may have a tapered shape, for example, such that the width of the upper end is greater than the width of the lower end in cross-section. The width of at least one upper surface of the plurality of second via layers 132c1 may be greater than the width of at least one lower surface of the plurality of second via layers 132c1. The width of the second via layer 132c1 may gradually decrease from the upper surface of the second via layer 132c1 toward the lower surface of the second via layer 132c1. The second via layer 132c1 may have a tapered shape, for example, such that the width of the upper end is greater than the width of the lower end in cross-section.

[0053] The first through via 131c may have a configuration in which the first via layer 131c1 and the first metal layer 131c2 are alternately arranged in the stacking direction. The second through via 132c may have a configuration in which the second via layer 132c1 and the second metal layer 132c2 are alternately arranged in the stacking direction.

[0054] The first metal layer 131c2 can be positioned at substantially the same level as the second electrode layer 122c. The first metal layer 131c2 may contain the same metallic material as the second electrode layer 122c. The second metal layer 132c2 can be positioned at substantially the same level as the first electrode layer 121c. The second metal layer 132c2 may contain the same metallic material as the first electrode layer 121c. In the present invention, being positioned at substantially the same level includes not only being positioned at exactly the same location with respect to the lamination and / or thickness direction, but also being positioned at approximately the same location.

[0055] The printed circuit board 100c may further include third via layers 151, 153 connecting a first through-via 131c to the first wiring layers 141, 143, and fourth via layers 152, 154 connecting a second through-via 132c to the second wiring layers 142, 144. The third via layers 151, 153 may be arranged on the first resist layer 112 and the second resist layer 113, respectively, and the fourth via layers 152, 154 may be arranged on the first resist layer 112 and the second resist layer 113, respectively. The third via layer 153 and the fourth via layer 154 arranged on the second resist layer 113 may each have tapered shapes in opposite directions in cross-section to the first via layer 131c1 and the second via layer 132c1, respectively, but the present invention is not limited thereto.

[0056] On the other hand, although not shown in the diagram, the capacitor section of the printed circuit board 100c can also be connected to mounted components via separate vias and / or wiring in addition to the third via layers 151 and 153, the fourth via layers 152 and 154, and the wiring layers 141, 142, 143, and 144.

[0057] Manufacturing method for printed circuit boards Figures 7a to 7h are schematic cross-sectional views illustrating an example of a manufacturing method for the printed circuit board 100 shown in Figure 3.

[0058] Referring to Figure 7a, after preparing the insulating layer 111, a first metal thin film layer 221 and a second metal thin film layer 222 can be formed on the upper and lower surfaces of the insulating layer 111, respectively. The metal thin film layers 221 and 222 can be formed, for example, by electroless plating, for example, by chemical copper plating. If necessary, the metal thin film layers 221 and 222 may also be formed by sputtering.

[0059] Referring to Figure 7b, holes h1 can be formed in the insulating layer 111, which has thin metal film layers 221 and 222 formed on its upper and lower surfaces. Holes h1 can be formed, for example, by mechanical processing.

[0060] Referring to Figure 7c, a dielectric via 120 can be formed by filling the hole h1 with a dielectric material. The dielectric material may be, for example, a mixture of dielectric particles and resin. Referring to Figure 7d, a metallic material can be filled into the empty space formed on the upper surface of the dielectric via 120 using electroless plating (chemical copper), electroplating (electrolytic copper), and / or sputtering. This allows the second metal thin film layer 222 to cover the upper surface of the insulating layer 111.

[0061] Referring to Figure 7e, a circuit can be formed by performing an etching process on the first metal thin film layer 221 and the second metal thin film layer 222 to remove a portion of the first metal thin film layer 221 and the second metal thin film layer 222. This allows the first electrode layer 121 and the second electrode layer 122 to be formed. Next, a separate insulating layer 111 can be laminated, and the first metal thin film layer 221 can be formed on the insulating layer 111.

[0062] Referring to Figure 7f, after repeating the steps shown in Figures 7a to 7e, a first resist layer 112 and a second resist layer 113 can be formed on the uppermost insulating layer 111 and the lowermost insulating layer 111, respectively.

[0063] Referring to Figure 7g, a first via hole VH1 and a second via hole VH2 are formed so as to penetrate multiple insulating layers 111, a first resist layer 112, and a second resist layer 113. The first via hole VH1 and the second via hole VH2 can be formed by methods such as mechanical processing.

[0064] Referring to Figure 7h, the first through via 131 and the second through via 132 are formed by filling the interiors of the first via hole VH1 and the second via hole VH2 with a metallic material. The first through via 131 and the second through via 132 can be formed using electroless plating (chemical copper), electrolytic plating (electrolytic copper), and / or sputtering.

[0065] Finally, by forming wiring layers 141, 142, 143, and 144 on the first resist layer 112 and the second resist layer 113 using electroless plating (chemical copper), electrolytic plating (electrocopper), and / or sputtering, the printed circuit board 100 shown in Figure 3 can be manufactured.

[0066] On the other hand, by not completely filling the interiors of the first via hole VH1 and the second via hole VH2 with a metallic substance, and instead forming conductive layers CL1 and CL2 along the walls of the first via hole VH1 and the second via hole VH2 using electroless plating (chemical copper), and filling the remaining area with an insulating substance, a printed circuit board 100a including the through vias 131a and 132a shown in Figure 4 can be manufactured.

[0067] Furthermore, in Figure 7f, before forming the first resist layer 112 and the second resist layer 113, the first via hole VH1 and the second via hole VH2 are formed, and the first through via 131b and the second through via 132b are formed inside the first via hole VH1 and the second via hole VH2, respectively, thereby enabling the production of the printed circuit board 100b shown in Figure 5.

[0068] Figures 8a to 8f are schematic cross-sectional views illustrating an example of a manufacturing method for the printed circuit board 100c shown in Figure 6.

[0069] First, prepare an insulating layer 111 on which the first metal thin film layer 221 and the second metal thin film layer 222 shown in Figure 7a are formed.

[0070] Referring to Figure 8a, holes h1-1, h2, and h3 can be formed in the insulating layer 111. Holes h1-1, h2, and h3 can be formed by methods such as laser drilling. As a result, holes h1-1, h2, and h3 can have a tapered shape such that the upper end is wider than the lower end in cross-section.

[0071] Referring to Figure 8b, a dielectric material can be filled into the hole h1-1 to form a dielectric via 120c. Referring to Figure 8c, the interiors of the holes h2 and h3 can be filled with a metallic material using electroless plating (chemical copper), electrolytic plating (electrolytic copper), and / or sputtering to form the first via layer 131c1 and the second via layer 132c1. Furthermore, the empty spaces formed on the upper surfaces of the first via layer 131c1, the second via layer 132c1, and the dielectric via 120 can also be filled with a metallic material so that the second metal thin film layer 222 covers the upper surface of the insulating layer 111.

[0072] Referring to Figure 8d, a circuit can be formed by performing an etching process on the first metal thin film layer 221 and the second metal thin film layer 222 to remove a portion of the first metal thin film layer 221 and the second metal thin film layer 222. This allows the first electrode layer 121c, the second electrode layer 122c, and the first metal layer 131c2 to be formed.

[0073] Referring to Figure 8e, a separate insulating layer 111 can be laminated, and the first metal thin film layer 221 can be formed on the insulating layer 111. Referring to Figure 8f, a circuit can be formed by performing an etching process on the first metal thin film layer 221 to remove a portion of it. This allows the first electrode layer 121c and the second metal layer 132c2 to be formed.

[0074] After repeating the steps shown in Figures 8a to 8f, a first resist layer 112 and a second resist layer 113 can be formed on the uppermost and lowermost insulating layers 111, respectively. Finally, after drilling holes in the resist layers 112 and 113, the printed circuit board 100c shown in Figure 6 can be manufactured by forming the third via layers 151 and 153, the fourth via layers 152 and 154, and the wiring layers 141, 142, 143, and 144.

[0075] The present invention is not limited by the embodiments described above or the accompanying drawings, but is limited by the claims provided herein. Accordingly, various forms of substitution, modification, and alteration are possible by persons with ordinary skill in the art, without departing from the technical idea of ​​the present invention as described in the claims, and these also fall within the scope of the present invention.

[0076] Furthermore, the expression "one embodiment" does not mean that each embodiment is the same as another, but is provided to emphasize and describe the unique and distinct characteristics of each embodiment. However, the above-presented embodiments do not preclude their realization in combination with the features of other embodiments. For example, even if a matter described in one embodiment is not described in another embodiment, it can be understood as a description related to the other embodiment, unless there is a description in the other embodiment that contradicts or is contrary to that matter.

[0077] In this invention, "connected" is a concept that includes not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, "electrically connected" is a concept that includes both cases where they are physically connected and cases where they are not connected. In addition, expressions such as "first," "second," etc., are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, within the scope of the rights, the first component may be named the second component, and similarly, the second component may be named the first component. [Explanation of Symbols]

[0078] 1000:Electronic equipment 1010: Mainboard 1020: Chip-related components 1030: Network-related components 1040: Other parts 1050: Camera 1060: Antenna 1070: Display 1080: Battery 1090: Battery 1100: Smartphone 1110: Motherboard 1020: Parts 1121: Parts Package 1130: Camera module 1140: Speaker 100, 100a, 100b, 100c: Printed circuit board 111: Insulating layer 120: Dielectric via 112, 113: Resist layer 121, 122, 121c, 122c: Electrode layer 131, 132, 131a, 132a, 131b, 132b, 131c, 132c: Through vias IC1, IC2: Insulating core CL1, CL2: Conductive layer 131c1, 132c1: Via layer 131c2, 132c2: Metal layer 141, 142, 143, 144: Wiring layer 151, 152, 153, 154: Beer layer 221, 222: Metal thin film layer

Claims

1. Multiple insulating layers, A dielectric via disposed inside at least one of the plurality of insulating layers, A first electrode layer and a second electrode layer are arranged facing each other with the dielectric via in between, A first through via penetrates at least one of the plurality of insulating layers and is connected to the first electrode layer, A printed circuit board comprising a second through-via that penetrates at least one of the plurality of insulating layers and is connected to the second electrode layer.

2. The printed circuit board according to claim 1, wherein the dielectric via contains a dielectric material that is different from the insulating material contained in the plurality of insulating layers.

3. The printed circuit board according to claim 1, wherein the dielectric via comprises a mixture of dielectric particles and resin.

4. The printed circuit board according to claim 1, wherein the dielectric vias are arranged inside each of the plurality of insulating layers.

5. The printed circuit board according to claim 1, wherein at least one of the first through via and the second through via has a columnar shape with substantially constant width.

6. The printed circuit board according to claim 1, wherein the dielectric via has a columnar shape with substantially constant width.

7. A first via hole and a second via hole are arranged that penetrate the aforementioned plurality of insulating layers. The printed circuit board according to claim 1, wherein the first through-via and the second through-via each contain a metallic material that fills the first via hole and the second via hole, respectively.

8. A first via hole and a second via hole are arranged that penetrate the plurality of insulating layers. The first through via includes a first insulating core disposed in the first via hole, and a first conductive layer disposed on the side surface of the first insulating core. The printed circuit board according to claim 1, wherein the second through via includes a second insulating core disposed in the second via hole and a second conductive layer disposed on the side surface of the second insulating core.

9. A first resist layer is disposed on the uppermost insulating layer among the plurality of insulating layers, A second resist layer is disposed on the lowest insulating layer among the plurality of insulating layers, A first wiring layer disposed on the first resist layer or the second resist layer and connected to the first through via, A printed circuit board according to any one of claims 1 to 8, further comprising: a second wiring layer disposed on the first resist layer or the second resist layer and connected to the second through-via.

10. A first resist layer is disposed on the uppermost insulating layer among the plurality of insulating layers, The present invention further includes a second resist layer disposed on the lowest insulating layer among the plurality of insulating layers, The printed circuit board according to any one of claims 1 to 8, wherein the first through-via and the second through-via are arranged at a distance from the upper surface of the first resist layer and the lower surface of the second resist layer, respectively.

11. The printed circuit board according to any one of claims 1 to 8, wherein the width of the upper surface of the dielectric via is greater than the width of the lower surface of the dielectric via.

12. The first through via includes a plurality of first via layers that penetrate at least a portion of each of the plurality of insulating layers, The aforementioned second through via includes a plurality of second via layers that penetrate at least a portion of each of the plurality of insulating layers, The width of the upper surface of at least one of the plurality of first via layers is greater than the width of the lower surface of at least one of the plurality of first via layers. The printed circuit board according to any one of claims 1 to 8, wherein the width of the upper surface of at least one of the plurality of second via layers is greater than the width of the lower surface of at least one of the plurality of second via layers.

13. Multiple insulating layers having dielectric vias, The dielectric vias are arranged alternately on either side of the first electrode layer and the second electrode layer, A first via layer that penetrates at least a portion of one of the plurality of insulating layers and is connected to the first electrode layer, A printed circuit board comprising: a second via layer that penetrates at least a portion of one of the plurality of insulating layers and is connected to the second electrode layer.

14. The printed circuit board according to claim 13, wherein the dielectric via comprises a mixture of dielectric particles and resin.

15. The printed circuit board according to claim 13, wherein the dielectric via has a tapered shape such that the width of the upper end is greater than the width of the lower end in cross-section.

16. The printed circuit board according to any one of claims 13 to 15, wherein the first via layer and the second via layer each have a tapered shape such that the width of the upper end is greater than the width of the lower end in cross-section.

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