Method and system for characterization of zero-noise extrapolation

Abstract

This provides a computer implementation method for error mitigation in quantum circuits running on a quantum processor. [Solution] A method in a quantum circuit in which each parameterized quantum gate G(θ) is associated with an error generator having an affine dependence on the absolute value of the gate parameter, including an idle error component and a linear error component, comprises selecting a target amplification coefficient for the linear error component and computing a gate transform that replaces the quantum gate with a product of subgates whose parameters satisfy a parameter conservation criterion. The gate transform is such that the linear error component is amplified by the target amplification coefficient and the idle error component is amplified by one or more idle amplification coefficients. The quantum circuit and one or more transformed quantum circuits are run multiple times, and the noisy and noise-amplified expectations of the observable quantities are collected, and the relaxed expectations are computed by extrapolation to zero noise.

Description

Technical Field

[0001] The present disclosure relates to the field of quantum computing, and in particular, to the field of error mitigation techniques for parameterized quantum gates and circuits. Background Art

[0002] Quantum computers are expected to dramatically expand the range of computational problems that can be efficiently solved, and have widespread applications across a broad range of industrial and academic fields. However, the development of quantum computers that can realize this potential is extremely dependent on reducing errors, which are the differences between actual and ideal implementations of quantum logic operations.

[0003] Practical quantum processors remain limited by the presence of noise in the physical operations used to implement quantum gates. Such noise accumulates with circuit depth and can significantly distort the expected value of an observable quantity measured at the end of a computation. While quantum error correction promises a long-term solution, today's quantum devices do not support the fault-tolerant overhead required for full error correction. As a result, error mitigation techniques that operate at the circuit execution and post-processing level have emerged as an important approach for improving computational accuracy on near-term quantum processors.

[0004] Zero-noise extrapolation is one such approach. This is based on running the same quantum circuit at different effective noise levels and using the results to estimate the value of an observable at zero noise. Existing methods for zero-noise extrapolation often impose constraints on noise amplification or require prior characterization of the underlying noise model. These constraints can limit efficiency, increase overhead, or reduce robustness in the presence of varying or context-dependent noise. Therefore, there is a need for improved methods that amplify noise in a controlled and predictable manner without relying on characterization and operate effectively on a broad class of noise models. Summary of the Invention

[0005] According to a first aspect of the presently disclosed subject matter, there is provided a computer-implemented method of error mitigation for a quantum circuit executed on a quantum processor. The quantum circuit comprises g noise (θ)=g (0) +g (1) |θ|, one or more quantum gates G(θ) having a gate parameter θ, and an error generator g noise (θ) having an affine dependence on the absolute value of the gate parameter, wherein g (0) defines an idle error component, and g (1) defines a linear error component. The method comprises: (i) selecting a target amplification factor s for the linear error component; (ii) when the target amplification factor satisfies s≧2, calculating one or more gate transformations, each gate transformation being configured to convert the quantum gate into a product of subgates, wherein a) each subgate is an instance of the quantum gate G operated at a parameter value θ j , and the parameter values over the product satisfy a parameter conservation criterion Σ j θ j(iii) Calculate the transformed error generator of the subgate product which satisfies =θ and includes (b) a transformed error generator which includes a transformed idle error component and a transformed linear error component, and when at least two gate transformations are computed, the transformed idle error component is an amplification of the idle error component by different idle amplification coefficients for each of the at least two gate transformations and the transformed linear error component is an amplification of the linear error component by the same target amplification coefficient for the at least two gate transformations; (iii) Execute the quantum circuit and the transformed quantum circuit which, for each occurrence of a quantum gate G(θ) across a set of circuit executions, one of the gate transformations is selected according to a probability distribution configured such that the expected value of the idle amplification coefficient is equal to the target amplification coefficient s across the probability distribution; (iv) Collect the noisy expected value of the observables from the execution of the quantum circuit and the noise-amplified expected value from the execution of the transformed quantum circuit; (v) Calculate the relaxed expected value of the observables by extrapolating to zero noise using the noisy expected value and the noise-amplified expected value.

[0006] In addition to the features described above, a computer implementation of error mitigation according to this aspect of the subject matter of the present disclosure may optionally include one or more of the following features (i) to (xv) in any technically possible combination or permutation: i. The target amplification coefficient s for the error generator is selected based on the decay of the expectation value of the observable quantity in the quantum circuit. ii. The target amplification coefficient s is set based on the decay exponent Λ of the expected value of the observable quantity in the quantum circuit, and the shot time ratio f between the transformed quantum circuit and the quantum circuit.

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[0007] According to a second aspect of the subject matter of this disclosure, a system for error mitigation of quantum circuits is provided, the system being a quantum processor configured to execute a quantum circuit comprising one or more quantum gates G(θ) having gate parameters θ, wherein each quantum gate is g noise (θ) = g (0) +g (1) |θ| and g (0) This defines the idle error component, g (1) Error generator g has an affine dependence on the absolute value of the gate parameter, such that it defines a linear error component. noise A typical controller comprising a quantum processor, a processor, and memory for storing instructions, associated with (θ), wherein when an instruction is executed by the processor, the typical controller... a. Select the target amplification coefficient s for the linear error component. b. Calculating one or more gate transformations when the target amplification coefficient satisfies s≧2, wherein each gate transformation is performed using a quantum gate G(θ) based on a parameter conservation criterion.

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[0008] In addition to the features described above, a system according to a second aspect of the subject matter of this disclosure may optionally include one or more of the features (i) to (xv) listed above in relation to the computer implementation method of the first aspect in any technically possible combination or permutation, and a typical controller is configured to implement the features of the corresponding method and accordingly cause a quantum processor to execute the resulting quantum circuit.

[0009] In this disclosure, the following terms and their derivatives should be understood in accordance with the following commentary.

[0010] A quantum circuit U is the product of the following quantum gates G i It may also be expressed as follows.

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[0011] Without losing generality, quantum gate G i The term "gate" is sometimes used to refer to a Pauli rank 1 gate, and as a result, Gate G i This can be written as follows:

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[0012] t is an index that distinguishes different gate types within the gate set, and θ is a gate parameter (e.g., rotation angle).

[0013] Quantum gates are noisy (i.e., not error-free) and can be represented by a superoperator G as follows:

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[0014] Here, g ideal This represents an ideal generator, i.e., a generator that operates without the desired noise, g noise This indicates the noise generator for the noise channel.

[0015] The term "Zero Noise Extrapolation" (ZNE) refers to amplified by a predetermined coefficient. noise While including a step, g does not amplify. ideal It can refer to techniques (for example, preservation or maintenance). In a further step, the observable quantity of interest is extrapolated to a zero-noise point using some (at least two) noise expectations. There are several ways to amplify the noise. The most basic method is unitary folding (UF), but currently the most efficient method is to characterize the noise model and amplify it stochastically (stochastic error amplification - PEA).

[0016] This invention relates to a noise generator g noise We propose an efficient method for amplifying noise. In order to amplify noise, as long as there are parameters to scale up the noise in a known way, in practice g noise There is no need to know this. The parameter at hand can be the gate rotation angle θ. Function form g noise Given that (θ) is known, noise can be amplified by applying the following transformation:

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[0017] In other words, a quantum circuit can be transformed into a transformed quantum circuit in which each generation of gate G(θ) can be replaced by a product of subgates, each with parameter value θ (j) It is implemented as follows, where θ (j) The set follows the parameter conservation criteria.

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[0018] Therefore, the ideal operation performed by the gate remains unchanged, and the noise generator is amplified by the target amplification coefficient s, as follows:

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[0019] Special θ corresponding to the standard unitary convolution method (j) =(-1) j+1 In the case of θ, s = 3 or greater, and therefore this option is abandoned.

[0020] In principle, this disclosure shares some similarities with the pulse stretching method described in Kim et al., 2023b, "Scalable error mitigation for noisy quantum circuits produces competitive expectation values," Nature Physics, 19(5):752-759. However, the latter requires pulse-level access and works only in very limited cases. Specifically, it is independent of the pulse amplitude, which decreases as the pulse is stretched, only when the gate error is dominated by idle-time error (i.e., depends only on the pulse duration). The method of the present invention is more robust and does not require pulse-level access.

[0021] In this disclosure, the noise generator may be subject to an affine or quadratic dependence on the gate parameters, i.e.,

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[0022] Among other possible examples, the Molmer-Sorensen (MS) gate, widely used in trap ion systems, is well known for having noise that scales nearly linearly with respect to the gate angle. Single qubit gates are well approximated by the quadratic error model in almost all actual QPU implementations.

[0023] This disclosure can be applied whenever the error generator of a parameterized gate exhibits a known functional dependency on the gate parameters. The particular functional form may be linear, affine, quadratic, or any other well-behaving dependency. This method requires that each gate type be associated with a known functional form for its error generator. Superoperator coefficient g (k) This may differ for each gate instance. If different gate types follow different functional forms, this method may nevertheless be applicable if parameter-preserving transformations are selected separately for each gate type, thereby achieving the desired amplification coefficient for each gate.

[0024] This disclosure may also be applied to gates having a Pauli rank greater than 1, such as iSWAP gates. Higher rank gates can be decomposed into a sequence of Pauli rank 1 turns. If parameterization of higher rank gates enables such decomposition, noise amplification achieved by transforming the full gate is equivalent to noise amplification obtained by decomposing the gate into rank 1 components, amplifying each component individually using the disclosed transforms, and constructing the result. [Brief explanation of the drawing]

[0025] Embodiments are described herein, as non-limiting examples, with reference to the accompanying drawings, in order to better understand the subject matter disclosed herein and to illustrate how it can actually be carried out. [Figure 1] A flowchart illustrating a method for mitigating errors according to embodiments of this disclosure is shown. [Figure 2] This document presents comparative data between the method according to the embodiments of this disclosure and the prior art method. [Figure 3] A computer implementing the method according to the embodiments of this disclosure is schematically illustrated. [Figure 4] A system that implements the method according to the embodiments of this disclosure is provided as a schematic example. [Modes for carrying out the invention]

[0026] This specification describes several examples of systems and methods useful for error mitigation in quantum circuits running on quantum processors.

[0027] The following detailed description includes numerous specific details to ensure a complete understanding of the subject matter. However, it will be understood by those skilled in the art that some examples of the subject matter can be carried out without these specific details. In other examples, well-known methods, procedures, components, and circuits are not described in detail so as not to obscure the subject matter of this disclosure.

[0028] As used herein, phrases such as “for example,” “etc.,” and “as an example,” and variations thereof, describe non-limiting embodiments of the subject matter of this disclosure.

[0029] In this specification, references to “one example,” “several examples,” “another example,” “other examples,” “one instance,” “several examples,” “another example,” “another example,” “one case,” “several cases,” “another case,” “other cases,” or variations thereof, mean that a particular feature, structure, or characteristic described is included in at least one example of the subject matter, but the appearance of the same term does not necessarily refer to the same example.

[0030] For clarity, certain features, structures, and / or properties disclosed herein, described in the context of separate examples, may be provided in combination in a single example. Conversely, various features, structures, and / or properties disclosed herein, described in the context of a single example for brevity, may be provided separately or in any preferred partial combination.

[0031] Unless otherwise specified, as will be apparent from the following descriptions, any use of terms such as “calculate,” “determine,” “select,” “execute,” “collect,” and “implement” throughout this specification may refer to actions and / or processes of any combination of software, hardware, and / or firmware. For example, these terms may, in some cases, refer to actions and / or processes of a programmable machine that manipulate and / or convert data, which is represented as a physical quantity such as an electronic quantity in the registers and / or memory of the programmable machine, into other data, which is similarly represented as a physical quantity in the memory, registers, and / or other such information storage, transmission, and / or display elements of the programmable machine.

[0032] Figure 1 is a box diagram illustrating a typical computer implementation method for error mitigation for quantum circuits according to embodiments of the present disclosure.

[0033] In step S100, a quantum circuit may be provided that is executed on a quantum processor. The quantum circuit comprises one or more parameterized quantum gates G(θ). It is assumed that the functional dependence of the error generator for each gate is known, for example, by showing the affine dependence on the absolute value of the gate parameter.

[0034] In a further step S200, a target amplification coefficient s for the linear error component may be selected. The value of s determines the extent to which the linear portion of the error generator is amplified by the next gate transformation. The target amplification coefficient may be selected, for example, based on the decay behavior observed in the quantum circuit, or based on expected performance considerations for the zero-noise extrapolation process, as will be described in more detail below. For example, if the decay parameter cannot be theoretically estimated, the target amplification may be refined after the initial run. The initial run may include an initial (small) relaxation batch, and the value of s may be refined based on the noisy amplified results obtained in the initial batch.

[0035] In some embodiments, the selection of the target amplification coefficient s may be based on quantitative information derived from the circuit, such as the decay behavior of the expected value of the observable quantity. The decay may be characterized by the decay exponent Λ, and the selection of s may further consider the shot-time ratio f associated with the transformed circuit, as will be described in more detail below.

[0036] In a further step S300a, if the target amplification coefficient is greater than 2, one or more gate transformations are calculated for each gate G(θ), and each transformation is performed on the gate, with parameter values ​​based on parameter conservation criteria.

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[0037] The parameter values for each transformation are selected such that the linear error component is amplified by the target coefficient s. The idle amplification coefficient of a transformation is equal to the number of subgates in the product, and may therefore differ between separate transformations.

[0038] When s is an integer, a single gate transformation can be selected such that the number of subgates is exactly s, whereby both the idle error component and the linear error component are amplified by s.

[0039] When s is a non-integer, a single transformation cannot produce an idle amplification coefficient equal to s, so at least two transformations with different idle amplification coefficients are used, such that one is less than s (e.g., strictly the largest integer less than s) and the other is greater than s (e.g., the aforementioned smallest integer greater than s). A probability distribution is then assigned to these transformations, such that the weighted average of their idle amplification coefficients equals the target amplification coefficient s. Therefore, probabilistic selection of these transformations during subsequent circuit operation is expected to ensure that the idle error component is amplified by the coefficient s, while the linear error component is deterministically amplified by s for all transformations. In this way, the probabilistic mixture of transformations produces the desired amplification while maintaining the ideal operation of the circuit.

[0040] In a further step S300b, a deterministic dual transformation routine is applied when the target amplification coefficient is within the range 1<s<2. For a single gate transformation, the idle amplification coefficient of the transformation is equal to the number of subgates in the product, which is greater than 2, so the linear component and the idle component cannot be amplified together by the same coefficient s.

[0041] Accordingly, two separate gate transformation circuits are calculated for each gate G(θ). Each gate transformation has its parameter values satisfying a parameter preservation criterion,

Formula

[0042] The expected values ​​measured from the execution of the untransformed circuit, as well as from the execution of the circuit transformed by the first and second gate transformations, are relaxed to <0> using the following zero-noise extrapolation process. miti To enable calculation:

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[0043] Here, <0> noisy This shows the expected value measured from the execution of the unconverted circuit. <0> amp,1 And, <0> amp,2 These represent the expected values ​​measured from the execution of the circuits transformed by the first and second gate transformations, respectively. Each of the first and second gate transforms has an idle error amplification coefficient s k and linear error amplification coefficient tk characterized thereby, where k is a transformation index.

[0044] This expression is well-defined as long as (s1-1)(t2-1)≠(s2-1)(t1-1), and provides a relaxed expected value of an observable quantity.

[0045] In some embodiments, the first idle amplification factor and the second idle amplification factor used in the deterministic dual transformation path may be equal. In addition, the second transformation is selected such that the second linear amplification factor remains equal to 1, whereby only the idle error component can be amplified while leaving the linear error component unchanged.

[0046] In a further step S400, the quantum processor executes a quantum circuit together with the transformed quantum circuit determined in step S300a or S300b.

[0047] If the selected amplification factor satisfies s≧2 and s is not an integer, the execution comprises executing the original circuit and, for each circuit shot, executing the transformed quantum circuit obtained by selecting one of the gate transformations prepared in step S300a according to a probability distribution that ensures the expected idle amplification factor is equal to s.

[0048] If the selected amplification factor satisfies s≧2 and s is an integer, the execution comprises executing the original circuit and executing the single transformed quantum circuit obtained from the corresponding gate transformation of step S300a.

[0049] If the selected amplification factor satisfies 1<s<2, the execution comprises executing the original circuit, the circuit prepared in step S300b and transformed by the (first) linear amplification transformation, and the circuit transformed by the (second) idle amplification transformation.

[0050] In a further step S500, measurement results obtained from executing the noisy quantum circuit and one or more transformed quantum circuits are processed to calculate a mitigated expected value of an observable quantity by extrapolation to the zero-noise limit.

[0051] When the target amplification coefficient satisfies s≧2 and s is an integer, the noisy expected value obtained from a single transformed quantum circuit and the noise-amplified expected value are used together to perform zero-noise extrapolation.

[0052] When the target amplification coefficient satisfies s≧2 and s is not an integer, the noisy expected value and the noise-amplified expected value (obtained from execution of stochastically selected transformation circuits) are combined to perform zero-noise extrapolation.

[0053] When the target amplification coefficient satisfies 1<s<2, the noisy expected value, the noise-amplified expected value obtained from executing the quantum circuit transformed by the first (linear amplification) transformation, and the expected value obtained from executing the quantum circuit transformed by the second (idle amplified) transformation are combined to calculate the mitigated expected value using zero-noise extrapolation.

[0054] In some embodiments, the error generator of each gate may have a quadratic error component in addition to the idle and linear components, and the method may further include applying one or more quadratic gate transforms. The quadratic gate transforms may be selected to provide controlled amplification of the quadratic error component while maintaining a parameter conservation criterion. In one example, the quadratic transform replaces gate G(θ) with the product of N subgates G(θ / N), thereby amplifying the idle error component by coefficient N and reducing the quadratic error component by coefficient 1 / N. In another example, the quadratic transform may include a product formed by G(θ(1+δ)) and G(-θδ), and the sequence of subgates G(0) amplifies the idle, linear, and quadratic error components according to a predetermined amplification coefficient. The transformed quantum circuits obtained from these quadratic gate transforms may also be executed, and the corresponding expectation values ​​may be incorporated into a zero-noise extrapolation process, thereby enabling the calculation of relaxed expectation values ​​of observable quantities under a quadratic-noise model, as will be described in more detail below.

[0055] To further illustrate the operation of the method of this disclosure and to provide additional technical context, the following sections present representative mathematical formulations and examples consistent with the method claimed herein and corresponding to the theoretical background on which the method is based.

[0056] In the case of linearity If the error generator of a quantum gate exhibits a purely linear dependence on the absolute value of the gate parameters, then the idle error component and the quadratic error component disappear, and as a result, the overall noise of the gate scales linearly with respect to the magnitude of the gate parameters. That is, g noise (θ) = g (1) It is |θ|.

[0057] In the case of a quantum gate G(θ), a gate transformation can be applied that replaces the gate with the product of two subgates, which are operated on with parameters θ(1+δ) and -θδ, respectively.

[0058] The parameters satisfy the parameter conservation criterion θ(1+δ)+-θδ=θ, and as a result, the ideal operation of the gate remains unchanged.

[0059] Since the linear component of the error generator depends on |θ|, the transformed product yields a transformed linear error component, which is the linear error component amplified by a linear amplification coefficient of 1+2δ.

[0060] This transformation provides a controlled and predictable increase in the linear error contribution while maintaining the intended gate behavior.

[0061] The execution of the non-converting circuit and the converting circuit provide noisy and noise-amplified expect values, respectively, enabling a zero-noise extrapolation (ZNE) process. The ZNE process infers the expect values ​​of the observables corresponding to the ideal (noise-free) execution of the circuit, which are also <0>. ideal This shows that, using exponential extrapolation, the corresponding relaxed expectation for the observable quantity 0 is as follows:

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[0062] Relaxed expected value <0> miti This represents the ideal expected value <0>. ideal This provides an estimate, which is obtained by extrapolating the measured noisy expectation and the noise-amplified expectation to the zero-noise limit. Here, δ is any positive real number, <0> noisy This represents the expected value of the observable quantity 0 measured from a noisy quantum circuit (i.e., untransformed), <0> amp This shows the expected value measured from a noise amplification circuit in which each instance of the quantum gate G(θ) is replaced by the above transformation.

[0063] Any amplification parameter δ can be adopted, but the efficiency of the relaxation process depends on selecting the optimal value. To determine this value, it is useful to consider two parameters.

[0064] The first optimization parameter is:

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[0065] The optimal amplification parameters satisfy the following conditions:

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[0066] The performance of a ZNE process can be quantified by overhead, defined as the ratio between (i) the total quantum processor time required to achieve a specified statistical precision when both the noisy quantum circuit and the noise-amplified transform circuit are running, and (ii) the time required to achieve the same statistical precision using only the noisy quantum circuit. Using an optimal value for δ, the overhead is as follows:

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[0067] For the range 1 ≤ f ≤ 2, the quantity,

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[0068] In the case of Affine In some embodiments, the idle error component of the error generator may not be negligible, and the gate duration does not tend to become zero as the gate parameter θ approaches 0. This behavior is typical, for example, for Mormer-Sorensen (MS) gates where T2 is not negligible. In such cases, the idle error component g (0) This cannot be ignored when constructing gate transforms. In that case, several approaches are possible.

[0069] Low amplification coefficient The first approach applies the same gate transformation used in the purely linear case, but with the parameter δ=0.5. Choosing δ=0.5 ensures that the resulting transformation amplifies the idle error component and the linear error component by the same coefficient. Since both components are amplified equally, this method remains applicable even when the idle error is significant.

[0070] The second approach uses two amplification operations. The first amplification is the same as that described for the linear case. The second amplification replaces each gate G(θ) with the product of two subgates G(θη) and G(θ(1-η)), where the parameter η is between 0 and 0.5. This additional amplification can be implemented in different forms, including variations that mix amplification of the linear error component and the idle error component. However, alternative forms generally offer lower efficiency.

[0071] Using the first approach, no modifications to the relaxation process are required. Under the second approach, the second amplification leaves the linear error component unchanged while amplifying the idle error component in the same way as the first amplification. In this case, the relaxed expectation value of the observable quantity 0 can be expressed as follows:

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[0072] To determine the optimal parameter selection in this setting, the previously defined damping index Λ is divided into two components, case G, such that Λ = Λ0 + Λ1. (1) Λ0 and case G associated with =0 (0) It can be decomposed into Λ1 associated with =0. As long as Λ1≦λ(1), the optimal strategy can be shown to be applying only the first approach, i.e., choosing δ=0.5 with a single amplification. When Λ1 exceeds λ(1), the optimal choice is as follows:

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[0073] The second amplification remains effective for any value η between 0 and 0.5. The corresponding overhead is given by:

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[0074] When evaluating amplification and overhead, it is assumed that Λ is known. In practice, estimating Λ may require iterative procedures. Such estimations inevitably introduce some degree of error, and the optimal overhead may not be precisely achieved. This limitation is inherent in all forms of zero-noise extrapolation. However, this method offers advantages in the following respects, as long as Λ1 ≤ λ(1): The amplification coefficient is robust and does not depend sensitively on the exact value of Λ, allowing for more efficient use of the method in this regime compared to other methods.

[0075] High amplification factor The gate transformation described above relied on replacing each gate with the product of two subgates. This limits the value of s used for amplification to s ≤ 2 when the decay exponent is small. Larger values ​​of s require the introduction of additional subgates to amplify the idle error component with the same coefficient as the linear error component, and increasing the number of subgates increases the overhead compared to limiting s to a value not exceeding 2.

[0076] Without this restriction, it may be desirable to increase s as the decay exponent decreases. It turns out that this can be achieved using a stochastic transformation mixture.

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[0077]

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[0078] The optimal choice is as follows:

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[0079] The linearly |θ|-dependent error generator component is amplified by a target amplification coefficient s = 1 + 2δ. Depending on the case, the probabilistic application of a transform with a different number of subgates corresponding to 2n and 2(n+1) and numbers in between ensures that the idle error component is also amplified by coefficient s = 1 + 2δ. This behavior applies when the idle-only decay index Λ0 << 1. However, Λ0 is typically a fraction of the total decay index Λ, while the total decay index itself is small in situations where a large value s is optimal, and this condition is usually satisfied.

[0080] In this case, circuit dispersion is introduced in addition to shot dispersion. However, the intrinsic circuit variation is small and therefore not expected to cause practical difficulties. Intrinsic circuit dispersion can be limited by the extreme case where two circuits are applied and fully amplified by either a short transform r or one long transform.

[0081]

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[0082] Using this, the optimal amplification is as follows:

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[0083] Here, f can be as large as 1 + 2δ, and the average number of gates per amplified circuit is multiplied by that number. This creates an implicit equation, but as λ, it depends very weakly on f, and the resulting equation is easily solved. The relaxed expectation and overhead continue to follow the relationships presented earlier, respectively.

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[0084] Introduction of quadratic terms For a first-order amplification parameter δ, the second-order error term g (2) (Also called the quadratic error component) is the linear error term g (1) It is observed that it is amplified together with. As a result, the modification of the aforementioned method is simply g (2) Rather than being something that cannot be ignored, the contribution g (2) δ 2 This may be necessary if the error cannot be ignored. In such cases, an additional amplification circuit can be used. This additional amplification can be implemented using the same type of gate transform described in relation to idle error amplification (low amplification coefficient), but applied with two different values ​​of the parameter η. Thus, two circuits are used, each with its own value η. For optimal separation of the error component, the choices η1=0 and η2=0.5 can be used even though any two different values ​​η are preferable.

[0085] In this choice, the relaxed expectation value of the observable quantity 0 can be expressed as follows:

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[0086] The optimization δ is expressed by the following relationship:

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[0087] Secondary error component g (2) The idle error component g (0) If it is significantly larger than this, rare but noteworthy cases may occur. In such situations, the additional idle error is acceptable, and the overall overhead can be reduced by limiting the number of noise amplification circuits to two. To achieve this, the following gate transformations can be used for the amplification circuits.

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[0088] In the formula, 0≦η j The parameter is ≤ 0.5. j The second amplification using ≤0.5 results in twice the idle error of the previously used transformation. η at this interval j Any choice of η may be used. However, to avoid amplification of the quadratic error component, the choice η is selected. j = 0 is preferable.

[0089] The first transformation is applied when the following is applicable:

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[0090] Reconsidering the quadratic term with high amplification coefficients Considering the above-mentioned probabilistic transformation,

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[0091] The reduction of the second-order error component can be achieved by the following transformation:

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[0092] To maximize the amplification of the quadratic error component, the following transformations can be used.

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[0093] This transformation amplifies the idle error component by coefficient N, the linear error component by coefficient 1+2δ, and the quadratic error component by coefficient 1+2δ+2δ 2 It amplifies only that much. This behavior is due to a probabilistic transformation.

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[0094] In the first method, the relaxed expectation can be expressed as follows:

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[0095] Context-dependent error The methods described above are presented at the level of individual gates. However, in some quantum processors, the noise affecting a gate may depend on the sequence of preceding gates, representing a non-Markov noise model. This situation can occur, for example, in systems where qubits are physically rounded to the interaction zone. In such systems, the position of a qubit before shuttle depends on previously applied gates, and errors associated with the shuttle operation itself may depend on this context. In these situations, applying an amplification transform to each gate individually (e.g., replacing each gate with a transform) is,

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[0096] To address this, the above method can be applied not at the level of individual gates, but at the level of unitary blocks (i.e., blocks of commutative gates). Define the circuit as follows:

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[0097] When a circuit is divided into such blocks, the transformation can be applied to the block rather than to the individual gates. For example, in amplification,

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[0098] Since gates within a block are interchangeable, the effect of this block-level transformation is identical to the effect of the corresponding gate-level transformation when the noise model is Markov (and non-coherent). Otherwise, block-level applications also amplify context-dependent errors.

[0099] Comparison with existing ZNE methods The method presented herein enables noise-controlled amplification using minimal heuristic assumptions, similar to probabilistic error amplification (PEA). With respect to relaxation overhead, the method presented herein exhibits significantly improved scaling compared to standard unitary folding-based zero-noise extrapolation (UF-ZNE). Unitary folding imposes a minimum amplification factor of 3 on the transformed circuit, resulting in at least the case of large attenuation exponents e 6Λ Similarly, an exponential overhead occurs. This dependency dominates the overhead of the high-capacity circuit and is substantially larger than the overhead associated with CHARM, as shown in Figure 2.

[0100] The method presented herein also achieves lower overhead than PEA, as shown in Figure 2. This advantage arises primarily from the variance between circuits introduced by PEA, which requires additional sampling overhead to suppress. An additional advantage of the method presented herein is that it does not require the characterization of the noise model. The absence of a characterization step reduces overhead, as characterization itself consumes quantum processor time, and avoids inaccuracies that may arise from incomplete or fluctuating noise model estimates. Furthermore, the method presented herein can mitigate noise components that are not readily amplified using PEA, such as leakage errors.

[0101] The data shown in Figure 2 demonstrate that the methods presented herein are particularly effective for high-capacity circuits, and that their overhead is weakly dependent on the presence of idle or quadratic error components, provided that these components do not dominate the overall noise. Figure 2 shows the overhead associated with several zero-noise extrapolation methods. For PEA, the curve does not include characterization time. We assume that the circuit execution time is 10 times the shot time. This is a reasonable estimate for many trapped ion systems, but the exact value depends on the quantum processor hardware. A single shot is used for each circuit. The band domain for the methods disclosed herein represents the range of possible values ​​for the shot-time ratio f, which varies between 1 and the amplification factor at each value of the decay index. For the idle error component, the model uses Λ0 = 0.2Λ, and for the quadratic error component, the model uses Λ2 = 0.1Λ. A unitary convolution method for the minimum convolution coefficient of 3 is shown, and its band domain represents the range of amplified shot-time coefficients from 1 to 3.

[0102] Figure 3 and the following discussion are intended to provide a brief and general description of exemplary computing environments in which the disclosed technology may be implemented. While not required, the disclosed technology is described in the general context of computer executable instructions, such as program modules, executed by a personal computer (PC). Generally, a program module includes routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. Furthermore, the disclosed technology may be implemented in other computer system configurations, including handheld devices, multiprocessor systems, microprocessor-based or programmable consumer electronics, network PCs, minicomputers, and mainframe computers. The disclosed technology may also be practiced in a distributed computing environment where tasks are performed by remote processing devices linked via a communication network. In a distributed computing environment, program modules may reside in both local and remote memory storage devices.

[0103] Referring to Figure 3, an exemplary system for implementing the disclosed technology includes a general-purpose (typical) computing device in the form of an exemplary conventional PC 1100, comprising one or more processing units 1110, a system memory 1120, and a system bus 1130 that connects various system components, including the system memory 1120, to one or more processing units 1110. The system bus 1130 may be one of several types of bus structures, including a memory bus or a memory controller, a peripheral bus, and / or a local bus using any of various bus architectures. The exemplary system memory 1120 includes read-only memory (ROM) 1122 and random-access memory (RAM) 1127. A basic input / output system (BIOS) 1125, which contains basic routines useful for transferring information between elements within the PC 1100, is stored in the ROM 1122. As shown in Figure 3, the system memory 1120 stores computer-executable instructions in its respective memory sections (collectively shown as executable software 1129 for performing any embodiment of the disclosed techniques, such as selecting a target amplification coefficient, calculating gate transformations, transforming quantum circuits, collecting expectation values ​​from quantum circuits and transformed quantum circuits, and calculating relaxed expectation values ​​using zero-noise extrapolation).

[0104] An exemplary PC1100 further includes one or more storage devices 1140, such as a hard disk drive for reading and writing to a hard disk, a magnetic disk drive for reading and writing to a removable magnetic disk, and / or an optical disk drive for reading and writing to a removable optical disk (such as a CD-ROM or other optical medium). Such storage devices can be connected to the system bus 1130 by a hard disk drive interface, a magnetic disk drive interface, and / or an optical drive interface, respectively. The drives and their associated computer-readable media provide non-volatile storage of computer-readable instructions, data structures, program modules, and other data for the PC1100. In the exemplary operating environment, other types of computer-readable media that can store data accessible by the PC may also be used, such as magnetic cassettes, flash memory, digital video discs, CDs, DVDs, RAM, NVRAM, and ROM. As used herein, the terms storage, memory, and computer-readable media do not include or encompass the propagating carrier or signal itself.

[0105] The operating system, one or more application programs, other program modules, and several program modules including program data may be stored in the storage device 1140. The storage of quantum measurement results and instructions for obtaining such measurements (and / or instructions for carrying out any embodiment of the disclosed technology) may also be stored in the storage device 1140. The user may input commands and information to the PC 1100 via one or more input devices 1150, such as a keyboard and a pointing device such as a mouse. Other input devices may include a digital camera, microphone, joystick, gamepad, satellite receiver antenna, scanner, etc. These and other input devices are often connected to one or more processing units 1110 via a serial port interface coupled to the system bus 1130, but may be connected by other interfaces such as a parallel port, game port, or universal serial bus (USB). A monitor 1180 or other type of display device is also connected to the system bus 1130 via an interface such as a video adapter. Other peripheral output devices 1160 may include speakers and a printer (not shown). In some cases, a user interface is displayed so that the user can input the circuit for synthesis and verify the success of the synthesis.

[0106] The PC1100 may operate in a networked environment using logical connections to one or more remote computers, such as remote computers 1190. In some examples, this may include one or more network or communication connections 1170. The remote computer 1190 may be another PC, server, router, network PC, peer device, or other common network node, and typically includes many or all of the elements described above with respect to the PC1100, although Figure 3 shows only the memory storage device 1195. The personal computer 1100 and / or remote computer 1190 may be connected to logical local area networks (LANs) and wide area networks (WANs). Such networking environments are common in offices, enterprise-wide computer networks, intranets, and the internet.

[0107] When used in a LAN networking environment, the PC1100 connects to the LAN via a network interface. When used in a WAN networking environment, the PC1100 typically includes a modem or other means for establishing communication over a WAN such as the Internet. In a networked environment, program modules or parts thereof described in relation to the personal computer 1100 may be stored in a remote memory storage device or other location on the LAN or WAN. The illustrated network connection is illustrative, and other means may be used to establish communication links between computers.

[0108] Referring to Figure 4, an exemplary system for implementing the disclosed technology includes a computing environment 1200, the environment including one or more quantum processing units 1210, each including one or more monitoring / measurement devices 1280. The quantum processing units execute quantum circuits provided by a typical processing unit 1220. The quantum circuits are downloaded to the quantum processing units 1210 or used (e.g., via control lines (quantum buses) 1270) to program or configure the quantum processing units. Procedures according to any of the disclosed embodiments (e.g., a high-level description of a set of gate sequences applied to implement the currently disclosed technology) may be stored in memory 1230.

[0109] Referring to Figure 4, a high-level description of quantum software can be translated into a set of gates (e.g., a sequence of quantum circuits). Such a high-level description may optionally be stored on one or more external computers 1260 outside the computing environment 1200 using one or more memory and / or storage devices 1265, and then, if necessary, can be downloaded to the computing environment 1200 via one or more communication connections 1240. The quantum circuits (according to any of the disclosed embodiments) are coupled to a quantum processor 1310.

[0110] The quantum processing unit may be one or more of the following, but is not limited to: (a) an ion-trap quantum computer, or (b) a cold-atom quantum computer. A set of gates (e.g., using any of the disclosed embodiments) may be transmitted to the quantum processing unit via control lines 1270 in a controller 1250 of a typical processor 1220 (or may be otherwise applied). In the illustrated example, the desired quantum computing process is carried out using one or more controllers 1250 specifically adapted to control one of the corresponding quantum processors 1210. The typical processor 1220 may further interact with a measurement / monitoring device (e.g., a readout device) 1280 to help control and implement the desired quantum computing process (e.g., by reading or measuring data results from the quantum processing unit when available). The typical processor may include any relevant functionality described with reference to the typical computing system of Figure 3.

[0111] While the principles of the disclosed technology have been described and illustrated with reference to the illustrated embodiments, it will be recognized that the illustrated embodiments can be modified in configuration and detail without departing from such principles. For example, elements of the illustrated embodiments shown in software can be implemented in hardware, and vice versa. Furthermore, technology from any example can be combined with technology described in any one or more of the other examples. It will be understood that procedures and functions, such as those described with reference to the illustrated examples, can be implemented in a single hardware or software module, or separate modules may be provided. The particular configurations described above are provided for convenient illustration purposes, and other configurations can be used.

Claims

1. A computer implementation method for error mitigation for a quantum circuit running on a quantum processor, wherein the quantum circuit is g ｎｏｉｓｅ (θ) = g （０） +g （１） One or more quantum gates G(θ) having gate parameter θ such that |θ|, and an error generator g having an affine dependence on the absolute value of the gate parameter. ｎｏｉｓｅ (θ) and g （０） However, define the idle error component, g （１） However, defining a linear error component, the method is i. Select a target amplification coefficient s for the linear error component. ii. When the target amplification coefficient is s ≥ 2, one or more gate transformations are calculated, wherein each gate transformation is configured to transform the quantum gate into a product of subgates. a. Each subgate has a parameter value θ ｊ An instance of quantum gate G operated by the parameter values ​​over the product, where the parameter conservation criterion Σjθ ｊ Satisfying =θ, b. When the transformed error generator of the subgate product includes a transformed idle error component and a transformed linear error component, and at least two gate transformations are calculated, - The converted idle error component is an amplification of the idle error component by different idle amplification coefficients for each of the at least two gate transforms, - Calculate that the transformed linear error component is an amplification of the linear error component with the same target amplification coefficient for at least two gate transformations. iii. Executing the quantum circuit and the transformed quantum circuit, wherein for each occurrence of the quantum gate G(θ) across the set of circuit executions, one of the gate transformations is selected according to the probability distribution configured such that the expected value of the idle amplification coefficient is equal to the target amplification coefficient s across the probability distribution. iv. Collecting the noisy expectation of the observable quantity from the execution of the quantum circuit, and the noise-amplified expectation from the execution of the transformed quantum circuit. v. A method comprising calculating the relaxed expectation of the observable quantity by extrapolating to zero noise using the noisy expectation and the noise-amplified expectation.

2. The method according to claim 1, wherein the target amplification coefficient s for the error generator is selected based on the decay of the expected value of the observable quantity in the quantum circuit.

3. The target amplification coefficient s is set based on the decay exponent Λ of the expected value of the observable quantity in the quantum circuit, and the shot time ratio f between the transformed quantum circuit and the quantum circuit. [Math 1] Therefore, λ is the following solution: [Math 2] The method according to claim 1.

4. The above-mentioned at least two gate transformations are two sets of parameter values, [Math 3] Defined by, each of which, for k ∈ {1, 2}, [Math 4] The method according to claim 1, which satisfies the requirements of claim 1.

5. The method according to claim 1, wherein the number of subgates differs between the two gate transformations, thereby providing different idle amplification coefficients for each gate transformation.

6. When s is a non-integer, at least two of the different idle amplification coefficients among the gate transforms are i. A first idle amplification coefficient equal to the largest integer strictly smaller than s, ii. The method according to claim 1, comprising a second idle amplification coefficient equal to the smallest integer strictly greater than s.

7. The method according to claim 1, wherein the target amplification coefficient s is an integer, and only one gate transform is calculated and applied across the set of circuit executions.

8. When the target amplification coefficient s is 1 < s < 2, i. Calculating linear amplification gate transformation and idle amplification transformation, each of which is configured to transform said quantum gate into a product of subgates, each subgate being a parameter value θ ｊ which is an instance of said quantum gate G operated with, and the parameter values over said product satisfy a parameter preservation criterion Σ ｊ θ ｊ =θ, Each subgate product associated with the transformed error generator includes a transformed idle error component and a transformed linear error component. - In the linear amplification transformation, the transformed linear error component is an amplification of the linear error component by a first linear amplification coefficient, and the transformed idle error component is an amplification of the idle error component by a first idle amplification coefficient. - In the idle amplification conversion, the converted idle error component is an amplification of the idle error component by a second idle amplification coefficient, and the converted idle error component is an amplification of the idle error component by a second idle amplification coefficient, ii. To collect the noisy expectation value obtained from the execution of the quantum circuit, the linearly amplified expectation value obtained from the execution of the circuit transformed by the linear amplification transform, and the idle amplified expectation value obtained from the execution of the circuit transformed by the idle amplification transform. iii. The method according to claim 1, further comprising extrapolating the relaxed expectation of the observable quantity to zero noise using the noisy expectation, the linearly amplified expectation, and the idle amplified expectation.

9. The method according to claim 8, wherein the first idle amplification coefficient and the second idle amplification coefficient are equal.

10. The method according to claim 8, wherein the second linear amplification coefficient is equal to 1.

11. The method according to claim 1, wherein the quantum gate G is decomposed into a product of Pauli rank 1 gates before the gate transformation is applied.

12. The method according to claim 1, wherein the gate transformation is applied to a block of commutative gates.

13. The method according to claim 1, wherein the quantum processor comprises a trap ion system.

14. The affine dependence of the error generator is θ ２ The method according to claim 1, further comprising a quadratic term proportional to [the given value].

15. G(θ) is a product of N subgates having integer N≧2 such that the corresponding idle error component is amplified by coefficient N and the corresponding quadratic error component is amplified by coefficient 1 / N. Ｎ The method according to claim 14, further comprising computing a quadratic transform to convert to, additionally performing and collecting expectation value measurements of the observable quantities for the quadratic transformed quantum circuit, wherein the relaxed expectation value is calculated using the collected expectation value of the quadratic transformed quantum circuit.

16. The corresponding idle error component is amplified by coefficient N, the corresponding linear error component is amplified by coefficient 1 + 2δ, and the corresponding quadratic error component is amplified by coefficient 1 + 2δ + 2δ ２ To amplify by a certain amount, G(θ) is defined as a product G(θ(1+δ))G(-θδ)G(0) with integer N≧2 and real parameter δ>0. Ｎ－２ The method according to claim 14, further comprising computing a quadratic transform to convert to, additionally performing and collecting expectation value measurements of the observable quantities for the quadratic transformed quantum circuit, wherein the relaxed expectation value is calculated using the collected expectation value of the quadratic transformed quantum circuit.

17. A system for mitigating errors in quantum circuits, wherein the system is i. A quantum processor configured to execute a quantum circuit comprising one or more quantum gates G(θ) having gate parameters θ, wherein each quantum gate is g ｎｏｉｓｅ (θ) = g （０） +g （１） |θ| and g （０） This defines the idle error component, g （１） An error generator g having an affine dependence on the absolute value of the gate parameter, such that it defines a linear error component. ｎｏｉｓｅ (θ) is associated with the quantum processor, ii. A typical controller comprising a processor and memory for storing instructions, wherein when an instruction is executed by the processor, the typical controller: a. Select a target amplification coefficient s for the linear error component. b. Calculating one or more gate transformations when the target amplification coefficient satisfies s ≥ 2, wherein each gate transformation is performed by applying a parameter conservation criterion to the quantum gate G(θ). [Math 5] Parameter values ​​{θ} that satisfy the condition ｊ Product G(θ) of subgates having} ｊ It is configured to convert to ), and the product of the subgates is associated with a converted error generator having a converted idle error component and a converted linear error component, and when at least two gate transformations are computed, - The converted idle error component is an amplification of the idle error component by different idle amplification coefficients for each of the at least two gate transforms, - Calculate that the transformed linear error component is an amplification of the linear error component with the same target amplification coefficient for at least two gate transformations. c. Causing the quantum processor to execute the quantum circuit and the transformed quantum circuit, wherein for each occurrence of the quantum gate G(θ) across the set of circuit executions, one of the gate transformations is selected according to the probability distribution configured such that the expected value of the idle amplification coefficient is equal to the target amplification coefficient s across the probability distribution. d. Collecting the noisy expectation value of at least one observable quantity from the execution of the quantum circuit, and the noisy amplified expectation value of the observable quantity from the execution of the transformed quantum circuit, and e. A system comprising a typical controller which causes the system to calculate the relaxed expectation of the observable quantity by extrapolating the noisy expectation and the noise-amplified expectation to zero noise.

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