Printed circuit board

Abstract

One of the several objectives of the present invention is to provide a printed circuit board that is applicable to high-multilayer, large-area products, enables thinning, miniaturization, and high performance, and is further advantageous in terms of pitch reduction and warpage control. [Solution] The present invention relates to a printed circuit board comprising: a plurality of first insulating layers; a plurality of first wiring layers each disposed within the plurality of first insulating layers; a first glass layer disposed above the plurality of first insulating layers and having a thickness thinner than at least one of the plurality of first insulating layers; a second glass layer disposed below the plurality of first insulating layers and having a thickness thinner than at least one of the plurality of first insulating layers; a second wiring layer disposed above the first glass layer; and a third wiring layer disposed below the second glass layer.

Description

[Technical Field]

[0001] The present invention relates to a printed circuit board. [Background Art]

[0002] In recent years, with the rapid increase in demand for high-performance computing and large-scale data processing, the server-centered semiconductor application market has been expanding rapidly. Accordingly, the demand for high-layer-count and large-area substrates for high-integration and high-bandwidth processing is increasing, which has continuously promoted the miniaturization and high performance of substrates and packages. In particular, as the demand for chiplets that integrate multiple chips into a single package to achieve distributed functions and heterogeneous integrated packages increases, the importance of reducing the spacing of fine wiring, ensuring the overall flatness of packages and substrates, and warpage suppression technology has emerged. However, the reality is that existing substrate technologies using organic material-based copper-clad laminates have shown limitations in terms of pitch reduction and warpage control. Particularly, in the case of server central processing units, an increasing number of technical developments are aimed at achieving high performance while reducing the overall thickness by switching from the conventional structure with a core layer to a coreless structure in which upper circuits are concentrated, which in turn creates greater difficulties in terms of warpage control. [Summary of the Invention] [Problem to be Solved by the Invention]

[0003] One of the several objects of the present invention is to provide a printed circuit board that is applicable to high-layer-count large-area products, can achieve thinning, miniaturization and high performance, and is more advantageous in terms of pitch reduction and warpage control. [Means for Solving the Problem]

[0004] One of the several solutions proposed through the present invention is to manufacture a multilayer coreless substrate, arrange glass layers on the upper side and lower side of the multilayer coreless substrate, and then form wiring layers respectively on these glass layers, or form a fine wiring layer on the upper glass layer using a thinner insulating layer.

[0005] For example, a printed circuit board according to one example may include a plurality of first insulating layers, a plurality of first wiring layers each disposed within the plurality of first insulating layers, a first glass layer disposed above the plurality of first insulating layers and thinner than at least one of the plurality of first insulating layers, a second glass layer disposed below the plurality of first insulating layers and thinner than at least one of the plurality of first insulating layers, a second wiring layer disposed above the first glass layer, and a third wiring layer disposed below the second glass layer.

[0006] For example, a printed circuit board according to one example includes a first substrate portion comprising a first insulating body, a first glass layer disposed on the upper surface of the first insulating body, a second glass layer disposed on the lower surface of the first insulating body, and a plurality of inner wiring layers disposed within the first insulating body, and a second substrate portion comprising a second insulating body disposed on the upper surface of the first glass layer, and a plurality of first outer wiring layers disposed on or within the second insulating body, wherein the insulation distance between any two first outer wiring layers adjacent to each other in the thickness direction among the plurality of first outer wiring layers may be smaller than the insulation distance between any two inner wiring layers adjacent to each other in the thickness direction among the plurality of inner wiring layers. [Effects of the Invention]

[0007] One of the various effects of the present invention is that it can be applied to high-multilayer, large-area products, enabling thinning, miniaturization, and high performance, and further providing a printed circuit board that is more advantageous in terms of pitch reduction and warpage control. [Brief explanation of the drawing]

[0008] [Figure 1] This is a block diagram illustrating an example of an electronic equipment system. [Figure 2] This is a schematic cross-sectional view showing an example of a printed circuit board. [Figure 3] Figure 2 is a schematic process diagram showing an example of the manufacturing process of a printed circuit board. [Figure 4] This is a schematic cross-sectional view showing another example of a printed circuit board. [Figure 5] Figure 4 is a schematic process diagram showing an example of the manufacturing process of a printed circuit board. [Figure 6] This is a schematic cross-sectional view showing yet another example of a printed circuit board. [Figure 7] This is a schematic cross-sectional view showing yet another example of a printed circuit board. [Modes for carrying out the invention]

[0009] The present invention will be described below with reference to the attached drawings. The shapes and sizes of the elements in the drawings may be exaggerated or reduced for clearer explanation.

[0010] Figure 1 is a block diagram illustrating an example of an electronic equipment system.

[0011] Referring to the drawing, the electronic device 1000 houses the main board 1010. The main board 1010 is physically and / or electrically connected to chip-related components 1020, network-related components 1030, and other components 1040, etc. These are also coupled with other electronic components, which will be described later, to form various signal lines 1090.

[0012] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPUs), graphics processors (e.g., GPUs), digital signal processors, cryptographic processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). It goes without saying that other different forms of chip-related electronic components may also be included. Furthermore, these chip-related components 1020 may be combined with each other. The chip-related components 1020 may also be in the form of a package that includes the chips and electronic components mentioned above.

[0013] Network-related component 1030 includes, but is not limited to, any other wireless and wired protocols designated as Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth®, 3G, 4G, 5G, and later. It also includes any other diverse wireless or wired standards and protocols. Furthermore, it goes without saying that network-related component 1030 may be combined with chip-related component 1020.

[0014] Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCCs (low-temperature co-firing ceramics), EMI (electromagnetic interference) filters, MLCCs (multi-layer ceramic condensers), etc. However, they are not limited to these, and may also include other passive elements in chip component form used for various other applications. It goes without saying that other components 1040 may be combined with chip-related components 1020 and / or network-related components 1030.

[0015] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that are or may not be physically and / or electrically connected to the main board 1010. Examples of other electronic components include a camera module 1050, an antenna module 1060, a display 1070, a battery 1080, etc. However, it is not limited to these, and may also include audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage devices (e.g., hard disk drives), CDs (compact disks), DVDs (digital versatile disks), etc. Needless to say, it may also include other electronic components used for various purposes depending on the type of electronic device 1000.

[0016] The electronic device 1000 may be a smartphone, personal digital assistant, digital video camera, digital still camera, network system, computer, monitor, tablet, laptop, netbook, television, video game, smart watch, automobile, server, etc. However, it is not limited to these, and it goes without saying that it may be any other electronic device that processes data.

[0017] Figure 2 is a schematic cross-sectional view showing an example of a printed circuit board.

[0018] Referring to the drawing, an example of a printed circuit board 100A includes a plurality of first insulating layers 111, 111a, a plurality of first wiring layers 121, 121a, 121b arranged within the plurality of first insulating layers 111, 111a, a first glass layer 151 arranged above the plurality of first insulating layers 111, 111a, a second glass layer 152 arranged below the plurality of first insulating layers 111, 111a, a second wiring layer 122 arranged above the first glass layer 151, a third wiring layer 123 arranged below the second glass layer 152, and a plurality of first wiring vias 131 that penetrate one or more of the plurality of first insulating layers 111, 111a and connect the plurality of first wiring layers 121, 121a, 121b to each other. The system may include a second wiring via 132 that penetrates both the uppermost first insulating layer 111a and the first glass layer 151 and connects the uppermost first wiring layer 121a and the second wiring layer 122 to each other, a third wiring via 133 that penetrates the second glass layer 152 and connects the lowermost first wiring layer 121b and the third wiring layer 123, a first solder resist layer 161 positioned above the first glass layer 151 and having a plurality of first openings h1 that expose at least a portion of the second wiring layer 122, and a second solder resist layer 162 positioned below the second glass layer 152 and having a plurality of second openings h2 that expose at least a portion of the third wiring layer 123. If necessary, a plurality of semiconductor chips 181, 182, 183 may be mounted on the first solder resist layer 161 via a plurality of electrically connecting metals 171, 172, 173. For example, the printed circuit board 100A in this example may be a package board, an interposer board, and / or a semiconductor package.

[0019] On the other hand, the plurality of first insulating layers 111, 111a, the plurality of first wiring layers 121, 121a, 121b, and the plurality of first wiring vias 131 may form a coreless multilayer substrate structure. For example, the plurality of first insulating layers 111, 111a may not include a separate core layer. For example, the plurality of first insulating layers 111, 111a may be a coreless structure composed of a plurality of build-up layers. Furthermore, first and second glass layers 151 and 152 may be respectively disposed on the upper side and the lower side of such a coreless multilayer substrate structure. In this case, the thickness of each of the first and second glass layers 151 and 152 may be smaller than that of at least one of the plurality of first insulating layers 111 and 111a, preferably smaller than that of at least one of the remaining first insulating layers 111 excluding the first insulating layer 111a disposed on the uppermost side. Therefore, the printed circuit board 100A according to an example can be applied to a high-multilayer large-area product including 50 or more build-up layers or 100 or more build-up layers, and can still be thinned, while being more advantageous in terms of warpage control. In addition, by applying the first glass layer 151 with excellent flatness, the second wiring layer 122 including fine wiring can be formed on the outermost side where the plurality of semiconductor chips 181, 182, 183 are mounted, which is more advantageous for miniaturization and high performance, and can also be more advantageous from the perspective of pitch reduction.

[0020] Hereinafter, components of the printed circuit board 100A will be described in more detail with reference to the drawings.

[0021] The plurality of first insulating layers 111, 111a may each contain an organic insulating material. The organic insulating material may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material containing an inorganic filler and / or an organic filler together with a resin. For example, the plurality of first insulating layers 111, 111a may each include a non-photosensitive insulating material such as ABF (Ajinomoto Build-up Film) or a photosensitive insulating material such as PID (Photo Imageable Dielectric), but are not limited thereto. The plurality of first insulating layers 111, 111a may have distinct boundaries from each other, or may be integrated without a distinct boundary. In the case of integration, the interlayer boundary between the plurality of first insulating layers 111, 111a can be generally estimated based on the lower surface of each of the plurality of wiring layers 121, 121a, 121b.

[0022] The plurality of first wiring layers 121, 121a, 121b and the second and third wiring layers 122, 123 may each contain a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The plurality of first wiring layers 121, 121a, 121b and the second and third wiring layers 122, 123 may each perform various functions according to the design. For example, they may include a signal pattern, a power pattern, a ground pattern, and the like. These patterns may each have various forms such as a line, a plane, a pad, and a land. The plurality of first wiring layers 121, 121a, 121b and the second and third wiring layers 122, 123 may each include an electroless plating layer (e.g., chemical copper) as a seed layer and an electrolytic plating layer (e.g., electrolytic copper) as a pattern layer. However, the structure is not limited thereto, and a sputtered layer (e.g., sputtered titanium / copper) may be included as the seed layer instead of the electroless plating layer. Alternatively, both a sputtered layer and an electroless plating layer may be included as the seed layer.

[0023] The uppermost first wiring layer 121a and the second wiring layer 122, and the lowermost first wiring layer 121b and the third wiring layer 123, may each be thinner than at least one of the remaining first wiring layers 121. For example, the wiring layers 121a, 121b, 122, and 123 formed on the outermost surface of the printed circuit board 100A according to one example can be formed thinner and finer. In particular, forming the wiring layers 121a and 122 formed on the outermost surface where the semiconductor chip is mounted thinner is advantageous for miniaturization and performance improvement, and may also be advantageous in terms of pitch reduction. If necessary, only the uppermost first wiring layer 121a and the second wiring layer 122 may each be thinner than at least one of the remaining first wiring layers 121, but this is not limited to this.

[0024] The multiple first wiring vias 131 and the second and third wiring vias 132 and 133 can each contain metal. The metals can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The multiple first wiring vias 131 and the second and third wiring vias 132 and 133 can each contain filled vias that fill via holes, or they can contain conformal vias that are positioned along the walls of the via holes. The multiple first wiring vias 131 and the second and third wiring vias 132 and 133 can each perform various functions depending on the design. For example, they can include ground vias, power vias, signal vias, and so on. Multiple first wiring vias 131 and second and third wiring vias 132 and 133 may each include an electroless plating layer (e.g., chemical copper) as a seed layer and an electroplating layer (e.g., electrolytic copper) as a pattern layer. However, the invention is not limited to this, and a sputtered layer (e.g., sputtered titanium / copper) may be included as a seed layer instead of an electroless plating layer. Alternatively, both a sputtered layer and an electroless plating layer may be included as seed layers.

[0025] Each of the multiple first wiring vias 131 may have a tapered shape in substantially the same direction as the second wiring via 132, and a tapered shape in substantially the opposite direction to the third wiring via 133. For example, the upper end width of each of the multiple first wiring vias 131 and second wiring vias 132 may be wider than the lower end width in cross-section, while the upper end width of the third wiring via 133 may be narrower than the lower end width in cross-section. Furthermore, the second wiring via 132 can penetrate not only the first glass layer 151 but also the uppermost first insulating layer 111a all at once. Such first to third wiring vias 131, 132, and 133 can be realized by forming a multilayer coreless substrate using a carrier, attaching a glass layer after carrier detachment, and processing vias on the outermost layer, as described in the process later. Consequently, this may be more advantageous in achieving the technical effects described above.

[0026] The first and second glass layers 151 and 152 may include glass that is an amorphous solid. The glass may include, for example, pure silicon dioxide (about 100% SiO2), soda-lime glass, borosilicate glass, aluminosilicate glass, etc. However, it is not limited to these, and alternative glass materials such as fluorine glass, phosphoric acid glass, chalcogen glass, etc. may also be used as materials. In addition, other additives may be further included to form glass having specific physical properties. Such additives may include not only calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda), but also magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, and carbonates and / or oxides of such elements and other elements. The first and second glass layers 151 and 152 may be layers distinct from organic insulating materials including glass fibers (glass fiber, glass cloth, glass fabric), such as CCL (copper clad laminate), PPG (prepreg), etc. For example, the first and second glass layers 151 and 152 may include glass panels that can be made to cover a large area, such as glass plates.

[0027] The first and second solder resist layers 161 and 162 may each contain, but are not limited to, liquid or film-type solder resists, and other types of insulating materials such as ABF may be used. Surface treatment layers and / or metal bumps may be formed on each pattern exposed to the plurality of first and second openings h1 and h2, as needed. The plurality of first and second openings h1 and h2 may each be in the form of SMD (Solder Mask Defined) and / or NSMD (Non Solder Mask Defined), but are not limited to these.

[0028] The multiple electrical connecting metals 171, 172, and 173 can each be formed from a low-melting-point metal, such as a solder of tin (Sn)-aluminum (Al)-copper (Cu), but this is merely an example and the material is not particularly limited thereto. The multiple electrical connecting metals 171, 172, and 173 may each be balls, pins, etc. The multiple electrical connecting metals 171, 172, and 173 may each be formed from multiple layers or from a single layer. When formed from multiple layers, it may include copper columns and solder, and when formed from a single layer, it may include tin-silver solder, but is not limited thereto. The multiple electrical connecting metals 171, 172, and 173 can be used to mount multiple semiconductor chips 181, 182, and 183.

[0029] Multiple semiconductor chips 181, 182, and 183 may each include an integrated circuit (IC) die in which hundreds to millions or more elements are integrated within a single chip. In this case, the integrated circuit may be, but is not limited to, logic chips such as a central processor (e.g., CPU), graphics processor (e.g., GPU), field-programmable gate array (e.g., FPGA), digital signal processor, cryptographic processor, microprocessor, microcontroller, application processor (e.g., AP), analog-to-digital converter, or ASIC (application-specific IC). Needless to say, it may also be other types such as memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, or HBM (High Bandwidth Memory). It may also be a semiconductor chip containing circuits that control various input / output devices, such as an input / output die (e.g., I / O Die). For example, the first and third semiconductor chips 181 and 183 may each be central processors (e.g., CPUs), and the second semiconductor chip 182 may be an input / output die (e.g., an I / O die), but is not limited to these.

[0030] If necessary, passive elements such as Si-Cap (Silicon Capacitor) or IPD (Integrated Passive Device) can be embedded inside multiple first insulating layers 111, 111a. The embedded passive elements may be connected to at least one of the multiple first wiring vias 131 and at least one of the multiple first wiring layers 121, 121a, 121b. Thus, they can be electrically connected to at least one of the multiple semiconductor chips 181, 182, 183.

[0031] Figure 3 is a schematic process diagram illustrating an example of the manufacturing process for the printed circuit board shown in Figure 2.

[0032] First, a carrier 210 can be prepared. The carrier 210 may be made of, for example, glass, but is not limited to this. A second glass layer 152 can be attached to the carrier 210. A first wiring layer 121b can be formed on the second glass layer 152. The first wiring layer 121b can be formed using high-resolution dry patterning (HRDP) technology. The process can be carried out symmetrically on the upper and lower sides of the carrier 210.

[0033] Next, multiple first insulating layers 111, 111a, the remaining multiple first wiring layers 121, 121a, 121b, and multiple first wiring vias 131 can be formed on the second glass layer 152. For example, a multilayer coreless substrate structure can be formed in the build-up process. The first glass layer 151 can be attached to the uppermost first insulating layer 111a. The process can be carried out symmetrically on the upper and lower sides with respect to the carrier 210.

[0034] Next, the carrier 210 can be detached. After detachment, the second and third wiring layers 122, 123 and the second and third wiring vias 132, 133 can be formed. For example, a first via hole penetrating the first glass layer 151 and the outermost first insulating layer 111a, and a second via hole penetrating the second glass layer 152 can be formed, a seed layer can be formed by sputtering or electroless plating, and electroplating can be performed to form the second and third wiring layers 122, 123 and the second and third wiring vias 132, 133.

[0035] Next, first and second solder resist layers 161 and 162 can be formed on the first and second glass layers 151 and 152, respectively. The first and second solder resist layers 161 and 162 can be formed by coating a liquid-type material and then curing it, or by laminating a film-type material and then curing it. In addition, multiple first and second openings h1 and h2 can be formed in the first and second solder resist layers 161 and 162, respectively. The multiple first and second openings h1 and h2 can be formed by a photolithography process, respectively. Subsequently, multiple semiconductor chips can be mounted using multiple electrically coupled metals as needed.

[0036] Through a series of processes, the printed circuit board 100A according to the example described above can be manufactured. Other details may be substantially the same as those described above.

[0037] Figure 4 is a schematic cross-sectional view showing another example of a printed circuit board.

[0038] Referring to the drawings, another example of a printed circuit board 100B may further include a second insulating layer 112 positioned between the second glass layer 152 and the third wiring layer 123 in the printed circuit board 100A described above. In this case, the third wiring via 133 can further penetrate the second insulating layer 112. For example, the second insulating layer 112 can penetrate both the second glass layer 152 and the second insulating layer 112 simultaneously. On the other hand, by introducing the second insulating layer 112, the adhesion and process reliability of the third wiring layer 123 can be improved.

[0039] The second insulating layer 112 may include an organic insulating material. The organic insulating material may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material containing an inorganic filler and / or organic filler together with the resin. For example, the second insulating layer 112 may include, but is not limited to, a non-photosensitive insulating material such as ABF (Ajinomoto Build-up Film) or a photosensitive insulating material such as PID (Photo Imageable Dielectric).

[0040] Other explanations may be substantially the same as those described for printed circuit board 100A in the example described above.

[0041] Figure 5 is a schematic process diagram showing an example of the manufacturing process of the printed circuit board shown in Figure 4.

[0042] First, a carrier 210 can be prepared. The carrier 210 may be, for example, a glass carrier or a copper foil laminate carrier, but is not limited to these. A second glass layer 152 can be attached to the carrier 210 via a second insulating layer 112. This allows for more stable attachment of the second glass layer 152, thereby improving process reliability in subsequent processes. A first wiring layer 121b can be formed on the second glass layer 152. The first wiring layer 121b can be formed using high-resolution dry patterning (HRDP) technology. The process can be carried out symmetrically on the upper and lower sides of the carrier 210.

[0043] Next, multiple first insulating layers 111, 111a, the remaining multiple first wiring layers 121, 121a, 121b, and multiple first wiring vias 131 can be formed on the second glass layer 152. For example, a multilayer coreless substrate structure can be formed in the build-up process. The first glass layer 151 can be attached to the uppermost first insulating layer 111a. The process can be carried out symmetrically on the upper and lower sides with respect to the carrier 210.

[0044] Next, the carrier 210 can be detached. After detachment, the second and third wiring layers 122, 123 and the second and third wiring vias 132, 133 can be formed. For example, a first via hole can be formed that penetrates the first glass layer 151 and the outermost first insulating layer 111a, and a second via hole can be formed that penetrates the second glass layer 152 and the second insulating layer 112. A seed layer can be formed by sputtering or electroless plating, and electroplating can be performed to form the second and third wiring layers 122, 123 and the second and third wiring vias 132, 133.

[0045] Next, first and second solder resist layers 161 and 162 can be formed on the first glass layer 151 and the second insulating layer 112, respectively. The first and second solder resist layers 161 and 162 can be formed by applying a liquid-type material and then curing it, or by laminating a film-type material and then curing it. In addition, multiple first and second openings h1 and h2 can be formed in the first and second solder resist layers 161 and 162, respectively. The multiple first and second openings h1 and h2 can each be formed by a photolithography process. Subsequently, if necessary, multiple semiconductor chips can be mounted using multiple electrically coupled metals.

[0046] Through a series of processes, a printed circuit board 100B relating to the other example described above can be manufactured. Other details may be substantially the same as those described above.

[0047] Figure 6 is a schematic cross-sectional view showing yet another example of a printed circuit board, and Figure 7 is a schematic cross-sectional view showing yet another example of a printed circuit board.

[0048] Referring to the drawings, the printed circuit boards 100C and 100D according to yet another example may further include, in the printed circuit boards 100A and 100B according to the first example and the other example described above, a plurality of third insulating layers 113 disposed above the first glass layer 151, a plurality of fourth wiring layers 124 disposed on each of the plurality of third insulating layers 113, and a plurality of fourth wiring vias 134 that penetrate one or more of the plurality of third insulating layers 113, connect the plurality of fourth wiring layers 124 to each other, and connect the lowest fourth wiring layer 124 to the second wiring layer 122 to each other. For example, in the printed circuit boards 100C and 100D according to yet another example, a fine wiring layer may be further formed above the first glass layer 151. In this case, the first solder resist layer 161 may be disposed above the plurality of third insulating layers 113, and the plurality of first openings h1 may each expose at least a portion of the uppermost fourth wiring layer 124.

[0049] Each of the multiple third insulating layers 113 may contain an inorganic insulating material. The inorganic insulating material may be, for example, silicon oxide or silicon nitride. However, it is not limited to these, and other inorganic insulating materials used as materials for inorganic insulating films in semiconductor processes can also be used. For example, each of the multiple third insulating layers 113 may contain, but is not limited to, silicon dioxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), boron nitride (BN), and / or silicon carbide (SiC). The multiple third insulating layers 113 can be separated by boundaries, or they can be integrated without boundaries. When integrated, the interlayer boundaries of the multiple third insulating layers 113 can be roughly predicted based on the lower surfaces of each of the multiple wiring layers 124. Each of the multiple third insulating layers 113 may be thinner than each of the multiple first insulating layers 111, 111a and the first and second glass layers 151, 152. Therefore, this may be more advantageous in the formation of fine wiring layers.

[0050] Each of the multiple fourth wiring layers 124 may contain a metal. The metals may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Each of the multiple fourth wiring layers 124 can perform various functions depending on the design. For example, they may include signal patterns, power patterns, ground patterns, etc. These patterns may each have various forms such as lines, planes, pads, and lands. Each of the multiple fourth wiring layers 124 may include a sputtered layer (e.g., sputtered titanium / copper) as a seed layer and an electroplated layer (e.g., electroplated copper) as a pattern layer. However, it is not limited to this, and an electroless plating layer (e.g., chemical copper) may also be included as a seed layer. Alternatively, both a sputtered layer and an electroless plating layer may be included as seed layers. Each of the multiple fourth wiring layers 124 may be thinner than at least one of the multiple first wiring layers 121, 121a, and 121b, preferably the remaining first wiring layers 121 excluding the uppermost and lowermost layers. This may be advantageous for forming fine wiring layers. For example, each of the multiple fourth wiring layers 124 may have a thickness of 1 μm or less, and each may have a line / space ratio of 3 μm / 3 μm or less, but is not limited thereto.

[0051] Each of the multiple fourth wiring vias 134 may contain a metal. The metals may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Each of the multiple fourth wiring vias 134 may contain a filled via that fills a via hole, or a conformal via that is positioned along the wall of the via hole. Each of the multiple fourth wiring vias 134 can perform various functions depending on the design. For example, they may include ground vias, power vias, signal vias, etc. Each of the multiple fourth wiring vias 134 may contain a sputtered layer (e.g., sputtered titanium / copper) as a seed layer and an electroplated layer (e.g., electroplated copper) as a pattern layer. However, it is not limited to this, and an electroless plating layer (e.g., chemical copper) may also be included as a seed layer. Alternatively, both a sputtered layer and an electroless plating layer may be included as seed layers. Each of the multiple fourth wiring vias 134 may have a smaller diameter than each of the multiple first wiring vias 131. This may be advantageous for forming a fine wiring layer. Each of the multiple fourth wiring vias 134 may have a tapered shape in substantially the same direction as the multiple first wiring vias 131 and second wiring vias 132, and a tapered shape in substantially the opposite direction to the third wiring via 133.

[0052] On the other hand, the multiple first insulating layers 111, 111a may be a first insulating body, the multiple first wiring layers 121, 121a, 121b may be multiple inner wiring layers, and the multiple first wiring vias 131 and the second and third wiring vias 132, 133 may be multiple inner wiring vias. Such a first insulating body, multiple inner wiring layers, multiple inner wiring vias, and first and second glass layers 151, 152 can constitute a first substrate portion. Furthermore, the multiple third insulating layers 113 may be a second insulating body, the multiple fourth wiring layers 124 may be multiple first outer wiring layers, and the multiple fourth wiring vias 134 may be multiple first outer wiring vias. Such a second insulating body, multiple first outer wiring layers, and multiple first outer wiring vias can constitute a second substrate portion. Also, the third wiring layer 123 may be a third outer wiring layer. From this viewpoint, the first insulating body of the first substrate portion may be a coreless structure composed of multiple build-up layers. Furthermore, at least one of the multiple first outer wiring layers of the second substrate portion may contain wiring with a relatively higher density than at least one of the multiple inner wiring layers of the first substrate portion. In addition, the first insulating body of the first substrate portion may include one or more non-photosensitive organic insulating materials and photosensitive organic insulating materials, and the second insulating body of the second substrate portion may include one or more silicon oxide films and silicon nitride films.

[0053] Other explanations may be substantially the same as those described for printed circuit boards 100A and 100B relating to the above example and other examples.

[0054] In this invention, thickness, width, length, pitch, depth, diameter, etc., can be measured using a scanning microscope or optical microscope based on a cross-section obtained by polishing or cutting the printed circuit board. The cut cross-section can be a vertical or horizontal cross-section, and each value can be measured based on the required cut cross-section. If the values ​​are not constant, the values ​​can be determined by the average value of the values ​​measured at any five points. The width of the upper and / or lower ends of the via can be measured on a cross-section obtained by cutting the substrate through the central axis of the via in the thickness direction. The depth of the via can be measured as the distance from the upper end to the lower end of the via on a cross-section obtained by cutting the substrate through the central axis of the via in the thickness direction.

[0055] In this invention, the expression "cover" can include not only cases of covering the entire surface but also cases of covering at least a part of it, and can include cases of covering not only directly but also indirectly. Furthermore, the expression "fill" can include not only cases of completely filling but also cases of generally filling, and can include cases where, for example, some voids or air pockets exist.

[0056] In this invention, "substantially" can be determined to include process errors, positional deviations, and measurement errors that occur during the manufacturing process. For example, "substantially the same line width, spacing, thickness, height, etc." can include not only cases where the numerical values ​​are exactly the same, but also cases where they are approximately similar. Furthermore, "substantially having a certain shape" can include not only cases where the shape is exactly the same, but also cases where it is approximately the same. In addition, "substantially coplane" can include not only cases where they are exactly on the same plane, but also cases where they are approximately on the same plane.

[0057] In this invention, "substantially identical materials" may mean not only completely identical materials, but also materials of the same type. For example, the composition of the materials may be substantially the same, but their specific compositional ratios may differ slightly.

[0058] In this invention, "on a cross-section" can mean the cross-sectional shape when the object is cut vertically, or the cross-sectional shape when the object is viewed from the side. Furthermore, "on a plane" can mean the planar shape when the object is cut horizontally, or the planar shape when the object is viewed from the top or bottom.

[0059] In this invention, terms such as "lower side," "lower part," and "bottom surface" are used for convenience to mean the downward direction relative to the cross-section in the drawing, while terms such as "upper side," "upper part," and "top surface" are used to mean the opposite direction. Furthermore, terms such as "side" and "side" are used to mean the direction perpendicular to the top and bottom surfaces. However, these definitions of direction are for illustrative purposes only, and the scope of rights in the patent claims is not specifically limited by such descriptions of direction; the concepts of "up" and "down" can change at any time.

[0060] In this invention, "connected" is a concept that includes not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, "electrically connected" is a concept that includes both cases where they are physically connected and cases where they are not connected. In addition, expressions such as "first," "second," etc., are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, within the scope of the rights, the first component may be named the second component, and similarly, the second component may be named the first component.

[0061] The expression "example" as used in this invention does not mean that each embodiment is the same as another, but is provided to highlight and illustrate the unique and distinct features of each. However, the examples presented above do not preclude their realization in combination with features of other examples. For example, even if a matter described in a particular example is not described in another example, it can be understood as a description related to that other example, unless there is a contradictory or contrary description of that matter in the other example.

[0062] The terms used in this invention are used merely to illustrate an example and are not intended to limit the invention. In this context, singular expressions include plural expressions unless the context clearly indicates a different meaning. [Explanation of Symbols]

[0063] 1000:Electronic equipment 1010: Mainboard 1020: Chip-related components 1030: Network-related components 1040: Other parts 1050: Camera 1060: Antenna 1070: Display 1080: Battery 1090: Signal line 100A, 100B, 100C, 100D: Printed circuit board 111, 111a, 112, 113: Insulating layer 121, 121a, 121b, 122, 123, 124: Wiring layer 131, 132, 133, 134: Wiring vias 151, 152: Glass layer 161, 162: Solder resist layer 171, 172, 173: Electrically connected metals 181, 182, 183: Semiconductor chips 210: Career

Claims

1. Multiple first insulating layers, A plurality of first wiring layers, each disposed within the plurality of first insulating layers, A first glass layer is disposed above the plurality of first insulating layers and is thinner than at least one of the plurality of first insulating layers, A second glass layer is disposed below the plurality of first insulating layers and is thinner than at least one of the plurality of first insulating layers, A second wiring layer is positioned above the first glass layer, A printed circuit board including a third wiring layer disposed below the second glass layer.

2. A plurality of first wiring vias that penetrate one or more of the plurality of first insulating layers and connect the plurality of first wiring layers to each other, A second wiring via penetrates the uppermost of the plurality of first insulating layers and the first glass layer, and connects the uppermost of the plurality of first wiring layers and the second wiring layer to each other. The printed circuit board according to claim 1, further comprising a third wiring via that penetrates the second glass layer and connects the third wiring layer to the lowest of the plurality of first wiring layers.

3. The printed circuit board according to claim 2, wherein each of the plurality of first wiring vias has a tapered shape in substantially the same direction as the second wiring via and a tapered shape in substantially the opposite direction to the third wiring via.

4. The material further includes a second insulating layer disposed between the second glass layer and the third wiring layer, The printed circuit board according to claim 2, wherein the third wiring via further penetrates the second insulating layer.

5. The printed circuit board according to claim 1, wherein the second wiring layer, the third wiring layer, and the first wiring layers located at the uppermost and lowermost ends of the plurality of first wiring layers are each thinner than at least one of the remaining first wiring layers.

6. A first solder resist layer is disposed above the first glass layer and has a plurality of first openings that each expose at least a portion of the second wiring layer, The printed circuit board according to claim 1, further comprising: a second solder resist layer disposed below the second glass layer and having a plurality of second openings that each expose at least a portion of the third wiring layer.

7. A plurality of third insulating layers are arranged above the first glass layer, The present invention further includes a plurality of fourth wiring layers, each of which is disposed on the plurality of third insulating layers, The printed circuit board according to claim 1, wherein each of the plurality of third insulating layers is thinner than each of the plurality of first insulating layers, the first glass layer, and the second glass layer.

8. Each of the aforementioned plurality of first insulating layers contains an organic insulating material. The printed circuit board according to claim 7, wherein each of the plurality of third insulating layers contains an inorganic insulating material.

9. The printed circuit board according to claim 7, wherein each of the plurality of fourth wiring layers is thinner than each of the remaining first wiring layers, excluding the uppermost and lowermost first wiring layers among the plurality of first wiring layers.

10. The printed circuit board according to claim 7, further comprising a plurality of fourth wiring vias that each penetrate one or more of the plurality of third insulating layers, connect the plurality of fourth wiring layers to each other, and connect the lowest fourth wiring layer among the plurality of fourth wiring layers to the second wiring layer.

11. A first solder resist layer having a plurality of first openings, which are arranged above the plurality of third insulating layers and expose at least a portion of the uppermost of the plurality of fourth wiring layers, The printed circuit board according to claim 7, further comprising: a second solder resist layer disposed below the second glass layer and having a plurality of second openings that each expose at least a portion of the third wiring layer.

12. A first substrate portion including a first insulating body, a first glass layer disposed on the upper surface of the first insulating body, a second glass layer disposed on the lower surface of the first insulating body, and a plurality of inner wiring layers disposed within the first insulating body, The invention includes a second insulating body disposed on the upper surface of the first glass layer, and a second substrate portion including a plurality of first outer wiring layers disposed on or within the second insulating body, A printed circuit board in which, among the plurality of first outer wiring layers, the insulation distance between any two first outer wiring layers adjacent to each other in the thickness direction is smaller than the insulation distance between any two inner wiring layers adjacent to each other in the thickness direction among the plurality of inner wiring layers.

13. The printed circuit board according to claim 12, wherein at least one of the plurality of first outer wiring layers includes wiring that is relatively denser than at least one of the plurality of inner wiring layers.

14. The printed circuit board according to claim 12, wherein the first insulating body has a coreless structure composed of a plurality of build-up layers.

15. The first insulating body includes one or more non-photosensitive organic insulating materials and photosensitive organic insulating materials. The printed circuit board according to claim 12, wherein the second insulating body includes one or more silicon oxide films and silicon nitride films.

16. The printed circuit board according to claim 12, further comprising a second outer wiring layer disposed on the lower surface of the second glass layer.

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