Dynamic On-Resistance Measurement Circuit

Abstract

A dynamic on-resistance measurement circuit is provided. [Solution] In the dynamic on-resistance measurement circuit 1000, the control circuit 200 is arranged to perform the following in this order: in the initial stress relief process, open only the second switch S2 to release the residual stress voltage of the transistor DUT to be measured along the second switch S2 and simultaneously store a common voltage in the energy storage circuit 100; in the stress voltage application process, close the second switch S2 and open the third and first switches S3 and S1 to apply a stress voltage to the transistor to be measured; and in the measurement process, close the first and third switches S1 and S3 and open the transistor to be measured and the second switch S2 so that a constant current flows to the transistor to be measured via the second switch S2 and inductance L to measure the voltage and current of the transistor to be measured, and calculate the dynamic on-resistance of the transistor to be measured based on the results.

Description

[Technical Field]

[0001] The present invention relates to dynamic on-resistance, and in particular, to a dynamic on-resistance measurement circuit. [Background Art]

[0002] Group III-V field-effect transistors (III-V FETs), such as gallium nitride (GaN) transistors, aluminum nitride (AlN) transistors and aluminum gallium nitride (AlGaN) transistors, have fast switching speed, low on-resistance and excellent transconductance characteristics, so they are widely applied in the field of power electronics including renewable energy power conversion, data center power supplies, consumer electronics, electric vehicles and the like. Compared with conventional silicon (Si) devices, III-V FETs can provide higher power density and conversion efficiency. However, the dynamic on-resistance of III-V FETs (sometimes denoted as Rds,on) varies with time and bias voltage conditions. Accurate measurement of dynamic on-resistance is of great significance for power efficiency and thermal design.

[0003] Conventionally, the dynamic on-resistance characteristics of III-V FETs are usually estimated by a time-constant model, and model parameters are extracted via a double pulse test (DPT) circuit. In DPT, the first pulse usually turns the device under test into a conducting state to simulate the behavior of an actually operating switch, and the second pulse performs key measurement for evaluating dynamic on-resistance. The prior art has a plurality of problems including that the off-blocking time cannot be controlled, measurement parameters cannot be adjusted independently, and inaccurate model parameters are caused by measurement being performed during the second current rising process.

[0004] Furthermore, commercial measurement equipment typically cannot simulate actual hard-switching conditions, and measurement results are susceptible to voltage and load influences. While sensitivity can be improved and current control can be added by modifying the measurement process, it can still be affected by coupled voltage / current, or the complexity and delay of the measurement may increase due to the need for additional components. Consequently, conventional technology lacks a method to accurately and controllably measure the dynamic on-resistance of III-V compound semiconductor field-effect transistors under actual hard-switching conditions, limiting the evaluation of power conversion efficiency and reliability. [Overview of the project] [Means for solving the problem]

[0005] To improve upon the aforementioned conventional technical shortcomings, the present invention provides a dynamic on-resistance measurement circuit suitable for measuring a transistor under test. The dynamic on-resistance measurement circuit of the present invention includes a plurality of switching elements, an energy storage circuit, and a control circuit. The energy storage circuit is connected between a first discharge node and a second discharge node while being connected to a shared power supply. The first end of the first switch is connected to the first discharge node, and the first end of the third switch is connected to the second discharge node. The second end of the first switch is connected to the first end of the second switch and the first end of the inductance. The first end of the transistor under test is connected to the second end of the third switch and the second end of the inductance. The second end of the second switch and the second end of the transistor under test are connected to a reference potential terminal. The control circuit is connected to the control terminal of each switching element. The control circuit is configured to perform the following steps in this order: in the initial stress relief process, open only the second switch to release the residual stress voltage of the transistor under test along the second switch; in the stress voltage application process, close the second switch and open the third switch and the first switch to apply the stress voltage to the first and second ends of the transistor under test; and in the measurement process, close the first and third switches and open the transistor under test and the second switch to measure the voltage and current between the first and second ends of the transistor under test, and calculate the dynamic on-resistance of the transistor under test based on the results.

[0006] In this embodiment, during the measurement process, the current is maintained at the stress current value to form a constant current.

[0007] In the embodiment, the control circuit is further configured to perform a stress voltage preparation process, which involves opening a third switch in advance, before performing the stress voltage application process after the initial stress relief process.

[0008] In the embodiment, the control circuit is further configured to perform a first discharge process after the measurement process, which involves closing the transistor under test, opening a third switch, and reducing the current.

[0009] In the embodiment, the control circuit is further configured to perform a second emission process, which involves performing the first emission process and then opening the transistor under test to reduce the current to zero.

[0010] In this embodiment, the energy storage circuit includes an energy storage capacitor. The energy storage capacitor is connected between the first end of the first switch and the first end of the third switch and is connected to a shared power supply.

[0011] In embodiments, the dynamic on-resistance measuring circuit of the present invention further includes an input power supply circuit. The input power supply circuit is arranged to supply an input voltage to the first end of a coupled third switch.

[0012] In this embodiment, the input power supply circuit includes an input capacitor and an input power supply. The first end of the input capacitor is connected to the first end of a third switch. The second end of the input capacitor is connected to the second end of the transistor under test and the second end of the second switch. The input power supply is connected to the input capacitor. The input power supply is configured to supply and store input power to the input capacitor and then discharge it through the input capacitor to the first end of the third switch.

[0013] In this embodiment, the transistor under test is a III-V compound semiconductor field-effect transistor.

[0014] In the embodiment, the transistor under test is a gallium nitride transistor, an aluminum nitride transistor, or an aluminum gallium nitride transistor.

[0015] Furthermore, the present invention provides a dynamic on-resistance measurement circuit suitable for measuring a transistor under test. The dynamic on-resistance measurement circuit of the present invention includes a plurality of switching elements, an energy storage circuit, and a control circuit. The energy storage circuit is connected to a shared power supply and is connected between a first discharge node and a second discharge node. The first end of the first switch is connected to the first discharge node, and the first end of the third switch is connected to the second discharge node. The second end of the first switch is connected to the first end of the second switch and the first end of the inductance. The first end of the transistor under test is connected to the second end of the third switch and the second end of the inductance. The second end of the second switch and the second end of the transistor under test are connected to a reference potential terminal. The control circuit is connected to the control terminal of each switching element. The control circuit is configured to perform the following steps in this order: in the stress voltage application process, open the third switch and the first switch to apply a stress voltage to the first and second terminals of the transistor under test; in the measurement process, close the third switch and the first switch, open the transistor under test and the second switch, allow current to flow through the second switch and inductance to the transistor under test, measure the voltage and current between the first and second terminals of the transistor under test, and calculate the dynamic on-resistance of the transistor under test based on the results; and in the discharge process, leave the second switch open, open the third switch, close the transistor under test, allow current to flow through the third switch, inductance and the transistor under test to the reference potential terminal for discharge.

[0016] In this embodiment, each time a continuous measurement operation is performed, the duration of the release process is shorter than the duration of the measurement process.

[0017] In this embodiment, each time a continuous measurement operation is performed, the duration of the release process is shorter than the duration of the stress voltage application process.

[0018] In this embodiment, the control circuit is configured to perform, in order each time a continuous measurement operation is performed, a stress voltage application process, a measurement process, and a release process, to obtain multiple dynamic on-resistances after performing the continuous measurement operation over multiple cycles, and to calculate the amount of change in dynamic on-resistance when a stress voltage is continuously applied to the transistor under test, based on the multiple dynamic on-resistances. [Brief explanation of the drawing]

[0019] [Figure 1] Circuit diagram of a dynamic on-resistance measurement circuit according to the first embodiment of the present invention. [Figure 2] Circuit diagram of a dynamic on-resistance measurement circuit according to a second embodiment of the present invention. [Figure 3] A flowchart illustrating the multi-stage process of a single measurement operation performed by a dynamic on-resistance measurement circuit according to the first and second embodiments of the present invention. [Figure 4] A flowchart of the specific steps in a multi-stage process of a single measurement operation performed by a dynamic on-resistance measurement circuit according to the first and second embodiments of the present invention. [Figure 5] A schematic diagram illustrating the switching of multiple switching elements in a dynamic on-resistance measurement circuit according to a second embodiment of the present invention. [Figure 6] A schematic diagram illustrating the switching of multiple switching elements in a dynamic on-resistance measurement circuit according to a second embodiment of the present invention. [Figure 7] A schematic diagram illustrating the switching of multiple switching elements in a dynamic on-resistance measurement circuit according to a second embodiment of the present invention. [Figure 8] A schematic diagram illustrating the switching of multiple switching elements in a dynamic on-resistance measurement circuit according to a second embodiment of the present invention. [Figure 9] Waveform diagrams of multiple signals from a dynamic on-resistance measurement circuit according to the first and second embodiments of the present invention. [Figure 10] A flowchart illustrating the multi-stage process of continuous measurement work performed by the dynamic on-resistance measurement circuit according to the first and second embodiments of the present invention. [Figure 11]Flowchart of specific steps in the multi-stage process of continuous measurement work performed by the dynamic on-resistance measurement circuit according to the first embodiment and the second embodiment of the present invention. [Figure 12] Schematic diagram of switching a plurality of switching elements of the dynamic on-resistance measurement circuit according to the second embodiment of the present invention. [Figure 13] Schematic diagram of switching a plurality of switching elements of the dynamic on-resistance measurement circuit according to the second embodiment of the present invention. [Figure 14] Waveform diagram of a plurality of signals of the dynamic on-resistance measurement circuit according to the second embodiment of the present invention. Description of Embodiments

[0020] For a better understanding of the features and technical content of the present invention, please refer to the following detailed description of the present invention and the accompanying drawings. However, the provided drawings are merely for reference and description, and are not intended to limit the present invention.

[0021] Hereinafter, the implementation modes of the present invention are described by specific embodiments, and those skilled in the art can understand the advantages and effects of the present invention based on the content disclosed in the present specification. The present invention can be implemented or applied by other different specific embodiments, and various modifications and changes can be made to each detail in the present specification based on different viewpoints and applications without departing from the concept of the present invention. In addition, it should be noted in advance that the accompanying drawings of the present invention are simple schematic descriptions, and are not drawn based on actual sizes. The following implementation modes further describe the technical content of the present invention in more detail, but the disclosed content does not limit the scope of protection of the present invention. In addition, as used herein, the term "or" may include any one or a combination of more of the related listed items according to actual circumstances.

[0022] Referring to FIG. 1, there is shown a circuit diagram of the dynamic on-resistance measurement circuit according to the first embodiment of the present invention.

[0023] The present invention provides a dynamic on-resistance measurement circuit 1000 suitable for measuring the dynamic on-resistance of a transistor DUT under test, and is particularly suitable for field-effect transistors made of III-V materials (e.g., gallium nitride transistors, aluminum nitride transistors, or aluminum gallium nitride transistors, but not limited to these). III-V compound semiconductor field-effect transistors have high-speed switching characteristics and low on-resistance characteristics, and their dynamic on-resistance changes with time and bias voltage conditions. Conventional measurement methods have made it difficult to accurately capture these characteristics under actual operating conditions. Therefore, the dynamic on-resistance measurement circuit 1000 provided by the present invention employs a groundbreaking arrangement of circuit components and measurement method to precisely measure the dynamic on-resistance of a transistor DUT under test made of various materials, such as III-V compound semiconductor field-effect transistors. By accurately obtaining the dynamic on-characteristics of III-V compound semiconductor field-effect transistors, it is possible to satisfy the requirements for high-efficiency power conversion and reliability.

[0024] To achieve the above objectives, the dynamic on-resistance measurement circuit 1000 of the present invention is arranged together with the transistor DUT under test, that is, connected to the first terminal, second terminal, and control terminal of the transistor DUT under test. In particular, the dynamic on-resistance measurement circuit 1000 of the present invention comprises a plurality of switching elements that can be controlled to be on and off (including a first switch S1, a second switch S2, and a third switch S3 as shown in Figure 1), and these switching elements and the transistor DUT under test form a symmetrical bridge structure (e.g., an H-bridge circuit configuration). This structure allows for flexible switching of the current direction and voltage path during a further multi-stage process to apply stress to the transistor DUT under test, simulate the stress it would experience in actual application, and then accurately measure the dynamic on-resistance of the transistor DUT under test.

[0025] For example, the first switch S1, the second switch S2, and the third switch S3 may be transistors or other types of switching elements, and the transistor under test DUT may be an N-channel enhancement-mode MOSFET as shown in Figure 1, or in practice, it may be replaced with other types of transistors. If the transistor is a field-effect transistor, the first terminal, second terminal, and control terminal described in this text are the drain, source, and gate, respectively.

[0026] The first end of the first switch S1 is connected to the first discharge node.

[0027] The second end of the first switch S1 is connected to the first end of the second switch S2. The first node between the second end of the first switch S1 and the first end of the second switch S2 is connected to the first end of the inductance L.

[0028] The first end of the third switch S3 is connected to the second discharge node.

[0029] The second end of the third switch S3 is connected to the first end of the transistor DUT under test. The second node between the second end of the third switch S3 and the first end of the transistor DUT under test is connected to the second end of the inductance L.

[0030] The second terminal of the second switch S2 and the second terminal of the transistor under test DUT are connected to a reference potential terminal. The dynamic on-resistance measurement circuit 1000 of the present invention may optionally include an input power supply circuit 300, the first terminal of which may be connected to the first terminal of the third switch S3, and the second terminal (e.g., the negative terminal) may be connected to this reference potential terminal.

[0031] To provide a controllable stress current and precisely measure the dynamic on-resistance of a transistor DUT under test while it is subjected to a predetermined stress, the dynamic on-resistance measurement circuit 100 of the present invention further includes an energy storage circuit 100 connected between a first discharge node and a second discharge node, while being connected to a shared power supply VCC. This avoids direct reliance on the shared power supply VCC. Simply providing a shared power supply VCC does not allow for the instantaneous supply of a large current. Compared to the shared power supply VCC, the energy storage circuit 100 can instantaneously provide a large current to apply stress. When the energy storage circuit 100 discharges, it forms a single discharge loop that gradually increases to a specified stress current value, controlling the rate at which the stress voltage applied to the transistor DUT under test rises (including controlling it to be a smooth rise to avoid spikes).

[0032] The dynamic on-resistance measurement circuit 1000 of the present invention may further include a control circuit 200 arranged to control the conduction state of a plurality of switching elements (including a first switch S1, a second switch S2, and a third switch S3 as shown in Figure 1). The control circuit 200 is connected to the control terminal of each switching element and the transistor under test DUT. In practice, the control circuit 200 described herein may be replaced with an external control circuit.

[0033] The control circuit 200 controls the progress of each switching element and the transistor DUT under test by switching between the on and off states, and further applies a stress voltage to the first terminal (e.g., drain) and the second terminal (e.g., source) of the transistor DUT under test.

[0034] Under conditions where the transistor DUT under test is subjected to a predetermined stress, the dynamic on-resistance measurement circuit 1000 of the present invention can precisely measure the dynamic on-resistance of the transistor DUT under test (e.g., a III-V compound semiconductor field-effect transistor), and furthermore, it can reflect the conduction characteristics in the environment in which the transistor DUT under test actually operates. In this way, it is possible to capture the instantaneous on-resistance of the transistor DUT under test, which changes with time and bias voltage, and also to provide reliable evaluation of power loss, efficiency analysis, and device lifetime, thereby meeting the requirements for high-efficiency power conversion and reliability.

[0035] Referring to Figure 2, a circuit diagram of a dynamic on-resistance measurement circuit according to a second embodiment of the present invention is shown. The common parts between the second embodiment and the first embodiment of the present invention will not be described in this text.

[0036] In the second embodiment, for example, the energy storage circuit 100 may include an energy storage capacitor Cst. In practice, the capacitor can be expanded and installed in the energy storage circuit 100, or replaced with other energy storage elements having the same function, which may be connected in series with the energy storage capacitor Cst, or replaced with other circuit components, or other circuit components may be installed separately.

[0037] The energy storage capacitor Cst is connected in parallel to the shared power supply VCC. The energy storage capacitor Cst is connected between the first terminal of the first switch S1 and the first terminal of the third switch S3, that is, between the first discharge node and the second discharge node.

[0038] The first end of the energy storage capacitor Cst is connected to the first end (e.g., the positive terminal) of the shared power supply VCC and is connected to the first end of the first switch S1 via a first discharge node. The second end of the energy storage capacitor Cst is connected to the second end (e.g., the negative terminal) of the shared power supply VCC and is connected to the second end of the third switch S3 via a second discharge node.

[0039] In the dynamic on-resistance measurement circuit 1000 of the present invention, the energy storage capacitor Cst is arranged together with the common power supply VCC, and its main function is the same as that of the energy storage circuit 100 described above, providing an instantaneous large current to form a controllable discharge loop, thereby smoothly increasing the stress current applied to the transistor DUT under test to a predetermined value.

[0040] In addition to arranging the energy storage capacitor Cst and the shared power supply VCC, the input power supply circuit 300 further installed in the dynamic on-resistance measurement circuit 1000 of the present invention may include an input capacitor Cin and an input power supply VIN. The first terminal of the input capacitor Cin is connected to the first terminal of the third switch S3. The second terminal of the input capacitor Cin is connected to the second terminal of the transistor under test DUT and the second terminal of the second switch S2.

[0041] The input power supply VIN is connected in parallel to the input capacitor Cin. The first terminal of the input power supply VIN (e.g., the positive terminal) is connected to the first terminal of the input capacitor Cin. The second terminal of the input power supply VIN (e.g., the negative terminal) is connected to the second terminal of the input capacitor Cin. The input power supply VIN provides input current to the input capacitor Cin, charges the input capacitor Cin until it has the input voltage, and discharges through the input capacitor Cin to supply the input voltage to the first terminal of the third switch S3.

[0042] In the dynamic on-resistance measurement circuit 1000 of the present invention, the input capacitor Cin and the input power supply VIN may be arranged in different combinations, and their main functions are to supplement and harmonize the circuit's bias voltage and voltage stabilization function. Specifically, the input capacitor Cin maintains a stable voltage at the measurement node between the first terminal of the third switch S3 and the second terminal of the transistor DUT under test, ensuring the accuracy of the stress applied to the transistor DUT under test and the voltage Vds between the measured first terminal (e.g., drain) and second terminal (e.g., source), while buffering instantaneous charge during the switching process to avoid measurement errors due to fluctuations in node voltage. At the same time, the input capacitor Cin and the input power supply VIN also provide a stable voltage to the first terminal of the third switch S3, ensuring conduction when the third switch S3 opens, and forming a precisely controlled stress-current loop.

[0043] By having two sets of capacitors and power supplies each perform different functions, the dynamic on-resistance measurement circuit 1000 of the present invention can simultaneously provide bias voltage stability for the transistor DUT under test, power supply to the positive terminal of the third switch S3, and controllability of the stress current during the measurement process, thereby ensuring accuracy in measuring the dynamic on-resistance of the transistor DUT under test.

[0044] The dynamic on-resistance measurement circuit 1000 shown in Figures 1 and 2 can perform various measurement operations. In this document, two types of measurement operations are given as examples: single-pass measurement operations (sometimes also called single-pulse measurement operations) as shown in Figures 3 to 9, and continuous measurement operations as shown in Figures 10 to 14. A detailed explanation is provided below.

[0045] Referring together to Figures 1 to 9, Figure 3 is a flowchart of the multi-stage process of a single measurement operation performed by the dynamic on-resistance measurement circuit according to the first and second embodiments of the present invention; Figure 4 is a flowchart of the specific steps in the multi-stage process of a single measurement operation performed by the dynamic on-resistance measurement circuit according to the first and second embodiments of the present invention; Figures 5 to 8 are schematic diagrams of switching multiple switching elements of the dynamic on-resistance measurement circuit according to the second embodiment of the present invention; and Figure 9 is a waveform diagram of multiple signals of the dynamic on-resistance measurement circuit according to the first and second embodiments of the present invention.

[0046] The control circuit 200 of the dynamic on-resistance measurement circuit 1000, as shown in Figures 1 and 2, executes the initial stress relief process (step S11 in Figure 3), the stress voltage preparation process (step S12 in Figure 3), the stress voltage application process (step S13 in Figure 3), the measurement process (step S14 in Figure 3), the first release process, and the second release process in this order during a single measurement operation. In practice, the stress voltage preparation process, the first release process, the second release process, or any combination thereof may be selectively omitted.

[0047] The initial stress relief process in step S11 in Figure 2 includes steps S201 to S204 as shown in Figure 3, the stress voltage preparation process in step S12 includes steps S205 and S206 as shown in Figure 3, the stress voltage application process in step S13 includes steps S207 to S210 as shown in Figure 3, and the measurement process includes steps S211 to S215 as shown in Figure 3. Specific technical details are described below.

[0048] In the initial stress relief process (step S11 in Figure 3), the shared power supply VCC (e.g., a voltage source or current source) supplies a shared current or voltage to the energy storage circuit 100 (step S201 in Figure 4) as shown in Figure 5, to store energy (step S202 in Figure 4), and charges the energy storage circuit 100 until it has a shared voltage, preparing it for use in the subsequent stress voltage application process to apply stress.

[0049] To ensure that the transistor DUT under test is in a stable and consistent initial state before measurement, the dynamic on-resistance measurement circuit 1000 of the present invention performs an initial stress removal process (step S11 in Figure 3) before measurement, thereby removing residual voltage stress accumulated in the transistor DUT during the previous operation or measurement process. By removing this residual stress, it is prevented from affecting the voltage distribution and conduction characteristics in subsequent stress application stages, thereby ensuring the accuracy and reproducibility of the measurement results. This reduces the measurement error of dynamic on-resistance due to residual stress, which is particularly important for III-V semiconductor components with high-frequency and high-speed switching characteristics.

[0050] More specifically, in the initial stress relief process (step S11 in Figure 3), the control circuit 200 opens only the second switch S2 (step S203 in Figure 4), as shown in Figure 5, and closes the first switch S1, the third switch S3, and the transistor DUT under test, thereby releasing the residual stress voltage of the transistor DUT under test along the second switch S2 (step S204 in Figure 4). This operation provides a controlled discharge path, allowing control of the voltage release rate and avoiding redistribution of carriers inside the transistor DUT under test due to sudden fluctuations in current.

[0051] As shown in Figure 9, during the initial stress relief process within the initial stress relief time interval T10, the control terminal (e.g., gate) of the second switch S2 opens upon receiving a high-potential control signal VG2 from the control circuit 200, while the control terminals of the third switch S3, the first switch S1, and the transistor under test DUT close upon receiving low-potential control signals VG3, VG1, and VGdut, respectively.

[0052] In the initial stress relief process (step S11 in Figure 3), the control circuit 200 maintains the closed state of the transistor DUT under test to avoid the generation of conduction current when the residual voltage is released, which could interfere with the discharge path or cause redistribution of internal carriers, thereby affecting the electrical stability of the transistor DUT under test. By keeping the transistor DUT under test closed and reducing the voltage Vds of the transistor DUT under test to zero, the residual voltage is completely released through a controlled path. In this way, the initial conditions when the stress voltage is later applied can be stably controlled, and the impact on subsequent measurement results can be avoided. This method improves the measurement reproducibility of the transistor DUT under test, which is particularly important for transistor DUTs made of wide-bandgap materials (e.g., GaN, SiC).

[0053] After performing the initial stress relief process (step S11 in Figure 3), the control circuit 200 then closes the second switch S2 (step S205 in Figure 4), opens the third switch S3 (step S206 in Figure 4), and performs the stress voltage preparation process (step S12 in Figure 3), as shown in Figure 6. In this way, a discharge loop can be directly formed when the third switch S3 is opened in the subsequent stress voltage application process. If the third switch S3 is not opened in advance, there is a possibility that the energy storage circuit 100 and the transistor DUT under test will be electrically disconnected, and a complete discharge loop cannot be immediately formed at the moment stress is applied, which may affect the establishment and application stability of the stress current.

[0054] Therefore, in the stress voltage preparation process, opening the third switch S3 in advance, as shown in Figure 6, can be considered a path preparation operation for the subsequent stress voltage application stage. The energy in the energy storage circuit 100 can then immediately flow through the inductance L and the transistor DUT under test when the first switch S1 is opened in the subsequent stress voltage application process (step S13 in Figure 3), forming a stable discharge path. In this way, measurement errors caused by instantaneous overvoltage or current peaks are avoided, and a stable discharge path is established in the initial stage of stress voltage application, improving the continuity of the discharge loop and the reproducibility of the stress application process. This operation is particularly important for the transistor DUT under test with high-voltage, high-speed switching characteristics, and can reduce instantaneous errors in dynamic on-resistance measurement.

[0055] In other words, opening the third switch S3 during the preparation phase stabilizes the continuity between the energy storage circuit 100 and the discharge loop, establishing a complete discharge path during the subsequent stress voltage application phase. This further improves electrical stability by ensuring that the stored energy is applied to the transistor DUT under test in a smooth and controlled manner, and helps reduce waveform distortion caused by switch delays or incomplete conduction.

[0056] As shown in Figure 9, when the stress voltage preparation process is performed within the stress voltage preparation time interval T11, the control signal VG2 received by the control terminal (e.g., gate) of the second switch S2 switches from a high potential to a low potential, thereby closing the second switch S2. Simultaneously, the control signal VG3 received by the control terminal of the third switch S3 switches from a low potential to a high potential, thereby opening the third switch S3. As a result, the voltage Vds between the first terminal (e.g., drain) and the second terminal (e.g., source) of the transistor under test DUT increases to the stress voltage value upon application of the stress voltage.

[0057] It is important to understand that the stress voltage preparation process can be selectively performed as needed in the actual application. If the discharge path remains stable in the previous operating cycle, or if the connection between the energy storage circuit 100 and the first and second discharge nodes has not been interrupted, the stress voltage preparation process can be omitted to simplify the control process. However, if it is necessary to ensure that the discharge loop is stably formed, or to avoid situations where electricity becomes discontinuous due to the delay of the switching element, performing the stress voltage preparation process can effectively improve the stability and reproducibility of the subsequent stress application stage.

[0058] After completing the stress voltage preparation process (step S12 in Figure 3) as described above, the control circuit 200 then opens the first switch S1 (step S207 in Figure 4) while keeping the third switch S3 open, as shown in Figure 7. This causes the current IL for discharging the energy storage circuit 100 (step S208 in Figure 4) to flow through the first switch S1, the inductance L, and the third switch S3 in that order, forming a discharge loop. As the current IL flowing through the inductance L gradually rises to the desired stress current value (step S209 in Figure 4), the stress voltage is applied to the first end (e.g., drain) and the second end (e.g., source) of the transistor DUT under test (step S210 in Figure 4). This allows the stress voltage application process (step S13 in Figure 3) to be executed.

[0059] As shown in Figure 9, when the stress voltage application process is performed within the stress voltage application time interval T12, the control signal VG3 received by the control terminal of the third switch S3 maintains a high potential, keeping the third switch S3 open. At the same time, the control signal VG1 received by the control terminal of the first switch S1 switches from a low potential to a high potential, opening the first switch S1.

[0060] The primary purpose of applying stress voltage in the stress voltage application process is to simulate the behavior of the transistor DUT under test when its operation is actually interrupted by high voltage. By applying a predetermined stress voltage, a charge trapping effect can be induced inside the transistor DUT under test. In particular, for wide-bandgap semiconductor materials such as GaN and SiC, electrons or holes may be trapped under high voltage Vds in the transistor DUT under test, potentially leading to an increase in dynamic on-resistance. By applying the same stress voltage before measurement, the initial conditions of the transistor DUT under test can be standardized, avoiding the impact of inconsistent conditions on the accuracy and reproducibility of subsequent measurement results.

[0061] After the stress application process is completed, the measurement process (step S14 in Figure 3) is executed. During the measurement process, the control circuit 200 closes the first switch S1 and the third switch S3 (step S211 in Figure 4), as shown in Figure 8, opens the transistor DUT under test and the second switch S2 (step S212 in Figure 4), and forms a closed loop between the transistor DUT under test, the inductance L, and the second switch S2. At this time, the first switch S1 and the third switch S3 switch from a conductive state to a closed state, and the energy storage circuit 100 stops supplying power to the inductance L. At this time, the current IL in the inductance L does not increase any further, and because the characteristics of the inductance L resist instantaneous fluctuations in current, the change in current IL can be smoothed, and as shown in Figure 9, within the measurement time interval T13, this current IL is maintained as a constant current (step S213 in Figure 4) and flows from the inductance L to the transistor DUT under test (step S214 in Figure 4). When a constant current IL flows through the transistor DUT under test, the control circuit 200 measures the voltage Vds between the first terminal (e.g., drain) and the second terminal (e.g., source) of the transistor DUT under test and the value of the constant current IL (step S215 in Figure 4), and calculates the dynamic on-resistance of the transistor DUT under test based on the measured voltage and current IL values.

[0062] Since the current is constant during the process of measuring the dynamic on-resistance of the transistor DUT under test, measurement errors caused by current fluctuations are avoided. By receiving the same carrier flow conditions in the measurement time interval T13 of the transistor DUT under test, the charge trap effect is stabilized, improving the accuracy of measuring the dynamic on-resistance of the transistor DUT under test.

[0063] The main technical feature of the present invention is that the dynamic on-resistance measurement circuit 1000 measures the dynamic on-resistance of the transistor DUT under measurement under the stress applied only once during the single measurement operation described above. The focus is on how the measurement and its preliminary work are performed, and the post-measurement process (e.g., discharge method) can be adapted to the actual needs.

[0064] To make it easier to implement, for example, the operations performed in a single measurement operation of the dynamic on-resistance measurement circuit 1000 may include a first discharge process, a second discharge process, or a combination thereof. After the measurement process, in the first discharge process, the control circuit 200 can reduce the current IL to a low current value by closing the transistor DUT under test and opening the third switch S3, and then perform the second discharge process to open the transistor DUT under test and reduce the current IL to zero.

[0065] Referring to Figures 10 to 14, Figure 10 is a flowchart of the multi-stage process of continuous measurement work performed by the dynamic on-resistance measurement circuit according to the first and second embodiments of the present invention; Figure 11 is a flowchart of the specific steps in the multi-stage process of continuous measurement work performed by the dynamic on-resistance measurement circuit according to the first and second embodiments of the present invention; Figures 12 and 13 are schematic diagrams of switching multiple switching elements of the dynamic on-resistance measurement circuit according to the second embodiment of the present invention; and Figure 14 is a waveform diagram of multiple signals of the dynamic on-resistance measurement circuit according to the second embodiment of the present invention.

[0066] The various operations performed by the dynamic on-resistance measurement circuit 1000 may include continuous measurement operations in addition to the single measurement operations described above. Performing a multi-stage process of continuous measurement operations means that the dynamic on-resistance measurement circuit 1000 in Figure 1 or Figure 2 can perform the stress voltage application process (step S21 in Figure 10), the measurement process (step S22 in Figure 10), and the release process (step S23 in Figure 10) in this order.

[0067] The stress voltage application process in step S21 in Figure 10 includes steps S201, S202, S206 to S210 as shown in Figure 11, the measurement process in step S22 includes steps S211 to S215 as shown in Figure 11, and the release process in step S23 includes steps S401 to S403 as shown in Figure 11. The contents of the same steps have already been explained above, so they will not be described further below.

[0068] It should be noted that while single-pass and continuous-pass measurement operations share the same basic circuit structure and switch operation logic, both control the on / off states of the first switch S1, the second switch S2, and the third switch S3 to create three stages: an increase in the current IL of the inductance L, constant recirculation, and a decrease. However, there are significant differences between single-pass and continuous-pass measurement operations in terms of operation flow and temporal relationships.

[0069] In single-pass measurement mode, performing a single-pass measurement involves only one initial stress relief process, one stress voltage application process, and one measurement (and release) process. Before each measurement, it is necessary to remove residual stress from the transistor DUT under test. By opening the third switch S3 and closing the other switches, the voltage Vds across the transistor DUT under test is reduced to zero, removing any charge traps or parasitic voltages that may have remained from the previous operation, ensuring that each measurement starts from a stress-free initial state. In this way, unexpected stress overlaps can be avoided, and the accuracy of the dynamic on-resistance in a single pulse can be improved.

[0070] Conversely, in continuous measurement, the continuous measurement operation is performed in multiple cycles, and each time the continuous measurement operation is performed, the stress voltage application process, the measurement process, and the release process are executed. Within one operation cycle T123 shown in Figure 14, one continuous measurement operation is performed, the stress voltage application process is performed in the stress voltage application time interval T21, the measurement process is performed in the measurement time interval T22, and the release process is performed in the release time T23.

[0071] Each time a continuous measurement operation is performed, during the discharge process, the transistor DUT under test is closed, the first switch S1 conducts, and the inductance current IL naturally decreases to near zero. When the current IL approaches or reaches zero, the second switch S2 is opened again, and the system proceeds to the stress application stage of the next cycle. This cycle operation automatically restores the current IL and voltage to a low-energy state, so there is no need to separately remove the residual stress of the transistor DUT under test (i.e., steps S203 to S205 in Figure 4 are omitted), and the initial conditions for each measurement are stabilized. When performing the multi-stage process of the continuous measurement operation, similar to the single measurement operation described above, when performing the measurement process of the on-resistance of the transistor DUT under test, the stress current Ids of the transistor DUT under test is maintained at a constant current value within the measurement time interval T22, as shown in Figure 14.

[0072] In other words, the dynamic on-resistance measurement circuit has self-cycling characteristics during continuous measurement operations, eliminating the need for a separate initial stress relief process. This not only maintains the continuity and efficiency of measurements but also simulates the actual operating conditions of power transistors as they rapidly and repeatedly switch. This continuous measurement operation allows for the evaluation of the dynamic on-resistance stability, accumulation effect, and long-term reliability of the transistor DUT under continuous stress.

[0073] In continuous measurement operations, when the release process is to be executed immediately after the measurement process has been completed, the control circuit 200 keeps the second switch S2 open (step S401 in Figure 11), opens the third switch S3, closes the transistor DUT under test (step S402 in Figure 11), and allows the current IL to flow through the third switch S3, inductance L, and the transistor DUT under test to the reference potential terminal (i.e., the input power supply circuit 300 in Figure 1 or the negative terminal of the input power supply VIN in Figure 2) to release energy such as power (step S403 in Figure 11).

[0074] Each time a continuous measurement operation is performed, the control circuit 200 executes the stress voltage application process, the stress voltage measurement process, and the stress voltage release process once in that order, thereby obtaining a single dynamic on-resistance of the transistor DUT under test. By performing the continuous measurement operation multiple times, multiple dynamic on-resistances can be obtained, and based on these, the amount of change in dynamic on-resistance when stress is continuously applied to the transistor DUT under test can be precisely evaluated.

[0075] Single-pass measurements are suitable for observing instantaneous dynamic on-resistance under a single stress, emphasizing consistency and reproducibility of measurement conditions. Continuous measurements can simulate operating environments such as the continuous switching of switching elements in actual circuits, reflecting changes in the conduction characteristics of the transistor under test under repeated stress, thereby improving measurement sensitivity and data stability.

[0076] In short, the present invention provides a dynamic on-resistance measurement circuit that can precisely control the timing and conditions of stress application, release, and measurement to a transistor under test (particularly a III-V compound semiconductor field-effect transistor) through the interaction of multiple switching elements, energy storage circuits, and control circuits. The conduction characteristics of III-V compound semiconductor field-effect transistors are susceptible to surface and interface trap charges, and their dynamic on-resistance changes with bias voltage and time conditions. If precise control is not performed during the measurement process, the trap effect interferes with the measurement results, resulting in unstable or inaccurate results. The dynamic on-resistance measurement circuit of the present invention performs a groundbreaking process through improved hardware circuitry, enabling precise setting and control of the operating conditions at each measurement stage, effectively suppressing the influence of the trap effect on the measurement, and ensuring that the dynamic on-resistance reflects the actual characteristics of the transistor under test.

[0077] The dynamic on-resistance measurement circuit of the present invention releases residual charge accumulated in the transistor under measurement through an initial stress removal process during a single measurement operation. Since each single measurement is performed independently, if residual stress is not removed beforehand, trap charges remaining from the previous operation may interfere with the stress applied in the current measurement and the measurement results, potentially leading to an unstable initial measurement state. The initial stress removal process ensures that the single measurement is performed under stable conditions, improving the accuracy and comparability of the dynamic on-resistance.

[0078] Furthermore, in the dynamic on-resistance measurement circuit of the present invention, the energy storage circuit of the present invention stores the energy provided by the shared power supply and releases it in a controllable manner, providing a stress current sufficient to simulate actual stress conditions. In the measurement process after stress is applied, this stress current is the current that flows to the transistor under test via the inductance, and by maintaining a constant current value through the inductance characteristics, measurement errors due to current fluctuations are avoided, ensuring that each measurement of the transistor under test is performed under consistent energy conditions, and further improving the accuracy and reproducibility of the measurement results.

[0079] Therefore, the dynamic on-resistance measurement circuit of the present invention overcomes the problems of conventional techniques, such as the difficulty in independently adjusting measurement conditions, the inability to precisely control the blocking time, and the susceptibility of measurement results to interference. This makes the evaluation of the dynamic characteristics of III-V compound semiconductor field-effect transistors more reliable and further improves the accuracy of power element performance certification and reliability analysis.

[0080] The information disclosed above represents only preferred and implementable embodiments of the present invention, and the claims of the present invention are not limited thereto. Therefore, any equivalent technical modifications made using the description and drawings of the present invention are all included within the scope of the claims of the present invention. [Explanation of Symbols]

[0081] 1000... Dynamic On-Resistance Measurement Circuit 100... Energy storage circuit S1...First switch S2...Second Switch S3...The third switch DUT... Transistor under test L...Inductance VCC...Shared power supply 200...control circuit 300...Input power supply circuit Cst... Energy Storage Capacitor Cin...Input Capacitor VIN...Input Power S11 to S14, S201 to S215, S21 to S23, S401 to S403...process IL, Ids...Current T10...Initial stress relief time interval T11... Stress-voltage preparation time interval T12, T21... Stress voltage application time interval T13, T22...Measurement time intervals VG3, VG2, VG1, VGdut... control signals Vds...voltage T23...Release time T123...Operating Cycle

Claims

1. A dynamic on-resistance measurement circuit suitable for measuring the transistor under test, An energy storage circuit connected to a shared power supply and connected between the first discharge node and the second discharge node, A plurality of switching elements, including a first switch, a second switch, and a third switch, wherein the first end of the first switch is connected to the first discharge node, the first end of the third switch is connected to the second discharge node, the second end of the first switch is connected to the first end of the second switch and the first end of the inductance, the first end of the transistor under test is connected to the second end of the third switch and the second end of the inductance, and the second end of the second switch and the second end of the transistor under test are connected to a reference potential terminal, Each of the switching elements includes a control circuit connected to its control terminal and arranged to perform a single measurement operation, The aforementioned single measurement operation is, In the initial stress relief process, only the second switch is opened to release the residual stress voltage of the transistor under test along the second switch, In the stress voltage application process, the second switch is closed, the third switch and the first switch are opened, and the stress voltage is applied to the first and second ends of the transistor under test. The measurement process includes, in this order, closing the first switch and the third switch, opening the transistor under test and the second switch, measuring the voltage and current between the first and second terminals of the transistor under test, and calculating the dynamic on-resistance of the transistor under test based on the results. Dynamic on-resistance measurement circuit.

2. In the measurement process described above, the current is maintained at the stress current value to form a constant current. The dynamic on-resistance measurement circuit according to claim 1.

3. The aforementioned control circuit further, The system is configured to perform a stress voltage preparation process, which involves opening the third switch in advance, after executing the initial stress relief process and before the stress voltage application process. The dynamic on-resistance measurement circuit according to claim 1.

4. The aforementioned control circuit further, After the measurement process, a first discharge process is performed to reduce the current by opening the third switch while closing the transistor under test. The dynamic on-resistance measurement circuit according to claim 1.

5. The aforementioned control circuit further, The system is configured to perform the first emission process, followed by a second emission process in which the transistor under test is opened and the current is reduced to zero. The dynamic on-resistance measurement circuit according to claim 4.

6. The aforementioned energy storage circuit is Includes an energy storage capacitor connected between the first discharge node and the second discharge node and connected to the shared power supply, The dynamic on-resistance measurement circuit according to claim 1.

7. The present invention further includes an input power supply circuit connected to the first terminal of the third switch and configured to supply an input voltage to the first terminal of the third switch. The dynamic on-resistance measurement circuit according to claim 1.

8. The aforementioned input power supply circuit is Input capacitor and, Includes an input power supply connected to the input capacitor, which is configured to supply and store input power to the input capacitor and discharge it to the first end of the third switch via the input capacitor, The first terminal of the input capacitor is connected to the first terminal of the third switch, and the second terminal of the input capacitor is connected to the second terminal of the transistor under test and the second terminal of the second switch. The dynamic on-resistance measurement circuit according to claim 7.

9. The transistor under test is a III-V compound semiconductor field-effect transistor. The dynamic on-resistance measurement circuit according to claim 1.

10. The transistor under measurement is a gallium nitride transistor, an aluminum nitride transistor, or an aluminum gallium nitride transistor. The dynamic on-resistance measurement circuit according to claim 1.

11. A dynamic on-resistance measurement circuit suitable for measuring the transistor under test, An energy storage circuit connected to a shared power supply and connected between the first discharge node and the second discharge node, A plurality of switching elements, including a first switch, a second switch, and a third switch, wherein the first end of the first switch is connected to the first discharge node, the first end of the third switch is connected to the second discharge node, the second end of the first switch is connected to the first end of the second switch and the first end of the inductance, the first end of the transistor under test is connected to the second end of the third switch and the second end of the inductance, and the second end of the second switch and the second end of the transistor under test are connected to a reference potential terminal, Each of the switching elements includes a control circuit connected to its control terminal and arranged to perform continuous measurement operations in multiple cycles, Each time the aforementioned continuous measurement operation is performed, In the stress voltage application process, the third switch and the first switch are opened, and the stress voltage is applied to the first and second terminals of the transistor under test. In the measurement process, the third switch and the first switch are closed, the transistor under test and the second switch are opened, the voltage and current between the first and second terminals of the transistor under test are measured, and the dynamic on-resistance of the transistor under test is calculated based on the results. The discharge process includes, in this order, keeping the second switch open, opening the third switch, closing the transistor under test, and discharging the current by passing it through the third switch, the inductance, and the transistor under test to the reference potential terminal. Dynamic on-resistance measurement circuit.

12. Each time the continuous measurement operation is performed, the duration of the release process is shorter than the duration of the measurement process. The dynamic on-resistance measurement circuit according to claim 11.

13. Each time the continuous measurement operation is performed, the duration of the release process is shorter than the duration of the stress voltage application process. The dynamic on-resistance measurement circuit according to claim 11.

14. In the measurement process described above, the current is maintained at the stress current value to form a constant current. The dynamic on-resistance measurement circuit according to claim 11.

15. The energy storage circuit includes an energy storage capacitor connected between the first end of the first switch and the first end of the third switch, and connected to the shared power supply. The dynamic on-resistance measurement circuit according to claim 11.

16. The input power supply circuit further includes an input voltage supplied to the first terminal of the third switch connected thereto. The dynamic on-resistance measurement circuit according to claim 11.

17. The aforementioned input power supply circuit is Input capacitor and, Includes an input power supply connected to the input capacitor, which is configured to supply and store input power to the input capacitor and discharge it to the first end of the third switch via the input capacitor, The first terminal of the input capacitor is connected to the first terminal of the third switch, and the second terminal of the input capacitor is connected to the second terminal of the transistor under test and the second terminal of the second switch. The dynamic on-resistance measurement circuit according to claim 16.

18. The transistor under test is a III-V compound semiconductor field-effect transistor. The dynamic on-resistance measurement circuit according to claim 11.

19. The transistor under measurement is a gallium nitride transistor, an aluminum nitride transistor, or an aluminum gallium nitride transistor. The dynamic on-resistance measurement circuit according to claim 11.

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