Semiconductor packages

Abstract

To provide a semiconductor package with improved electromagnetic interference shielding effects between its components. [Solution] The semiconductor package 10 includes a package substrate 100 which includes a wiring pattern, The interposer substrate 200 is located on a package substrate and includes a body 220, through electrodes 243 and ground through electrodes 245 penetrating the body, rewiring patterns 250 and ground rewiring patterns 260 connected to the through electrodes, a rewiring insulating layer 240 surrounding at least a portion of the rewiring patterns, and ground interposer substrate pads 271 and interposer substrate pads 273; a first chip 300 on the interposer substrate; a second chip 500 on the interposer substrate spaced horizontally apart from the first chip; and a shielding film 500 covering the exposed surface of the first chip and the exposed surface of the second chip, the shielding film being in contact with the ground interposer substrate pads.

Description

Technical Field

[0001] The present invention relates to a semiconductor package, and more specifically, to a semiconductor package including an EMI shielding film. Background Art

[0002] In recent years, for micro devices, as chip sizes have decreased and the number of input / output terminals has increased due to the miniaturization of process technology and the diversification of functions, the pitch of electrode connection portions has been gradually miniaturized, and as the integration of various functions has been accelerated, system-level packaging technology for integrating a plurality of devices into one package has emerged.

[0003] However, in system-level packaging technology, as the operating speed of electronic components increases and various functions are added, Electro Magnetic Interference (EMI) occurs between components, and research to improve this phenomenon continues. Summary of the Invention Problem to be Solved by the Invention

[0004] The present invention has been made in view of the above prior art, and an object of the present invention is to provide a semiconductor package with improved electromagnetic interference shielding effect between components.

[0005] The problem to be solved by the present invention is not limited to the above problem, and other problems can be clearly understood by those skilled in the art from the following description. Means for Solving the Problem

[0006] In order to solve the technical problem, the present invention provides the following semiconductor package.

[0007] A semiconductor package according to one aspect of the present invention made to achieve the above objectives includes a package substrate including a wiring pattern; an interposer substrate located on the package substrate and including a body, a through electrode penetrating the body, a rewiring pattern connected to the through electrode, a rewiring insulating layer surrounding at least a portion of the rewiring pattern, and an interposer substrate pad; a first chip on the interposer substrate; a second chip horizontally separated from the first chip on the interposer substrate; and a shielding film covering the exposed surface of the first chip and the exposed surface of the second chip, wherein the through electrode includes a ground through electrode, the rewiring pattern includes a ground rewiring pattern, the interposer substrate pad includes a ground interposer substrate pad, and the shielding film is in contact with the ground interposer substrate pad.

[0008] To achieve the above objective, a semiconductor package according to another aspect of the present invention includes a package substrate including a first wiring pattern and a second wiring pattern, a first external connection terminal and a second external connection terminal located on the lower surface of the package substrate, a body located on the upper surface of the package substrate, a first through electrode and a second through electrode penetrating the body, a first rewiring pattern electrically connected to the first through electrode, a second rewiring pattern electrically connected to the second through electrode, a rewiring insulating layer, a first interposer substrate pad connected to the first rewiring pattern on the rewiring insulating layer, and a second interposer substrate pad connected to the second rewiring pattern on the rewiring insulating layer. The present invention relates to an interposer substrate including an interposer substrate pad, a first substrate connecting bump and a second substrate connecting bump located between the package substrate and the interposer substrate, a first chip on the interposer substrate, a second chip horizontally separated from the first chip on the interposer substrate, and a shielding film covering the top surface of the interposer substrate, the top and side surfaces of the first chip, and the top and side surfaces of the second chip, wherein the first wiring pattern, the first external connecting terminal, the first through electrode, the first rewiring pattern, the first substrate connecting bump, and the first interposer substrate pad transmit a ground signal.

[0009] A semiconductor package according to yet another aspect of the present invention made to achieve the above objectives includes: a package substrate including a first wiring pattern and a second wiring pattern; a first external connection terminal and a second external connection terminal located on the lower surface of the package substrate; an interposer substrate located on the upper surface of the package substrate and including a body, a first through electrode and a second through electrode penetrating the body, a first rewiring pattern electrically connected to the first through electrode, a second rewiring pattern electrically connected to the second through electrode, a rewiring insulating layer, a first interposer substrate pad connected to the first rewiring pattern on the rewiring insulating layer, and a second interposer substrate pad connected to the second rewiring pattern on the rewiring insulating layer; a first substrate connecting bump and a second substrate connecting bump located between the package substrate and the interposer substrate; and an underfill material layer surrounding the first substrate connecting bump and the second substrate connecting bump. The package includes a first chip on the interposer substrate, a second chip horizontally separated from the first chip on the interposer substrate, a shielding film covering the top surface of the interposer substrate, the top and side surfaces of the first chip, and the top and side surfaces of the second chip, and a molding member covering the top surface of the package substrate, the side and top surfaces of the interposer substrate, and the shielding film, wherein the first wiring pattern, the first external connection terminal, the first through electrode, the first rewiring pattern, the first substrate connection bump, and the first interposer substrate pad transmit a ground signal, the shielding film and the molding member are located between the first chip and the second chip, and the first interposer substrate pad, the first through electrode, the first substrate connection bump, and the first external connection terminal do not overlap vertically with the first chip and the second chip, respectively. [Effects of the Invention]

[0010] According to the present invention, it is possible to provide a semiconductor package that can efficiently prevent electromagnetic interference phenomena between its components. [Brief explanation of the drawing]

[0011] [Figure 1A] This is a schematic plan view showing a semiconductor package according to an embodiment of the present invention. [Figure 1B] This is a schematic plan view showing a semiconductor package according to an embodiment of the present invention. [Figure 2] This is a cross-sectional view along the line A1-A1' in Figure 1B. [Figure 3] This is a schematic cross-sectional view showing one embodiment of the first chip shown in Figure 2. [Figure 4] This is a schematic cross-sectional view showing one embodiment of the first chip shown in Figure 2. [Figure 5] This is a schematic cross-sectional view showing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 6] This is a schematic cross-sectional view showing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 7] This is a schematic cross-sectional view showing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 8] This is a schematic cross-sectional view showing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 9] This is a schematic cross-sectional view showing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 10] This is a cross-sectional view illustrating the method for manufacturing a semiconductor package of the present invention. [Figure 11] This is a cross-sectional view illustrating the method for manufacturing a semiconductor package of the present invention. [Figure 12] This is a cross-sectional view illustrating the method for manufacturing a semiconductor package of the present invention. [Figure 13] This is a cross-sectional view illustrating the method for manufacturing a semiconductor package of the present invention. [Figure 14] This is a cross-sectional view illustrating the method for manufacturing a semiconductor package of the present invention. [Figure 15] This is a cross-sectional view illustrating the method for manufacturing a semiconductor package of the present invention. [Modes for carrying out the invention]

[0012] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. For the same components in the drawings, the same reference numerals are used, and redundant descriptions related thereto will be omitted.

[0013] FIG. 1A is a plan view schematically showing a semiconductor package according to an embodiment of the present invention. FIG. 1B is a plan view schematically showing a semiconductor package according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line A1-A1' of FIG. 1B.

[0014] Referring to FIG. 1A to FIG. 2, semiconductor packages 1 and 10 include a package substrate 100, an interposer substrate 200, a first chip 300, a second chip 400, and a shielding film 500. According to an exemplary embodiment, the package substrate 100 is located under the interposer substrate 200, and is electrically connected to the interposer substrate 200 and external connection terminals 150 and 160, respectively. The semiconductor package 1 shown in FIG. 1A and the semiconductor package 10 shown in FIG. 1B are plan views illustrating embodiments of semiconductor packages 1 and 10 including a package substrate 100, an interposer substrate 200, a first chip 300, a second chip 400, and a shielding film 500, and the following description is based on FIG. 1B.

[0015] In the following drawings, the X-axis direction and the Y-axis direction indicate directions parallel to the surface of the package substrate 100, and the X-axis direction and the Y-axis direction are understood as directions perpendicular to each other. The Z-axis direction indicates a direction perpendicular to the top or bottom surface of the package substrate 100, in other words, a direction perpendicular to the X-Y plane. In addition, in the following drawings, the first horizontal direction, the second horizontal direction, and the vertical direction are understood as follows. The first horizontal direction is understood as the X-axis direction, the second horizontal direction is understood as the Y-axis direction, and the vertical direction is understood as the Z-axis direction.

[0016] The package substrate 100 is a substrate on which the interposer substrate 200 is mounted. In some embodiments, the package substrate 100 is a motherboard on which a plurality of types of semiconductor chips and packages are mounted. In some embodiments, the package substrate 100 may also be a substrate that functions as a bridge, receiving electrical signals from the interposer substrate 200 and transmitting the signals to an external device. The package substrate 100 is also connected to ground.

[0017] According to an exemplary embodiment, the package substrate 100 is a printed circuit board (PCB) including wiring patterns 120, 130 and an insulating layer 110 surrounding the wiring patterns therein. In this case, the wiring patterns 120, 130 are made of copper, nickel, stainless steel or beryllium copper, and the insulating layer 110 is made of at least one material selected from the group consisting of phenolic resin, epoxy resin, and polyimide. The insulating layer 110 includes at least one material selected from, for example, FR-4 (Flame Retardant 4), Tetrafunctional epoxy, Polyphenylene ether, Epoxy / polyphenylene oxide, BT (Bismaleimide triazine), Thermount, Cyanate ester, Polyimide, and Liquid crystal polymer.

[0018] According to an exemplary embodiment, the wiring patterns 120, 130 include a first wiring pattern 120 that transmits a ground signal, and a second wiring pattern 130 that transmits power / signal signals. According to an exemplary embodiment, the second wiring pattern 130 can also transmit other signals in addition to power / signal signals. In the present specification, the first wiring pattern 120 is also referred to as a ground wiring pattern.

[0019] External connection terminals 150 and 160 are located on the underside of the package substrate 100. The external connection terminals 150 and 160 are mounted on the underside of the package substrate 100 and are configured to transmit signals received from the wiring patterns 120 and 130 of the package substrate 100 to external devices. The external connection terminals 150 and 160 include a first external connection terminal 160 connected to a first wiring pattern 120 and a second external connection terminal 150 connected to a second wiring pattern 130. According to exemplary embodiments, the first external connection terminal 160 transmits a ground signal. In some embodiments, the first external connection terminal 160 is directly connected to ground. The second external connection terminal 150 transmits a power / signal signal. According to exemplary embodiments, the second external connection terminal 150 can transmit signals other than power / signals. In this specification, the first external connection terminal 160 is also referred to as the ground external connection terminal.

[0020] According to exemplary embodiments, the external connectors 150, 160 are formed as solder balls. However, according to embodiments, the external connectors 150, 160 may also have a structure including pillars and solder. The external connectors 150, 160 include at least one of copper (Cu), silver (Ag), gold (Au), and tin (Sn).

[0021] The interposer substrate 200 is mounted on the package substrate 100. According to an exemplary embodiment, the interposer substrate 200 is mounted on the package substrate 100 in a flip-chip manner via substrate linking bumps 181, 183. According to an exemplary embodiment, an underfill material layer 170 surrounding the substrate linking bumps 181, 183 is placed between the interposer substrate 200 and the package substrate 100. The underfill material layer 170 is made of, for example, an epoxy resin formed by a capillary underfill method. However, in some embodiments, a molding member may be directly filled into the gap between the interposer substrate 200 and the package substrate 100 via a molded underfill process. In this case, the underfill material layer 170 is optional.

[0022] According to an exemplary embodiment, the substrate linkage bumps 181 and 183 include a first substrate linkage bump 181 connected to a first wiring pattern 120, and a second substrate linkage bump 183 connected to a second wiring pattern 130. The first substrate linkage bump 181 transmits a ground signal between the interposer substrate 200 and the package substrate 100. The second substrate linkage bump 183 transmits a power / signal signal between the interposer substrate 200 and the package substrate 100. According to an exemplary embodiment, the second substrate linkage bump 183 can transmit signals other than power / signals. In this specification, the first substrate linkage bump 181 is also referred to as a ground substrate linkage bump.

[0023] The interposer substrate 200 is formed on a silicon base and electrically connects the first chip 300 and the second chip 400 mounted on the interposer substrate 200. In other words, the interposer substrate 200 acts as a connecting passage that electrically connects the first chip 300 and the second chip 400. According to an exemplary embodiment, if the first chip 300 and the second chip 400 are different types of chips or chip structures, the first chip 300 and the second chip 400 send and receive electrical signals to each other via the interposer substrate 200.

[0024] The interposer substrate 200 includes a body 220, through electrodes 243, 245, a redistribution insulating layer 240, and redistribution patterns 250, 260. The body 220 includes an upper surface and a lower surface. The body 220 includes silicon (Si), for example, crystalline silicon, polycrystalline silicon, or amorphous silicon. Alternatively, the body 220 includes a semiconductor element such as germanium (Ge), or a compound semiconductor such as SiC (silicon carbide), GaAs (gallium arsenide), InAs (indium arsenide), and InP (indium phosphide). On the other hand, the body 220 may also have an SOI (silicon on insulator) structure. For example, the body 220 includes a BOX layer (buried oxide layer).

[0025] The through electrodes 243 and 245 penetrate the body 220 vertically (Z). The through electrodes 243 and 245 extend vertically (Z) from the top surface to the bottom surface of the body 220 and are electrically connected to the substrate connecting bumps 181 and 183. According to an exemplary embodiment, the through electrodes 243 and 245 have a tapered shape in which the horizontal width decreases or increases as the level along the vertical (Z) direction increases. According to an exemplary embodiment, the through electrodes 243 and 245 may include through silicon vias (TSVs).

[0026] The through electrodes 243 and 245 include a first through electrode 245 connected to a first substrate connecting bump 181, and a second through electrode 243 connected to a second substrate connecting bump 183. The first through electrode 245 is configured to transmit a ground signal, and the second through electrode 243 is configured to transmit a power / signal signal. According to exemplary embodiments, the second through electrode 243 can transmit signals other than power / signals. In this specification, the first through electrode 245 is also referred to as the ground through electrode.

[0027] The redistribution insulation layer 240 is located on the upper surface of the body 220. The redistribution insulation layer 240 surrounds at least a portion of the redistribution patterns 250, 260. According to an exemplary embodiment, the redistribution insulation layer 240 is provided by laminating multiple layers together along the vertical direction (Z). The redistribution patterns 250, 260 serve as electrical connection passages that penetrate the upper and lower surfaces of the redistribution insulation layer 240.

[0028] According to an exemplary embodiment, the redistribution insulating layer 240 is formed from a PID (photoimageable dielectric) or a photosensitive polyimide (PSPI).

[0029] According to exemplary embodiments, the redistribution patterns 250, 260 are metals or metal alloys such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), and ruthenium (Ru), but are not limited thereto. In some embodiments, the redistribution patterns 250, 260 may be formed by laminating metals or metal alloys on a seed layer containing copper, titanium, titanium nitride, or titanium tungsten. The redistribution patterns 250, 260 include redistribution line patterns and redistribution via patterns. The redistribution line patterns have a shape that extends horizontally along at least one surface, either the upper or lower, of each of the multiple redistribution insulating layers 240 that are laminated in the vertical direction (Z). The redistribution via pattern has a shape that extends vertically (Z) through the redistribution insulating layer 240. The redistribution via pattern electrically connects redistribution line patterns located at different vertical levels. In some embodiments, at least a portion of the redistribution line patterns can be formed together with the redistribution via pattern to form an integral part.

[0030] The rewiring patterns 250 and 260 include a first rewiring pattern 260 connected to a first through electrode 245 and a second rewiring pattern 250 connected to a second through electrode 243. The first rewiring pattern 260 is configured to transmit a ground signal, and the second rewiring pattern 250 is configured to transmit a power / signal signal. In this specification, the first rewiring pattern 260 is also referred to as a ground rewiring pattern.

[0031] The interposer substrate pads 271 and 273 are located on the upper surface of the interposer substrate 200. According to an exemplary embodiment, the interposer substrate pads 271 and 273 are exposed perpendicularly (Z) to the redistribution insulation layer 240. In some embodiments, at least a portion of the sides of the interposer substrate pads 271 and 273 are exposed to the redistribution insulation layer 240.

[0032] According to an exemplary embodiment, the interposer substrate pads 271, 273 include a first interposer substrate pad 271 connected to a first redistribution pattern 260, and a second interposer substrate pad 273 connected to a second redistribution pattern 250. The first interposer substrate pad 271 is connected to a shielding film 500 and configured to transmit a ground signal. The second interposer substrate pad 273 is connected to at least one of a first chip coupling bump 390 and a second chip coupling bump 490. In this specification, the first interposer substrate pad 271 is also referred to as a ground interposer substrate pad.

[0033] The first chip 300 is located on the interposer substrate 200. According to an exemplary embodiment, the first chip 300 is mounted on the interposer substrate 200 in a flip-chip manner via first chip linking bumps 390 and first chip pads 395, such as microbumps. According to an exemplary embodiment, an underfill material layer 370 surrounding the first chip linking bumps 390 is placed between the first chip 300 and the interposer substrate 200. The underfill material layer 370 consists of, for example, an epoxy resin formed by a capillary underfill method.

[0034] The first chip 300 is a semiconductor chip or a chip stack structure. According to an exemplary embodiment, if the first chip 300 is a semiconductor chip, then the first chip 300 is a memory chip. The memory chip may be a volatile memory chip such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), or a non-volatile memory chip such as PRAM (Phase-change Random Access Memory), MRAM (Magnetoresistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory), or RRAM (Resistive Random Access Memory).

[0035] According to an exemplary embodiment, if the first chip 300 is a chip stacking structure, the chip stacking structure is a high-bandwidth memory package (HBM) or wire-bonded memory package in which multiple memory chips are stacked vertically (Z). This will be described in detail with reference to Figures 3 and 4.

[0036] The second chip 400 is separated from the first chip 300 along the horizontal direction (X and / or Y) and mounted on the interposer substrate 200. The second chip 400 is mounted on the interposer substrate 200 in a flip-chip manner via second chip linking bumps 490 and second chip pads 495, such as microbumps. According to an exemplary embodiment, an underfill material layer 470 surrounding the second chip linking bumps 490 is placed between the second chip 400 and the interposer substrate 200. The underfill material layer 470 consists of, for example, an epoxy resin formed by a capillary underfill method.

[0037] According to an exemplary embodiment, the second chip 400 is a logic chip. The logic chip is, for example, a microprocessor such as a central processing unit (CPU), a graphics processing unit (GPU), or an application processor (AP), an analog element, or a digital signal processor.

[0038] However, the first chip 300 is not limited to a memory chip, nor is the second chip 400 limited to a logic chip. In some embodiments, the first chip 300 and the second chip 400 may each be a memory chip or a logic chip, or the first chip 300 may be a logic chip and the second chip 400 may be a memory chip.

[0039] Multiple units of each of the first external connection terminal 160, the first substrate connection bump 181, the first through electrode 245, and the first interposer substrate pad 271 are provided. Each of the first external connection terminal 160, the first substrate connection bump 181, the first through electrode 245, and the first interposer substrate pad 271 is located lateral to the first chip 300, between the first chip 300 and the second chip 400, and lateral to the second chip 400. Here, lateral is understood as the direction opposite to the direction in which the first chip 300 and the second chip 400 face each other. For example, the lateral direction of the first chip 300 is understood as the direction opposite to the direction in which the first chip 300 and the second chip 400 face each other, and the lateral direction of the second chip 400 is understood as the direction opposite to the direction in which the second chip 400 and the first chip 300 face each other.

[0040] The first external connection terminal 160, the first substrate connection bump 181, the first through electrode 245, and the first interposer substrate pad 271 do not overlap with the first chip 300 and the second chip 400 in the vertical direction (Z).

[0041] The shielding film 500 is configured to prevent electromagnetic interference. According to an exemplary embodiment, the shielding film 500 is configured to shield against EMI (Electro Magnetic Interference). The shielding film 500 comprises a conductive material comprising one or more selected from the group consisting of metals and ceramics, specifically one or more selected from the group consisting of copper (Cu), gold (Au), silver (Ag), and titanium (Ti).

[0042] Furthermore, the shielding film 500 may contain a conductive resin. The conductive resin consists of a combination of carbon-based resins to which one or more of aluminum, ceramics, or silicon are added.

[0043] The shielding film 500 covers the surface of the first chip 300 and the surface of the second chip 400. According to an exemplary embodiment, the shielding film 500 completely covers the surface of the first chip 300 that is exposed from the underfill material layer 370. The shielding film 500 also completely covers the surface of the second chip 400 that is exposed from the underfill material layer 470.

[0044] The shielding film 500 covers the top and sides of the first chip 300 and the top and sides of the second chip 400.

[0045] According to an exemplary embodiment, the shielding film 500 covers the upper surface of the interposer substrate 200 in addition to the respective surfaces of the first chip 300 and the second chip 400. In this case, the shielding film 500 covers the first interposer substrate pad 271. According to an exemplary embodiment, the shielding film 500 covering the first interposer substrate pad 271 is located at a higher vertical level than the shielding film 500 covering the upper surface of the redistribution insulation layer 240. Since the first interposer substrate pad 271 protrudes vertically (Z) from the upper surface of the redistribution insulation layer 240, the shielding film 500 covering the first interposer substrate pad 271 is located at a higher vertical level than the shielding film 500 covering the upper surface of the redistribution insulation layer 240. Since the shielding film 500 covers the sides of the first interposer substrate pad 271, the shielding film 500 in lateral contact with the first interposer substrate pad 271 extends along the vertical direction (Z).

[0046] The shielding film 500 covers the surfaces exposed by the underfill material layers 370 and 470 from the interposer substrate 200, the first chip 300, and the second chip 400, respectively. In this case, the shielding film 500 covering the underfill material layers 370 and 470 has a slope. The slope is at a predetermined angle with respect to the upper surface of the interposer substrate 200.

[0047] In the semiconductor package 10 according to this disclosure, the shielding film 500 completely covers the components of the semiconductor package 10, specifically the first chip 300 and the second chip 400 in the embodiments shown in Figures 1 and 2, thus minimizing electromagnetic interference between the first chip 300 and the second chip 400. Furthermore, since the shielding film 500 is connected to the first interposer substrate pad 271, the first rewiring pattern 260, the first through-electrode 245, the first substrate connecting bump 181, the first wiring pattern 120, and the first external connecting terminal 160 that transmit ground signals, the shielding film 500 can be grounded without forming a separate ground pattern.

[0048] Furthermore, in order to efficiently ground the shielding film 500, the first external connecting terminal 160, the first substrate connecting bump 181, the first through electrode 245, and the first interposer substrate pad 271 are each located to the side of the first chip 300, to the side of the second chip 400, and between the first chip 300 and the second chip 400, thereby efficiently preventing electromagnetic interference between the first chip 300 and the second chip 400.

[0049] Figure 3 is a schematic cross-sectional view showing one embodiment of the first chip in Figure 2. In the following, we will omit any content that overlaps with what has been explained with reference to Figures 1 and 2, and will mainly explain the differences.

[0050] Referring to Figure 3, the first chip 300 is a chip stack structure. In this case, the first chip 300 includes a base chip 320, a first semiconductor chip 310, an adhesive layer 335, and a dummy chip 330. The base chip 320 is the chip located at the bottom end of the first chip 300. According to an exemplary embodiment, at least one of the upper and lower surfaces of the base chip 320 has a flat shape.

[0051] According to an exemplary embodiment, the base chip 320 integrates and transmits signals from a plurality of first semiconductor chips 310 stacked on top of the base chip 320 to the outside, or transmits signals and power from the outside to the first semiconductor chips 310. Accordingly, the base chip 320 is also referred to herein as a buffer chip or control chip.

[0052] The base chip 320 includes various types of individual devices. These individual devices include various microelectronic devices, such as MOSFETs (metal-oxide-semiconductor field effect transistors) like CMOS transistors (complementary metal-insulator-semiconductor transistors), system LSIs (large-scale integrations), image sensors such as CIS (CMOS imaging sensors), MEMS (micro-electro-mechanical systems), active elements, and passive elements. In some embodiments, the base chip 320 does not include memory cells. For example, semiconductor devices included in the base chip 320 include serial-parallel conversion circuits, DFTs (design for test), JTAGs (Joint Test Action Groups), MBISTs (memory builtin self-tests), and signal interface circuits such as PHYs.

[0053] Inside the base chip 320 is a through-electrode 325 that penetrates the base chip 320 vertically (Z). The through-electrode 325 contacts the base chip pad 321 located on the upper surface of the base chip 320. The through-electrode 325 is electrically connected to the base chip pad 321.

[0054] The base chip pad 321 and dielectric layer 323 are located on the upper surface of the base chip 320. The dielectric layer 323 surrounds the base chip pad 321. The dielectric layer 323 surrounds the sides of the base chip pad 321. The upper surface of the base chip pad 321 is exposed vertically above the dielectric layer 323.

[0055] The first semiconductor chip 310 is stacked vertically (Z) on the base chip 320. The first semiconductor chip 310 is bonded to the base chip 320 via direct bonding. Direct bonding includes dielectric-to-dielectric bonding, copper (Cu)-to-copper bonding, and hybrid bonding in which dielectric-to-dielectric bonding and metal-to-metal bonding occur together. Direct bonding is a diffusion bonding method in which two interfaces containing the same material are placed facing each other, then brought into contact with each other and heated so that the metal atoms or dielectric material in contact with each other become one through diffusion. Hybrid bonding includes hybrid copper bonding.

[0056] The first semiconductor chip 310 is bonded to the base chip 320 by direct bonding. For example, the semiconductor chip pad 311 and dielectric layer 313 on the lower surface of the first semiconductor chip 310 are in contact with the base chip pad 321 and dielectric layer 323 on the upper surface of the base chip 320 in a perpendicular direction (Z). Specifically, the semiconductor chip pad 311 on the lower surface of the first semiconductor chip 310 is in contact with the base chip pad 321 on the upper surface of the base chip 320 in a perpendicular direction (Z), and the dielectric layer 313 on the lower surface of the first semiconductor chip 310 is in contact with the dielectric layer 323 on the upper surface of the base chip 320 in a perpendicular direction (Z). In this case, the semiconductor chip pad 311 and dielectric layer 313 on the lower surface of the first semiconductor chip 310 are bonded to the base chip pad 321 and dielectric layer 323 on the upper surface of the base chip 320 by direct bonding. In Figure 3, an interface is shown between the semiconductor chip pad 311 and dielectric layer 313 on the lower surface of the first semiconductor chip 310 and the base chip pad 321 and dielectric layer 323 on the upper surface of the base chip 320. However, the interface may disappear when the semiconductor chip pad 311 and dielectric layer 313 on the lower surface of the first semiconductor chip 310 are directly bonded to the base chip pad 321 and dielectric layer 323 on the upper surface of the base chip 320.

[0057] According to exemplary embodiments, a plurality of first semiconductor chips 310 are provided. The plurality of first semiconductor chips 310 are defined as chips located below the dummy chip 330, stacked vertically (Z) on the base chip 320, among the plurality of chips included in the first chip 300. According to exemplary embodiments, the first semiconductor chip 310 is also referred to as a memory chip or core chip.

[0058] According to an exemplary embodiment, the first semiconductor chip 310 includes a semiconductor chip pad 311, a dielectric layer 313, and a through-electrode 315. The semiconductor chip pad 311 is provided on the upper and lower surfaces of the first semiconductor chip 310, respectively. The dielectric layer 313 surrounds the semiconductor chip pad 311 on the upper and lower surfaces of the first semiconductor chip 310, respectively. In this case, the dielectric layer 313 surrounds the sides of the semiconductor chip pad 311, and one of the upper or lower surfaces of the semiconductor chip pad 311 is exposed perpendicularly (Z) from the dielectric layer 313.

[0059] The first semiconductor chip 310 includes a first semiconductor substrate. The first semiconductor substrate has a bottom surface and an upper surface that are opposite to each other. The bottom surface is the surface facing the interposer substrate 200. The bottom surface is also called the active surface, and the upper surface opposite the bottom surface is also called the inactive surface.

[0060] The first semiconductor substrate includes silicon (Si), for example, crystalline silicon, polycrystalline silicon, or amorphous silicon. Alternatively, the first semiconductor substrate includes a semiconductor element such as germanium (Ge), or a compound semiconductor such as SiC (silicon carbide), GaAs (gallium arsenide), InAs (indium arsenide), and InP (indium phosphide). On the other hand, the first semiconductor substrate may also have a silicon on insulator (SOI) structure. For example, the first semiconductor substrate includes a buried oxide layer (BOX layer). The first semiconductor substrate includes conductive regions, for example, impurity-doped wells or impurity-doped structures. Furthermore, the first semiconductor substrate may have various element isolation structures, such as a shallow trench isolation (STI) structure.

[0061] The first semiconductor chip 310 includes a first semiconductor device layer. According to an exemplary embodiment, the first semiconductor device layer is formed on the underside, which is the active surface of the first semiconductor substrate. The first semiconductor device layer includes a core region and a first dummy region. Discrete elements are formed in the core region of the first semiconductor device layer. The discrete elements include various microelectronic devices, such as MOSFETs (metal-oxide-semiconductor field effect transistors) such as CMOS transistors (complementary metal-insulator-semiconductor transistors), large-scale integration systems (LSIs), image sensors such as CMOS imaging sensors (CISs), micro-electro-mechanical systems (MEMS), active elements, passive elements, and the like.

[0062] The first semiconductor chip 310 includes a first wiring layer. The first wiring layer is separated from the first semiconductor substrate perpendicularly, with the first semiconductor device layer in between. The first wiring layer is electrically connected to the first semiconductor device layer. The first wiring layer includes a multilayer wiring pattern and vias connecting the wiring patterns to each other.

[0063] The through-electrode 315 penetrates the first semiconductor substrate of the first semiconductor chip 310 in the vertical direction (Z). The through-electrode 315 penetrates the first semiconductor element layer and the first semiconductor substrate. The through-electrode 315 is electrically connected to the wiring pattern provided in the first wiring layer. The through-electrode 315 may have a tapered shape in which the horizontal width decreases or increases as the level increases along the vertical direction. At least a portion of the through-electrode 315 is columnar. The through-electrode 315 is a through silicon via (TSV). According to an exemplary embodiment, among a plurality of first semiconductor chips 310, the first semiconductor chip 310_U located at the uppermost end does not include a through-electrode 315.

[0064] According to an exemplary embodiment, the surface roughness of the upper surface of the first semiconductor chip 310_U located at the top is rougher than the surface roughness of the upper surfaces of the other first semiconductor chips 310.

[0065] In some embodiments, the vertical thickness of the uppermost first semiconductor chip 310_U among the multiple first semiconductor chips 310 is substantially the same as the vertical (Z) thickness of the other first semiconductor chips 310.

[0066] Multiple first semiconductor chips 310 are stacked in a single row along the vertical direction (Z). For example, the sides of each of the multiple first semiconductor chips 310 are located on the same plane. However, this is not the only option; the multiple first semiconductor chips 310 can also be stacked in an offset along one direction.

[0067] In some embodiments, multiple first semiconductor chips 310 are stacked vertically (Z) via direct bonding. For example, a semiconductor chip pad 311 and dielectric layer 313 on the upper surface of one first semiconductor chip 310 are in contact vertically (Z) with a semiconductor chip pad 311 and dielectric layer 313 on the lower surface of a first semiconductor chip 310 located above the first semiconductor chip 310. Specifically, a semiconductor chip pad 311 on the upper surface of one first semiconductor chip 310 is in contact vertically (Z) with a semiconductor chip pad 311 on the lower surface of a first semiconductor chip 310 located above the first semiconductor chip 310, and a dielectric layer 313 on the upper surface of one first semiconductor chip 310 is in contact vertically (Z) with a dielectric layer 313 on the lower surface of a first semiconductor chip 310 located above the first semiconductor chip 310. In this case, the semiconductor chip pad 311 and dielectric layer 313 on the upper surface of one first semiconductor chip 310 are bonded by direct bonding to the semiconductor chip pad 311 and dielectric layer 313 on the lower surface of the first semiconductor chip 310 located above the first semiconductor chip 310. In Figure 3, an interface is shown as existing between the semiconductor chip pad 311 and dielectric layer 313 on the upper surface of one first semiconductor chip 310 and the semiconductor chip pad 311 and dielectric layer 313 on the lower surface of the first semiconductor chip 310 located above the first semiconductor chip 310. However, the interface may disappear when the semiconductor chip pad 311 and dielectric layer 313 on the upper surface of one first semiconductor chip 310 are directly bonded to the semiconductor chip pad 311 and dielectric layer 313 on the lower surface of the first semiconductor chip 310 located above the first semiconductor chip 310.

[0068] Since the first semiconductor chips 310 are stacked by direct bonding, no adhesive layers or bumps are interposed between multiple first semiconductor chips 310.

[0069] According to an exemplary embodiment, the first semiconductor chip 310 includes a memory chip. According to an exemplary embodiment, the memory chip is a high-bandwidth memory package (HBM) or wire-bonded memory package in which a plurality of memory chips are stacked vertically (Z). However, the semiconductor chip may include, but is not limited to, a microprocessor such as a central processing unit (CPU), a graphics processing unit (GPU), or an application processor (AP), an analog element, or a logic chip such as a digital signal processor.

[0070] The dummy chip 330 is stacked vertically (Z) on the uppermost first semiconductor chip 310_U. The dummy chip 330 is stacked on the uppermost first semiconductor chip 310_U via an adhesive layer 335. According to exemplary embodiments, the dummy chip 330 is not electrically connected to the first semiconductor chip 310. In some embodiments, the thickness of the dummy chip 330 along the vertical (Z) direction is greater than the thickness of the first semiconductor chip 310 along the vertical (Z) direction.

[0071] The adhesive layer 335 is located between the dummy chip 330 and the first semiconductor chip 310_U located at the uppermost end. In an exemplary embodiment, the adhesive layer 335 is a layer configured to adhere the dummy chip 330 onto the first semiconductor chip 310_U located at the uppermost end. The adhesive layer 335 is a film that has adhesive properties of its own. For example, the adhesive layer 335 is a double-sided adhesive film. According to an exemplary embodiment, the adhesive layer 335 is a tape-type material layer, a liquid coating-curing material layer, or a combination thereof. The adhesive layer 335 also includes a thermal setting structure, a thermal plastic, a UV cure material, or a combination thereof. The adhesive layer 335 is also referred to as a DAF (Die attach film) or NCF (Non-Conductive film).

[0072] The first molding member 391 is formed on the upper surface of the base chip 320 so as to surround the first semiconductor chip 310 and the dummy chip 330. The first molding member 391 is formed from a molding material such as EMC or a photosensitive material such as PIE (photoimagable encapsulant). In some embodiments, a portion of the first molding member 391 is made of an insulating material such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. However, it is not limited to these, and the first molding member 391 is formed from a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin containing reinforcing materials such as inorganic fillers, specifically ABF (Ajinomoto Build-up Film), FR-4, BT, etc. According to an exemplary embodiment, the upper surface of the first molding member 391 is coplane with the upper surface of the dummy chip 330.

[0073] Figure 4 is a schematic cross-sectional view showing one embodiment of the first chip in Figure 2. In the following, we will omit any content that overlaps with what was explained with reference to Figure 3 and mainly explain the differences.

[0074] Referring to Figure 4, the first chip 301 is a chip stacking structure. In this case, the first chip 301 includes a base chip 320, a first semiconductor chip 310, an adhesive layer 335, and a dummy chip 330.

[0075] An underfill material layer 327 is located between the base chip 320 and the first semiconductor chip 310, and between each first semiconductor chip 310. The base chip 320 and the first semiconductor chip 310 are connected via chip linking bumps 329, and first semiconductor chips 310 adjacent to each other in the perpendicular direction (Z) are connected via chip linking bumps 319. Unlike the first chip 300 in Figure 3, the first chip 301 in Figure 4 is constructed by stacking the base chip 320 and multiple first semiconductor chips 310 in a flip-chip manner via bumps such as microbumps.

[0076] Figure 5 is a schematic cross-sectional view showing a semiconductor package according to an exemplary embodiment of the present invention. In the following, we will omit any content that overlaps with the explanation given with reference to Figures 1 to 4, and will mainly explain the differences.

[0077] Referring to Figure 5, the semiconductor package 11 includes an interposer substrate 200, a first chip 300, a second chip 400, and a shielding film 501. The package substrate 100 is located below the interposer substrate 200 and is electrically connected to the interposer substrate 200 and the external connection terminals 150 and 160, respectively. The package substrate 100 includes wiring patterns 120 and 130 and an insulating layer 110. The wiring patterns 120 and 130 include a first wiring pattern 120 for transmitting ground signals and a second wiring pattern 130 for transmitting power / signal signals. According to an exemplary embodiment, the second wiring pattern 130 can transmit signals other than power / signal. The external connection terminals 150 and 160 are located on the underside of the package substrate 100. The external connection terminals 150 and 160 include a first external connection terminal 160 connected to a first wiring pattern 120, and a second external connection terminal 150 connected to a second wiring pattern 130.

[0078] The interposer substrate 200 is mounted on the package substrate 100. Between the interposer substrate 200 and the package substrate 100, an underfill material layer 170 is placed, surrounding the substrate connecting bumps 181 and 183. The substrate connecting bumps 181 and 183 include a first substrate connecting bump 181 connected to a first wiring pattern 120, and a second substrate connecting bump 183 connected to a second wiring pattern 130. The interposer substrate 200 includes a body 220, through electrodes 243 and 245, a redistribution insulation layer 240, and redistribution patterns 250 and 260. The through electrodes 243 and 245 include a first through electrode 245 connected to the first substrate connecting bump 181, and a second through electrode 243 connected to the second substrate connecting bump 183.

[0079] The rewiring insulation layer 240 is located on the upper surface of the body 220. The rewiring insulation layer 240 surrounds at least a portion of the rewiring patterns 250, 260. The rewiring patterns 250, 260 include a first rewiring pattern 260 connected to a first through electrode 245, and a second rewiring pattern 250 connected to a second through electrode 243.

[0080] According to an exemplary embodiment, the interposer substrate pads 271 and 273 include a first interposer substrate pad 271 connected to a first redistribution pattern 260, and a second interposer substrate pad 273 connected to a second redistribution pattern 250.

[0081] The first chip 300 is located on the interposer substrate 200. According to an exemplary embodiment, the first chip 300 is mounted on the interposer substrate 200 in a flip-chip manner via first chip linkage bumps 390 and first chip pads 395, such as microbumps. According to an exemplary embodiment, an underfill material layer 370 surrounding the first chip linkage bumps 390 is placed between the first chip 300 and the interposer substrate 200.

[0082] The second chip 400 is separated from the first chip 300 along the horizontal direction (X and / or Y) and mounted on the interposer substrate 200. The second chip 400 is mounted on the interposer substrate 200 in a flip-chip manner via second chip linkage bumps 490 and second chip pads 495, such as microbumps. According to an exemplary embodiment, an underfill material layer 470 surrounding the second chip linkage bumps 490 is placed between the second chip 400 and the interposer substrate 200.

[0083] The shielding film 501 covers the upper surface of the interposer substrate 200, at least a portion of the side surface of the redistribution insulating layer 240, the surface of the first chip 300 exposed from the underfill material layer 370, and the surface of the second chip 400 exposed from the underfill material layer 470. The shielding film 501 covers at least a portion of the side surface of the redistribution insulating layer 240. As a result, the shielding film 501 in contact with the side surface of the redistribution insulating layer 240 has a shape that extends in the vertical direction (Z).

[0084] The shielding film 501 covers the first interposer substrate pad 271. Since the first interposer substrate pad 271 protrudes vertically (Z) from the rewiring insulating layer 240, the shielding film 501 covering the first interposer substrate pad 271 is located at a higher vertical level than the shielding film 501 covering the upper surface of the rewiring insulating layer 240. Since the shielding film 501 covers the sides of the first interposer substrate pad 271, the shielding film 501 in contact with the first interposer substrate pad 271 in the lateral direction has a shape that extends along the vertical direction (Z).

[0085] The shielding film 501 covers the surfaces exposed by the underfill material layers 370 and 470 from the interposer substrate 200, the first chip 300, and the second chip 400, respectively. In this case, the shielding film 501 covering the underfill material layers 370 and 470 has a slope. The slope is at a predetermined angle with respect to the upper surface of the interposer substrate 200.

[0086] Figure 6 is a schematic cross-sectional view showing a semiconductor package according to an exemplary embodiment of the present invention. In the following, we will omit any content that overlaps with the explanation given with reference to Figures 1 to 5, and will mainly explain the differences.

[0087] Referring to Figure 6, the semiconductor package 12 includes an interposer substrate 200, a first chip 300, a second chip 400, and a shielding film 502. The package substrate 100 is located below the interposer substrate 200 and is electrically connected to the interposer substrate 200 and the external connection terminals 150 and 160, respectively. The package substrate 100 includes wiring patterns 120 and 130 and an insulating layer 110. The wiring patterns 120 and 130 include a first wiring pattern 120 for transmitting ground signals and a second wiring pattern 130 for transmitting power / signal signals. According to an exemplary embodiment, the second wiring pattern 130 can transmit signals other than power / signal. The external connection terminals 150 and 160 are located on the underside of the package substrate 100. The external connection terminals 150 and 160 include a first external connection terminal 160 connected to a first wiring pattern 120, and a second external connection terminal 150 connected to a second wiring pattern 130.

[0088] The interposer substrate 200 is mounted on the package substrate 100. Between the interposer substrate 200 and the package substrate 100, an underfill material layer 170 is placed, surrounding the substrate connecting bumps 181 and 183. The substrate connecting bumps 181 and 183 include a first substrate connecting bump 181 connected to a first wiring pattern 120, and a second substrate connecting bump 183 connected to a second wiring pattern 130. The interposer substrate 200 includes a body 220, through electrodes 243 and 245, a redistribution insulation layer 240, and redistribution patterns 250 and 260. The through electrodes 243 and 245 include a first through electrode 245 connected to the first substrate connecting bump 181, and a second through electrode 243 connected to the second substrate connecting bump 183.

[0089] The rewiring insulation layer 240 is located on the upper surface of the body 220. The rewiring insulation layer 240 surrounds at least a portion of the rewiring patterns 250, 260. The rewiring patterns 250, 260 include a first rewiring pattern 260 connected to a first through electrode 245, and a second rewiring pattern 250 connected to a second through electrode 243.

[0090] According to an exemplary embodiment, the interposer substrate pads 271 and 273 include a first interposer substrate pad 271 connected to a first redistribution pattern 260, and a second interposer substrate pad 273 connected to a second redistribution pattern 250.

[0091] The first chip 300 is located on the interposer substrate 200. According to an exemplary embodiment, the first chip 300 is mounted on the interposer substrate 200 in a flip-chip manner via first chip linkage bumps 390 and first chip pads 395, such as microbumps. According to an exemplary embodiment, an underfill material layer 370 surrounding the first chip linkage bumps 390 is placed between the first chip 300 and the interposer substrate 200.

[0092] The second chip 400 is separated from the first chip 300 along the horizontal direction (X and / or Y) and mounted on the interposer substrate 200. The second chip 400 is mounted on the interposer substrate 200 in a flip-chip manner via second chip linkage bumps 490 and second chip pads 495, such as microbumps. According to an exemplary embodiment, an underfill material layer 470 surrounding the second chip linkage bumps 490 is placed between the second chip 400 and the interposer substrate 200.

[0093] The shielding film 502 covers the top and side surfaces of the interposer substrate 200, the surfaces of the underfill material layer 170 that are exposed from the interposer substrate 200 and the package substrate 100, at least a portion of the side surfaces of the redistribution insulating layer 240, the surface of the first chip 300 that is exposed from the underfill material layer 370, and the surface of the second chip 400 that is exposed from the underfill material layer 470.

[0094] Since the shielding film 502 covers the top and sides of the interposer substrate 200, electromagnetic interference generated from the interposer substrate 200 can be prevented.

[0095] The shielding film 502 covers the first interposer substrate pad 271. Since the first interposer substrate pad 271 protrudes vertically (Z) from the rewiring insulating layer 240, the shielding film 502 covering the first interposer substrate pad 271 is located at a higher vertical level than the shielding film 502 covering the upper surface of the rewiring insulating layer 240. Since the shielding film 502 covers the sides of the first interposer substrate pad 271, the shielding film 502 in contact with the first interposer substrate pad 271 in the lateral direction has a shape that extends along the vertical direction (Z).

[0096] The shielding film 502 covers the surfaces exposed by the underfill material layers 370 and 470 from the interposer substrate 200, the first chip 300, and the second chip 400, respectively. In this case, the shielding film 502 covering the underfill material layers 370 and 470 has a slope. The slope is at a predetermined angle with respect to the upper surface of the interposer substrate 200.

[0097] Furthermore, the shielding film 502 covers the surface of the underfill material layer 170 that is exposed from the interposer substrate 200 and the package substrate 100. As a result, the shielding film 502 covers the sides of the underfill material layer 170. In this case, the shielding film 502 covering the sides of the underfill material layer 170 is inclined with respect to the upper surface of the package substrate 100. The inclination is at a predetermined angle with respect to the upper surface of the package substrate 100.

[0098] Figure 7 is a schematic cross-sectional view showing a semiconductor package according to an exemplary embodiment of the present invention. In the following, we will omit any content that overlaps with the explanation given with reference to Figures 1 to 6, and will mainly explain the differences.

[0099] The semiconductor package 13 in Figure 7 includes an interposer substrate 200, a first chip 300, a second chip 400, and a shielding film 503. Unlike the semiconductor package 12 in Figure 6, the shielding film 503 covers the top surface of the package substrate 100. Because the shielding film 503 covers the top surface of the package substrate 100, electromagnetic interference phenomena originating from the package substrate 100 are prevented.

[0100] Figure 8 is a schematic cross-sectional view showing a semiconductor package according to an exemplary embodiment of the present invention. The following description will omit any content that overlaps with the explanation given with reference to Figures 1 to 7.

[0101] Referring to Figure 8, the semiconductor package 14 includes an interposer substrate 200, a first chip 300, a second chip 400, a shielding film 500, and a second molding member 690. The second molding member 690 surrounds the shielding film 500, the interposer substrate 200, and the package substrate 100. The second molding member 690 also fills the space between the first chip 300 and the second chip 400. The shielding film 500 and the molding member 690 are located between the first chip 300 and the second chip 400.

[0102] Figure 9 is a schematic cross-sectional view showing a semiconductor package according to an exemplary embodiment of the present invention. In the following, we will omit any content that overlaps with the explanation given with reference to Figures 1 to 8, and will mainly explain the differences.

[0103] Referring to Figure 9, the semiconductor package 20 includes an interposer substrate 200, a first chip 300, a second chip 400, and a shielding film 500. The first chip 300 and the second chip 400 are bonded to the interposer substrate 200 by direct bonding. Direct bonding includes dielectric-to-dielectric bonding, copper (Cu)-to-copper bonding, and hybrid bonding in which dielectric-to-dielectric bonding and metal-to-metal bonding occur simultaneously. Direct bonding is a diffusion bonding method in which two interfaces containing the same material are placed facing each other, then brought into contact with each other and heated so that the metal atoms or dielectric material in contact with each other become one through diffusion.

[0104] According to an exemplary embodiment, the first chip pad 395 and the second interposer substrate pad 273 are in contact in the vertical direction (Z). The first chip bonding insulating layer 397 is in contact in the vertical direction (Z) with the bonding insulating layer 275 located on the redistribution insulating layer 240.

[0105] According to an exemplary embodiment, the second chip pad 495 and the second interposer substrate pad 273 are in contact in the vertical direction (Z). The second chip bonding insulating layer 497 is in contact in the vertical direction (Z) with the bonding insulating layer 275 located on the redistribution insulating layer 240.

[0106] The bonding insulating layer 275 surrounds the sides of the first interposer substrate pad 271 and the second interposer substrate pad 273. As a result, the top surface of the first interposer substrate pad 271, the top surface of the second interposer substrate pad 273, and the top surface of the bonding insulating layer 275 are coplane.

[0107] The shielding film 500 covers the upper surfaces of the first chip 300, the second chip 400, and the bonding insulating layer 275. The shielding film 500 also covers the upper surface of the first interposer substrate pad 271. In this case, the upper surface of the first interposer substrate pad 271 is coplane with the upper surface of the bonding insulating layer 275, so the vertical level of the shielding film 500 covering the upper surface of the first interposer substrate pad 271 is at the same vertical level as the shielding film 500 covering the bonding insulating layer 275.

[0108] Figures 10 to 12 are cross-sectional views illustrating the manufacturing method of the semiconductor package of the present invention. In the following, we will omit any content that overlaps with the explanation given with reference to Figures 1 to 9, and will mainly explain the differences.

[0109] Referring to Figure 10, a package substrate 100 and an interposer substrate 200 mounted and electrically connected to the package substrate 100 are provided. The package substrate 100 and the interposer substrate 200 are electrically connected by substrate connecting bumps 181 and 183. The interposer substrate 200 includes a body 220, through electrodes 243 and 245, a redistribution insulating layer 240, and redistribution patterns 250 and 260.

[0110] Referring to Figure 11, interposer substrate pads 271 and 273 are formed on the interposer substrate 200, and the first chip 300 and the second chip 400 are mounted on them. The first chip 300 and the second chip 400 are mounted on the interposer substrate 200 using a flip-chip method as shown in Figure 11. In some embodiments, the first chip 300 and the second chip 400 are mounted on the interposer substrate 200 by direct bonding, as described with reference to Figure 9.

[0111] Referring to Figure 12, a shielding film 500 is formed to cover the upper surface of the interposer substrate 200, the first chip 300, and the second chip 400. The shielding film 500 is formed through a sputtering process and a spray coating process. The shielding film 500 is connected to the first interposer substrate pad 271 and is connected to ground via the first interposer substrate pad 271, the first rewiring pattern 260, the first through electrode 245, the first substrate connecting bump 181, the first wiring pattern 120, and the first external connecting terminal 160.

[0112] Figures 13 to 15 are cross-sectional views illustrating the manufacturing method of the semiconductor package of the present invention. In the following, we will omit any content that overlaps with the explanation given with reference to Figures 1 to 12, and mainly explain the differences.

[0113] Referring to Figure 13, an interposer substrate 200 and a first chip 300 and a second chip 400 mounted on the interposer substrate 200 are provided. The first chip 300 and the second chip 400 are mounted on the interposer substrate 200 by a flip-chip method or a direct bonding method.

[0114] Referring to Figure 14, the package substrate 100 is mounted on the underside of the interposer substrate 200. The package substrate 100 is mounted on the underside of the interposer substrate 200 via substrate connecting bumps 181 and 183.

[0115] Referring to Figure 15, a shielding film 500 is formed to cover the top surface of the interposer substrate 200, the first chip 300, and the second chip 400. The shielding film 500 is connected to the first interposer substrate pad 271 and is connected to ground via the first interposer substrate pad 271, the first rewiring pattern 260, the first through electrode 245, the first substrate connecting bump 181, the first wiring pattern 120, and the first external connecting terminal 160.

[0116] As described above, exemplary embodiments have been disclosed in the drawings and specification. While specific terms have been used to describe embodiments in this specification, these are solely for the purpose of illustrating the technical idea of ​​the invention and not to limit its meaning or scope. Therefore, a person with ordinary skill in the relevant art will understand that various modifications and equivalent other embodiments are possible. [Explanation of Symbols]

[0117] 1, 10, 11, 12, 13, 14, 20 Semiconductor packages 100 Package Substrates 110 Insulating layer 120 First wiring pattern (ground wiring pattern) 130 Second Wiring Pattern 150 Second external connection terminal 160 First external connection terminal (ground external connection terminal) 170, 327, 370, 470 Underfill material layer 181 First circuit board connecting bump (ground circuit board connecting bump) 183 Second board connecting bump 200 Interposer boards 220 Body 240 Rewiring Insulation Layer 243 2nd through electrode 245 First through electrode (ground through electrode) 250 Second rewiring pattern 260 First rewiring pattern (ground rewiring pattern) 271 First interposer substrate pad (ground interposer substrate pad) 273 Second interposer substrate pad 275 Bonding Insulation Layer 300, 301 First chip 310 First Semiconductor Chip 311 Semiconductor Chip Pad 313, 323 Dielectric layer 320 base chip 321 Base Tip Pad 315, 325 Through electrode 319, 329 Chip linking bump 330 Dummy Chips 335 Adhesive layer 390 First chip connecting bump 391 First Molding Member 395 First tip pad 397 First Chip Bonding Insulating Layer 400 Second chip 490 Second chip connecting bump 495 Second tip pad 497 Second Chip Bonding Insulating Layer 500, 501, 502, 503 Shielding membrane 690 Second molding member

Claims

1. A package substrate including a wiring pattern, An interposer substrate located on the package substrate, comprising a body, a through electrode penetrating the body, a rewiring pattern connected to the through electrode, a rewiring insulating layer surrounding at least a portion of the rewiring pattern, and an interposer substrate pad, The first chip on the interposer substrate, A second chip is horizontally separated from the first chip on the interposer substrate, The invention includes a shielding film that covers the exposed surface of the first chip and the exposed surface of the second chip, The through electrode includes a ground through electrode. The aforementioned rewiring pattern includes a ground rewiring pattern, The interposer substrate pad includes a ground interposer substrate pad. A semiconductor package characterized in that the shielding film is in contact with the ground interposer substrate pad.

2. The shielding film covers the upper surface of the interposer substrate. The semiconductor package according to claim 1, characterized in that the portion of the shielding film that covers the ground interposer substrate pad is located at a vertical level higher than the portion of the shielding film that covers the upper surface of the redistribution insulating layer.

3. A ground board connecting bump for transmitting a ground signal is located between the interposer board and the package board. A ground external connection terminal for transmitting a ground signal is located on the lower surface of the aforementioned package substrate. The semiconductor package according to claim 1, characterized in that each of the ground interposer substrate pad, the ground through electrode, the ground substrate connecting bump, and the ground external connecting terminal is located in the lateral direction of the first chip, in the lateral direction of the second chip, and between the first chip and the second chip.

4. The first chip is located on the interposer substrate via the first chip connecting bump, The second chip is located on the interposer substrate via a second chip connecting bump. The semiconductor package according to claim 1, characterized in that an underfill material layer is located between the first chip and the interposer substrate, and between the second chip and the interposer substrate.

5. The shielding film covers the underfill material layer, The semiconductor package according to claim 4, characterized in that the shielding film in contact with the underfill material layer has an inclination that forms a predetermined angle with respect to the upper surface of the interposer substrate.

6. A bonding insulating layer is located on the upper surface of the aforementioned rewiring insulating layer. The bonding insulating layer covers the side surface of the interposer substrate pad, A first chip pad and a first chip bonding insulating layer covering the sides of the first chip pad are located on the lower surface of the first chip. A second chip pad and a second chip bonding insulating layer covering the sides of the second chip pad are located on the lower surface of the second chip. The semiconductor package according to claim 1, characterized in that each of the first chip pad and the second chip pad is in contact with the interposer substrate pad in a direction perpendicular to the interposer substrate pad.

7. The semiconductor package according to claim 1, characterized in that the shielding film covers at least a portion of the side surface of the redistribution insulating layer.

8. The semiconductor package according to claim 1, characterized in that the shielding film covers the upper and side surfaces of the interposer substrate and the upper surface of the package substrate.

9. A package substrate including a first wiring pattern and a second wiring pattern, A first external connection terminal and a second external connection terminal located on the lower surface of the package substrate, An interposer substrate located on the upper surface of the package substrate, including a body, a first through electrode and a second through electrode penetrating the body, a first rewiring pattern electrically connected to the first through electrode, a second rewiring pattern electrically connected to the second through electrode, a rewiring insulating layer, a first interposer substrate pad connected to the first rewiring pattern on the rewiring insulating layer, and a second interposer substrate pad connected to the second rewiring pattern on the rewiring insulating layer, A first substrate connecting bump and a second substrate connecting bump are located between the package substrate and the interposer substrate, The first chip on the interposer substrate, A second chip is horizontally separated from the first chip on the interposer substrate, The interposer substrate includes a shielding film covering the upper surface, the upper and side surfaces of the first chip, and the upper and side surfaces of the second chip. A semiconductor package characterized in that the first wiring pattern, the first external connection terminal, the first through electrode, the first rewiring pattern, the first substrate connection bump, and the first interposer substrate pad transmit a ground signal.

10. The semiconductor package according to claim 9, characterized in that the first interposer substrate pad, the first through electrode, the first substrate connecting bump, and the first external connecting terminal are each located in the lateral direction of the first chip, in the lateral direction of the second chip, and between the first chip and the second chip.

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