Semiconductor equipment

Abstract

It can retain stored data even when power is not supplied, and it can also withstand a limited number of write cycles. One of the objectives is to provide a semiconductor device with a novel structure that is free from limitations. [Solution] A material that can sufficiently reduce the off-current of the transistor, for example, A semiconductor device is constructed using oxide semiconductor material, which is a side-gap semiconductor. By using semiconductor materials that can sufficiently reduce the off-current of the device, it is possible to achieve long-term operation. It is possible to store information in this way. Also, the timing of potential changes in the signal line can be written. The timing of the potential change in the word line is delayed. This prevents data writing errors. It is possible to prevent this.

Description

[Technical Field]

[0001] The disclosed invention relates to a semiconductor device utilizing a semiconductor element and a method for driving the same. ru. [Background technology]

[0002] Memory devices using semiconductor elements are volatile, meaning that the stored data is lost when the power supply is cut off. They can be broadly classified into two types: physical data and non-volatile data, which retains its contents even when the power supply is cut off. .

[0003] A typical example of a volatile memory device is DRAM (Dynamic Random Access Memory). DRAM has a memory (cess memory). DRAM selects transistors that make up the memory elements. By accumulating electric charge in the capacitor, it stores information.

[0004] Based on the principle described above, in DRAM, when information is read, the charge in the capacitor is lost, therefore, Each time the data is read, a write operation is required again. Also, the transistors that make up the memory element In an inverter, the leakage current between the source and drain in the off state (off current), etc. Therefore, even when a transistor is not selected, charge flows out or in, so data The retention period is short. Therefore, a write operation (refresh operation) is performed again at a predetermined interval. It is necessary, and it is difficult to sufficiently reduce power consumption. Also, the power supply will be cut off. Because the memory content is lost, long-term memory retention requires the use of other materials such as magnetic or optical materials. A storage device is required.

[0005] Another example of volatile memory is SRAM (Static Random Access Memory). SRAM has memory. SRAM uses circuits such as flip-flops to store information. Because it retains data, a refresh operation is unnecessary, which is an advantage over DRAM in this respect. However, because it uses circuits such as flip-flops, the cost per unit of memory capacity is high. There is a problem that it will become less effective. Also, there is the issue that if the power supply is cut off, the memory contents will be lost. Therefore, it is no different from DRAM.

[0006] A typical example of a non-volatile memory device is flash memory. Flash memory is a type of non-volatile memory device. The transistor has a floating gate between its gate electrode and channel formation region, Because memory is stored by holding an electric charge in a floating gate, the data retention period is extremely short. It has the advantage of being able to last for a very long time (semi-permanently) and not requiring the refresh operation necessary for volatile memory devices. It has points (see, for example, Patent Document 1).

[0007] However, the gate insulating layer that makes up the memory element is affected by the tunnel current generated during writing. Due to degradation, a problem arises where the memory element ceases to function after a predetermined number of write cycles. To mitigate the effects of this problem, for example, the number of write cycles for each memory element can be made uniform. While this method is employed, achieving it requires complex peripheral circuits. However, even if such methods are adopted, the fundamental problem of lifespan will not be resolved. Therefore, flash memory is unsuitable for applications where information needs to be rewritten frequently.

[0008] Also, in order to inject charge into the floating gate, or to remove that charge This requires a high voltage, as well as a circuit for that purpose. Furthermore, charge injection... Alternatively, removal can take a relatively long time, and speeding up writing and erasing is not easy. That's another problem. [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] Japanese Patent Publication No. 57-105889 [Overview of the Initiative] [Problems that the invention aims to solve]

[0010] In view of the above-mentioned problems, in one aspect of the disclosed invention, the stored contents are stored even when power is not supplied. To provide a new semiconductor device structure that allows for data retention and has no limit on the number of write cycles. One of its objectives is to achieve this. [Means for solving the problem]

[0011] The disclosed invention provides a material that can sufficiently reduce the off-current of a transistor, for example For example, a semiconductor device is constructed using oxide semiconductor material, which is a wide-bandgap semiconductor. By using semiconductor materials that can sufficiently reduce the off-current of the inverter, long-term operation is possible. It is possible to retain information over time.

[0012] Furthermore, the timing of the potential change in the signal line is set to be earlier than the timing of the potential change in the write word line. Delaying the process helps prevent data writing errors.

[0013] One aspect of the present invention includes a write word line, a read word line, a bit line, and a source line. , signal lines, a memory cell array consisting of multiple memory cells, a first drive circuit, and a second drive The device has a dynamic circuit and a memory cell, one of which has a first gate electrode, a first source electrode, and a first do A first transistor including a rain electrode and a first channel formation region, and a second gate electrode A second electrode, a second source electrode, a second drain electrode, and a second channel forming region It has a transistor and a capacitive element, and the first channel formation region is the second channel formation region It is composed of semiconductor materials different from those in the region, and consists of a first gate electrode and a second drain electrode. And, one of the electrodes of the capacitive element is electrically connected to form a node that holds the charge, The first drive circuit is electrically connected to the first drain electrode via a bit line, and also, The second source electrode is electrically connected via a signal line, and the second drive circuit is a readout circuit. It is electrically connected to the other electrode of the capacitive element via a code line, and also via a write word line. The second gate electrode is electrically connected, and the second drive circuit enters the write word line. This is a semiconductor device that has the function of delaying the signal input to the signal line compared to the signal being transmitted.

[0014] Furthermore, one aspect of the present invention includes a write word line, a read word line, a bit line, and a saw A signal line, a memory cell array consisting of multiple memory cells, a first drive circuit, and It has two drive circuits and a delay circuit, and one of the memory cells has a first gate electrode and a first socket A first transistor including a drain electrode, a first drain electrode, and a first channel formation region. and a second gate electrode, a second source electrode, a second drain electrode, and a second channel type The device comprises a second transistor including a channel formation region and a capacitive element, wherein the first channel formation region is It is composed of a semiconductor material different from the second channel formation region, and comprises a first gate electrode, The second drain electrode and one of the electrodes of the capacitive element are electrically connected to hold the charge. The node is configured, and the first drive circuit connects to the first drain electrode via a bit line and electrically It is connected to the second source electrode via a signal line, and is also electrically connected to the second drive The circuit is electrically connected to the other electrode of the capacitive element via the read word line, and also, The second gate electrode is electrically connected via the embedded word line, and the delay circuit is electrically connected to the signal line. It is a semiconductor device that is electrically connected.

[0015] Furthermore, one aspect of the present invention includes a write word line, a read word line, a bit line, and a saw A signal line, a memory cell array consisting of multiple memory cells, a first drive circuit, and It has two drive circuits, and one of the memory cells has a first gate electrode, a first source electrode, and A first transistor including a drain electrode and a first channel formation region, and a second gate Includes a first electrode, a second source electrode, a second drain electrode, and a second channel forming region. It has a second transistor and a capacitive element, and the first channel formation region is the second channel It is composed of a semiconductor material different from the region forming the electrode, and comprises a first gate electrode and a second electrode. The electrode and one of the electrodes of the capacitive element are electrically connected to form a node that holds the charge. The first drive circuit is electrically connected to the first drain electrode via a bit line. Furthermore, the second drive circuit is electrically connected to the second source electrode via a signal line, and reads It is electrically connected to the other electrode of the capacitive element via the output word line, and also writes word The first buffer circuit is connected to the signal line via a wire, which is electrically connected to the second gate electrode. The second buffer circuit is connected to the write word line, and the first buffer circuit is configured The channel length of the transistors that make up the second buffer circuit is the channel length of the transistors that make up the second buffer circuit. It is a semiconductor device with a length greater than the Nel length.

[0016] Furthermore, in the above configuration, a potential conversion circuit is used to output a potential higher than the power supply potential to the second drive circuit. It may also be configured to include a circuit.

[0017] Furthermore, in the above configuration, the plurality of memory cells are arranged in series between the bit line and the source line. It connects to the network.

[0018] Furthermore, in the above configuration, between the bit line and the multiple memory cells connected in series, The wires are electrically connected.

[0019] Furthermore, in the above configuration, a switch controls the connection between the bit line and signal line and the output terminal. It has a switch that controls the connection between the bit line and signal line and the input terminal, and wiring. The bit lines and signal lines are electrically connected.

[0020] Furthermore, in the above configuration, the second channel formation region of the second transistor is made of oxide semiconductor material. It is composed of a conductor.

[0021] Furthermore, in the above configuration, the second drive circuit is a potential conversion circuit and a writing word It has a level shift circuit that is electrically connected to a line or read word line.

[0022] In addition, in the above, an oxide semiconductor may be used to construct a transistor, but disclosure The invention is not limited to this. Materials that can achieve off-current characteristics equivalent to oxide semiconductors, For example, wide-bandgap materials such as silicon carbide (more specifically, for example, E Semiconductor materials with an energy gap Eg greater than 3eV may also be used.

[0023] In this specification, the terms "above" and "below" refer to the relative positions of the constituent elements, such as "directly above" or This does not necessarily mean "directly below". For example, "gate electrode on the gate insulating layer". If the expression is ", then exclude those that include other components between the gate insulating layer and the gate electrode. do not have.

[0024] Furthermore, in this specification, the terms "electrode" and "wiring" do not limit the functionality of these components. It is not fixed. For example, "electrode" can be used as part of "wiring". The reverse is also true. Furthermore, the terms "electrode" and "wiring" can refer to multiple "electrodes" and "wiring". This also includes cases where the "lines" are formed as a single unit.

[0025] Furthermore, the "source" and "drain" functions are used when employing transistors with different polarities. However, this can change when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" may be used interchangeably. It shall be done.

[0026] In this specification, etc., "electrically connected" means "having some kind of electrical effect." This includes cases where the connection is made via ". Here, "something that has some electrical effect" The term "connection" is not particularly limited as long as it enables the exchange of electrical signals between connected objects.

[0027] For example, "things that have some kind of electrical effect" include electrodes and wiring, as well as transistors. These include switching elements, resistive elements, inductors, capacitors, and various other functional elements. This includes elements such as [specific components]. [Effects of the Invention]

[0028] Transistors using oxide semiconductors have extremely low off-currents, so we decided to use them. It is possible to retain memory content for an extremely long period of time. In other words, refresh function This eliminates the need for manual operation, or makes it possible to significantly reduce the frequency of refresh operations. Therefore, power consumption can be significantly reduced. Also, in the event of no power supply (however, Even if the electrical potential is fixed, the memory contents can be retained over a long period of time. It is possible.

[0029] Furthermore, the semiconductor device according to the disclosed invention does not require a high voltage for writing information, and There are no issues with degradation of the child. For example, unlike conventional non-volatile memory, it does not use floating gates. Because there is no need to inject electrons into it or extract electrons from the floating gate, Problems such as deterioration of the gate insulating layer do not occur at all. In other words, the semiconductor according to the disclosed invention. The device does not have the limitations on the number of rewrite cycles that are a problem with conventional non-volatile memory, and Reliability improves dramatically. Furthermore, the on and off states of the transistors allow information to be transmitted. Because writing is performed, high-speed operation can be easily achieved. Also, to erase information Another advantage is that it requires no action.

[0030] Furthermore, transistors using materials other than oxide semiconductors are capable of sufficiently high-speed operation. Therefore, by using this in combination with a transistor using an oxide semiconductor, This ensures sufficient speed in the operation of the device (for example, the information retrieval operation). Furthermore, transistors using materials other than oxide semiconductors are used in various applications requiring high-speed operation. It is possible to suitably realize circuits (logic circuits, drive circuits, etc.).

[0031] Thus, transistors using materials other than oxide semiconductors (more broadly, transistors that can achieve sufficient high speed) A transistor capable of operation, and a transistor using an oxide semiconductor (more broadly, a 10 By integrating a transistor with a small off-current (in minutes) into one unit, it possesses unprecedented features. This enables the realization of semiconductor devices. [Brief explanation of the drawing]

[0032] [Figure 1] Circuit diagram of a semiconductor device. [Figure 2] Circuit diagram of a semiconductor device. [Figure 3] Timing chart. [Figure 4] Circuit diagram of a semiconductor device. [Figure 5] Circuit diagram of a semiconductor device. [Figure 6] Circuit diagram of a semiconductor device. [Figure 7] Circuit diagram of a semiconductor device. [Figure 8] Circuit diagram of a semiconductor device. [Figure 9] Cross-sectional and plan views of a semiconductor device. [Figure 10] Cross-sectional view of the manufacturing process for semiconductor devices. [Figure 11] Cross-sectional view of the manufacturing process for semiconductor devices. [Figure 12] Cross-sectional view of the manufacturing process for semiconductor devices. [Figure 13] Cross-sectional view of the manufacturing process for semiconductor devices. [Figure 14] A diagram illustrating electronic devices using semiconductor devices. [Figure 15] A diagram showing the characteristics of a transistor using an oxide semiconductor. [Figure 16]Circuit diagram for characterizing transistors using oxide semiconductors. [Figure 17] A timing chart diagram for characterizing transistors using oxide semiconductors. [Figure 18] A diagram showing the characteristics of a transistor using an oxide semiconductor. [Figure 19] A diagram showing the characteristics of a transistor using an oxide semiconductor. [Figure 20] A diagram showing the characteristics of a transistor using an oxide semiconductor. [Figure 21] A diagram showing the results of the memory window width investigation. [Figure 22] Circuit diagram of a semiconductor device. [Figure 23] Circuit diagram of a semiconductor device. [Figure 24] Circuit diagram of a semiconductor device. [Figure 25] Circuit diagram of a semiconductor device [Figure 26] Cross-sectional and plan views of a semiconductor device. [Figure 27] Circuit diagram of a semiconductor device [Modes for carrying out the invention]

[0033] An example of an embodiment of the present invention will be described below with reference to the drawings. However, the present invention is as follows The description is not limited to the present invention, and without departing from the spirit and scope of the present invention, its form and Those skilled in the art will readily understand that the details can be modified in various ways. Therefore, the present invention is as follows: The description of the embodiment shown is not to be limited to the content described herein.

[0034] Note that the position, size, and scope of each component shown in the drawings, etc., are for ease of understanding. The position, size, and range of the edges may not be shown. Therefore, the disclosed invention is not necessarily However, this is not limited to the location, size, and scope disclosed in drawings, etc.

[0035] Furthermore, the ordinal numbers such as "1st," "2nd," and "3rd" used in this specification, etc., are intended to avoid confusion of constituent elements. This is added to avoid any misunderstandings and does not mean that the number is limited.

[0036] (Embodiment 1) In this embodiment, the circuit configuration and operation of a semiconductor device according to one aspect of the disclosed invention are described below. The following will be explained with reference to Figures 1 to 3. Note that in the circuit diagrams, oxide semiconductors are used. Sometimes, the sign "OS" is added to indicate that it is a transistor.

[0037] <Basic circuit> First, the basic circuit configuration and its operation will be explained with reference to Figure 1. In the semiconductor device shown in A-1), the first wiring (1st Line) and transistor 1 The drain electrode (or source electrode) of the 60 is electrically connected to the second wiring (2nd The line (and the source electrode (or drain electrode) of transistor 160 are electrically connected. They are connected. Also, the third wire (3rd Line) and the source of transistor 162 An electrode (or drain electrode) is electrically connected to the fourth line. And, it is electrically connected to the gate electrode of transistor 162. And, The gate electrode of transistor 160 and the drain electrode (or source electrode) of transistor 162 are It is electrically connected to one of the electrodes of the capacitive element 164, and the fifth line is The other electrode of the capacitive element 164 is electrically connected.

[0038] Here, for example, a transistor using an oxide semiconductor is applied to transistor 162. Transistors using oxide semiconductors have the characteristic of having an extremely low off-current. Therefore, by turning off transistor 162, transistor 160 It is possible to maintain the potential of the gate electrode for an extremely long period of time. And the capacitance element Having child 164 helps retain the charge applied to the gate electrode of transistor 160. This makes it easier to retrieve the stored information.

[0039] Note that the transistor 160 is not particularly limited. From this perspective, for example, transistors using single-crystal silicon, switching It is preferable to use high-speed transistors.

[0040] Furthermore, as shown in Figure 1(B), it is also possible to omit the capacitive element 164. .

[0041] In the semiconductor device shown in Figure 1(A-1), the potential of the gate electrode of transistor 160 can be maintained. By utilizing its unique characteristics, it is possible to write, store, and read information in the following ways: ru.

[0042] First, we will explain how to write and retain information. First, the potential of the fourth wire is... The potential is set so that transistor 162 is turned on, thereby turning on transistor 162. As a result, the potential of the third wiring is controlled by the gate electrode of transistor 160 and the capacitive element 1 It is given to 64. That is, a predetermined charge is given to the gate electrode of transistor 160. (to write). Here, two charges that give different potentials (hereinafter referred to as giving a low potential) Charge Q L Charge Q, which gives a high potential H (that) It should be noted that charges providing three or more different potentials can be applied to increase the memory capacity . This operation is acceptable. Thereafter, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned off , and the transistor 162 is turned off, whereby the charge applied to the gate of the transistor 160 electrode is held (hold step).

[0043] Since the off-state current of the transistor 162 is extremely low, the charge in the gate electrode of the transistor 160 can be held for a long time.

[0044] Next, reading of information will be described. A state where a predetermined potential (constant potential) is applied to the second wiring , when an appropriate potential (reading potential) is applied to the fifth wiring, the gate of the transistor 160 takes different potentials depending on the amount of charge held in the electrode. In general, in a transis tor 160 when it is an n-channel type, Q is applied to the gate electrode of the transistor 160 H is supplied the apparent threshold V in this case th_H is lower than the apparent threshold V when Q is applied to the gate electrode of the transistor 160 L is supplied, the apparent threshold V in this case th_L This is because it becomes lower than that. Here, the appa rent threshold refers to the potential of the fifth wiring that is necessary to turn the transistor 160 into an "on state" It refers to the potential of . Therefore, the potential of the fifth wiring is V th_H and V th_L between by setting the potential to V0, the charge applied to the gate electrode of the transistor 160 can be discrimina ted. For example, when Q is supplied during writing H is supplied, the potential of the fifth wiring is V 0(>V th_H ), the transistor 160 is turned "on". When Q L is supplied​ If this occurs, the potential of the fifth wiring will be V0( <V th_L Even if it becomes transistor 16 0 remains in the "off state". Therefore, by looking at the potential of the first wire, it is maintained It is possible to extract the information that is present.

[0045] Furthermore, when memory cells are arranged in an array, only the information of the desired memory cell is used. It is necessary to be able to read the information. In this way, the information of a predetermined memory cell is read, and If information from an external memory cell is not read, the transistor 160 between each memory cell... When they are connected in parallel, the fifth memory cell that is not the target of reading Regardless of the gate electrode state, transistor 160 will be in the "off state" relative to the line. The potential, that is, V th_H A smaller potential should be applied. Also, between each memory cell If transistors 160 are connected in series, they are not included in the reading. Regardless of the state of the gate electrode, transistor 160 is connected to the fifth wiring of the memory cell. The potential that results in the "on state," that is, V th_L A higher potential is applied to the fifth wire. That's all you need to do.

[0046] Next, we will explain how to rewrite information. Rewriting information involves writing the information as described above and This is done in the same way as holding. In other words, the potential of the fourth wire is set when transistor 162 is ON. The potential is set to such a state, and transistor 162 is turned on. This changes the potential of the third wiring. (The potential related to the new information) is applied to the gate electrode of transistor 160 and the capacitive element 164. It is then given. After that, the potential of the fourth wire is set to the potential at which transistor 162 turns off. By turning off transistor 162, the gate voltage of transistor 160 is turned off. The poles become charged with new information.

[0047] Thus, the semiconductor device relating to the disclosed invention directly generates information through subsequent writing. It is possible to rewrite the information. Therefore, it is necessary in flash memory and other applications. It eliminates the need to extract charge from the floating gate using high voltage, and the erase operation This can suppress the decrease in operating speed caused by this. In other words, high-speed operation of semiconductor devices is possible. It will be revealed.

[0048] Note that the drain electrode (or source electrode) of transistor 162 is connected to transistor 160. By being electrically connected to the gate electrode, it is used as a non-volatile memory element. It performs the same function as the floating gate of a loading-gate transistor. In this case, the drain electrode (or source electrode) of transistor 162 and transistor 16 The point where the gate electrode of transistor O is electrically connected is sometimes called the node FG. If 162 is off, the node FG can be considered to be embedded in the insulator, node A charge is retained in FG. The off-current of transistor 162, which uses an oxide semiconductor, is Because it is less than 1 / 100,000th the size of a transistor formed by a recon semiconductor, It is possible to ignore the loss of charge accumulated at node FG due to leakage from TA162. In other words, the transistor 162 using an oxide semiconductor allows information to be transmitted even without a power supply. It is possible to realize a non-volatile memory device that can retain data.

[0049] For example, the off-current of transistor 162 at room temperature (25°C) is 10 Hz (1 Hz (Zepto Amperes are 1 x 10 -21 A) The capacitance value of the capacitive element 164 is approximately 10 fF. In some cases, at least 10 4 Data can be retained for more than a second. However, it goes without saying that this will vary depending on the transistor characteristics and capacitance values.

[0050] Furthermore, in the semiconductor device of the disclosed invention, conventional floating gate type transistor The problem of gate insulating film (tunnel insulating film) degradation, which has been pointed out in the case of the TA, does not exist. In other words, the gate when injecting electrons into a floating gate, which has been a problem in the past This eliminates the problem of dielectric degradation. This is due to the theoretical limitation of the number of write cycles. This means that it does not exist. Also, conventional floating gate type transients The high voltage required for writing and erasing in the original system is no longer necessary.

[0051] The semiconductor device shown in Figure 1(A-1) consists of elements such as transistors that make up the semiconductor device. It is possible to consider this as including resistance and capacitance, as shown in Figure 1(A-2). In other words, in Figure 1(A-2), transistor 160 and capacitive element 164 are, respectively, It is assumed that it is composed of resistance and capacitance. R1 and C1 are respectively These are the resistance and capacitance values ​​of the capacitive element 164, where the resistance value R1 constitutes the capacitive element 164. This corresponds to the resistance value due to the insulating layer. Also, R2 and C2 are, respectively, transistors. The resistance and capacitance values ​​are 160, and the resistance value R2 is when transistor 160 is ON. This corresponds to the resistance value due to the gate insulating layer, and the capacitance value C2 is the so-called gate capacitance (gate electrode and, Capacitance formed between the source electrode or drain electrode, and the gate electrode and channel type This corresponds to the capacity value of the volume formed between the constituent region and the surrounding region.

[0052] The resistance between the source and drain electrodes when transistor 162 is in the off state (actual) If ROS (also called effective resistance) is defined as the gate leakage current of transistor 162 is sufficiently small. Under the following conditions, R1 and R2 are R1 ≥ ROS (R1 is greater than or equal to ROS), R2 ≥ R If S (R2 is greater than or equal to ROS) is satisfied, then the charge retention period (which means the information retention period) is determined. (This is also possible) is primarily determined by the off-current of transistor 162.

[0053] Conversely, if the above conditions are not met, the off-current of transistor 162 will be sufficiently small. However, it becomes difficult to ensure a sufficient retention period. Other than the off-current of transistor 162. Leakage current (for example, between the source electrode and gate electrode in transistor 160) This is because the resulting leakage current, etc., is large. For this reason, the disclosure in this embodiment The semiconductor device has R1 ≥ ROS (R1 is greater than or equal to ROS) and R2 ≥ ROS (R2 is greater than or equal to ROS). It is desirable that the relationship (S or higher) is satisfied.

[0054] On the other hand, it is desirable that C1 and C2 satisfy the relationship C1 ≥ C2 (C1 is greater than or equal to C2). By increasing C1, when controlling the potential of node FG by the fifth wiring, the fifth This allows the potential of the wiring to be efficiently supplied to node FG, and then supplied to the fifth wiring. The potential difference between potentials (for example, between the readout potential and the non-readout potential) can be kept low. This is for the purpose of cutting.

[0055] Thus, by satisfying the above-mentioned relationship, it is possible to realize a more suitable semiconductor device. Yes. Note that R1 and R2 are the gate insulating layer of transistor 160 and the capacitive element 164. It is controlled by the insulating layer. The same applies to C1 and C2. Therefore, gate insulation It is desirable to appropriately set the material and thickness of the layers so as to satisfy the above-mentioned relationship.

[0056] In the semiconductor device shown in this embodiment, node FG is a flow such as flash memory. It functions similarly to the floating gate of a ting-gate transistor, but in this implementation... The node FG in this form has characteristics that are fundamentally different from floating gates such as flash memory. It has.

[0057] In flash memory, the potential applied to the control gate is high, so that potential is To avoid affecting the floating gates of adjacent cells, the spacing between cells is... It becomes necessary to maintain a certain level of integration. This is one of the factors that hinders the high integration of semiconductor devices. And the factor in question is a flash current generated by applying a high electric field. This stems from the fundamental principles of spearfishing.

[0058] On the other hand, the semiconductor device according to this embodiment is a transistor switch using an oxide semiconductor. It operates by tunneling and does not use the principle of charge injection by tunnel current as described above. In other words, it does not require a high electric field for charge injection, as in flash memory. Therefore, there is no need to consider the effect of the high electric field from the control gate on adjacent cells. Therefore, high integration becomes easier.

[0059] Furthermore, the fact that a high electric field is not required and large peripheral circuits (such as boost converters) are not needed is also a plus. This is an advantage over shrink memory. For example, the memory cell according to this embodiment is marked The applied voltage (the maximum and minimum potentials applied simultaneously to each terminal of the memory cell) The maximum value of the difference is when writing two levels (1 bit) of information in a single memory cell. The voltage can be 5V or less, preferably 3V or less.

[0060] Furthermore, the relative permittivity εr1 of the insulating layer constituting the capacitive element 164 and the transistor 160 are When the relative permittivity εr2 of the gate insulating layer is made different, the area S of the capacitive element 164 1 and the area S2 of the region with gate capacitance in transistor 160 are such that 2·S2≧S 1 (2·S2 is greater than or equal to S1), preferably S2≧S1 (S2 is greater than or equal to S1), C It is easy to achieve 1 ≥ C2 (where C1 is greater than or equal to C2). Specifically, for example, the capacity element The insulating layer constituting sub-164 is a film made of a high-k material such as hafnium oxide. , or the intersection of a film made of a high-k material such as hafnium oxide and a film made of an oxide semiconductor A layered structure is adopted to make εr1 10 or more, preferably 15 or more, and the transistor 160 is constructed In the gate insulating layer, silicon oxide is used, and 3 ≤ εr² ≤ 4 (where εr² is 3 It can be set to (4 or less) above.

[0061] By using such a configuration in combination, the semiconductor device according to the disclosed invention can be made even more advanced. Integration is possible.

[0062] Furthermore, in order to increase the memory capacity of semiconductor devices, in addition to high integration, multi-level cell technology can be employed. It is also possible to configure the memory cell to write three or more levels of information. Therefore, compared to writing two levels (1 bit) of information, it is possible to increase the memory capacity. Yes, it is possible. For example, the charge Q that gives a low potential, as described above. L , charge Q that gives high potential H In addition , By applying a charge Q that provides another potential to the gate electrode of transistor 160, multi-level amplification is achieved. This can be expressed in a relatively large-scale circuit configuration (for example, 15F). 2 ~50 F 2 Even when using the minimum machining dimensions (F), sufficient storage capacity can be secured.

[0063] <Application Example 1> Next, we will discuss a more specific circuit configuration and operation using the circuit shown in Figure 1, as shown in Figure 2 and Refer to Figure 3 and write the command.

[0064] Figure 2(A) is an example of a circuit diagram of a semiconductor device having (m × n) memory cells 170. The configuration of memory cell 170 in Figure 2 is the same as in Figure 1(A-1). That is, Figure 2 As shown in (B), the first wiring in Figure 1(A-1) corresponds to the bit line in Figure 2(B). This corresponds to BL, and the second wiring in Figure 1(A-1) corresponds to the source line SL in Figure 2(B). Correspondingly, the third wiring in Figure 1(A-1) corresponds to the signal line S in Figure 2(B), The fourth wiring in 1(A-1) corresponds to the write word line WWL in Figure 2(B). The fifth wiring in Figure 1(A-1) is in phase with the read word line RWL in Figure 2(B). This applies. However, in Figure 2(A), the first row of memory cells 170(1,1)~(1,n) Only is directly connected to bit line BL, and the memory cell 170(m,1)~(m,n) of the mth row Only the source line SL is directly connected. Memory cell 170 in the other row is connected to the other memory in the same column. It is electrically connected to the bit line BL and source line SL via cell 170.

[0065] The semiconductor device shown in Figure 2 has m write word lines WWL (where m is an integer greater than or equal to 2) and m lines The read word line RWL, the n source lines SL (where n is an integer greater than or equal to 2), and the n bits The T line BL, n signal lines S, and memory cells 170 arranged in a matrix of m rows x n columns. A memory cell array arranged in a rix pattern, and n bit lines BL and n signal lines S The first drive circuit 190 is connected, along with m write word lines WWL and m read lines. It has a second drive circuit 192 connected to the word line RWL, and a first drive circuit 190 and The second drive circuit 192 is connected by wiring WRITE and wiring READ. .

[0066] In addition, the address selection signal line A is connected to the second drive circuit 192. Selection signal line A is a wire that transmits a signal to select the row address of a memory cell.

[0067] Regarding the first drive circuit 190 and the second drive circuit 192 shown in Figure 2(A), see Figure 23. Refer to the explanation. The first drive circuit 190 and the second drive circuit 192 are connected by wiring. and connected by wiring READ.

[0068] The first drive circuit 190 includes a readout circuit 211, a control circuit 212, and a delay circuit 213. It is composed of a buffer circuit 214 and an input terminal IN, control circuit 212, delay It is connected to the signal line S via circuit 213 and buffer circuit 214. Also, bit The readout circuit 211, which is connected to line BL, is connected to the output terminal OUT.

[0069] The second drive circuit 192 includes a decoder circuit 221, a control circuit 222, and a buffer circuit 22 3. It consists of a buffer circuit 224. Address selection signal line A is connected to the decoder circuit It is connected to 221. Also, the decoder circuit 221 is connected to the control circuit 222. The control circuit 222 is connected to the write word line WWL via the buffer circuit 223. Furthermore, the control circuit 222 reads the word line RWL via the buffer circuit 224. Connected.

[0070] Writing, retaining, and reading data are essentially the same as in Figure 1. The specific writing operation is as follows. Note that Figure 2(B) is used as an example. See also Figure 23, and apply a potential V1 (a potential lower than the power supply potential VDD) to node FG. The following describes the case where either the quasi-potential GND is applied, but the relationship of the potential applied to node FG The scope is not limited to this. Also, the data retained when a potential V1 is applied to node FG Data "1", data retained when a reference potential GND is applied to node FG. Set it to 0.

[0071] First, data writing is performed by a read-only device connected to the memory cell 170 to be written to. The potential of the writing line RWL is set to GND, and the potential of the writing word line WWL is set to V2 (higher than V1). Select memory cell 170 to write to, for example, VDD.

[0072] When writing data "0" to memory cell 170, connect signal line S to GND and write to memory cell 170. When writing data "1" to the Ricell 170, V2 is applied to the signal line S. Since the potential of the written word line WWL is set to V2, V1 can be applied to node FG. It is possible.

[0073] Data retention is achieved by adjusting the potential of the read word line RWL and the write word line WWL. This is done by connecting it to GND.

[0074] If the potential of the read word line RWL is fixed to GND, the potential of node FG will be the same as when writing. It is fixed to the potential. That is, if node FG is given data "1" V1. The potential of node FG becomes V1, and node FG is given GND, which is data "0". If present, the potential of node FG will be GND.

[0075] Since the write word line WWL is connected to GND, data "1" and data "0" Regardless of which of the following is written, transistor 162 will be in the off state. Because the off-current of transistor 162 is extremely small, the charge on the gate electrode of transistor 160 remains constant for a long time. It is retained over time.

[0076] Data is read via the read word line R connected to the memory cell 170 to be read. The potential of WL and the potential of the write word line WWL are set to GND, and the read target is The potential of the read word line RWL connected to the memory cell 170 is set to V2, and the write This is done by setting the potential of the written word line WWL to GND.

[0077] The potential of the read word line RWL connected to the memory cell 170 to be read is set to GND. Then, the node FG of the memory cell 170 to be read is given data "1", which is V1. If this is the case, transistor 160 will be in the ON state. Meanwhile, data is sent to node FG. If GND (which is 0") is provided, transistor 160 will be in the off state.

[0078] Also, the power of the read word line RWL connected to the memory cell 170 that is not to be read. If we set the position to V2 and the potential of the write word line WWL to GND, then the data to be read will be... If the memory cell 170 does not contain data "1", and data "0" In any case where the data is written, transistor 160 will be in the ON state.

[0079] In other words, the above read operation results in the data "1" being stored in the memory cell 170 that is being read. If data is written, transistor 160 turns ON, and the potential of bit line BL is affected. The value decreases. Also, if data "0" is written, transistor 160 is The state changes to "F," and the potential of the bit line BL at the start of reading is maintained or increases.

[0080] Furthermore, if the above configuration is adopted, the data retention operation and data retrieval operation will be The potential of the read word line RWL and the write word line WWL are GND. Therefore, the data "1" has been written to all memory cells 170 in the target column. In this case, transistor 160 turns ON, and regardless of whether it is held or read out, The SL line and BL line become conductive. This leads to increased power consumption, which is a problem. There are such situations. In order to sufficiently suppress the power consumption caused by these situations, memory cell 1 It is advisable to place a selection transistor between 70 and the source line SL or bit line BL. Alternatively, in operations other than readout, the potentials of the source line SL and the bit line BL should be equal. stomach.

[0081] Figure 3 shows an example of a timing chart relating to the more detailed operation of the semiconductor device shown in Figure 2(A). This indicates the following. The names READ, A, etc. in the timing chart refer to the electrical information shown in the timing chart. This indicates the wiring to which a position is assigned, and if there are multiple wires with similar functions, the wiring is assigned a position. They are distinguished by adding _1, _2, etc., to the end of their names. For simplicity, the explanation here will be simplified. Therefore, we will explain using a semiconductor device in which memory cells 170 are arranged in a 2x2 grid as an example. The disclosed inventions are not limited to these.

[0082] The timing chart shown in Figure 3 writes data "1" to all memory cells. Write 1), then read all the written data (read 1), and then the first row The data "1" is written to the memory cell in the first column and the memory cell in the second row and second column, and Write the data "0" to the memory cell in the 1st row, 2nd column and the memory cell in the 2nd row, 1st column. The power of each wire when writing (2) and then reading all the written data (2) This indicates the relationship between ranks.

[0083] In write 1, WRITE is set to a high potential and READ to a low potential for writing to the memory cell. Prepare the circuit to enable loading. The second drive circuit 192 controls the load according to the potentials of A_1 and A_2. The selection signal is output to RWL and WWL. Here, if A_1 is at a high potential, the first row If an eye is selected and A_2 has a high potential, the second row will be selected. The WWL of the selected row will have a high potential, while the RWL will have a low potential regardless of whether it is selected or not. .

[0084] In write 1, data "1" is written to all memory cells, so row selection is required. In accordance with the timing, S_1 and S_2 are set to high potential. The signal input period should be longer than the signal input period of WWL. Alternatively, S_1 and S The signal input of _2 is delayed compared to the signal input of WWL. S_1 and S_2 signal input period If the interval is short, or if the signal inputs for S_1 and S_2 are earlier than the signal input for WWL, This is because the writing to the memory cell may be insufficient. For example, a delay circuit 213 can be connected to S_1 or S_2 to input the signals of S_1 or S_2. The force can be delayed compared to the WWL signal input. Alternatively, the battery connected to S_1 or S_2 can be used. The size (e.g., channel length) of the transistors that make up circuit 214 is connected to WWL. The size of the transistors constituting the buffer circuit 223 (e.g., channel length) is larger than the size of the transistors constituting the buffer circuit 223. By reducing the drive capability, the signal inputs of S_1 and S_2 are used to control the WWL signal input. The force should be delayed. Alternatively, a buffer circuit 214 can be configured to connect to S_1 or S_2. The size of the transistor (e.g., channel width) is determined by the buffer circuit 2 connected to the WWL. The size of the transistors that make up 23 (e.g., channel width) is made smaller to increase the driving capability. By dropping the signal, the signal inputs for S_1 and S_2 can be delayed compared to the signal input for WWL. Note that the potentials of BL_1 and BL_2 do not pose a major problem during writing (high voltage (It can be a low-voltage position or a low-voltage position.)

[0085] In read 1, WRITE is set to a low potential and READ to a high potential, and data is obtained from the memory cell. The system is set up to allow reading. The second drive circuit 192 performs row selection according to A_1 and A_2. The signal is output to RWL and WWL. Here, if A_1 is at a high potential, the first line is If selected, and A_2 has a high potential, the second row is selected. Also, the RW of the selected row L will be low potential, the RWL of unselected rows will be high potential, and WWL will be selected or unselected. Regardless of the selection, the potential will be low.

[0086] As a result of the above operation, BL_1 and BL_2 will hold the memory cells of the selected row. A potential is assigned according to the data being read. Note that the potentials of S_1 and S_2 are read out. Sometimes it's not a problem.

[0087] The relationship of potentials between each wire in write 2 is the same as in write 1. However, the When the data "1" is written to the memory cell in the first row, first column and the memory cell in the second row, second column, Then, the data "0" is written to the memory cell in the first row, second column and the memory cell in the second row, first column. To achieve this, S_1 and S_2 are set to low or high potential in accordance with the timing of row selection. do.

[0088] The potential relationship of each wire in readout 2 is the same as in readout 1. BL_1 The potential of BL_2 is determined according to the data held in the memory cell of the selected row. It becomes clear that it can be obtained.

[0089] Furthermore, in the above-described writing operation, the signal input to the write word line WWL is more reliable than the signal input to the write word line WWL. To delay the signal input to line S, for example, the delay circuit shown in Figure 4 is used as the first drive It is preferable to install it within circuit 190 and connect it to signal line S. Connect the delay circuit to signal line S. Therefore, the change in potential of the signal line S is delayed by the change in potential of the written word line WWL. This allows for the suppression of writing errors to memory cell 170.

[0090] Next, regarding the delay circuit 213 provided in the first drive circuit 190 shown in Figure 23, see Figure 4( This will be explained with reference to A), (B), (C), (D) and Figure 22.

[0091] As the delay circuit 213, an even number of inverters are connected in series as shown in Figure 4(A). A path can be used. Also, as shown in Figure 4(B), an even number of inputs connected in series Configurations in which capacitive elements are added to the barta, or, as shown in Figure 4(C), an even number of elements connected in series A configuration with a resistor added to the inverter is also possible. Furthermore, as shown in Figure 4(D), in series A configuration may be used in which resistors and capacitive elements are added to an even number of inverter circuits connected to the inverter. .

[0092] Alternatively, in the writing operation described above, the signal input to the write word line WWL is greater than In order to delay the signal input to signal line S, the first drive circuit 190 and the second drive circuit In the buffer circuit provided in the path 192, the buffer circuit of the first drive circuit 190 The size of the transistor in path 214 (e.g., channel length) is determined by the second drive circuit 192. The size of the transistor in the buffer circuit 223 may be larger than the size of the first The size of the transistors in the buffer circuit 214 of the drive circuit 190 (for example, channel The width is the size of the transistors in the buffer circuit 223 of the second drive circuit 192 (example). For example, it can be made smaller than the channel width. In this case as well, the power of the write word line WWL By changing the position, the change in the potential of the signal line S can be delayed, and writing to the memory cell 170 can be delayed. This can help reduce errors caused by over-compression.

[0093] Next, regarding the readout circuit 211 provided in the second drive circuit 192 shown in Figure 23, Refer to section 22 for further explanation.

[0094] Figure 22(A) shows a schematic of the readout circuit. This readout circuit consists of a transistor and a sensor. It has a amp circuit.

[0095] During reading, terminal A is connected to bit line BL, to which the memory cell to be read is connected. Furthermore, a bias potential Vbias is applied to the gate electrode of the transistor, and terminal A The potential is controlled.

[0096] The memory cell 170 exhibits different resistance values ​​depending on the data stored. Specifically, If the selected memory cell 170's transistor 160 is ON, it will be in a low-resistance state. If transistor 160 of the selected memory cell 170 is in the off state, it will be in a high-resistance state. .

[0097] When the memory cell is in a high-resistance state, the potential at terminal A becomes higher than the reference potential Vref, and sense The amplifier circuit outputs a potential (data "0") corresponding to the potential at terminal A. On the other hand, the memory... When the resistor is in a low-resistance state, the potential at terminal A becomes lower than the reference potential Vref, and the sense amplifier turns The path outputs a potential (data "1") corresponding to the potential of terminal A.

[0098] In this way, by using a read circuit, data can be read from the memory cell. . Note that the readout circuit of the present embodiment is merely an example. Other known circuits may be used. Further, the readout circuit may include a precharge circuit. Instead of the reference potential Vref, a configuration in which a reference bit line is connected may also be adopted.

[0099] FIG. 22(B) shows a differential sense amplifier, which is an example of a sense amplifier circuit. Differential sense amplifier includes an input terminal Vin(+), an input terminal Vin(-), and an output terminal Vout, and amplifies a difference between Vin(+) and Vin(-). If Vin(+)>Vin(-), Vout is substantially a High output, and if Vin(+)<Vin(-), Vout is substantially a Low output.

[0100] FIG. 22(C) shows a latch-type sense amplifier, which is an example of a sense amplifier circuit. The latch-type sense amplifier includes input / output terminals V1 and V2, and input terminals for control signals Sp and Sn. First, the signal Sp is set to High and the signal Sn is set to Low to cut off the power supply potential (Vdd). Then, potentials to be compared are applied to V1 and V2. Thereafter, when the signal Sp is set to Low, the signal S n is set to High, and the power supply potential (Vdd) is supplied, if the potentials V1in and V2 in to be compared satisfy a relationship of V1in>V2in, an output of V1 becomes High and an output of V2 becomes Low , and if the relationship V1in<V2in is satisfied, the output of V1 becomes Low and the output of V2 becomes Hig h. Using such a relationship, the difference between V1in and V2in can be amplified .

[0101] <Application Example 2> Next, a circuit configuration different from the circuit configuration shown in FIG. 2 will be described with reference to FIG. 5.

[0102] ​Figure 5(A) is an example of a circuit diagram of a semiconductor device having (m × n) memory cells 170. The configuration of memory cell 170 in Figure 5(A) is the same as in Figure 2(B), so a detailed explanation is not necessary. The "Akira" part will be omitted.

[0103] The semiconductor device shown in Figure 5(A) has m write word lines WWL (where m is an integer greater than or equal to 2) and m read word lines RWL, n source lines SL (where n is an integer greater than or equal to 2), and n The bit line BL, n signal lines S, and memory cells 170 arranged in m rows x n columns. A matrix array of memory cells, a potential conversion circuit 180, and n bits A first drive circuit 190 connected to line BL and n signal lines S, and m write words. A second drive circuit 192 is connected to line WWL and m read word lines RWL, and Here, the potential conversion circuit 180 is connected to the second drive circuit 192 by wiring VHL. The second drive circuit 192 outputs a potential higher than the power supply potential VDD (high potential: VH). In this embodiment, the WRITE and READ wirings are connected to potential conversion circuits. By connecting to 180, the potential is converted to match the output of the first drive circuit 190. However, the disclosed invention is not limited to this. Potential conversion circuit 180, first drive circuit The 190 and the second drive circuit 192 are connected by wiring WRITE and wiring READ. It's also fine to have a structure that doesn't involve continuation.

[0104] In addition, the address selection signal line A is connected to the second drive circuit 192. Selection signal line A is a wire that transmits a signal to select the row address of a memory cell.

[0105] Regarding the first drive circuit 190 and the second drive circuit 192 shown in Figure 5(A), see Figure 24. Refer to the explanation. The first drive circuit 190 and the second drive circuit 192 are connected by wiring. And connected by wiring READ. Also, wiring WRITE and wiring READ Each of these is connected to the potential conversion circuit 180.

[0106] The first drive circuit 190 includes a readout circuit 211, a control circuit 212, and a delay circuit 213. It is composed of a buffer circuit 214 and an input terminal IN, control circuit 212, delay It is connected to the signal line S via circuit 213 and buffer circuit 214. Also, bit The readout circuit 211, which is connected to line BL, is connected to the output terminal OUT.

[0107] The second drive circuit 192 includes a decoder circuit 221, a control circuit 222, and a buffer circuit 22 It consists of 3, a buffer circuit 224, and a level shift circuit 225. The select signal line A is connected to the decoder circuit 221. Also, the decoder circuit 221 is It is connected to the control circuit 222, and the control circuit 222 is connected to the level shift circuit 225 and the battery It is connected to the write word line WWL via circuit 223. Also, control circuit 22 2 is connected to the read word line RWL via the buffer circuit 224. For the output circuit 211, please refer to Figure 22, and for the delay circuit 213, please refer to Figure 4. Here, the write word line WWL outputs either GND or VH.

[0108] Data writing, retention, and reading are the same as in Figure 2. However, the configuration During writing, the potential of the writing word line WWL is set to a potential higher than the power supply potential. can be set to (VH). Accordingly, a sufficiently high potential can be applied to the node FG , enabling longer-term data retention. In addition, the discriminating power of data is improved.

[0109] As an example of the potential conversion circuit 180, FIG. 6 shows an example of a booster circuit that performs 4-stage boosting. FIG. 6 illustrates that, the input terminal of the first transistor 1300 (here, the source terminal or the drai n terminal, which refers to the terminal connected to the gate terminal) is supplied with the power supply potential VDD . The output terminal of the first transistor 1300 (here, the source terminal or the drain termi nal, which refers to the terminal not connected to the gate terminal) is connected to the second transistor 131 0's input terminal and one terminal of the first capacitive element 1350. Similarly, the secon d transistor 1310's output terminal is connected to the input terminal of the third transistor 1320 and the secon d capacitive element 1360's one terminal. The following structure is the same, thus detailed description is omitted, but it can also be stated that one terminal of the n-th capacitive element is connected to the output terminal of the n-th transistor (n is a natural number). In FIG. 6, the output terminal of the final-stage transistor is outp ut terminal connected to a transistor 1390 which is connected to the power supply VDD, but the present invention is not limited to this configuration . For example, a configuration in which a capacitor connected to the ground potential GND is further added may also be adopte d. Note that in FIG. 6, the output of the fifth transistor 1340 serves as the output VH of the booster circuit .

[0110] Furthermore, the clock signal CP_CLK is input to the other terminal of the second capacitive element 1360 and the other terminal of the fourth capacitive element 1380 Additionally, the other terminal of the first capacitive element 1350 The other terminal of the third capacitive element 1370 is connected to the inverted clock signal CP_CLK. The clock signal CP_CLKB is input. That is, the other end of the 2k capacitance element The child is input with the clock signal CP_CLK, and the other terminal of the 2k-1 capacitance element is connected to it. It can be said that the inverted clock signal CP_CLKB is input (k: natural number). Of course, The lock signal CP_CLK and the inverting clock signal CP_CLKB should be used interchangeably. It is possible.

[0111] When the clock signal CP_CLK is Low, i.e., when the inverted clock signal CP_CLKB is Low If the value is High, the second capacitive element 1360 and the fourth capacitive element 1380 are filled. Nodes N1 and N3 are powered and capacitively coupled with the inverted clock signal CP_CLKB. The potential is a predetermined voltage (corresponding to the potential difference between the High and Low states of the clock signal CP_CLK). The voltage is increased by (amount). Meanwhile, the node capacitively couples with the clock signal CP_CLK. The potentials of nodes N2 and N4 are lowered by a predetermined voltage.

[0112] As a result, the charge is transferred through the second transistor 1310 and the fourth transistor 1330. The system moves, and the potentials of nodes N2 and N4 are raised to predetermined values.

[0113] Next, when the clock signal CP_CLK becomes High and the inverted clock signal becomes Low, The potentials of nodes N2 and N4 are further increased. Meanwhile, the potentials of nodes N1 and N4 The potential of N3 is lowered by a predetermined voltage.

[0114] As a result, the first transistor 1300, the third transistor 1320, and the fifth transistor Charge moves through ZISTA 1340, resulting in nodes N1, N3 and N The potential at point 5 will be raised to the predetermined potential. In this way, each node The potential at which is V N5 =V N4(CP_CLK=High) >V N3(CP_CLK=Lo w) >V N2(CP_CLK=High) >V N1(CP_CLK=Low) >Vdd and This results in a voltage boost. Note that the boost circuit configuration is limited to those that perform a 4-stage boost. It is not fixed. The number of stages in the boost circuit can be changed as needed.

[0115] Furthermore, the transistors used in the boost circuit include oxide semiconductors with good off-current characteristics. By using transistors, the voltage holding time at each node can be extended.

[0116] Next, regarding the level shift circuit 225 (level shifter) provided in the second drive circuit 192... I will explain.

[0117] Figures 7 and 8 show examples of boost level shift circuit diagrams. The configuration of the level shifter shown in Figure 7. The following applies: The source terminal of the first p-type transistor 1200 and the third p-type transistor The source terminals of the 1230 are both electrically connected to a power supply that provides a potential of VH. The drain terminal of the first p-type transistor 1200 is connected to the second p-type transistor 1210. The source terminal is electrically connected to the drain terminal of the third p-type transistor 1230, It is electrically connected to the source terminal of the fourth p-type transistor 1240. The drain terminal of transistor 1210 is the drain terminal of the first n-type transistor 1220. and electrically connected to the gate terminal of the third p-type transistor 1230, and the fourth p-type transistor The drain terminal of transistor 1240 is connected to the drain terminal of the second n-type transistor 1250. It is electrically connected to the gate terminal of the first p-type transistor 1200. The source terminal of the first n-type transistor 1220 and the source terminal of the second n-type transistor 1250 Both children are given GND (=0[V]).

[0118] In Figure 7, the input signal (I) is connected to the gate terminal of the second p-type transistor 1210, and the The gate terminal of the n-type transistor 1220 is input to the inverted signal (IB) of the input signal. This is the gate terminal of the fourth p-type transistor 1240 and the second n-type transistor 1250 The gate terminal is input to the output signal (O) of the fourth p-type transistor 1240. It is taken out from the drain terminal. Also, from the drain terminal of the second p-type transistor 1210. It is also possible to extract the inverted signal (OB) of the output signal.

[0119] The basic operation of the level shifter shown in Figure 7 will be explained. When a High signal is input to the input signal (I)... When this happens, the first n-type transistor 1220 becomes conductive, and the third p-type transistor When the potential GND is input to the gate terminal of transistor 1230, the third p-type transistor 1230 is led When the system is in operation, a Low signal is output to the inverted signal (OB) of the output signal. The potential becomes GND. On the other hand, the inverting input signal (IB) is Low at this time, so the fourth The first p-type transistor 1240 becomes conductive, and the second n-type transistor 1250 becomes non-conductive. The circuit becomes open. Here, the third p-type transistor 1230 and the fourth p-type transistor 12 Since both 40 are in a conductive state, a High is output to the output signal (O), and at this time the The rank will be VH.

[0120] When the potential of the input signal (I) is low, the transistor of the level shifter shown in Figure 7 is as described above. It operates in the opposite way, outputting a Low signal from the output signal (O), and the potential at this time is GND and Yes.

[0121] In this way, an output signal (O) can be obtained by converting the amplitude of the input signal. In other words, the level shifter shown in Figure 7 changes the power of the input signal (I) between High and Low. The potential difference can be converted into the potential difference between the High and Low states of the output signal (O).

[0122] Figure 8 shows an example of a boost level shift circuit diagram different from Figure 7. The level shifter shown in Figure 8... The configuration is as follows: the source terminal of the first p-type transistor 1260 and the second p The source terminals of the type 1280 transistor are electrically connected to a power supply that provides a potential VH. The drain terminal of the first n-type transistor 1270 is connected to the first p-type transistor 1 The drain terminal of transistor 260 and the gate terminal of the second p-type transistor 1280 are electrically connected. The drain terminal of the second n-type transistor 1290 is connected to the second p-type transistor 12 The drain terminal of 80 and the gate terminal of the first p-type transistor 1260 are electrically connected. Furthermore, the source terminal of the first n-type transistor 1270 and the second n-type transistor Both source terminals of the Ta1290 are connected to GND (=0[V]).

[0123] In Figure 8, the input signal (I) is input to the gate terminal of the first n-type transistor 1270. The inverted signal (IB) of the input signal is then sent to the gate terminal of the second n-type transistor 1290. The input is received. The output signal (O) is taken from the drain terminal of the second n-type transistor 1290. It is then output. Also, the output signal is inverted from the drain terminal of the first n-type transistor 1270. It is also possible to extract the signal (OB).

[0124] The basic operation of the level shifter shown in Figure 8 will be explained. When a High signal is input to the input signal (I)... When this happens, the first n-type transistor 1270 becomes conductive, and the second p-type transistor When the potential GND is input to the gate terminal of transistor 1280, the second p-type transistor 1280 is led When the system is in operation, a Low signal is output to the inverted signal (OB) of the output signal. The potential becomes GND. On the other hand, the inverting input signal (IB) is Low at this time, so the second The n-type transistor 1290 becomes non-conductive. Here, the second p-type transistor 12 Since 80 is in a conducting state, a High is output to the output signal (O), and the potential at this time is It becomes VH.

[0125] When the potential of the input signal (I) is Low, the transistor of the level shifter shown in Figure 8 is as described above. It operates in the opposite way, outputting a Low signal from the output signal (O), and the potential at this time is GND and Yes.

[0126] In this way, an output signal (O) can be obtained by converting the amplitude of the input signal. In other words, the level shifter shown in Figure 8 changes the power of the input signal (I) between High and Low. The potential difference can be converted into the potential difference between the High and Low states of the output signal (O).

[0127] The potential converted to a high potential by the potential conversion circuit 180 shown in Figure 6 is included in the second drive circuit 192. Using the boost level shifters shown in Figures 7 and 8, each word line WWL is used to write each word line. The output is sent to the memory cell 170. Furthermore, the electric current is converted to a high potential by the potential conversion circuit 180. The position is adjusted using a boost level shifter included in the first drive circuit 190, from the signal line S to each It is also possible to configure it to output to a Morisel 170.

[0128] The configurations and methods described in this embodiment are suitable for use with configurations and methods described in other embodiments. They can be used in any combination.

[0129] (Embodiment 2) In this embodiment, the configuration of a semiconductor device and a method for manufacturing the same according to one aspect of the disclosed invention are described below. This will be explained with reference to Figures 9 to 13.

[0130] <Cross-sectional and planar configurations of semiconductor devices> Figure 9 shows an example of the configuration of a semiconductor device. Figure 9(A) shows a cross-section of the semiconductor device, and Figure 9( Figure B) shows the planes of the semiconductor device. Here, Figure 9(A) is the same as A in Figure 9(B). This corresponds to the cross-sections at 1-A2 and B1-B2. (See Figures 9(A) and 9(B)) The semiconductor device has a transistor 160 made of a first semiconductor material at the bottom, and at the top The device has a transistor 162 made of a second semiconductor material. It is desirable that the first semiconductor material and the second semiconductor material be different materials. For example, the first semiconductor The first material is a semiconductor material other than an oxide semiconductor (such as silicon), and the second semiconductor material is an oxide semiconductor. It can be made into a semiconductor. Transistors using materials other than oxide semiconductors can operate at high speed. This is easy. On the other hand, transistors using oxide semiconductors have characteristics that make long-term operation difficult. Enables charge retention.

[0131] The above explanation assumes that all transistors are n-channel transistors. However, it goes without saying that p-channel transistors can be used. The technical essence of the invention is to have sufficient off-current, such as in oxide semiconductors, to retain information. The advantage lies in using semiconductor materials in transistor 162 that can reduce semiconductors. This section describes the specific configuration of the semiconductor device, including the materials used and the structure of the semiconductor device. It doesn't have to be limited to physical objects.

[0132] In Figure 9, transistor 160 is located on a substrate containing a semiconductor material (e.g., silicon). A channel formation region 116 is provided in 00, and is provided so as to sandwich the channel formation region 116 The impurity region 120, the metal compound region 124 adjacent to the impurity region 120, and the channel A gate insulating layer 108 provided on the gate forming region 116, and a gate insulating layer 108 provided on the gate insulating layer 108 It has a gate electrode 110 and a drain electrode. Note that in the figure, the source electrode and drain electrode are not explicitly shown. Although they may not have electrodes, for convenience, we refer to such devices as transistors. There is a connection. Also, in this case, in order to explain the connection relationship of the transistor, the source region and do The rain region is sometimes included in the terminology used to refer to the source electrode and drain electrode. In this context, the term "source electrode" may include the source region.

[0133] Furthermore, an element isolation insulating layer 106 is provided on the substrate 100 so as to surround the transistor 160. An insulating layer 128 and an insulating layer 130 are provided to cover the transistor 160. Furthermore, in order to achieve high integration, as shown in Figure 9, transistor 160 is It is desirable to have a configuration without an idwall insulating layer. On the other hand, transistor 160 When prioritizing the characteristics of the gate electrode 110, a sidewall insulating layer is provided on the side surface of the gate electrode 110. An impurity region 120 may be provided, which includes regions with different concentrations of pure substances.

[0134] In Figure 9, transistor 162 has a source electrode or drain provided on the insulating layer 130. Inlet electrode 142a, and source electrode or drain electrode 142b, and source electrode or The drain electrode 142a and the source electrode or drain electrode 142b are electrically connected. The oxide semiconductor layer 144, the source electrode or drain electrode 142a, and the source electrode Alternatively, the drain electrode 142b, the gate insulating layer 146 covering the oxide semiconductor layer 144, and the gate A gate electrode 148 is provided on the insulating layer 146 so as to be superimposed on the oxide semiconductor layer 144. a and the gate between the source electrode or drain electrode 142a and the oxide semiconductor layer 144. The insulating layer 143a in the region superimposed on electrode 148a, and the source electrode or drain electrode 142 The insulating layer 143 in the region between b and the oxide semiconductor layer 144 that overlaps with the gate electrode 148a. It has b and . Furthermore, the capacitance between the source electrode or drain electrode and the gate electrode is reduced. In order to reduce it, it is desirable to provide insulating layer 143a and insulating layer 143b, It is also possible to omit the layer 143a and the insulating layer 143b.

[0135] Here, the oxide semiconductor layer 144 is sufficiently free of impurities such as hydrogen, and It is desirable that the material be highly purified by supplying sufficient oxygen. Specifically, for example, the hydrogen concentration of the oxide semiconductor layer 144 is 5 × 10⁻⁶. 19 atoms / cm 3 The following is preferable: 5 x 10 18 atoms / cm 3 The following is more preferable: 5 x 10 17 a toms / cm 3 The following applies. Note that the hydrogen concentration in the oxide semiconductor layer 144 is secondary. Secondary Ion Mass Spectrometry (SIMS) This is measured by (scopy). In this way, the hydrogen concentration is sufficiently reduced to achieve high purity. The defect levels in the energy gap caused by oxygen deficiency are converted and, with sufficient oxygen supply, In the reduced oxide semiconductor layer 144, the carrier concentration is 1 × 10⁻⁶ 12 / cm 3 Less than desired Or, 1 x 10 11 / cm 3 Less than 1.45 × 10 10 / cm 3 Less than and Yes. For example, the off-current at room temperature (25°C) (here, per unit channel width (1 μm) The value of (1 zA) is 100 zA (1 zA (zeptoampere) is 1 × 10⁻¹⁰ -21 A) The following is preferable This becomes 10 zA or less. Thus, the oxidation is i-type (intrinsic) or substantially i-type. By using a semiconductor material, it is possible to obtain a transistor 162 with extremely excellent off-current characteristics. can.

[0136] Furthermore, in transistor 162 of Figure 9, leakage between elements caused by miniaturization is suppressed. To achieve this, an island-shaped oxide semiconductor layer 144 is used, but the island-shaped processing A configuration without this may be adopted. If the oxide semiconductor layer is not processed into an island shape, the processing will be affected. This prevents contamination of the oxide semiconductor layer 144 due to chipping.

[0137] In Figure 9, the capacitive element 164 is a source electrode or drain electrode 142a, an oxide semiconductor. It consists of layer 144, gate insulating layer 146, and electrode 148b. That is, source The electrode or drain electrode 142a functions as one of the electrodes of the capacitive element 164, and electrode 1 48b will function as the other electrode of the capacitive element 164.

[0138] In addition, in the capacitive element 164 of Figure 9, an oxide semiconductor layer 144 and a gate insulating layer 146 are stacked. By doing so, insulation is provided between the source electrode or drain electrode 142a and electrode 148b. Sufficient performance can be ensured. Of course, in order to ensure sufficient capacity, oxide semiconductors A capacitive element 164 without a body layer 144 may also be used. A capacitive element 164 having a similarly formed insulating layer may also be used. If it is not necessary, it is also possible to omit the capacitive element 164.

[0139] Furthermore, in transistor 162 and capacitive element 164, the source electrode or drain electrode The ends of electrode 142a and the source electrode or drain electrode 142b are tapered. It is preferable to do so. Source electrode or drain electrode 142a, source electrode or drain By making the end of electrode 142b tapered, the coverage of the oxide semiconductor layer 144 is improved. This is because it improves performance and prevents breakage. Here, the taper angle is, for example, 3 The taper angle shall be between 0° and 60°. Note that the taper angle refers to a layer having a tapered shape (for example, The source electrode or drain electrode 142a) is positioned perpendicular to its cross-section (the plane perpendicular to the surface of the substrate). This shows the angle of inclination between the side and bottom surfaces of the layer when observed from a straight direction.

[0140] In this embodiment, transistor 162 and capacitive element 164 are connected to transistor 160. They are arranged in a superimposed manner. By adopting such a planar layout, high Integration is possible. For example, if the minimum processing dimension is F, the area occupied by the memory cell is 15 F 2 ~25F 2 It is possible to do so.

[0141] An insulating layer 150 is provided on the transistor 162 and the capacitive element 164, An insulating layer 152 is provided on the edge layer 150. Then, a gate insulating layer 146, insulating layer An electrode 154 is provided in the opening formed in the insulating layer 152, etc. Wiring 156 is formed on top, which connects to electrode 154. Note that in Figure 9, electrode 154 is used The source electrode or drain electrode 142b is connected to the wiring 156, but disclosure The invention is not limited thereto. For example, the source electrode or drain electrode 142b can be directly... It may be brought into contact with the metal compound region 124. Alternatively, the wiring 156 may be directly connected to the source electrode or It may also be brought into contact with the drain electrode 142b.

[0142] <Methods for fabricating semiconductor devices> Next, we will describe an example of a method for manufacturing the above semiconductor device. Below, we will first explain the lower part The method for fabricating the lunger 160 will be explained with reference to Figures 10 and 11, and then the above Figures 12 and 13 show the method for fabricating the transistor 162 and the capacitance element 164. Refer to the explanation.

[0143] <Method for fabricating the lower transistor> First, prepare a substrate 100 containing semiconductor material (see Figure 10(A)). The substrate 100 can be a single-crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate It is possible to apply plates, compound semiconductor substrates such as silicon germanium, and SOI substrates. Yes. Here, when a single-crystal silicon substrate is used as the substrate 100 containing semiconductor material. An example of this will be shown. Generally speaking, a "SOI substrate" is a substrate with silicon on an insulating surface. This refers to a substrate having a semiconductor layer, but in this specification, it refers to a substrate having a silicon layer on an insulating surface. This concept is used to include substrates with a semiconductor layer made of materials other than semiconductors. The semiconductor layer of the "SOI substrate" is not limited to a silicon semiconductor layer. The substrate has a configuration in which a semiconductor layer is provided on an insulating substrate such as a glass substrate, with an insulating layer in between. It shall include the following.

[0144] In particular, when using a single-crystal semiconductor substrate such as silicon as the substrate 100 containing semiconductor material, In such cases, it is preferable because it can speed up the read operation of the semiconductor device.

[0145] A protective layer 102 is formed on the substrate 100, which serves as a mask for forming an element isolation insulating layer. (See Figure 10(A)). The protective layer 102 can be, for example, silicon oxide or silicon nitride. An insulating layer made of silicon oxynitride or the like can be used. In order to control the threshold voltage of the transistor, an impurity is imparted to impart n-type conductivity. Monochemical elements or impurity elements that impart p-type conductivity may be added to the substrate 100. In the case of ricon, impurities that impart n-type conductivity include, for example, phosphorus and arsenic. This can be achieved. Furthermore, examples of impurities that impart p-type conductivity include boron and aluminum. Materials such as nium and gallium can be used.

[0146] Next, etching is performed using the protective layer 102 as a mask, and the material covered by the protective layer 102 is then... A portion of the substrate 100 in the area where there is no semiconductor material (the exposed area) is removed. This removes the other semiconductor material. A semiconductor region 104 is formed, separated from the other region (see Figure 10(B)). Dry etching is preferred for this process, but wet etching may also be used. The etching gas and etching solution should be selected appropriately according to the material to be etched. It is possible.

[0147] Next, an insulating layer is formed to cover the semiconductor region 104, and the region superimposed on the semiconductor region 104 By selectively removing the insulating layer, an element isolation insulating layer 106 is formed (see Figure 10(C)). (See image). The insulating layer is formed using silicon oxide, silicon nitride, silicon oxynitride, etc. The insulating layer can be removed using polishing treatments such as CMP (chemical mechanical polishing) or etching. There are various processes such as polishing, but any of them can be used. Furthermore, after the formation of the semiconductor region 104, Alternatively, after the formation of the element isolation insulating layer 106, the protective layer 102 is removed.

[0148] Next, an insulating layer is formed on the surface of the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. To accomplish.

[0149] The insulating layer will later become the gate insulating layer, for example, the heat treatment of the surface of the semiconductor region 104 ( It can be formed by thermal oxidation treatment or thermal nitriding treatment. Instead of heat treatment, high density Plasma treatment may be applied. High-density plasma treatment can be performed using, for example, helium (He), a Noble gases such as argone (Ar), krypton (Kr), and xenon (Xe), oxygen, and nitrogen oxides. This can be done using a mixed gas such as ammonia, nitrogen, and hydrogen. Of course, CVD The insulating layer may be formed using methods such as silicon oxide or sputtering. Silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, Yttrium oxide, hafnium silicate (HfSi x O y (x>0, y>0), nitrogen Hafnium silicate (HfSi) with added x O y N z (x>0, y>0, z>0) , nitrogen-added hafnium aluminate (HfAl x O y N z (x>0, y>0, z It is desirable to have a single-layer or multi-layer structure including >0)). Also, the thickness of the insulating layer is For example, the wavelength is 1 nm to 100 nm, preferably 10 nm to 50 nm. It is possible.

[0150] The layer containing conductive material is made of metallic materials such as aluminum, copper, titanium, tantalum, and tungsten. It can be formed using [a specific method]. Furthermore, using semiconductor materials such as polycrystalline silicon, conductive [a specific method] can be used. A layer containing the material may be formed. The formation method is not particularly limited and may include vapor deposition, CVD, and sputtering. Various film deposition methods such as taring and spin coating can be used. The example shown illustrates a case where a layer containing a conductive material is formed using a metallic material. Let's assume that.

[0151] Subsequently, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108 , forming the gate electrode 110 (see Figure 10(C)).

[0152] Next, phosphorus (P) or arsenic (As) is added to the semiconductor region 104 to form a channel region. Forms region 116 and impurity region 120 (see Figure 10(D)). Note that here n-type Although phosphorus or arsenic is added to form a transistor, it forms a p-type transistor. In such cases, impurity elements such as boron (B) or aluminum (Al) can be added. The concentration of impurities to be added can be set as appropriate, but the semiconductor device is becoming increasingly miniaturized. In such cases, it is desirable to increase the concentration.

[0153] Furthermore, a sidewall insulating layer is formed around the gate electrode 110, and different impurity elements are used. It is also possible to form an impurity region by adding impurities at a specific concentration.

[0154] Next, a metal layer 122 is formed to cover the gate electrode 110, impurity region 120, etc. (Figure) See 11(A). The metal layer 122 is formed by vacuum deposition, sputtering, or spin coating. It can be formed using various film deposition methods such as the method. The metal layer 122 is in the semiconductor region 10 A metal material is used that reacts with the semiconductor material constituting 4 to form a low-resistance metal compound. It is desirable to form it in this way. Examples of such metallic materials include titanium and tantalum. Examples include tungsten, nickel, cobalt, and platinum.

[0155] Next, heat treatment is applied to react the metal layer 122 with the semiconductor material. This causes A metal compound region 124 is formed in contact with the pure material region 120 (see Figure 11(A)). When using polycrystalline silicon or the like as the gate electrode 110, the gold of the gate electrode 110 A metal compound region will also be formed in the area that comes into contact with the member layer 122.

[0156] As for the above heat treatment, for example, heat treatment by irradiation with a flash lamp can be used. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds is important. To improve controllability, it is desirable to use a method that can achieve heat treatment in a very short time. It appears that the above-mentioned metallic compound region is formed by the reaction between a metallic material and a semiconductor material. This is a region in which conductivity is sufficiently enhanced. This allows for a significant reduction in electrical resistance and improvement of the device characteristics. After forming region 124, the metal layer 122 is removed.

[0157] Next, insulating layers 128 and 130 are applied to cover each of the components formed by the above-described process. Formed (see Figure 11(B)). Insulating layers 128 and 130 are made of silicon oxide and oxynitriding. Formed using materials containing inorganic insulating materials such as silicon, silicon nitride, and aluminum oxide. This is possible. In particular, a low-dielectric material can be used for the insulating layer 128 and the insulating layer 130. By using this method, it is possible to significantly reduce capacitance caused by the overlapping of various electrodes and wiring. Therefore, it is preferable. Furthermore, the insulating layer 128 and insulating layer 130 are porous using these materials. A porous insulating layer may be applied. In a porous insulating layer, the dielectric constant is lower compared to a high-density insulating layer. Because this decreases, it is possible to further reduce the capacitance caused by electrodes and wiring. The insulating layer 128 and the insulating layer 130 are formed using organic insulating materials such as polyimide and acrylic. It is also possible to do so. Note that here, a laminated structure of insulating layer 128 and insulating layer 130 is used. However, the embodiments of the disclosed invention are not limited thereto. It may consist of one layer or three or more layers. A layered structure would also work.

[0158] As a result, a transistor 160 is formed using a substrate 100 containing semiconductor material (Figure See 11(B). Such transistors 160 have the characteristic of being capable of high-speed operation. It has this feature. Therefore, by using this transistor as a readout transistor, This allows for high-speed retrieval of information.

[0159] Subsequently, as a pre-formation treatment for transistor 162 and capacitive element 164, an insulating layer 128 The insulating layer 130 is subjected to CMP treatment to expose the upper surface of the gate electrode 110 (Figure 11( See C). In addition to CMP treatment, other processes for exposing the upper surface of the gate electrode 110 include E. While it is possible to apply processes such as ching, the goal is to improve the characteristics of transistor 162. Therefore, it is desirable to make the surfaces of insulating layer 128 and insulating layer 130 as flat as possible. .

[0160] Furthermore, before and after each of the above processes, additional steps are taken to form electrodes, wiring, semiconductor layers, insulating layers, etc. It may include a degree of [something]. For example, the wiring structure may be a laminated structure of an insulating layer and a conductive layer. By employing a multilayer wiring structure, it is also possible to realize highly integrated semiconductor devices.

[0161] <Method for fabricating the upper transistor> Next, a conductive layer is formed on the gate electrode 110, insulating layer 128, insulating layer 130, etc. The electrode layer is selectively etched to remove the source electrode or drain electrode 142a, and the source electrode Alternatively, the drain electrode 142b is formed (see Figure 12(A)).

[0162] The conductive layer is produced using PVD methods such as sputtering, or CVD methods such as plasma CVD. It can be formed by [doing something]. Also, the conductive layer material can be aluminum, chromium, copper, Elements selected from tantalum, titanium, molybdenum, and tungsten, or the elements mentioned above, are used as components. Alloys such as manganese, magnesium, zirconium, and beryllium can be used. Using materials such as luminum, neodymium, scandium, or a combination of these. That's good too.

[0163] The conductive layer may be a single layer or a laminated structure of two or more layers. For example, titanium Single-layer structures of silicon films and titanium nitride films, single-layer structures of silicon-containing aluminum films, aluminum A two-layer structure in which a titanium film is laminated on a titanium film, and a two-layer structure in which a titanium film is laminated on a titanium nitride film. Examples include a three-layer structure in which a titanium film, an aluminum film, and another titanium film are laminated. Oh, when the conductive layer is a single-layer structure of titanium film or titanium nitride film, it has a tapered shape. Source electrode or drain electrode 142a, and source electrode or drain electrode 142 One advantage is that it is easy to process into form b.

[0164] Furthermore, the conductive layer may be formed using a conductive metal oxide. These include indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), and oxide Indium tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO), oxidation Indium zinc oxide alloy (In2O3-ZnO), or these metal oxide materials Products containing lycon or silicon oxide can be used.

[0165] Etching of the conductive layer involves the formation of the source electrode or drain electrode 142a, and the saw It is preferable that the end of the drain electrode 142b be tapered. Here, the taper angle is preferably, for example, 30° or more and 60° or less. The ends of the source electrode or drain electrode 142a and the source electrode or drain electrode 142b The gate insulating layer 14 is formed later by etching it into a tapered shape. This improves the coverage of 6 and prevents breakage at the edges.

[0166] The channel length (L) of the upper transistor is the source electrode or drain electrode 142a, This is determined by the distance between the lower ends of the source electrode or drain electrode 142b. Mask formation dew used when forming transistors with a channel length (L) of less than 25 nm When using light, extremely ultraviolet (Ultraviolet) light with wavelengths of a few nanometers to tens of nanometers is used. It is preferable to use aviolet. Ultraviolet exposure offers high resolution and depth of field. It is also large. Therefore, the channel length (L) of the transistor that is formed later should be 10 nm or more. It is also possible to set the size to 000 nm (1 μm) or less, which can increase the operating speed of the circuit. Furthermore, miniaturization makes it possible to reduce the power consumption of semiconductor devices.

[0167] Furthermore, an insulating layer that functions as a base layer may be provided on top of insulating layer 128 and insulating layer 130. The insulating layer can be formed using methods such as PVD or CVD.

[0168] Next, an insulating layer 143a is placed on the source electrode or drain electrode 142a, and the source electrode or An insulating layer 143b is formed on the drain electrode 142b (see Figure 12(B)). ). The insulating layer 143a and insulating layer 143b are connected to the source electrode or drain electrode 142a and After forming an insulating layer covering the source electrode or drain electrode 142b, select the insulating layer. It can be formed by etching. Also, insulating layer 143a and insulating layer 143b This is formed so as to overlap with a portion of the gate electrode that is formed later. By doing so, the capacitance between the gate electrode and the source or drain electrode is reduced. It is possible.

[0169] Insulating layer 143a and insulating layer 143b are silicon oxide, silicon oxynitride, silicon nitride, acid It can be formed using materials containing inorganic insulating materials such as aluminum oxide. In particular, insulating By using low-k dielectric materials for layer 143a and insulating layer 143b, the gate This makes it possible to significantly reduce the capacitance between the electrode and the source or drain electrode. Therefore, it is preferable. Furthermore, the insulating layer 143a and insulating layer 143b are porous using these materials. A porous insulating layer may be applied. In a porous insulating layer, the dielectric constant is lower compared to a high-density insulating layer. Because the capacitance decreases, the capacitance between the gate electrode and the source or drain electrode is further reduced. It is possible to reduce it.

[0170] Furthermore, this reduces the capacitance between the gate electrode and the source or drain electrode. Therefore, it is preferable to form insulating layer 143a and insulating layer 143b, but the insulating layer It is also possible to have a configuration that does not include this feature.

[0171] Next, source electrode or drain electrode 142a, and source electrode or drain electrode 1 After forming an oxide semiconductor layer to cover 42b, the oxide semiconductor layer is selectively etched. This process forms an oxide semiconductor layer 144 (see Figure 12(C)).

[0172] The oxide semiconductor layer is made of quaternary metal oxides such as In-Sn-Ga-Zn-O or ternary metal oxides. The group oxides are In-Ga-Zn-O, In-Sn-Zn-O, and In-Al-Zn- O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, Sn-Al-Zn-O-based, Binary metal oxides include In-Zn-O, In-Ga-O, Sn-Zn-O, and Al -Zn-O system, Zn-Mg-O system, Sn-Mg-O system, In-Mg-O system, and monocrystalline metals It can be formed using oxides such as In-O, Sn-O, and Zn-O.

[0173] In particular, In-Ga-Zn-O oxide semiconductor materials have sufficiently high resistance in the absence of an electric field. Because the current can be made sufficiently small, and the field effect mobility is also high, semiconductors It is suitable as a semiconductor material for use in the device.

[0174] A typical example of an In-Ga-Zn-O oxide semiconductor material is InGaO3(ZnO). m There are some that are written as (m>0, m: non-natural number). Also, M is used instead of Ga, and I nMO3(ZnO) m Oxide semiconductor materials that are expressed as (m>0, m: non-natural number) Yes, there is. Here, M is gallium (Ga), aluminum (Al), iron (Fe), nickel. One or multiple metallic elements selected from (Ni), manganese (Mn), cobalt (Co), etc. It shows a number of metallic elements. For example, M can be Ga, Ga and Al, Ga and Fe, G a and Ni, Ga and Mn, Ga and Co, etc. can be applied. The composition described is derived from the crystal structure and should be noted as merely one example. do.

[0175] For fabricating oxide semiconductor layers using the sputtering method, the target is In:Ga:Zn= It is preferable to use a material with a composition ratio of 1:x:y (where x is greater than or equal to 0, and y is between 0.5 and 5). It is suitable. For example, the composition In2O3:Ga2O3:ZnO = 1:1:2 [molar ratio] Metal oxide targets with a specific ratio can be used. Also, In2O3:Ga2 Metal oxide targets having a composition ratio of O3:ZnO=1:1:1 [molar ratio], and I Metal oxides with a composition ratio of n2O3:Ga2O3:ZnO = 1:1:4 [molar ratio] The target and the composition ratio of In2O3:Ga2O3:ZnO=1:0:2 [molar ratio] It is also possible to use metal oxide targets that possess certain properties.

[0176] In this embodiment, an amorphous oxide semiconductor layer is made of an In-Ga-Zn-O-based metal oxide The material will be formed by sputtering using a physical target.

[0177] The relative density of metal oxides in the metal oxide target is 80% or more, preferably 95% or more. More preferably, it is 99.9% or higher. A metal oxide target with a high relative density is used. This makes it possible to form an oxide semiconductor layer with a dense structure.

[0178] The formation atmosphere for oxide semiconductor layers can be a noble gas atmosphere (typically argon), an oxygen atmosphere, or... Alternatively, a mixed atmosphere of a noble gas (typically argon) and oxygen is preferable. In particular, impurities such as hydrogen, water, hydroxyl groups, and hydrides should be present at a concentration of 1 ppm or less (ideally). It is preferable to use a high-purity gas atmosphere in which impurities have been removed to a concentration of 10 ppb or less. .

[0179] When forming an oxide semiconductor layer, for example, the workpiece is kept in a processing chamber under reduced pressure. The temperature of the object to be processed is 100°C or higher and less than 550°C, preferably 200°C or higher and less than 400°C. Heat the workpiece so that it is positioned downwards. Alternatively, the temperature of the workpiece during the formation of the oxide semiconductor layer. The temperature may be set to room temperature (25℃ ± 10℃). Then, while removing moisture from the processing chamber, hydrogen Sputtered gas from which water and other impurities have been removed is introduced, and the oxide semiconductor layer is cut using the above target. To form. By forming an oxide semiconductor layer while heating the workpiece, the oxide semiconductor layer It is possible to reduce the impurities contained in the material. In addition, it is possible to reduce damage caused by sputtering. Yes, it is possible. To remove moisture from the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, using cryopumps, ion pumps, titanium sublimation pumps, etc. This can be done. Alternatively, a turbomolecular pump with a cold trap can be used. By using a cryopump or similar device to exhaust the system, hydrogen and water can be removed from the treatment chamber. This allows for a reduction in the impurity concentration in the oxide semiconductor layer.

[0180] For example, the formation conditions for the oxide semiconductor layer include a distance of 17 between the workpiece and the target. 0mm, pressure 0.4Pa, DC power 0.5kW, atmosphere oxygen (oxygen 100%) %) atmosphere, or argon (100% argon) atmosphere, or a mixture of oxygen and argon Conditions such as atmosphere can be applied. Note that a pulsed DC power supply is used. This reduces the amount of powdery material (also called particles or dust) generated during film formation, and also improves the film thickness distribution. This is preferable because it results in uniformity. The thickness of the oxide semiconductor layer is preferably 1 nm to 50 nm. The wavelength should be between 1 nm and 30 nm, more preferably between 1 nm and 10 nm. By using a thick oxide semiconductor layer, it is possible to suppress the short-channel effect associated with miniaturization. It is possible. However, the appropriate thickness depends on the oxide semiconductor material being applied and the application of the semiconductor device. Since the thickness varies, it can be selected according to the materials used and the intended application.

[0181] Furthermore, before forming the oxide semiconductor layer by sputtering, argon gas is introduced and plastic Reverse sputtering is performed to generate zuma, and deposits on the formed surface (e.g., the surface of the insulating layer 130) are removed. It is preferable to remove it. Here, reverse sputtering is the process in which sputtering is performed. Instead of making ions collide with the target, we will make ions collide with the treatment surface. This refers to a method of modifying a surface by causing ions to collide with the surface to be treated. In this method, a high-frequency voltage is applied to the surface being treated under an argon atmosphere, and plasma is generated near the workpiece. There are methods for generating it, among others. Note that nitrogen, helium, oxygen, etc. can be used instead of an argon atmosphere. You may apply a nighttime atmosphere.

[0182] Subsequently, it is desirable to perform a heat treatment (first heat treatment) on the oxide semiconductor layer. The first heat treatment removes excess hydrogen (including water and hydroxyl groups) from the oxide semiconductor layer. By optimizing the structure of the oxide semiconductor layer, the defect levels in the energy gap can be reduced. The temperature of the first heat treatment is, for example, 300°C or more and less than 550°C, or 400°C or more and 50°C. Keep the temperature below 0°C.

[0183] Heat treatment involves, for example, introducing the workpiece into an electric furnace using a resistance heating element, and performing the treatment under a nitrogen atmosphere. This can be done under conditions of 450°C for 1 hour. During this time, the oxide semiconductor layer is not exposed to the atmosphere. Furthermore, ensure that no water or hydrogen is mixed in.

[0184] Heat treatment equipment is not limited to electric furnaces; it also utilizes heat conduction or thermal radiation from a heated medium such as gas. A device that heats the object to be processed may be used. For example, LRTA (Lamp Ra PID Thermal Anneal) device, GRTA (Gas Rapid The RTA (Rapid Thermal Annealing) for devices such as thermal annealing equipment. ) The device can be used. The LRTA device uses halogen lamps and metal halide lamps. xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps This device heats the object to be processed by radiating light (electromagnetic waves) emitted from lamps such as fountains. A GRTA apparatus is a device that performs heat treatment using high-temperature gas. The gas used is argon. Noble gases such as nitrogen, or inert gases that do not react with the material being treated by heat treatment. It is used.

[0185] For example, as a first heat treatment, the object to be treated is placed in a heated inert gas atmosphere for several minutes. After interheating, a GRTA treatment may be performed in which the workpiece is removed from the inert gas atmosphere. Using GRTA treatment enables high-temperature heat treatment in a short time. Furthermore, the heat resistance temperature of the workpiece... It can be applied even under temperature conditions exceeding [a certain degree]. Furthermore, during the process, an inert gas is used, along with oxygen. You may switch to a gas containing [the specified substance]. Perform the first heat treatment in an oxygen-containing atmosphere. This is because it can reduce defect levels in the energy gap caused by oxygen deficiency. .

[0186] The inert gas atmosphere can be nitrogen or a noble gas (helium, neon, argon, etc.). It is desirable to apply an atmosphere whose main component is ( ) and which does not contain water, hydrogen, etc. For example, nitrogen, helium, neon, argon, and other noble gases introduced into heat treatment equipment. The purity should be 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher. That is, the impurity concentration should be 1 ppm or less, preferably 0.1 ppm or less.

[0187] In any case, the first heat treatment reduces impurities, resulting in a type i (intrinsic semiconductor) or type i By forming an oxide semiconductor layer that is extremely close to the original, transistors with extremely superior characteristics can be realized. It can be expressed.

[0188] By the way, the heat treatment described above (the first heat treatment) has the effect of removing hydrogen, water, etc. This heat treatment can also be called a dehydration treatment or a dehydrogenation treatment. Dehydrogenation treatment is performed after the formation of the oxide semiconductor layer or the gate insulating layer, and after the formation of the gate electrode. It can also be done at later times, such as afterwards. Hydrogenation treatment can be performed multiple times, not just once.

[0189] Etching of the oxide semiconductor layer can be performed either before or after the above heat treatment. It is also acceptable to proceed in this manner. Furthermore, from the perspective of miniaturizing the elements, it is preferable to use dry etching. Suitable, but wet etching may also be used. Regarding etching gas and etching solution... The appropriate method can be selected depending on the material to be etched. If there are no issues, the oxide semiconductor layer may be used without being processed into an island shape.

[0190] Next, a gate insulating layer 146 is formed in contact with the oxide semiconductor layer 144, and then gate insulating A gate electrode 148a is formed on layer 146 in the region where it overlaps with the oxide semiconductor layer 144. , an electrode 148b is formed in the region that overlaps with the source electrode or drain electrode 142a (Figure 12(D)).

[0191] The gate insulating layer 146 can be formed using methods such as CVD or sputtering. The gate insulating layer 146 is made of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. Mu, tantalum oxide, hafnium oxide, yttrium oxide, gallium oxide, hafnium silicate Kate (HfSi x O y (x>0, y>0), nitrogen-added hafnium silicate (HfSi x O y N z (x>0, y>0, z>0), nitrogen-added hafnium aluminum Minate (HfAl x O y N z Formed to include (x>0, y>0, z>0), etc. It is preferable to do so. The gate insulating layer 146 may be a single layer structure or a laminated structure. Good. Also, the thickness is not particularly limited, but when miniaturizing semiconductor devices, It is desirable to make it thin in order to ensure the operation of the DISTA. For example, when using silicon oxide In this case, the wavelength should be between 1 nm and 100 nm, preferably between 10 nm and 50 nm. can.

[0192] As mentioned above, thinning the gate insulation layer can lead to gate leakage caused by the tunnel effect, etc. This poses a problem. To resolve the gate leakage problem, the gate insulating layer 146 contains hafny oxide. HfSi x O y (x>0 , y>0)), nitrogen-doped hafnium silicate (HfSi x O y N z (x>0, y>0, z>0), nitrogen-added hafnium aluminate (HfAl x O y N z ( It is preferable to use high-dielectric constant (high-k) materials such as x>0, y>0, z>0). By using igh-k material for the gate insulating layer 146, electrical characteristics are ensured while the gate It becomes possible to increase the film thickness to suppress leakage. A film containing silicon oxide, silicon nitride, silicon oxide nitride, silicon oxide, and a It may also be a laminated structure with a film containing luminium or any other material.

[0193] After the formation of the gate insulating layer 146, a second heat treatment is performed under an inert gas atmosphere or an oxygen atmosphere. It is desirable to perform the treatment. The heat treatment temperature should be between 200°C and 450°C, preferably 25°C. The temperature range is between 0°C and 350°C. For example, heat treatment can be performed at 250°C for 1 hour under a nitrogen atmosphere. Yes, that's fine. By performing a second heat treatment, variations in the electrical characteristics of the transistors are reduced. This is possible. Also, if the gate insulating layer 146 contains oxygen, the oxide semiconductor layer 144 By supplying oxygen to the oxide semiconductor layer 144, oxygen vacancies are filled, and an i-type (intrinsic) semiconductor is formed. Alternatively, an oxide semiconductor layer 144 that is very close to type i can be formed.

[0194] In this embodiment, the second heat treatment is performed after the formation of the gate insulating layer 146. The timing of the second heat treatment is not limited to this. For example, the second heat treatment may be performed after the formation of the gate electrode. Heat treatment may be performed. Alternatively, a second heat treatment may be performed immediately following the first heat treatment, or the second heat treatment may be performed immediately following the first heat treatment. The first heat treatment may also serve as the second heat treatment, or the second heat treatment may also serve as the first heat treatment. You can do that.

[0195] As described above, by applying at least one of the first heat treatment and the second heat treatment, The semiconductor layer 144 is purified to the highest possible degree so that it contains as few impurities as possible other than its main component. can.

[0196] The gate electrode 148a and electrode 148b are formed after a conductive layer is formed on the gate insulating layer 146. The conductive layer can be formed by selectively etching the gate electric The conductive layers that will become electrode 148a and electrode 148b are produced by PVD methods including sputtering, It can be formed using CVD methods such as plasma CVD. For details, see source electrode. This is similar to the case of drain electrode 142a, and these descriptions can be taken into consideration.

[0197] Next, an insulating layer 15 is applied to the gate insulating layer 146, the gate electrode 148a, and the electrode 148b. Forms insulation layer 150 and insulating layer 152 (see Figure 13(A)). Insulating layer 150 and insulating layer 15 2 can be formed using methods such as PVD or CVD. Also, silicon oxide, acid Contains inorganic insulating materials such as silicon nitride, silicon nitride, hafnium oxide, and aluminum oxide. It can be formed using various materials.

[0198] Furthermore, insulating layers 150 and 152 use materials with low dielectric constants or structures with low dielectric constants (porous). It is desirable to use a structure such as a porous structure. The dielectric constant of insulating layer 150 and insulating layer 152 is lowered. By doing so, capacitance between wiring and electrodes can be reduced, and the operating speed can be increased. This is for the purpose of cutting.

[0199] In this embodiment, a laminated structure of insulating layer 150 and insulating layer 152 is used, but the disclosure is... One aspect of the invention is not limited thereto. It may be a single layer, or a laminated structure of three or more layers. That's also good. Furthermore, it's possible to have a configuration without an insulating layer.

[0200] Furthermore, it is desirable that the insulating layer 152 be formed so that its surface is flat. By forming the insulating layer 152 so that it becomes flat, when the semiconductor device is miniaturized, In addition, electrodes, wiring, and the like can be suitably formed on the insulating layer 152. The insulating layer 152 is planarized using methods such as CMP (chemical mechanical polishing). It is possible.

[0201] Next, the gate insulating layer 146, insulating layer 150, and insulating layer 152 are coated with the source electrode or drain. An opening is formed that reaches electrode 142b (see Figure 13(B)). The formation of this opening is done by This is done by selective etching using a tool such as a squeegee.

[0202] Subsequently, an electrode 154 is formed in the opening, and wiring 15 is placed on the insulating layer 152 in contact with the electrode 154. Form 6 (see Figure 13(C)).

[0203] Electrode 154 has a conductive layer formed in the region including the opening using methods such as PVD or CVD. Afterward, a portion of the conductive layer is removed using methods such as etching or CMP. It can be formed by the following.

[0204] More specifically, for example, a thin titanium film is formed in the region including the opening by the PVD method, and CV After forming a thin titanium nitride film using method D, a tungsten film was formed to embed it in the opening. A method can be applied to achieve this. Here, the titanium film formed by the PVD method is The oxide film on the formation surface (such as the native oxide film) is reduced, and the lower electrode, etc. (here, the source electrode or It has the function of reducing the contact resistance with the drain electrode 142b). The titanium nitride film has a barrier function that suppresses the diffusion of conductive materials. A copper film may be formed by plating after a barrier film made of titanium nitride or the like has been formed.

[0205] Furthermore, when removing a portion of the conductive layer to form an electrode, the surface should be made flat. Processing is desirable. For example, a thin titanium film or titanium nitride film can be formed in the region including the opening. If a tungsten film is formed to fill the opening afterwards, the subsequent CMP treatment Through this process, unwanted tungsten, titanium, titanium nitride, etc. are removed, and the surface The flatness can be improved. In this way, the surface including the electrode 154 can be planarized. This allows for the formation of good electrodes, wiring, insulating layers, semiconductor layers, etc., in subsequent processes. This becomes possible.

[0206] Wiring 156 is used for PVD methods such as sputtering and CVD methods such as plasma CVD. The conductive layer is formed using [a specific method], and then the conductive layer is patterned to create the conductive layer. Furthermore, the materials used for the conductive layer include aluminum, chromium, copper, tantalum, titanium, and molybdenum. It is possible to use elements selected from tungsten, or alloys containing the aforementioned elements. Yes, it's possible. Manganese, magnesium, zirconium, beryllium, neodymium, scandium Any of these materials, or a combination of several of them, may be used. For details, see source electrode. Alternatively, it is similar to the drain electrode 142a, etc.

[0207] As described above, a transistor 162 using a highly purified oxide semiconductor layer 144, and Capacitive element 164 is completed (see Figure 13(C)).

[0208] In the transistor 162 shown in this embodiment, the oxide semiconductor layer 144 is made highly pure. Because it is contained, its hydrogen concentration is 5 × 10 19 atoms / cm 3 The following is preferable: 5x 10 18 atoms / cm 3 The following is more preferable: 5 x 10 17 atoms / cm 3 below Furthermore, the carrier density of the oxide semiconductor layer 144 is as follows in a typical silicon wafer. Carrier density (1 × 10⁻⁶) 14 / cm 3 A sufficiently small value (for example, 1) compared to the degree ×10 12 / cm 3 Less than, more preferably 1.45 × 10 10 / cm 3 Take the value less than (). And the off-current of transistor 162 also becomes sufficiently small. For example, transistor 16 The off-current at room temperature (25°C) for 2 (here, the value per unit channel width (1 μm)) is 100 zA (1 zA (zeptampere) is 1 × 10⁻¹⁰ -21 A) Preferably 10 zA The following applies.

[0209] By using the highly purified and intrinsically purified oxide semiconductor layer 144 in this way, transient It becomes easier to sufficiently reduce the off-current of the transistor. And such a transistor By using this technology, a semiconductor device capable of retaining memory contents for an extremely long period of time can be obtained. ru.

[0210] The configurations and methods described in this embodiment are suitable for use with configurations and methods described in other embodiments. They can be used in any combination.

[0211] (Embodiment 3) In this embodiment, a semiconductor device with a configuration different from that shown in Figures 2 and 5 is shown in Figures 25 to 27. See the explanation below.

[0212] Figure 25(A) is an example of a circuit diagram of a semiconductor device having (m × n) memory cells 170. Yes. The configuration of memory cell 170 in Figure 25(A) is the same as in Figure 2(B), so details are not required. I will omit the detailed explanation.

[0213] The semiconductor device shown in Figure 25(A) has a configuration that is generally similar to that of the semiconductor device shown in Figure 2(A). The difference between the semiconductor device shown in Figure 2(A) and the semiconductor device shown in Figure 25(A) is the bit line. The key is whether or not wiring 195, which is electrically connected to BL, is provided. In other words, Figure 25( The semiconductor device shown in A) has wiring 195 that is electrically connected to the bit line BL. Wiring 195 has the function of maintaining the potential of the bit line supplied to the memory cell at an appropriate value. In a configuration where a large number of memory cells are connected in series, as in the disclosed invention, the memory cells This is because voltage drops can make it difficult to read the information.

[0214] For example, a configuration in which 64 memory cells are connected in series is considered as a unit, and each unit is appropriately Wiring 195 is connected to each unit so that a potential is applied. Even with a configuration having a number of memory cells, information can be read out efficiently. Oh, the number of memory cells each unit has isn't limited to 64. It could be 32, 128, etc. It is possible to set it as appropriate, within a range that does not affect the read operation.

[0215] Figure 26 shows an example of the configuration of the semiconductor device shown in Figure 25. Figure 26(A) shows the semiconductor device Figure 26(A) shows the cross-section, and Figure 26(B) shows the plane of the semiconductor device. Here, Figure 26(A) shows the cross-section, and Figure 26(A) shows the plane of the semiconductor device. ) corresponds to the cross-sections at C1-C2 and D1-D2 in Figure 26(B). A characteristic feature of this configuration is that it is electrically connected to the source electrode or drain electrode 142a. In addition to the wiring 156b, there is also wiring 156a. The wiring 156a is shown in Figure 25 This corresponds to wiring 195 which is electrically connected to bit line BL in Figure 26(B). Although not explicitly stated, wiring 156a and wiring 156b are parallel to each other, as shown in Figure 26(B). It exists in a form that extends vertically.

[0216] The operation of the above semiconductor device is the same as in the case of Figure 2(A). For details, see the previous implementation. You should refer to the corresponding description of the form.

[0217] Even when adopting the configurations shown in Figure 2(A) or Figure 5(A), the signal line S is connected to the above wiring. By using it instead, it is possible to obtain a similar effect. In this case, for example, see Figure 27. As shown, the bit line BL and the signal line S are electrically connected, and the bit line BL and A switch 231 controls the connection between the signal line S and the output terminal OUT, and the bit line BL and signal The configuration includes a switch 232 that controls the connection between line S and input terminal IN, and a wiring SW. It is possible to adopt this. In this case, the signal supplied to the wiring switch is used for reading. Sometimes you can turn on switch 231, and when writing, turn on switch 232. Note that the signals supplied to the wiring switch are the signals from the WRITE and READ wiring. Based on this, the signal is generated by the signal generation circuit 233. When adopting such a configuration, Since it is not necessary to provide the wiring 195 shown in Figure 25, suitable reading operation is maintained while semi It is possible to further increase the integration density of conductive devices.

[0218] Note that the other configurations in Figure 27 are the same as in Figure 23. For details, please refer to the explanation in Figure 23. It can be taken into consideration.

[0219] Note that the configuration shown in this embodiment is a modified example of the semiconductor device shown in Figure 2(A), but Figure 5 (A) may be a modified example of the semiconductor device shown.

[0220] The configurations and methods described in this embodiment are suitable for use with configurations and methods described in other embodiments. They can be used in any combination.

[0221] (Embodiment 4) In this embodiment, when applying the semiconductor device described in the above embodiment to an electronic device, This will be explained using Figure 14. In this embodiment, a computer and a mobile phone (mobile Telephones (also called mobile phones), personal information terminals (including portable game consoles, audio playback devices, etc.) (mu), digital camera, digital video camera, electronic paper, television equipment (tele The above-mentioned semiconductor device is applied to electronic devices such as a radio or television receiver. Let me explain the cases in which this occurs.

[0222] Figure 14(A) shows a notebook-type personal computer, consisting of chassis 701, chassis 702, It consists of a display unit 703, a keyboard 704, etc., and a casing 701 and a casing 702. At least one of them is provided with the semiconductor device shown in the previous embodiment. It offers high-speed data writing and reading, long-term memory retention, and sufficient power consumption. This will result in a notebook-type personal computer with significantly reduced performance.

[0223] Figure 14(B) shows a personal digital assistant (PDA), and the main body 711 has a display unit 713 and an external A separate interface 715 and operation buttons 714 are provided. It is equipped with a stylus 712 for operating the end. Inside the main body 711, as in the previous embodiment, The semiconductor device shown is provided. Therefore, information can be written to and read at high speed. A portable information terminal capable of long-term memory retention and with significantly reduced power consumption will be realized. .

[0224] Figure 14(C) shows an e-reader 720 with electronic paper implemented, consisting of a casing 721 and a casing 72 It consists of two enclosures, 721 and 723, respectively, each containing a display unit 7 25 and a display unit 727 are provided. The housing 721 and housing 723 are connected by the shaft portion 737 It is connected and can open and close using the shaft portion 737 as an axis. Unit 21 includes a power supply 731, operation keys 733, a speaker 735, etc. (Cabinet 721) At least one of the housings 723 is provided with the semiconductor device shown in the previous embodiment. Therefore, it allows for high-speed writing and reading of information, long-term memory retention, and erasure. This will enable the creation of e-books with significantly reduced power consumption.

[0225] Figure 14(D) shows a mobile phone, which consists of two casings, casing 740 and casing 741. Furthermore, the casings 740 and 741 slide and unfold as shown in Figure 14(D). It can be transformed from a separate state to an overlapping state, and can be miniaturized to suit portability. The enclosure 741 includes a display panel 742, a speaker 743, a microphone 744, and an operating panel. Key 745, pointing device 746, camera lens 747, external connection terminal 74 It is equipped with 8, etc. Also, the housing 740 has a solar cell 749 that charges the mobile phone. It also features an external memory slot 750, etc. Furthermore, the antenna is built into the housing 741. It is provided. At least one of the housings 740 and 741 is equipped with the semiconductor equipment shown in the previous embodiment. A storage space is provided. Therefore, information can be written and read at high speed, and long-term storage is possible. A mobile phone that can be held while consuming significantly reduced power will be realized.

[0226] Figure 14(E) shows a digital camera, consisting of the main body 761, display unit 767, eyepiece unit 763, and control panel. It consists of a power switch 764, a display unit 765, a battery 766, etc. Inside 761, the semiconductor device shown in the previous embodiment is provided. Therefore, the information book It offers high-speed write and read operations, long-term data retention, and significantly reduced power consumption. A digital camera that achieves this will be realized.

[0227] Figure 14(F) shows a television device 770, consisting of a housing 771, a display unit 773, and a stand. It consists of 775 and other components. The television device 770 is operated by the casing 771. This can be done using the switch or the remote control unit 780. The housing 771 and the remote control unit The machine 780 is equipped with the semiconductor device shown in the previous embodiment. Therefore, information It offers high-speed writing and reading, long-term memory retention, and sufficiently low power consumption. A reduced-scale television system will be realized.

[0228] As described above, the electronic device shown in this embodiment is equipped with the semiconductor device according to the previous embodiment. It is included. Therefore, electronic devices with reduced power consumption can be realized. [Examples]

[0229] In this example, the off-current of a transistor using a highly purified oxide semiconductor was determined. Let's explain the results.

[0230] First, the off-current of a transistor using a highly purified oxide semiconductor must be sufficiently small. Taking this into consideration, a transistor with a sufficiently large channel width W of 1m was prepared to measure the off-current. The following was performed. Figure 15 shows the results of measuring the off-current of a transistor with a channel width W of 1m. In Figure 15, the horizontal axis represents the gate voltage VG, and the vertical axis represents the drain current ID. When voltage VD is +1V or +10V, the gate voltage VG is in the range of -5V to -20V. The transistor's off-current is the detection limit of 1 × 10⁻⁶. -12 It was found to be less than or equal to A. Also, the transistor's off-current (here, the value per unit channel width (1 μm)) This is 1 aA / μm (1 × 10⁻⁶). -18 It was found that the value would be less than or equal to A / μm.

[0231] Next, we will more accurately determine the off-current of a transistor using a highly purified oxide semiconductor. The results will be explained below. As mentioned above, the transistor using a highly purified oxide semiconductor... The off-current of the zista is 1 × 10⁻¹⁶, which is the detection limit of the measuring instrument. -12 It was found to be less than or equal to A. Therefore, a characteristic evaluation element was fabricated to obtain a more accurate value of the off-current (measurement in the above measurement). We will now explain the results of determining values ​​below the detection limit of the device.

[0232] First, the characteristic evaluation elements used in the current measurement method will be explained with reference to Figure 16.

[0233] The characteristic evaluation element shown in Figure 16 consists of three measurement systems 800 connected in parallel. 0 represents the capacitive element 802, transistor 804, transistor 805, and transistor 806. , has transistor 808. Transistor 804, transistor 805, transistor Transistors 806 and 808 use high-purity oxide semiconductors. The standard was applied.

[0234] In the measurement system 800, one of the source terminals and drain terminals of transistor 804 is connected to, One terminal of the capacitive element 802 and the source and drain terminals of the transistor 805 One side is connected to the power supply (the power supply that provides V2). Also, the saw of transistor 804 The other end of the terminals, the source terminal and the drain terminal, and the source terminal and drain terminal of transistor 808. One side of the child, the other side of the terminal of the capacitive element 802, and the gate terminal of the transistor 805 are connected. It is continued. Also, the source terminal and the other drain terminal of transistor 808, One of the source and drain terminals of transistor 806 and the gateway of transistor 806 The terminal is connected to the power supply (the power supply that provides V1). Also, the base of transistor 805 The other end of the drain terminal and the source terminal and drain of transistor 806 The other end of the terminal is connected to it and serves as an output terminal.

[0235] The gate terminal of transistor 804 has two states: ON state and OFF state. A potential Vext_b2 that controls the state is supplied, and the gate terminal of transistor 808 is The potential Vext_b1 that controls the ON and OFF states of the transistor 808 is supplied. Additionally, a voltage (Vout) is output from the output terminal.

[0236] Next, a method for measuring current using the above-mentioned characteristic evaluation element will be described.

[0237] First, we will briefly describe the initialization period during which a potential difference is applied to measure the off-current. During the initialization period, the gate terminal of transistor 808 is turned ON. The potential Vext_b1 to be used as the state is input. This controls the source terminal of transistor 804. The node connected to the other of the child or drain terminal (i.e., the source of transistor 808) One of the terminals and drain terminal, the other terminal of the capacitive element 802, and transistor 80 A potential V1 is applied to node A (which is connected to the gate terminal of 5). Here, The potential V1 is, for example, a high potential. Also, transistor 804 is in the OFF state at Vext_b2. By applying a potential that puts it into a certain state, transistor 804 is kept in the off state.

[0238] Subsequently, a potential is applied to the gate terminal of transistor 808 to turn it off. Enter Vext_b1 to turn off transistor 808. Transistor 808 After turning it off, the potential V1 is set to a low potential. Here too, transistor 804 is off. This state is assumed. Also, potential V2 is assumed to be the same potential as potential V1. Thus, the initialization period is defined as follows. The initialization period ends. A potential difference is generated between the child and drain terminals, and between node A and transistor 808 A potential difference will occur between the source terminal and the other drain terminal, so the transient A small charge flows through transistors 804 and 808. In other words, an off-current is generated. do.

[0239] Next, we will briefly explain the measurement period for the off-current. During the measurement period, the transistor The potential of either the source or drain terminal of the 804 (i.e., V2), and The potential (i.e., V1) of the other terminal of the source or drain terminal of the transistor 808 is Keep it fixed at a low potential. On the other hand, during the measurement period, the potential of node A is not fixed (flow (This puts it into a charging state). As a result, charge flows to transistor 804, and over time... In both cases, the amount of charge held at node A changes. As the device moves, the potential at node A fluctuates. Therefore, the output potential Vout at the output terminal also fluctuates. ru.

[0240] The details of the relationship between each potential during the initialization period in which the above potential difference is applied, and during the subsequent measurement period. A detailed (timing chart) is shown in Figure 17.

[0241] During the initialization period, first, the potential Vext_b2 is set when transistor 804 is in the ON state. This will result in a potential (high potential) such that the potential of node A becomes V2, i.e., a low potential. This results in VSS. Note that applying a low potential (VSS) to node A is not essential. The potential Vext_b2 is set to a potential (low potential) such that transistor 804 is in the off state. Next, the transistor 804 is turned off. Then, the potential Vext_b1 is set to The potential (high potential) is set such that the transistor 808 turns ON. The potential of A becomes V1, i.e., high potential (VDD). Then, Vext_b1 is transmitted. The potential is set such that the ZISTA 808 is in the OFF state. This causes node A to float. The system enters a state of inactivity, and the initialization period ends.

[0242] During the subsequent measurement period, potentials V1 and V2 were determined by the inflow of charge into node A. Alternatively, the potential is set such that charge flows out from node A. Here, potentials V1 and V Set 2 to low potential (VSS). However, at the timing when measuring the output potential Vout... This requires the output circuit to be activated, so V1 is temporarily set to a high potential (VDD). There are such cases. Note that the period during which V1 is at a high potential (VDD) is short enough not to affect the measurement. This will be the period.

[0243] As described above, a potential difference is applied, and once the measurement period begins, as time progresses, at node A... The amount of charge held fluctuates, and the potential of node A fluctuates accordingly. This is a transient. This means that the potential at the gate terminal of the 805 fluctuates, and therefore, over time, the output... The potential of the terminal's output potential Vout will also change.

[0244] The method for calculating the off-current from the obtained output potential Vout is described below.

[0245] Before calculating the off-current, the potential V at node A is... A Then, find the relationship with the output potential Vout. Accordingly, the potential V of node A can be obtained from the output potential Vout A From the above-described relationship, the potential V of node A can be expressed as a function of the output potential Vout by the following expression A .

[0246] [Math.]]

[0247] Further, the charge Q at node A A is expressed by the following expression using the potential V at node A A , the capacitance C connected to node A A and a constant (const) . Here, the capacitance connected to node A C A is the sum of the capacitance of capacitive element 802 and other capacitances.

[0248] [Math.]]

[0249] The current I at node A A is the time derivative of the charge flowing into node A (or the charge flowing out from node A) , and thus the current I at node A A is expressed by the following expression.

[0250] [Math.]]

[0251] As described above, the current I at node A can be obtained from the capacitance C connected to node A A and the output potential Vout at the output terminal A of the current I at node A A can be obtained.

[0252] By the method described above, leakage current flowing between the source and drain of a transistor in an off-state can be​ It can measure the off-current.

[0253] In this example, a highly purified oxide with a channel length L = 10 μm and a channel width W = 50 μm was used. Using semiconductor materials, transistors 804, 805, 806, and A converter 808 was fabricated. In addition, in each of the parallel measurement systems 800, a capacitive element 802 The capacitance values ​​were set to 100 fF, 1 pF, and 3 pF.

[0254] In this embodiment, the measurements were taken with VDD = 5V and VSS = 0V. In this case, the potential V1 is generally set to VSS, and every 10 to 300 seconds, 100 mse Vout was measured as VDD only during period c. It was also used to calculate the current I flowing through the element. The time interval Δt was assumed to be approximately 30,000 seconds.

[0255] Figure 18 shows the relationship between the elapsed time (Time) and the output potential (Vout) related to the current measurement described above. Figure 18 shows that the electrical potential changes over time.

[0256] Figure 19 shows the off-current at room temperature (25°C) calculated by the current measurement described above. Figure 19 shows the relationship between the source-drain voltage V and the off-current I. From 19, under the condition of a source-drain voltage of 4V, the off-current is approximately 40 zA / μm. It was found that... Also, under the condition of a source-drain voltage of 3.1V, the off-current... It was found to be less than 10 zA / μm. Note that 1 zA is equal to 10 -21 It represents A.

[0257] Furthermore, regarding the off-current calculated by the above current measurement under a temperature environment of 85°C: This is shown in Figure 20. Figure 20 shows the source-drain voltage V and the off voltage at a temperature of 85°C. This shows the relationship with current I. Figure 20 shows the condition where the source-drain voltage is 3.1V. In this case, the off-current was found to be 100 zA / μm or less.

[0258] In this embodiment, a transistor using a highly purified oxide semiconductor can be used for off-voltage operation. It was confirmed that the flow was sufficiently reduced. [Examples]

[0259] The number of rewriteable memory cells according to one embodiment of the disclosed invention was investigated. The results of this investigation will be explained with reference to Figure 21.

[0260] The semiconductor device used in the investigation is the one with the circuit configuration shown in Figure 1(A-1). A transistor corresponding to transistor 162 used an oxide semiconductor. Capacitive element 16 For the capacitance element corresponding to 4, one with a capacitance value of 0.33pF was used.

[0261] The investigation involves determining the initial memory window width and the number of times information is retained and written. This was done by comparing it with the memory window width after it was returned. Information storage in memory cells The data is stored and written to the wiring corresponding to the third wiring in Figure 1(A-1), with 0V. Either 0V or 5V is applied to the wire corresponding to the fourth wire. This was done by providing a voltage. If the potential of the wiring corresponding to the fourth wiring is 0V, then Is the transistor corresponding to transistor 162 (the writing transistor) in the off state? Then, the potential applied to node FG is maintained. The potential of the wiring corresponding to the fourth wiring is 5V. In this case, since the transistor corresponding to transistor 162 is in an on state, the third potential of the wiring corresponding to the third wiring is applied to node FG.

[0262] Memory window width is one of the indicators representing the characteristics of a storage device. Here, different storage states refers to the relationship between the potential Vcg of the wiring corresponding to the fifth wiring and the drain current Id of the transistor corresponding to transistor 160 (read transistor), and is the shift amount ΔVcg of the curve (V cg-Id curve) representing this relationship. The different storage states are a state where 0V is applied to node FG (hereinafter referred to as Low state) and a state where 5V is applied to node FG (hereinafter referred to as High state). That is, the memory window width can be confirmed by sweeping the potential Vcg in the Low state and the High state.

[0263] FIG. 21(A) shows the memory window width in an initial state, and the results after 1×10 9 write cycles of performing writing are shown as investigation results of the memory window width. In FIG. 21(A), the horizontal axis represents V cg (V), and the vertical axis represents Id (A).

[0264] As shown in FIG. 21(A), before and after performing as many as 1×10 9 write cycles, the Vcg-Id curve for writing in High state and the Vcg-Id curve for writing in Low state exhibit almost no change. In addition, regarding the shift amount (ΔVcg) between the Vcg-Id curve for writing in High state and the Vcg-Id curve for writing in Low state, almost no change is observed before and after 1×10 9 write cycles of writing.

[0265] Figure 21(B) shows the transistor during High state writing or Low state writing. The potential of the wiring corresponding to the fifth wiring required to turn on 160, and the number of rewrites. This shows the relationship. In Figure 21(B), the horizontal axis represents the number of rewrites, and the vertical axis represents the fifth wiring. The potential of the corresponding wiring, i.e., the apparent threshold voltage V of transistor 160 th (V) vinegar.

[0266] The threshold can generally be calculated using the tangent method. Specifically, the horizontal axis is the gauge. Let the drain voltage Vg be the value of the square root of the drain current Id on the vertical axis of the curve, and then consider the slope of the curve. Find the tangent line at the point where the value is maximum. Then, compare that tangent line with the horizontal axis (value of the gate voltage Vg). The intercept is used as the threshold. In Figure 21(B), the apparent threshold V is also obtained using the tangent method. th of I calculated it.

[0267] Table 1 shows the memory window width calculated from Figure 21(B). The width is the apparent threshold V of transistor 160 during writing in the High state. th_ H And the apparent threshold V of transistor 160 during low state writing. th_L and The difference was calculated to find it.

[0268] [Table 1]

[0269] Table 1 shows that the memory cell in this embodiment allows writing 1 × 10⁻⁶ times. 9 Before and after the operation, memory The change in window width was less than 2%, specifically 1.68%. Therefore, 1 x 109 It was shown that the semiconductor device did not degrade before and after each write operation.

[0270] Figure 21(C) shows the relationship between the number of rewrite cycles and the transconductance (gm) of the memory cell. In Figure 21(C), the horizontal axis represents the number of rewrites, and the vertical axis represents the transconductance (g The value of m) is shown.

[0271] When the transconductance (gm) of a memory cell decreases, it helps distinguish between the write state and the erase state. Although this may result in difficulties, as shown in Figure 21(C), the memory cell of this embodiment is 10 9 It can be seen that there is almost no change in the gm value even after rewriting it multiple times. The semiconductor device according to this embodiment is 10 9 It does not degrade even after multiple rewrites, making it extremely reliable. It can be said to be a semiconductor device.

[0272] As described above, a memory cell according to one aspect of the disclosed invention performs retention and writing 1 0 9 Even after being repeated many times, its properties do not change, and it has extremely high rewrite resistance. According to one aspect of the present invention, an extremely reliable memory cell and an extremely reliable device equipped with the same This means that highly reliable semiconductor devices can be realized. [Explanation of symbols]

[0273] 100 circuit boards 102 Protective layer 104 Semiconductor field 106 element isolation insulating layer 108 Gate Insulation Layer 110 Guard Station 116 Channel formation region 120 Impurity region 122 Metal layer 124 Metal compound area 128 Insulating layer 130 Insulating layer 142a Source electrode or drain electrode 142b Source electrode or drain electrode 143a Insulating layer 143b Insulating layer 144 Oxide semiconductor layer 146 Gate Insulation Layer 148a Token 148b Electrode 150 Insulating layer 152 Insulating layer 154 Electrode 156 Wiring 156a Wiring 156b Wiring 160 transistors 162 transistors 164 Capacitive elements 170 cell cells 180 Potential Conversion Circuit 190 First drive circuit 192 Second drive circuit 195 Wiring 211 Readout Circuit 212 Control circuits 213 Delay Circuit 214 Buffer Circuit 221 Decoder Circuit 222 Control circuits 223 Buffer Circuit 224 Buffer Circuit 225 Level Shift Circuit 231 switches 232 switches 233 Signal generation circuit 701 cabinet 702 cabinet 703 Display section 704 Keyboard 711 Main Unit 712 Stylus 713 Display section 714 Operation Buttons 715 External Interface 720 eBooks 721 cabinet 723 cabinet 725 Display section 727 Display section 731 Power supply 733 Operation Keys 735 Speakers 737 Shaft 740 cabinets 741 cabinets 742 Display Panel 743 Speakers 744 Microphone 745 Operation Keys 746 Pointing devices 747 Camera Lenses 748 External connection terminal 749 solar cells 750 external memory slots 761 Main Unit 763 Eyepiece 764 Operation Switch 765 Display section 766 Battery 767 Display section 770 Television equipment 771 cabinet 773 Display section 775 Stand 780 Remote Control Unit 800 Measurement System 802 Capacitive element 804 Transistor 805 Transistor 806 Transistors 808 transistors 1200 p-type transistor 1210 p-type transistor 1220 n-type transistor 1230 p-type transistor 1240 p-type transistor 1250 n-type transistor 1260 p-type transistor 1270 n-type transistor 1280 p-type transistor 1290 n-type transistor 1300 transistors 1310 Transistors 1320 transistors 1330 transistors 1340 transistors 1350 Capacitive element 1360 Capacitive elements 1370 Capacitive element 1380 Capacitive element 1390 transistors

Claims

[Claim 1] It comprises a write word line, a read word line, a bit line, a source line, a signal line, a memory cell array consisting of multiple memory cells, a first drive circuit, and a second drive circuit. One of the aforementioned memory cells is A first transistor comprising a first electrode, a first source electrode, a first drain electrode, and a first channel forming region, A second transistor comprising a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region, It has a capacitive element, The second channel-forming region includes an oxide semiconductor. The first gate electrode, the second drain electrode, and one of the electrodes of the capacitive element are electrically connected. The capacitive element is configured to maintain the voltage between its electrodes when the second transistor is turned off. The first drive circuit is electrically connected to the first drain electrode via the bit line, and is also electrically connected to the second source electrode via the signal line. The second drive circuit is electrically connected to the other electrode of the capacitive element via the read word line, and is also electrically connected to the second gate electrode via the write word line. The second drive circuit is a semiconductor device having the function of delaying the signal input to the signal line compared to the signal input to the write word line.

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