Semiconductor equipment

Abstract

To suppress the intrusion of external ions into the semiconductor layer. [Solution] The semiconductor device 10 comprises a barrier layer 40 having a smaller diffusion coefficient than the insulating films 38 and 39, provided on the surface of the insulating films 38 and 39; a main electrode 21 covering both the insulating films 38 and 39 and the barrier layer 40; and a passivation film overlapping the barrier layer 40 in a plan view. The insulating films 38 and 39 have a plurality of first openings 38a and 39a that penetrate the insulating films 38 and 39 in the thickness direction of the first semiconductor layer 33. The barrier layer 40 has a plurality of second openings 40a that penetrate the barrier layer 40 in the thickness direction and communicate with the plurality of first openings 38a and 39a. The main electrode 21 is embedded across the first openings 38a and 39a and the second openings 40a that communicate with each other. The angles formed by the inner surfaces of the first openings 38a and 39a with respect to the thickness direction are different from the angles formed by the inner surface of the second opening 40a, which communicates with the first openings 38a and 39a, with respect to the thickness direction.

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices. [Background technology]

[0002] For example, in semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) used in automotive inverter devices, it is known that a protective film is formed on the electrodes (see, for example, Patent Document 1). [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-136472 [Summary] However, when an organic protective film such as polyimide is used as a protective film, there is a risk that external ions may pass through the protective film.

[0004] A semiconductor device according to one aspect of the present disclosure is a semiconductor device comprising a cell region in which a plurality of cells are formed, and an outer peripheral region provided outside the cell region so as to surround the cell region, wherein the cell region comprises a first semiconductor layer of a first conductivity type, a gate electrode, and an insulating film covering the surface of the gate electrode, the semiconductor device comprising a barrier layer provided on the surface of the insulating film having a smaller diffusion coefficient than the insulating film, a main electrode provided so as to cover both the insulating film and the barrier layer, and a passivation film overlapping at least a portion of the barrier layer in a plan view, wherein the insulating film comprises a plurality of first openings penetrating the insulating film in the thickness direction of the first semiconductor layer, the barrier layer comprises a plurality of second openings penetrating the barrier layer in the thickness direction and communicating with the plurality of first openings, respectively, the main electrode is embedded across the first openings and the second openings communicating with each other, and the angle formed by the inner surface of the first opening with respect to the thickness direction and the angle formed by the inner surface of the second opening communicating with the first opening with respect to the thickness direction are different from each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] [Figure 1] FIG. 1 is a plan view of the semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a plan view showing a state where a protective film is removed from the semiconductor device of FIG. 1. [Figure 3] FIG. 3 is a cross-sectional view showing an example of the cross-sectional structure of a cell region. [Figure 4] FIG. 4 is a cross-sectional view showing the cross-sectional structure taken along line 4-4 of the semiconductor device of FIG. 1. [Figure 5] FIG. 5 is an enlarged view of a gate finger and an emitter routing portion of FIG. 4. [Figure 6] FIG. 6 is an enlarged view of a part of the FLR portion of FIG. 4. [Figure 7] FIG. 7 is an enlarged view of an equipotential ring of FIG. 4. [Figure 8] FIG. 8 is an explanatory view illustrating an example of manufacturing steps of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is an explanatory view illustrating an example of manufacturing steps of the method for manufacturing a semiconductor device. [Figure 10] FIG. 10 is an explanatory view illustrating an example of manufacturing steps of the method for manufacturing a semiconductor device. [Figure 11] FIG. 11 is an explanatory view illustrating an example of manufacturing steps of the method for manufacturing a semiconductor device. [Figure 12] FIG. 12 is an explanatory view illustrating an example of manufacturing steps of the method for manufacturing a semiconductor device. [Figure 13] FIG. 13 is an explanatory view illustrating an example of manufacturing steps of the method for manufacturing a semiconductor device. [Figure 14] FIG. 14 is an explanatory view illustrating an example of manufacturing steps of the method for manufacturing a semiconductor device. [Figure 15] FIG. 15 is an explanatory view illustrating an example of manufacturing steps of the method for manufacturing a semiconductor device. [Figure 16] FIG. 16 is an explanatory view illustrating an example of manufacturing steps of the method for manufacturing a semiconductor device. [Figure 17] Figure 17 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 18] Figure 18 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 19] Figure 19 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 20] Figure 20 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 21] Figure 21 is a cross-sectional view showing a part of the FLR section of the semiconductor device according to the second embodiment. [Figure 22] Figure 22 is a cross-sectional view showing an example of the cross-sectional structure of a cell region. [Figure 23] Figure 23 is an explanatory diagram illustrating an example of the manufacturing process for a semiconductor device according to the second embodiment. [Figure 24] Figure 24 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 25] Figure 25 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 26] Figure 26 is a cross-sectional view showing a part of the FLR section of the semiconductor device according to the third embodiment. [Figure 27] Figure 27 is an explanatory diagram illustrating an example of the manufacturing process for a semiconductor device according to the third embodiment. [Figure 28] Figure 28 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 29] Figure 29 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 30] Figure 30 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 31] Figure 31 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 32] Figure 32 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 33] Figure 33 is an explanatory diagram illustrating an example of a manufacturing process for semiconductor devices. [Figure 34] Figure 34 is a cross-sectional view showing a portion of the FLR section of the modified semiconductor device. [Figure 35] Figure 35 is a cross-sectional view showing a portion of the outer periphery structure of the modified semiconductor device.

[0006] [Detailed explanation] The embodiments of the semiconductor device will be described below with reference to the drawings. The embodiments shown below are examples of configurations and methods for realizing the technical concept, and the materials, shapes, structures, arrangements, dimensions, etc. of each component are not limited to those described below.

[0007] [First Embodiment] (Configuration of a semiconductor device) The configuration of the semiconductor device 10 of the first embodiment will be described with reference to Figures 1 to 7.

[0008] The semiconductor device 10 in this embodiment is a trench-gate type IGBT (Insulated Gate Bipolar Transistor). This semiconductor device 10 is used, for example, as a switching element in an in-vehicle inverter device. In this case, a current of, for example, 5A to 1000A flows through the semiconductor device 10.

[0009] As shown in Figure 1, the semiconductor device 10 is formed in the shape of a rectangular plate, for example. In this embodiment, the main surface 10s of the semiconductor device 10 is formed in the shape of a square, for example. In this embodiment, the length of one side of the main surface 10s is about 11 mm. That is, the chip size of the semiconductor device 10 in this embodiment is 11 mm square. The semiconductor device 10 has a back surface 10r (see Figure 3) facing away from the main surface 10s, and four side surfaces 10a to 10d formed between the main surface 10s and the back surface 10r. The side surfaces 10a to 10d are, for example, surfaces that connect the main surface 10s and the back surface 10r, and are perpendicular to both the main surface 10s and the back surface 10r.

[0010] In the following description, the direction in which the main surface 10s and the back surface 10r of the device face is referred to as the "z-direction." The z-direction can also be said to be the height direction of the semiconductor device 10. Two mutually orthogonal directions that are perpendicular to the z-direction are referred to as the "x-direction" and the "y-direction." In this embodiment, the side surfaces 10a and 10b of the device constitute both end surfaces in the x-direction of the semiconductor device 10, and the side surfaces 10c and 10d of the device constitute both end surfaces in the y-direction of the semiconductor device 10. For convenience, the direction from the back surface 10r of the device toward the main surface 10s of the device is referred to as "upward," and the direction from the main surface 10s of the device toward the back surface 10r of the device is referred to as "downward."

[0011] As shown in Figure 2, the semiconductor device 10 is equipped with an emitter electrode 21 and a gate electrode 22 as external electrodes for connecting to the outside of the semiconductor device 10. The emitter electrode 21 is an electrode that constitutes the emitter of the IGBT. The emitter electrode 21 has a recessed area 21a that is recessed in the y-direction. The recessed area 21a opens toward the side surface 10c of the device.

[0012] The gate electrode 22 is an electrode that constitutes the gate of the IGBT, and is the electrode to which a drive voltage signal for driving the semiconductor device 10 is supplied from outside the semiconductor device 10. The gate electrode 22 is located adjacent to the emitter electrode 21 in the y-direction. The gate electrode 22 fits into the housing recess 21a of the emitter electrode 21.

[0013] As shown by the dashed line in Figure 2, the semiconductor device 10 comprises a cell region 11 in which multiple cells are formed, and an outer peripheral region 12 provided outside the cell region 11 so as to surround the cell region 11. Here, "cell" refers to a main cell in which a transistor is formed. In other words, the cell region 11 is the region in which the transistor is formed. The outer peripheral region 12 is formed on the outer periphery of the main surface 10s of the device when viewed from the z direction. The outer peripheral region 12 is the region surrounding the emitter electrode 21, excluding the region in which the gate electrode 22 is formed.

[0014] An emitter electrode 21 is provided in the cell region 11. The emitter electrode 21 is formed over most of the cell region 11. When viewed from the z direction, the cell region 11 has a shape that follows the shape of the emitter electrode 21.

[0015] The outer peripheral region 12 is a region where a termination structure to improve the dielectric breakdown voltage of the semiconductor device 10 is provided. The outer peripheral region 12 is the region surrounding the emitter electrode 21, excluding the region where the gate electrode 22 is formed. The gate electrode 22 is provided in the region enclosed by the cell region 11 and the outer peripheral region 12.

[0016] The outer peripheral region 12 is provided with a pair of gate fingers 23A and 23B, an emitter routing section 24, an FLR (Field Limiting Ring) section 25, and an equipotential ring 26. The emitter electrode 21, gate electrode 22, gate fingers 23A and 23B, emitter routing section 24, FLR section 25, and equipotential ring 26 all include a common metal film. This metal film is formed from a material including, for example, AlCu (an alloy of aluminum and copper).

[0017] The pair of gate fingers 23A and 23B are for quickly supplying the current supplied to the gate electrode 22 to cells in the portion of the emitter electrode 21 that is far from the gate electrode 22. The pair of gate fingers 23A and 23B are integrated with the gate electrode 22. The pair of gate fingers 23A and 23B are connected to the end of the gate electrode 22 in the y-direction that is closer to the side surface 10c of the device.

[0018] The gate finger 23A extends from the gate electrode 22 toward the device side 10a and is formed to surround the emitter electrode 21 from the device side 10c, device side 10a, and device side 10d. The gate finger 23B extends from the gate electrode 22 toward the device side 10b and is formed to surround the emitter electrode 21 from the device side 10c, device side 10b, and device side 10d. The tip of the gate finger 23A and the tip of the gate finger 23B face each other with a gap in the x direction in the portion closer to the device side 10d than the emitter electrode 21.

[0019] The emitter routing portion 24 is a part integrated with the emitter electrode 21 and is formed in an annular shape to surround the pair of gate fingers 23A and 23B. The FLR section 25 is a termination structure for improving the breakdown voltage of the semiconductor device 10 and is provided outside the emitter routing section 24. The FLR section 25 is formed in an annular shape surrounding the emitter electrode 21 and the gate electrode 22. In this embodiment, the FLR section 25 is formed to be a closed annular shape. The FLR section 25 has the function of improving the breakdown voltage of the semiconductor device 10 by mitigating the electric field in the outer peripheral region 12 and suppressing the influence of external ions.

[0020] The equipotential ring 26 is a termination structure for improving the breakdown voltage of the semiconductor device 10, and is formed in an annular shape to surround the FLR portion 25. As shown in Figure 1, the equipotential ring 26 is formed on the outermost periphery of the main surface 10s of the device. In this embodiment, the equipotential ring 26 is formed to be a closed annular shape. The equipotential ring 26 has the function of improving the breakdown voltage of the semiconductor device 10.

[0021] As shown in Figure 1, the semiconductor device 10 includes an emitter electrode 21, a gate electrode 22, a pair of gate fingers 23A and 23B, an emitter routing portion 24, an FLR portion 25, and a passivation film 13 covering the equipotential ring 26. The passivation film 13 is a protective film that protects the semiconductor device 10 from the outside. The passivation film 13 is an organic insulating film formed from a material including, for example, polyimide (PI).

[0022] The passivation film 13 has a first opening 14 and a second opening 15. The first opening 14 exposes a portion of the emitter electrode 21, thereby forming an emitter electrode pad 16. The second opening 15 exposes most of the gate electrode 22, thereby forming a gate electrode pad 17. In this way, the openings 14 and 15 form pads for conductive members (not shown) from outside the semiconductor device 10 to join.

[0023] Figure 3 shows an example of a cross-sectional structure of a part of the cell region 11. For convenience, in Figure 3, some hatching of components of the semiconductor device 10 in the cell region 11 has been omitted.

[0024] As shown in Figure 3, the semiconductor device 10 includes a semiconductor substrate 30. The semiconductor substrate 30 is, for example, n - It is formed from a material containing silicon (Si) of a specific type. The semiconductor substrate 30 has a thickness of, for example, 50 μm to 200 μm.

[0025] The semiconductor substrate 30 has a substrate front surface 30s and a substrate back surface 30r facing opposite sides to each other in the z-direction. In other words, the z-direction can also be referred to as the thickness direction of the semiconductor substrate 30. Therefore, the phrase "viewed from the z-direction" can also be referred to as "viewed from the thickness direction of the semiconductor substrate 30".

[0026] The semiconductor substrate 30 is sequentially arranged from the substrate back surface 30r toward the substrate front surface 30s as p + -type collector layer 31, an n-type buffer layer 32, and an n - -type drift layer 33 that are stacked. A collector electrode 29 is formed on the substrate back surface 30r. The collector electrode 29 is formed over substantially the entire surface of the substrate back surface 30r. The surface of the collector electrode 29 opposite to the substrate back surface 30r constitutes the device back surface 10r of the semiconductor device 10. In the present embodiment, the drift layer 33 corresponds to a "first semiconductor layer of a first conductivity type".

[0027] As the p-type dopant for the collector layer 31, for example, B (boron), Al (aluminum), or the like is used. The dopant concentration of the collector layer 31 is, for example, 1×10 15 cm -3 or more and 2×10 19 cm -3 or less.

[0028] As the n-type dopant for the buffer layer 32 and the drift layer 33, for example, N (nitrogen), P (phosphorus), As (arsenic), or the like is used. The dopant concentration of the buffer layer 32 is, for example, 1×10 15 cm -3 or more and 5×10 17 cm -3 or less. The dopant concentration of the drift layer 33 is lower than that of the buffer layer 32, and is, for example, 1×10 13 cm -3 or more and 5×10 14 cm -3 or less.

[0029] A p-type base region 34 is formed on the surface of the drift layer 33, i.e., the substrate surface 30s. The base region 34 is formed over almost the entire surface of the substrate surface 30s. The dopant concentration of the base region 34 is, for example, 1 × 10⁻⁶. 16 cm -3 The above 1 x 10 18 cm -3 The following applies: The depth of the base region 34 from the substrate surface 30s is, for example, 1.0 μm or more and 4.0 μm or less. In this embodiment, the z-direction is the thickness direction of the drift layer 33. In other words, "viewed from the z-direction" can also be said as "viewed from the thickness direction of the drift layer 33." Since the drift layer 33 corresponds to the first semiconductor layer, "viewed from the z-direction" can also be said as "viewed from the first semiconductor layer."

[0030] Multiple trenches 35 are arranged side by side on the surface (substrate surface 30s) of the base region 34 in the cell region 11. Each trench 35 extends, for example, along the y-direction and is spaced apart from each other in the x-direction. This divides the cell into striped main cells 11A. The spacing between adjacent trenches 35 in the x-direction (distance between the centers of the trenches 35) is, for example, 1.5 μm to 7.0 μm. The width of each trench 35 (dimension of the trench 35 in the x-direction) is, for example, 0.5 μm to 3.0 μm. Each trench 35 penetrates the base region 34 in the z-direction and extends partway through the drift layer 33. Note that each trench 35 may be formed in a grid pattern to divide the matrix-shaped main cells 11A.

[0031] On the surface of the base region 34 in the cell region 11 (substrate surface 30s), n +An emitter region 36 of type 1 is formed. The emitter region 36 is located on both sides of the trench 35 in the x-direction. In other words, the emitter region 36 can be said to be located on both sides of the trench 35 in the arrangement direction of the trench 35 within the base region 34. Therefore, between adjacent trenches 35 in the x-direction, two emitter regions 36 are arranged with a gap between them in the x-direction. The depth of each emitter region 36 is, for example, 0.2 μm to 0.6 μm. Also, the dopant concentration of each emitter region 36 is higher than that of the base region 34, for example, 1 × 10⁻¹⁶. 19 cm -3 The above 5 x 10 20 cm -3 The following applies:

[0032] On the surface of the base region 34 in the cell region 11 (substrate surface 30s), p + A base contact region 37 of type 1 is formed. The base contact region 37 is located adjacent to the emitter region 36 in the x-direction. That is, the base contact region 37 is located between the x-direction of two emitter regions 36 that are located between adjacent trenches 35 in the x-direction. Each base contact region 37 may be formed deeper than the emitter region 36. The depth of each base contact region 37 is, for example, 0.2 μm or more and 0.8 μm or less. Also, the dopant concentration of each base contact region 37 is higher than that of the base region 34, for example, 5 × 10⁻¹⁶. 18 cm -3 The above 1 x 10 20 cm -3 The following applies:

[0033] An insulating film 38 is integrally formed on both the inner surface of each trench 35 and the substrate surface 30s. Therefore, it can also be said that the insulating film 38 is formed on the surface of the drift layer 33. The insulating film 38 has, for example, silicon oxide (SiO2). The thickness of the insulating film 38 is, for example, 1100 Å to 1300 Å. The insulating film 38 in the cell region 11 can also be said to constitute the gate insulating film.

[0034] An electrode material, such as polysilicon, is embedded in each trench 35 via an insulating film 38. The electrode material embedded in each trench 35 is electrically connected to either the gate electrode 22 (gate fingers 23A, 23B) or the emitter electrode 21. In other words, the electrode material embedded in each trench 35 forms a gate trench 22A and an emitter trench 21A. In this embodiment, gate trenches 22A and emitter trenches 21A are alternately provided in the arrangement direction of the multiple trenches 35. In this embodiment, both the gate trenches 22A and emitter trenches 21A are embedded up to the open end of each trench 35.

[0035] An intermediate insulating film 39 is formed on the surface 38s of the insulating film 38 provided on the substrate surface 30s. The intermediate insulating film 39 has, for example, SiO2. The thickness of the intermediate insulating film 39 is thicker than that of the insulating film 38, for example, 3000 Å or more and 15000 Å or less.

[0036] A barrier layer 40 is formed on the surface 39s of the intermediate insulating film 39. The barrier layer 40 has the function of suppressing the penetration of external ions from the passivation film 13 to the substrate surface 30s of the semiconductor substrate 30. Specifically, the barrier layer 40 has a material with a smaller external ion diffusion coefficient than the passivation film 13. In this embodiment, the barrier layer 40 has a material with a smaller external ion diffusion coefficient than the intermediate insulating film 39. Furthermore, the barrier layer 40 has a material with a smaller external ion diffusion coefficient than the insulating film 38. In summary, the barrier layer 40 has a material with a smaller external ion diffusion coefficient than the passivation film 13, the intermediate insulating film 39, and the insulating film 38. The barrier layer 40 is formed from a material containing, for example, silicon nitride. In this embodiment, the barrier layer 40 has SiN as silicon nitride. The thickness of the barrier layer 40 is thinner than the thickness of the intermediate insulating film 39. The barrier layer 40 is formed in a shape that follows the surface 39s of the intermediate insulating film 39.

[0037] The emitter electrode 21 is formed on the intermediate insulating film 39 and the barrier layer 40. In other words, both the intermediate insulating film 39 and the barrier layer 40 are interlayer insulating films that fill the space between the emitter electrode 21 and the gate trench 22A, and between the emitter electrode 21 and the emitter trench 21A. The barrier layer 40 can also be said to be interposed between the intermediate insulating film 39 and the emitter electrode 21. The barrier layer 40 has a surface 40s and a back surface 40r. The surface 40s is in contact with the emitter electrode 21, and the back surface 40r is in contact with the surface 39s of the intermediate insulating film 39.

[0038] The insulating film 38 is provided with a plurality of openings 38a that penetrate the insulating film 38 in the z direction. Each opening 38a is located in a position that overlaps with the base contact region 37 when viewed from the z direction.

[0039] The intermediate insulating film 39 is provided with a plurality of openings 39a that penetrate the intermediate insulating film 39 in the z direction. Each opening 39a is located in a position that overlaps with the base contact region 37 when viewed from the z direction.

[0040] The barrier layer 40 has a plurality of barrier layer-side openings 40a that penetrate the barrier layer 40 in the z direction. Each barrier layer-side opening 40a is located in a position that overlaps with the base contact region 37 when viewed from the z direction.

[0041] In this embodiment, the inner surface 39b constituting the opening 39a and the inner surface 40b constituting the barrier layer side opening 40a are flush with each other. The emitter electrode 21 is connected to the base contact region 37 via the opening 39a and the barrier layer side opening 40a.

[0042] In this way, the base contact region 37 is exposed through the opening 38a of the insulating film 38, the opening 39a of the intermediate insulating film 39, and the barrier layer side opening 40a. In other words, these openings 38a, 39a, and 40a constitute contact holes for bringing the emitter electrode 21 into contact with the base contact region 37.

[0043] The emitter electrode 21 has plug electrodes 21b embedded in each of the contact holes. The plug electrodes 21b are made of, for example, tungsten (W). In this embodiment, the plug electrodes 21b are provided such that their tip is embedded from the substrate surface 30s of the semiconductor substrate 30. The emitter electrode 21 has an electrode body portion 21c that covers each plug electrode 21b. The electrode body portion 21c is provided on each plug electrode 21b. The electrode body portion 21c protrudes above both the intermediate insulating film 39 and the barrier layer 40. The electrode body portion 21c covers the barrier layer 40.

[0044] More specifically, the emitter electrode 21 has a barrier metal layer 21e. The barrier metal layer 21e is formed on the surface 40s of the barrier layer 40, the inner surface 39b that constitutes the opening 39a, the inner surface 40b that constitutes the barrier layer-side opening 40a, the inner surface 38b that constitutes the opening 38a, and the surface (substrate surface 30s) of the drift layer 33 opened by these openings 38a, 39a, and 40a. The barrier metal layer 21e is formed, for example, by a laminated structure of Ti (titanium) and TiN (titanium nitride). Therefore, the barrier metal layer 21e constitutes the portion of each plug electrode 21b that is in contact with each inner surface 38b, 39b, 40b and the substrate surface 30s, and the portion of the electrode body 21c that is in contact with the surface 40s of the barrier layer 40.

[0045] The detailed configuration of the outer region 12 will be described with reference to Figures 4 to 7. Figure 4 shows a cross-sectional structure of a part of the outer peripheral region 12. Figure 5 shows a magnified view of the gate finger 23A and emitter routing portion 24 within the outer peripheral region 12 of Figure 4. Figure 6 shows a magnified view of a part of the FLR portion 25 and its surroundings within the outer peripheral region 12 of Figure 4. Figure 7 shows a magnified view of a part of the equipotential ring 26 and its surroundings within the outer peripheral region 12 of Figure 4. Note that, for convenience, the hatching of the components of the semiconductor device 10 has been omitted in Figures 4 to 7.

[0046] As shown in Figures 4 to 7, a drift layer 33 is also formed in the outer peripheral region 12. Both the insulating film 38A and the intermediate insulating film 39 are formed on the substrate surface 30s of the semiconductor substrate 30 in the outer peripheral region 12. In other words, the insulating film 38A and the intermediate insulating film 39 can be said to cover the surface of the drift layer 33 in the outer peripheral region 12. The insulating film 38A of the outer peripheral region 12 includes the insulating film 38 of the cell region 11. The insulating film 38A is formed separately from the insulating film 38. Furthermore, a barrier layer 40 is formed on the surface 39s of the intermediate insulating film 39 in the outer peripheral region 12, similar to the cell region 11. In this embodiment, the insulating film 38A corresponds to the "first insulating film," and the intermediate insulating film 39 corresponds to the "second insulating film."

[0047] As shown in Figure 6, the insulating film 38A has a substrate-side insulating film 38B formed on the substrate surface 30s of the semiconductor substrate 30, and an insulating film 38 as an anti-substrate-side insulating film formed on the surface 38Bs of the substrate-side insulating film 38B. In other words, the insulating film 38A in this embodiment has a two-layer laminated structure of the substrate-side insulating film 38B and the insulating film 38. The substrate-side insulating film 38B is an oxide film formed by thermal oxidation of the semiconductor substrate 30. For this reason, the intermediate insulating film 39 laminated on the insulating film 38A can also be said to be formed on the surface 38s of the insulating film 38.

[0048] As shown in Figure 4, a p-type base region 34A is formed in the region of the outer peripheral region 12 adjacent to the cell region 11. The base region 34A, like the base region 34, is formed on the substrate surface 30s of the semiconductor substrate 30. The base region 34A is partially formed in the drift layer 33. Therefore, the surface of the base region 34A is covered by the insulating film 38A and the intermediate insulating film 39. Thus, it can be said that the insulating film 38A and the intermediate insulating film 39 (both see Figure 5) cover the surface of the drift layer 33 and the surface of the base region 34A. The dopant concentration of the base region 34A is, for example, 1 × 10⁻⁶. 16 cm -3 The above 1 x 10 18 cm -3 The following applies:

[0049] The depth of the base region 34A in the outer peripheral region 12 is greater than that of the base region 34 in the cell region 11 (see Figure 3). More specifically, the depth of the base region 34A in the outer peripheral region 12 is greater than that of the trench 35. In this embodiment, the base region 34A extends to a position that overlaps with the outer peripheral portion of the emitter electrode 21 when viewed from the z direction. In other words, the base region 34A is also formed on the outer peripheral portion of the cell region 11. The barrier layer 40 (see Figure 5) is provided at a position that overlaps with the base region 34A when viewed from the z direction. The barrier layer 40 covers the base region 34A when viewed from the z direction. In this embodiment, the barrier layer 40 is formed to extend beyond the outer edge of the base region 34A when viewed from the z direction. Here, in this embodiment, the base region 34A corresponds to the "second semiconductor region of the second conductivity type".

[0050] As shown in Figure 4, the FLR portion 25 is formed outside the base region 34A. The FLR portion 25 is composed of a plurality (four in this embodiment) of annular conductive and semiconductor regions that are spaced apart from each other.

[0051] Multiple (four in this embodiment) annular guard rings 25a to 25d are formed on the substrate surface 30s of the semiconductor substrate 30. In this embodiment, the guard rings 25a to 25d are formed in a closed annular shape. The guard rings 25a to 25d are partially formed in the drift layer 33. The guard rings 25a to 25d are semiconductor regions of the second conductivity type (p-type in this embodiment) and are spaced apart from each other in a direction perpendicular to the z-direction. The guard rings 25a to 25d are arranged in the order of guard ring 25a, guard ring 25b, guard ring 25c, and guard ring 25d as you move away from the emitter electrode 21. The width Wge of the outermost guard ring 25d is greater than the width Wg of the other guard rings 25a to 25c. For example, B, Al, etc., are used as the p-type dopant for each guard ring 25a to 25d. The dopant concentrations in each guard ring 25a to 25d are, for example, the same as the dopant concentration in the base region 34A, for example, 1 × 10⁻⁶. 16 cm-3 The above 1 x 10 18 cm -3 The following applies. In this case, the guard rings 25a to 25d and the base region 34A may be formed in the same process. Here, in this embodiment, the guard rings 25a to 25d correspond to the "second semiconductor region of the second conductivity type". The width Wge of the guard ring 25d can be arbitrarily changed. For example, the width Wge of the guard ring 25d may be equal to the width Wg of the guard rings 25a to 25c.

[0052] The FLR section 25 has field plates 25e to 25h that are provided in accordance with the guard rings 25a to 25d. Viewed from the z direction, field plate 25e is provided in a position that overlaps with guard ring 25a, field plate 25f is provided in a position that overlaps with guard ring 25b, field plate 25g is provided in a position that overlaps with guard ring 25c, and field plate 25h is provided in a position that overlaps with guard ring 25d. Field plate 25e is in contact with guard ring 25a, field plate 25f is in contact with guard ring 25b, field plate 25g is in contact with guard ring 25c, and field plate 25h is in contact with guard ring 25d. In this embodiment, field plates 25e to 25h correspond to the "electrode section".

[0053] Figure 6 is an enlarged view of the guard rings 25a, 25b and field plates 25e, 25f and their surroundings within the FLR section 25. The configuration of guard ring 25a and field plate 25e is the same as that of guard rings 25b, 25c and field plates 25f, 25g. Also, the configuration of guard ring 25d and field plate 25h is the same as that of guard ring 25a and field plate 25e, except that field plate 25h extends outward. For this reason, the configuration of guard ring 25a and field plate 25e will be described below, and the descriptions of the configurations of guard rings 25b-25d and field plates 25f-25h will be omitted.

[0054] The barrier layer 40, the intermediate insulating film 39, and the insulating film 38A each have openings 40c, 39c, and 38c on the barrier layer side, respectively, at positions that overlap with the guard ring 25a when viewed from the z direction. The barrier layer side opening 40c penetrates the barrier layer 40 in the z direction, the opening 39c penetrates the intermediate insulating film 39 in the z direction, and the opening 38c penetrates the insulating film 38A in the z direction. The barrier layer side openings 40c, 39c, and 38c are in communication with each other. When viewed from the z direction, the opening areas of each of the barrier layer side openings 40c, 39c, and 38c are smaller than the surface area of ​​the guard ring 25a. In other words, these openings 40c, 39c, and 38c form contact holes that expose a portion of the surface of the guard ring 25a and allow it to come into contact with the field plate 25e. The inner surface 40d that constitutes the barrier layer side opening 40c, the inner surface 39d that constitutes the opening 39c, and the inner surface 38d that constitutes the opening 38c are flush with each other.

[0055] As shown in Figure 6, the portion of the insulating film 38A that constitutes the opening 38c is inclined toward the drift layer 33 as it approaches the inner surface 38d of the opening 38c. In this embodiment, the opening end of the insulating film 38A has a curved portion 38j. The curved portion 38j is curved toward the drift layer 33 as it approaches the opening center of the opening 38c. The intermediate insulating film 39 covers the curved portion 38j.

[0056] The field plate 25e is in contact with the guard ring 25a by fitting into the barrier layer side opening 40c and openings 39c and 38c. The field plate 25e includes a first portion 27 provided within the openings 39c and 38c, and a second portion 28 having a protruding portion 28a that protrudes laterally from the first portion 27 and overlaps with the intermediate insulating film 39. In this embodiment, the first portion 27 and the second portion 28 are provided separately. The first portion 27 is made of, for example, W (tungsten), and the second portion 28 is made of, for example, AlCu. The first portion 27 can also be said to be provided within the barrier layer side opening 40c. The protruding portion 28a is located within the guard ring 25a when viewed from the z direction.

[0057] The second portion 28 is provided on the first portion 27. The second portion 28 protrudes from the intermediate insulating film 39 on the side opposite to the drift layer 33. In other words, the second portion 28 protrudes above the intermediate insulating film 39. The protruding portion 28a constitutes the end of the second portion 28. More specifically, viewed from the z direction, the protruding portion 28a constitutes both ends in the direction perpendicular to the direction in which the field plate 25e extends, i.e., both ends in the width direction of the field plate 25e. The second portion 28 curves toward the surface 39s of the intermediate insulating film 39 as it extends outward in the width direction of the field plate 25e. The second portion 28 is formed by wet etching. The shape of the second portion 28 can also be said to be a shape processed by wet etching.

[0058] The lower end of the first part 27 is embedded in the upper part of the guard ring 25a. In the part of the guard ring 25a corresponding to the first part 27, p + A type p-type contact region 25p is formed. For example, B, Al, etc., are used as the p-type dopant in the contact region 25p. The dopant concentration in the contact region 25p is higher than that of the guard ring 25a, for example, 5 × 10⁻¹⁶. 18 cm -3 The above 1 x 10 20 cm -3 The following applies:

[0059] The field plate 25e has a barrier metal layer 25m. The barrier metal layer 25m is formed on the surface 40s of the barrier layer 40, the inner surface 39d that constitutes the opening 39c, the inner surface 40d that constitutes the barrier layer side opening 40c, the inner surface 38d that constitutes the opening 38c, and the surface (substrate surface 30s) of the drift layer 33 opened by these openings 38c, 39c, and 40c. The barrier metal layer 25m is formed, for example, by a laminated structure of Ti and TiN. Therefore, the barrier metal layer 25m consists of a portion of the first portion 27 that is in contact with each of the inner surfaces 38d, 39d, 40d and the surface of the drift layer 33, and a portion of the second portion 28 that is in contact with the surface 40s of the barrier layer 40.

[0060] The barrier layer 40 has an intermediate portion 41 which is the part that fits between the protrusion 28a of the field plate 25e and the guard ring 25a. In this embodiment, the intermediate portion 41 is sandwiched between the protrusion 28a of the field plate 25e and the intermediate insulating film 39. Therefore, it can also be said that the barrier layer 40 has a portion (intermediate portion 41) that is sandwiched between the intermediate insulating film 39 and the protrusion 28a of the field plate 25e. The intermediate portion 41 has a barrier layer-side opening 40c through which the first portion 27 of the field plate 25e is inserted. Therefore, when viewed from the z direction, the intermediate portion 41 extends to the opening edge of the opening 39c of the intermediate insulating film 39 through which the first portion 27 of the field plate 25e is inserted.

[0061] The barrier layer 40 extends inward from the contact hole of the guard ring 25a to the emitter routing section 24 (see Figure 5). The barrier layer 40 extends, for example, from the contact hole of the guard ring 25a to the contact hole of the guard ring 25b. Therefore, when viewed from the z direction, the barrier layer 40 covers the entire guard ring 25a. Furthermore, when viewed from the z direction, the barrier layer 40 is formed to protrude from the outer edge of the guard ring 25a.

[0062] As shown in Figure 4, the field plate 25h has a projection 28a that extends on the opposite side from the field plate 25g which is longer than the projection 28a of the field plate 25e. The portion of the projection 28a of the field plate 25h that extends on the opposite side from the field plate 25g protrudes from the guard ring 25d when viewed from the z direction.

[0063] As shown in Figure 4, when viewed from the z direction, a gate finger 23A (23B) and an emitter routing portion 24 are formed at a position overlapping with the base region 34A. The gate finger 23A (23B) is formed at a position spaced outward from the emitter electrode 21.

[0064] As shown in Figure 5, the gate finger 23A has a gate layer 23a formed on the surface 38s of the insulating film 38 and a gate wiring 23b formed on the surface 40s of the barrier layer 40.

[0065] The gate layer 23a is made of, for example, polysilicon and is formed to surround the emitter electrode 21 from the apparatus side surfaces 10c, 10a, and 10d (see Figure 1). The gate layer 23a is covered by an intermediate insulating film 39. An oxide film 23c is formed on the surface of the gate layer 23a.

[0066] The gate wiring 23b is positioned so as to overlap with the gate layer 23a when viewed from the z direction. The gate wiring 23b is integrated with the gate electrode 22. Barrier layer-side openings 40e, 39e, and 23e are provided in the barrier layer 40, the intermediate insulating film 39, and the oxide film 23c at positions corresponding to the gate finger 23A, respectively. The barrier layer-side opening 40e penetrates the barrier layer 40 in the z direction, the opening 39e penetrates the intermediate insulating film 39 in the z direction, and the opening 23e penetrates the oxide film 23c in the z direction. The barrier layer-side openings 40e and 39e, 23e are in communication with each other. As a result, the gate layer 23a is exposed through the barrier layer-side openings 40e and 39e, 23e. The gate wiring 23b enters the barrier layer-side openings 40e and 39e, 23e and is in contact with the gate layer 23a. In other words, these barrier layer-side openings 40e and 39e, 23e constitute contact holes for the gate wiring 23b to contact the gate layer 23a. The inner surface 40f that constitutes the barrier layer side opening 40e and the inner surface 39f that constitutes the opening 39e are flush with each other.

[0067] The gate wiring 23b includes a first portion 23ba provided within the opening 39e and a second portion 23bb having a protruding portion 23bc that protrudes laterally from the first portion 23ba and overlaps with the intermediate insulating film 39. In this embodiment, the first portion 23ba and the second portion 23bb are provided separately. The first portion 23ba is made of, for example, W (tungsten), and the second portion 23bb is made of, for example, AlCu. It can also be said that the first portion 23ba is provided within the barrier layer side opening 40e.

[0068] The first portion 23ba is positioned so as to overlap both the gate layer 23a and the gate wiring 23b when viewed from the z direction. The first portion 23ba penetrates both the intermediate insulating film 39 on the gate layer 23a and the barrier layer 40 on the intermediate insulating film 39 in the z direction. In this embodiment, the first portion 23ba is embedded in the upper portion of the gate layer 23a.

[0069] In the gate layer 23a, the portion where the first part 23ba is embedded contains p +A contact region 23d, which is a type of semiconductor region, is formed. For example, B, Al, etc., are used as the p-type dopant for the contact region 23d. The dopant concentration of the contact region 23d is higher than that of the base region 34A, for example, 5 × 10⁻⁶. 18 cm -3 The above 1 x 10 20 cm -3 The following applies:

[0070] The second portion 23bb is provided on the first portion 23ba. The second portion 23bb protrudes from the intermediate insulating film 39 on the side opposite to the base region 34A. In other words, the second portion 23bb protrudes above the intermediate insulating film 39. The protruding portion 23bc constitutes the end of the second portion 23bb. More specifically, viewed from the z direction, the protruding portion 23bc constitutes both ends in the direction perpendicular to the direction in which the gate wiring 23b extends, i.e., both ends in the width direction of the gate wiring 23b. The second portion 23bb curves toward the surface 39s of the intermediate insulating film 39 as it extends outward in the width direction of the gate wiring 23b. The second portion 23bb is formed by wet etching. The shape of the second portion 23bb can also be said to be the shape processed by wet etching.

[0071] The gate wiring 23b has a barrier metal layer 23m. The barrier metal layer 23m is formed on the surface 40s of the barrier layer 40, the inner surface 39f that constitutes the opening 39e, the inner surface 40f that constitutes the barrier layer-side opening 40e, the inner surface that constitutes the opening 23e, and the surface of the gate layer 23a opened by these openings 23e, 39e, and 40e. The barrier metal layer 23m is formed, for example, by a laminated structure of Ti and TiN. Therefore, the barrier metal layer 23m consists of the portion of the first part 23ba that is in contact with each of the inner surfaces 39f and 40f and the surface of the gate layer 23a, and the portion of the second part 23bb that is in contact with the surface 40s of the barrier layer 40.

[0072] The barrier layer 40 has an intermediate portion 41 which is the part that is inserted between the protruding portion 23bc of the gate wiring 23b and the base region 34A. In this embodiment, the intermediate portion 41 is sandwiched between the protruding portion 23bc of the gate wiring 23b and the intermediate insulating film 39. Therefore, it can also be said that the barrier layer 40 has a portion (intermediate portion 41) that is sandwiched between the intermediate insulating film 39 and the protruding portion 23bc of the gate wiring 23b. The intermediate portion 41 has a barrier layer-side opening 40e through which the first portion 23ba of the gate wiring 23b is inserted. Therefore, when viewed from the z direction, the intermediate portion 41 extends to the opening edge of the opening 39e in the intermediate insulating film 39 through which the first portion 23ba of the gate wiring 23b is inserted.

[0073] The emitter routing portion 24 is made of a metal film and is formed on the surface 40s of the barrier layer 40. The emitter routing portion 24 is formed on the outer periphery of the base region 34A. Barrier layer-side openings 40g, 39g, and 38g are provided in the barrier layer 40, the intermediate insulating film 39, and the insulating film 38 at positions corresponding to the emitter routing portion 24, respectively. The barrier layer-side opening 40g penetrates the barrier layer 40 in the z direction, the opening 39g penetrates the intermediate insulating film 39 in the z direction, and the opening 38g penetrates the insulating film 38 in the z direction. The barrier layer-side openings 40g and 39g, 38g are in communication with each other. As a result, the base region 34A is exposed through the barrier layer-side openings 40g and 39g, 38g. The emitter routing portion 24 enters the barrier layer-side openings 40g and 39g, 38g and is in contact with the base region 34A. In other words, these barrier layer-side openings 40g and 39g, 38g constitute contact holes for the emitter routing portion 24 to contact the base region 34A. The inner surface 40h that constitutes the barrier layer side opening 40g, the inner surface 39h that constitutes the opening 39g, and the inner surface 38h that constitutes the opening 38g are flush with each other.

[0074] The emitter routing portion 24 includes a first portion 24a provided within the openings 39c and 38c, and a second portion 24b having a protruding portion 24c that protrudes laterally from the first portion 24a and overlaps with the intermediate insulating film 39. In this embodiment, the first portion 24a and the second portion 24b are provided separately. The first portion 24a is made of, for example, W (tungsten), and the second portion 24b is made of, for example, AlCu. The protruding portion 24c is located within the base region 34A when viewed from the z direction.

[0075] The lower end of the first part 24a is embedded in the upper part of the base region 34A. In the base region 34A, the portion corresponding to the first part 24a is p + A type-1 contact region 34B is formed. For example, B, Al, etc., are used as the p-type dopant in the contact region 34B. The dopant concentration in the contact region 34B is higher than that of the base region 34A, for example, 5 × 10⁻¹⁶. 18 cm -3 The above 1 x 10 20 cm -3 The following applies:

[0076] The second portion 24b is provided on the first portion 24a. The second portion 24b protrudes from the intermediate insulating film 39 on the side opposite to the base region 34A. In other words, the second portion 24b protrudes above the intermediate insulating film 39. The protruding portion 24c constitutes the end of the second portion 24b. More specifically, viewed from the z direction, the protruding portion 24c constitutes both ends in a direction perpendicular to the direction in which the emitter routing portion 24 extends, i.e., both ends in the width direction of the emitter routing portion 24. The second portion 24b curves toward the surface 39s of the intermediate insulating film 39 as it extends outward in the width direction of the emitter routing portion 24. The second portion 24b is formed by wet etching. The shape of the second portion 24b can also be said to be the shape processed by wet etching.

[0077] The emitter routing section 24 has a barrier metal layer 24m. The barrier metal layer 24m is formed on the surface 40s of the barrier layer 40, the inner surface 39h that constitutes the opening 39g, the inner surface 40h that constitutes the barrier layer side opening 40g, the inner surface 38h that constitutes the opening 38g, and the surface (substrate surface 30s) of the drift layer 33 opened by these openings 38g, 39g, and 40g. The barrier metal layer 24m is formed, for example, by a laminated structure of Ti and TiN. Therefore, the barrier metal layer 24m consists of the portion of the first section 24a that is in contact with each of the inner surfaces 38h, 39h, and 40h and the surface of the drift layer 33, and the portion of the second section 24b that is in contact with the surface 40s of the barrier layer 40.

[0078] The barrier layer 40 has an intermediate portion 41 which is the part that is inserted between the protruding portion 24c of the emitter routing portion 24 and the base region 34A. In this embodiment, the intermediate portion 41 is sandwiched between the protruding portion 24c and the intermediate insulating film 39. Therefore, it can also be said that the barrier layer 40 has a portion (intermediate portion 41) that is sandwiched between the intermediate insulating film 39 and the protruding portion 24c. The intermediate portion 41 has a barrier layer-side opening 40g through which the first portion 24a of the emitter routing portion 24 is inserted. Therefore, when viewed from the z direction, the intermediate portion 41 extends to the opening edge of the opening 39g in the intermediate insulating film 39 through which the first portion 24a of the emitter routing portion 24 is inserted.

[0079] As shown in Figure 4, an equipotential ring 26 is formed outside the FLR portion 25. Both the insulating film 38 and the intermediate insulating film 39 are also formed in the region where the equipotential ring 26 is formed.

[0080] As shown in Figure 7, the equipotential ring 26 is formed on the surface of the drift layer 33 (substrate surface 30s) with a first conductivity type (n + It has a channel stop region 26a of type (type), internal wiring 26b provided within the insulating film 38 and the intermediate insulating film 39, and surface-side wiring 26c provided on the surface 40s of the barrier layer 40.

[0081] The channel stop region 26a is formed from a position overlapping with the surface wiring 26c when viewed from the z direction to the side surface 10a of the device. The channel stop region 26a is positioned outward (closer to the side surface 10a) relative to the internal wiring 26b. The dopant concentration in the channel stop region 26a is the same as, for example, the dopant concentration in the emitter region 36 (see Figure 3), and is 1 × 10⁻⁶. 19 cm -3 The above 5 x 10 20 cm -3 The following applies. In this case, for example, the channel stop region 26a is formed in the same process as the emitter region 36.

[0082] The internal wiring 26b is provided on the surface 38s of the insulating film 38 and is covered by the intermediate insulating film 39. Since the intermediate insulating film 39 is covered by the barrier layer 40, it can also be said that the internal wiring 26b is covered by the barrier layer 40. The internal wiring 26b is formed of an electrode material such as polysilicon. The internal wiring 26b is formed in the same process as the gate layer 23a of the gate finger 23A (see Figure 5). An oxide film 26d is formed on the surface of the internal wiring 26b.

[0083] Barrier layer-side openings 40p, 39p, and 38p are provided in the barrier layer 40, the intermediate insulating film 39, and the oxide film 23c at positions corresponding to the channel stop region 26a, respectively. The barrier layer-side opening 40p penetrates the barrier layer 40 in the z direction, the opening 39p penetrates the intermediate insulating film 39 in the z direction, and the opening 38p penetrates the insulating film 38 in the z direction. The barrier layer-side openings 40p and 39p, 38p are in communication with each other. As a result, the channel stop region 26a is exposed through the barrier layer-side openings 40p and 39p, 38p. The surface-side wiring 26c enters the barrier layer-side openings 40p and 39p, 38p and is in contact with the channel stop region 26a. In other words, these barrier layer-side openings 40p and 39p, 38p constitute contact holes for the surface-side wiring 26c to contact the channel stop region 26a. The inner surface 40q that constitutes the barrier layer side opening 40p, the inner surface 39q that constitutes the opening 39p, and the inner surface 39q that constitutes the opening 38p are flush with each other.

[0084] Barrier layer-side openings 40u, 39u, and 26e are provided in the barrier layer 40, the intermediate insulating film 39, and the oxide film 26d at positions corresponding to the internal wiring 26b, respectively. The barrier layer-side opening 40u penetrates the barrier layer 40 in the z direction, the opening 39u penetrates the intermediate insulating film 39 in the z direction, and the opening 26e penetrates the oxide film 26d in the z direction. The barrier layer-side openings 40u and 39u, 26e are in communication with each other. As a result, the internal wiring 26b is exposed through the barrier layer-side openings 40u and 39u, 26e. The surface-side wiring 26c enters the barrier layer-side openings 40u and 39u, 26e and is in contact with the internal wiring 26b. In other words, these barrier layer-side openings 40u and 39u, 26e constitute contact holes for the surface-side wiring 26c to contact the internal wiring 26b. The inner surface 40t that constitutes the barrier layer side opening 40u and the inner surface 39t that constitutes the opening 39u are flush with each other.

[0085] The surface wiring 26c includes two first portions 26f and 26g, and a second portion 26i having a protruding portion 26h that protrudes laterally from each of the first portions 26f and 26g and overlaps with the intermediate insulating film 39. In this embodiment, the first portions 26f and 26g and the second portion 26i are provided individually. The first portions 26f and 26g are formed of a material containing, for example, W (tungsten), and the second portion 26i is formed of a material containing, for example, AlCu. The first portion 26f is in contact with the channel stop region 26a, and the first portion 26g is in contact with the internal wiring 26b. For this reason, it can be said that the first portion 26f is provided within the barrier layer side opening 40p, and the first portion 26g is provided within the barrier layer side opening 40u.

[0086] The first portion 26f is positioned so as to overlap with both the channel stop region 26a and the surface wiring 26c when viewed from the z direction. The first portion 26f penetrates all of the insulating films 38, 38B on the channel stop region 26a, the intermediate insulating film 39 on the insulating film 38, and the barrier layer 40 on the intermediate insulating film 39 in the z direction.

[0087] The first portion 26g is positioned so as to overlap both the internal wiring 26b and the second portion 26i when viewed from the z direction. The first portion 26g is located inward of the first portion 26f. The first portion 26g penetrates both the oxide film 26d and the intermediate insulating film 39 on the internal wiring 26b, and the barrier layer 40 on the intermediate insulating film 39, in the z direction. In this embodiment, the first portion 26g is embedded in the upper portion of the internal wiring 26b.

[0088] The second portion 26i is provided on the first portions 26f and 26g. The second portion 26i protrudes from the intermediate insulating film 39 on the side opposite to the drift layer 33. In other words, the second portion 26i protrudes above the intermediate insulating film 39. The protruding portion 26h consists of the end of the second portion 26i and the portion of the second portion 26i between the first portion 26f and the first portion 26g when viewed from the z direction. More specifically, when viewed from the z direction, the protruding portion 26h consists of both ends in the direction perpendicular to the direction in which the surface wiring 26c extends, that is, both ends in the width direction of the surface wiring 26c and the portion between the first portion 26f and the first portion 26g in the direction in which the surface wiring 26c extends.

[0089] The surface-side wiring 26c has a barrier metal layer 26m. The barrier metal layer 26m is formed on the surface 40s of the barrier layer 40, the inner surface 39q that constitutes the opening 39p, the inner surface 40q that constitutes the barrier layer-side opening 40p, the inner surface 38q that constitutes the opening 38p, and the surface (substrate surface 30s) of the drift layer 33 opened by these openings 38p, 39p, and 40p. Furthermore, the barrier metal layer 26m is formed on the inner surface 39t that constitutes the opening 39u, the inner surface 40t that constitutes the barrier layer-side opening 40u, the inner surface 26j that constitutes the opening 26e, and the surface of the internal wiring 26b opened by these openings 26e, 39u, and 40u. Therefore, the barrier metal layer 26m constitutes the portion of the first part 26f that is in contact with each of the inner surfaces 38q, 39q, and 40q, and the portion that is in contact with the surface of the channel stop region 26a. Furthermore, the barrier metal layer 26m comprises portions of the first portion 26g that are in contact with the inner surfaces 26j, 39t, and 40t, and portions that are in contact with the surface of the internal wiring 26b. The barrier metal layer 26m also comprises portions of the second portion 26i that are in contact with the surface 40s of the barrier layer 40. The barrier metal layer 26m is formed, for example, by a laminated structure of Ti and TiN.

[0090] The barrier layer 40 has an intermediate portion 41 which is the part that is inserted between the protruding portion 26h of the surface wiring 26c and the drift layer 33. In this embodiment, the intermediate portion 41 is sandwiched between the protruding portion 26h of the surface wiring 26c and the intermediate insulating film 39. Therefore, it can also be said that the barrier layer 40 has a portion (intermediate portion 41) that is sandwiched between the intermediate insulating film 39 and the protruding portion 26h of the surface wiring 26c. The intermediate portion 41 has barrier layer-side openings 40p and 40u through which the first portions 26f and 26g of the surface wiring 26c are inserted. Therefore, when viewed from the z direction, the intermediate portion 41 extends to the opening edges of the openings 39p and 39u in the intermediate insulating film 39 through which the first portions 26f and 26g of the surface wiring 26c are inserted.

[0091] As shown in Figures 4 to 7, the outer peripheral region 12 is covered by the passivation film 13. In other words, the barrier layer 40 can also be said to be covered by the passivation film 13 when viewed from the z direction. In this embodiment, the areas of the barrier layer 40 in which the gate fingers 23A, 23B, field plates 25e to 25h, and equipotential rings 26 are not formed are covered by the passivation film 13 with the surface 40s of the barrier layer 40 in contact with the passivation film 13. For this reason, the barrier layer 40 can also be said to be provided between the passivation film 13 and the drift layer 33.

[0092] Furthermore, the passivation film 13 is positioned above the intermediate insulating film 39 and overlaps with the intermediate insulating film 39 when viewed from the z direction. In other words, the passivation film 13 can be said to cover the intermediate insulating film 39.

[0093] (Method of manufacturing semiconductor devices) The manufacturing method of the semiconductor device 10 of the first embodiment will be described with reference to Figures 8 to 20. For convenience, Figures 8 to 20 show a simplified representation of the semiconductor device 10 during the manufacturing process. Therefore, the shape and size of the components of the semiconductor device 10 in Figures 8 to 20 may differ from those of the components of the semiconductor device 10 in Figures 1 to 4. Figures 8 to 20 show the manufacturing processes of a part of the cell region 11, the gate finger 23A, and a part of the FLR portion 25. Furthermore, for convenience, Figures 7 to 20 will be used to describe the manufacturing method of one semiconductor device 10. Hereinafter, the manufacturing method of the semiconductor device 10 of this embodiment is not limited to the manufacturing of one semiconductor device 10, but may also be used to manufacture multiple semiconductor devices 10.

[0094] The manufacturing method of the semiconductor device 10 of this embodiment includes a step of preparing a semiconductor substrate 830 formed from a material containing Si. The semiconductor substrate 830 has n as a first conductivity type semiconductor layer - It has a drift layer 33 of type 1. The drift layer 33 is formed over the entire semiconductor substrate 830. The semiconductor substrate 830 has a substrate surface 830s and a substrate back surface (not shown) that face opposite each other in the thickness direction (z direction). For this reason, the substrate surface 830s can also be said to be the surface of the drift layer 33. In this embodiment, the step of preparing the semiconductor substrate 830 corresponds to the "step of forming a first semiconductor layer of the first conductivity type in the peripheral region".

[0095] As shown in Figure 8, the manufacturing method of the semiconductor device 10 in this embodiment includes a step of forming a substrate-side insulating film 838B on the portion of the substrate surface 830s of the semiconductor substrate 830 that corresponds to the outer peripheral region 12. The substrate-side insulating film 838B is an insulating film that corresponds to the substrate-side insulating film 38B of the semiconductor device 10.

[0096] The step of forming the substrate-side insulating film 838B includes a step of thermally oxidizing the semiconductor substrate 830 to form a first insulating layer on the substrate surface 830s, a step of wet etching the first insulating layer, and a step of dry etching the first insulating layer.

[0097] Specifically, first, the semiconductor substrate 830 is thermally oxidized to form an oxide film over the entire surface of the semiconductor substrate 830. Next, the portion of the oxide film other than the outer peripheral region 12 of the substrate surface 830s of the semiconductor substrate 830 is removed. More specifically, the thickness of the oxide film is first reduced by wet etching. Meanwhile, in the outer peripheral region 12, the thickness of the oxide film is partially reduced using a mask. Next, the oxide film is removed by dry etching. In the outer peripheral region 12, the portion exposed by the mask is removed by dry etching. Through these steps, the substrate-side insulating film 838B is formed on the substrate surface 830s of the semiconductor substrate 830.

[0098] As shown in Figure 9, the manufacturing method of the semiconductor device 10 of this embodiment includes a step of forming a p-type well region 834 as a second conductivity type semiconductor region on a semiconductor substrate 830. Specifically, p-type impurities are selectively implanted into the substrate surface 830s of the semiconductor substrate 830. Subsequently, the p-type impurities are diffused by heat treatment of the semiconductor substrate 830. Through these steps, the well region 834 is formed. The well region 834 is partially formed in the drift layer 33. The surface of the well region 834 constitutes the substrate surface 830s and is therefore a continuous surface with the surface of the drift layer 33. Here, the well region 834 includes a base region 34A and guard rings 25a to 25d (guard ring 25d is not shown in Figure 9). Here, the step of forming the well region 834 on the semiconductor substrate 830 corresponds to "a step of partially forming a second semiconductor region of a second conductivity type having a surface continuous with the surface of the first semiconductor layer in the first semiconductor layer." Furthermore, it can be said that the well region 834 is covered by the substrate-side insulating film 838B.

[0099] As shown in Figure 10, the manufacturing method of the semiconductor device 10 in this embodiment includes a step of forming a plurality of trenches 835 in the semiconductor substrate 830. Specifically, first, a trench mask (not shown) is formed on the substrate surface 830s of the semiconductor substrate 830. Next, the trench mask is selectively etched. That is, when viewed from the z direction, the region of the trench mask in which the trenches 835 will be formed is etched. As a result, the region of the substrate surface 830s of the semiconductor substrate 830 in which the trenches 835 will be formed is exposed on the trench mask. Subsequently, the region of the substrate surface 830s of the semiconductor substrate 830 in which the trenches 835 will be formed is etched. As a result, trenches 835 are formed in the semiconductor substrate 830.

[0100] As shown in Figure 11, the manufacturing method of the semiconductor device 10 of this embodiment includes the steps of forming an insulating film 838 and forming an electrode. In the process of forming the insulating film 838, first, the semiconductor substrate 830 is thermally oxidized, forming an oxide film over the entire surface of the semiconductor substrate 830, including the inner surfaces of each trench 835. As a result, the insulating film 838 is formed on the cell region 11 of the substrate surface 830s of the semiconductor substrate 830. The insulating film 838 is the insulating film corresponding to the insulating film 38. The insulating film 838 in the cell region 11 is a gate insulating film and is also formed on the inner surfaces of each trench 835. Furthermore, in the outer peripheral region 12 of the semiconductor substrate 830, the insulating film 838 is laminated on the surface 838Bs of the substrate-side insulating film 838B.

[0101] Next, in the electrode formation process, electrode material PS such as polysilicon is embedded in each trench 835 and formed on the substrate surface 830s of the semiconductor substrate 830. This forms the gate trench 22A and the emitter trench 21A.

[0102] As shown in Figure 12, the manufacturing method of the semiconductor device 10 of this embodiment comprises the steps of etching the electrode material PS and forming an insulating film 838 on the electrode material PS. In the process of etching the electrode material PS, the electrode material PS is removed by etching from the cell region 11 of the substrate surface 830s of the semiconductor substrate 830, from the gate fingers 23A, 23B and gate electrode 22 of the outer peripheral region 12, and from the region other than the internal wiring 26b of the equipotential ring 26.

[0103] Next, in the step of forming an insulating film 838 on the electrode material PS, the electrode material PS embedded in each trench 835, the electrode material PS forming the gate fingers 23A, 23B and the gate electrode 22, and the electrode material PS forming the internal wiring 26b of the equipotential ring 26 are oxidized. As a result, an insulating film 838 is formed on each electrode material PS. Here, the electrode material PS of the gate fingers 23A, 23B corresponds to the gate layer 23a, and the insulating film 838 on the electrode material PS corresponds to the oxide film 23c of the gate fingers 23A, 23B and the oxide film 26d of the internal wiring 26b of the equipotential ring 26.

[0104] As shown in Figure 13, the manufacturing method of the semiconductor device 10 of this embodiment includes a step of forming a base region 34, an emitter region 36, and a channel stop region 26a (see Figure 7). Specifically, n-type and p-type dopants are selectively ion-implanted and diffused into the substrate surface 830s of the semiconductor substrate 830, thereby forming a p-type base region 34 and an n-type dopant. + The emitter region 36 and channel stop region 26a are formed sequentially. In other words, the emitter region 36 and channel stop region 26a are formed in the same process.

[0105] As shown in Figure 14, the manufacturing method of the semiconductor device 10 in this embodiment includes a step of forming an intermediate insulating film 839. The intermediate insulating film 839 is formed over the entire substrate surface 830s of the semiconductor substrate 830, for example, by chemical vapor deposition (CVD). The intermediate insulating film 839 is an insulating film corresponding to the intermediate insulating film 39. The intermediate insulating film 839 is laminated on the insulating film 838. In this case, in the cell region 11, the insulating film has a two-layer structure consisting of the insulating film 838 formed on the substrate surface 830s of the semiconductor substrate 830 and the intermediate insulating film 839. In the region where the gate electrode 22 and gate fingers 23A and 23B are formed, the insulating film has a two-layer structure consisting of the insulating film 838 formed on the electrode material PS and the intermediate insulating film 839. On the other hand, in the peripheral region 12, the insulating film has a three-layer structure consisting of the substrate-side insulating film 838B formed on the substrate surface 830s of the semiconductor substrate 830, the insulating film 838, and the intermediate insulating film 839. Thus, in this embodiment, the steps for forming the substrate-side insulating film 838B, the insulating film 838, and the intermediate insulating film 839 correspond to the "step for forming an insulating film that covers the surface of the first semiconductor layer and the surface of the second semiconductor region."

[0106] As shown in Figure 15, the manufacturing method of the semiconductor device 10 in this embodiment includes a step of forming a barrier layer 840. The barrier layer 840 is an insulating layer corresponding to the barrier layer 40 of the semiconductor device 10. The barrier layer 840 is formed of a material with a smaller diffusion coefficient than the intermediate insulating film 839 and insulating films 838, 838B. In this embodiment, the barrier layer 840 is made of a material containing silicon nitride (SiN) and is formed over the entire surface 839s of the intermediate insulating film 839, for example by CVD.

[0107] As shown in Figure 16, the manufacturing method of the semiconductor device 10 of this embodiment includes a step of forming an opening. In the cell region 11, openings 861 are formed by etching, penetrating the barrier layer 840, the intermediate insulating film 839, and the insulating film 838, respectively. The openings 861 in the cell region 11 expose the base region 34. These openings 861 form recesses 831 on the substrate surface 830s of the semiconductor substrate 830 corresponding to the base region 34.

[0108] In the outer peripheral region 12, openings 862 are formed by etching so as to penetrate the barrier layer 840, the intermediate insulating film 839, and the insulating film 838, respectively. The openings 862 in the outer peripheral region 12 individually expose, for example, the guard rings 25a to 25d. The openings 862 form recesses 832 on the substrate surface 830s of the semiconductor substrate 830 corresponding to the guard rings 25a to 25d.

[0109] In the region where gate fingers 23A and 23B are formed, openings 863 are formed by etching so as to penetrate the barrier layer 840, the intermediate insulating film 839, and the insulating film 838, respectively. The openings 863 in the region where gate fingers 23A and 23B are formed expose, for example, the electrode material. The openings 863 form recesses 833 on the surface of the electrode material. The formation of openings 861 to 863 forms insulating films 38 and 38A, the intermediate insulating film 39, and the barrier layer 40.

[0110] As shown in Figure 17, the manufacturing method of the semiconductor device 10 of this embodiment includes the step of forming the base contact region 37, contact region 23d, contact region 34B, and contact region 25p. Specifically, a p-type dopant is ion-implanted and diffused into the substrate surface 830s of the semiconductor substrate 830 through an opening, thereby forming the base contact region 37, contact region 23d, contact region 34B, and contact region 25p. + The base contact region 37, contact region 23d, contact region 34B, and contact region 25p are formed in the same shape. Figure 17 shows the base contact region 37, contact region 23d, and contact region 25p.

[0111] As shown in Figures 18 and 19, the manufacturing method of the semiconductor device 10 in this embodiment includes the steps of forming the emitter electrode 21, gate electrode 22, gate wiring 23b of gate fingers 23A and 23B, emitter routing section 24, field plates 25e to 25h, and equipotential ring 26. In this embodiment, the steps of forming the emitter electrode 21, gate electrode 22, gate wiring 23b of gate fingers 23A and 23B, emitter routing section 24, field plates 25e to 25h, and equipotential ring 26 correspond to the "step of forming the electrode section". Note that in Figures 18 and 19, the emitter electrode 21, gate wiring 23b of gate finger 23A, and field plates 25e to 25g are shown.

[0112] As shown in Figure 18, first, a first metal layer is formed on the surface 39s of the intermediate insulating film 39 and on the inner surfaces of each opening 861-863 by sputtering, for example, using titanium (Ti). Subsequently, a second metal layer is formed on the first metal layer by sputtering, using titanium nitride (TiN). This forms a barrier metal layer 823. Here, the barrier metal layer 823 corresponds to the barrier metal layer 21e of the emitter electrode 21, the barrier metal layer 23m of the gate finger 23A (23B), the barrier metal layer 24m of the emitter routing section 24, the barrier metal layer 25m of the field plates 25e-25h, and the barrier metal layer 26m of the equipotential ring 26. In other words, in this embodiment, the barrier metal layers 21e, 23m, 24m, 25m, and 26m are formed by the same process.

[0113] Next, plug electrodes 821 having tungsten (W) are embedded in each of the openings 861 to 863. Here, the plug electrodes 821 correspond to the plug electrode 21b of the emitter electrode 21, the first portion 23ba of the gate finger 23A (23B), the first portion 24a of the emitter routing portion 24, the first portion 27 of the field plates 25e to 25h, and the first portions 26f and 26g of the equipotential ring 26. In other words, in this embodiment, the plug electrode 21b and the first portions 23ba, 24a, 27, 26f, and 26g are formed by the same process.

[0114] Next, an electrode layer 822 is formed by sputtering using AlCu. The electrode layer 822 is formed over the entire intermediate insulating film 39 when viewed from the z direction. Here, the electrode layer 822 corresponds to the electrode body portion 21c of the emitter electrode 21, the second portion 23bb of the gate finger 23A (23B), the second portion 24b of the emitter routing portion 24, the second portion 28 of the field plates 25e to 25h, and the second portion 26i of the equipotential ring 26. In other words, in this embodiment, the electrode body portion 21c and the second portions 23bb, 24b, 28, and 26i are formed by the same process.

[0115] As shown in Figure 19, the emitter electrode 21, gate electrode 22, gate fingers 23A, 23B, emitter routing portion 24, field plates 25e to 25h, and equipotential ring 26 are formed by etching the electrode layer 822. Figure 19 shows the emitter electrode 21, gate finger 23A, and field plates 25e to 25g.

[0116] As shown in Figure 20, the manufacturing method of the semiconductor device 10 in this embodiment includes a step of forming a passivation film 13. Specifically, a passivation layer made of an organic material such as polyimide is formed over the entire substrate surface 830s of the semiconductor substrate 830 when viewed from the z direction, so as to cover the emitter electrode 21, gate electrode 22, gate fingers 23A, 23B, field plates 25e to 25h, and equipotential rings 26. Subsequently, openings are formed by etching to expose the emitter electrode 21 and gate electrode 22. This forms the passivation film 13, the emitter electrode pad 16, and the gate electrode pad 17. The passivation film 13 covers both the emitter electrode 21, gate electrode 22, gate fingers 23A, 23B, field plates 25e to 25h, and equipotential rings 26, and the barrier layer 40.

[0117] Although not shown in the figures, the manufacturing method of the semiconductor device 10 in this embodiment includes the steps of forming a buffer layer 32, a collector layer 31, and a collector electrode 29. Specifically, the buffer layer 32 and the collector layer 31 are sequentially formed by selective ion implantation and diffusion of n-type and p-type dopants into the back surface of the semiconductor substrate 830. Subsequently, the collector electrode 29 is formed on the surface of the collector layer 31 opposite to the buffer layer 32. The semiconductor device 10 is manufactured through these steps. Figures 8 to 20 show only a part of the manufacturing process of the semiconductor device 10, and the manufacturing method of the semiconductor device 10 may include steps not shown in Figures 8 to 20.

[0118] (Operation of the semiconductor device of the first embodiment) The passivation film 13, which is an organic insulating film such as polyimide, is formed over the entire main surface 10s of the semiconductor device 10 to protect it from external ions, for example. In other words, the passivation film 13 covers the entire outer peripheral region 12. However, because the passivation film 13 has a high diffusion coefficient, there is a risk that external ions may diffuse and pass through the passivation film 13.

[0119] When the intermediate insulating film 39 and insulating films 38,38A, which have a silicon oxide film, are charged by external ions, in particular when the intermediate insulating film 39 and insulating film 38A in the outer peripheral region 12 (for example, the FLR portion 25) are charged by external ions, the spread of the electric field in each guard ring 25a to 25d will differ, which may result in a voltage lower than the preset withstand voltage.

[0120] Therefore, in order to suppress the charging of the intermediate insulating film 39 and insulating films 38,38A by external ions, it is conceivable to provide a barrier layer having a silicon nitride film with a low diffusion coefficient. In one example, when a barrier layer is provided in the FLR section 25, the barrier layer may be provided, for example, on the surface 39s of the intermediate insulating film 39 and on the surfaces of the field plates 25e to 25h.

[0121] However, because the z-direction positions of the surfaces of the field plates 25e~25h and the surface 39s of the intermediate insulating film 39 are different, the portion of the barrier layer between the surface 39s of the intermediate insulating film 39 and the surfaces of the field plates 25e~25h forms a stepped shape. Here, cracks are prone to occur in the stepped portion of the barrier layer. Therefore, if cracks occur in the barrier layer, external ions may penetrate the intermediate insulating film 39 through the cracks, potentially causing it to become charged.

[0122] On the other hand, in this embodiment, the barrier layer 40 has an intermediate portion 41 sandwiched between the protrusions 28a of the field plates 25e to 25h and the intermediate insulating film 39. As a result, the barrier layer 40 does not have a stepped shape, and the portion of the intermediate insulating film 39 below the protrusions 28a is protected by the barrier layer 40. Therefore, the occurrence of cracks in the barrier layer 40 is suppressed, and thus the charging of the intermediate insulating film 39 by external ions due to cracks can be suppressed.

[0123] (Effects of the semiconductor device of the first embodiment) The semiconductor device 10 of this embodiment provides the following advantages. (1-1) The outer peripheral region 12 of the semiconductor device 10 includes an insulating film 38A and an intermediate insulating film 39 that cover both the drift layer 33 and the guard rings 25a to 25d, field plates 25e to 25h that penetrate the insulating film 38A and the intermediate insulating film 39 and contact the guard rings 25a to 25d individually, and a passivation film 13 that covers the insulating film 38A, the intermediate insulating film 39, and the field plates 25e to 25h. The field plates 25e to 25h include a first portion 27 provided within the openings 38c, 39c, and a second portion 28 having a protruding portion 28a that protrudes laterally from the first portion 27 and overlaps with the insulating film 38A and the intermediate insulating film 39. The semiconductor device 10 includes a barrier layer 40 provided between the passivation film 13 and the drift layer 33, which has a diffusion coefficient smaller than both the insulating film 38A and the intermediate insulating film 39 and the passivation film 13. The barrier layer 40 has a portion that fits between the protruding portion 28a of the field plate 25e to 25h and the guard ring 25a to 25d.

[0124] In this configuration, the barrier layer 40 is positioned between the protrusions 28a of the field plates 25e to 25h and the guard rings 25a to 25d, so that the lower portion of the protrusions 28a in the intermediate insulating film 39 is covered by the barrier layer 40. This protects the lower portion of the protrusions 28a in the intermediate insulating film 39 from external ions.

[0125] Furthermore, since a portion of the barrier layer 40 is embedded between the protrusion 28a and the guard rings 25a to 25d, it is not necessary to form the barrier layer 40 on the second portion 28 including the protrusion 28a in order to protect the lower portion of the protrusion 28a in the intermediate insulating film 39. This prevents the barrier layer 40 from becoming stepped. Therefore, since the occurrence of cracks in the barrier layer 40 is suppressed, the intermediate insulating film 39 corresponding to the FLR portion 25 can be prevented from being charged by external ions, and the decrease in the breakdown voltage of the FLR portion 25 can be suppressed.

[0126] Furthermore, since the configuration of the barrier layer 40 for the emitter routing section 24 and gate fingers 23A, 23B is the same as the configuration of the barrier layer 40 for the FLR section 25, crack formation can also be suppressed in the barrier layer 40 for the emitter routing section 24 and gate fingers 23A, 23B.

[0127] (1-2) The barrier layer 40 is formed on the surface 39s of the intermediate insulating film 39. The barrier layer 40 has an intermediate portion 41 which is sandwiched between the intermediate insulating film 39 and the protruding portions 28a of the field plates 25e to 25h.

[0128] With this configuration, the barrier layer 40 takes shape along the surface 39s of the intermediate insulating film 39. Therefore, the barrier layer 40 is not formed on the surface of the field plates 25e to 25h. In other words, the barrier layer 40 does not cover the field plates 25e to 25h including the second portion 28, and the field plates 25e to 25h are exposed from the barrier layer 40. This suppresses the formation of a stepped shape in the barrier layer 40. Therefore, the occurrence of cracks in the barrier layer 40 can be suppressed. Furthermore, since the configuration of the barrier layer 40 for the emitter routing portion 24 and gate fingers 23A and 23B is the same as the configuration of the barrier layer 40 for the FLR portion 25, the occurrence of cracks in the barrier layer 40 for the emitter routing portion 24 and gate fingers 23A and 23B can also be suppressed.

[0129] (1-3) The intermediate portion 41 of the barrier layer 40 has a barrier layer-side opening 40c. The inner surface 40d of the barrier layer-side opening 40c is flush with the inner surface 39d of the opening 39c of the intermediate insulating film 39.

[0130] In this configuration, the intermediate portion 41 of the barrier layer 40 is formed over the entire region where the protrusions 28a of the field plates 25e to 25h and the intermediate insulating film 39 overlap when viewed from the z direction. Therefore, the charging of the intermediate insulating film 39 by external ions can be further suppressed.

[0131] (1-4) When viewed from the z direction, the barrier layer 40 extends beyond the outer edges of the guard rings 25a to 25d. With this configuration, when viewed from the z direction, it is possible to suppress charging by external ions in the region of the intermediate insulating film 39 that overlaps with the guard rings 25a to 25d. Therefore, a decrease in the breakdown voltage of the FLR portion 25 can be suppressed.

[0132] (1-5) The thickness of the barrier layer 40 is thinner than the thickness of the intermediate insulating film 39. This configuration allows for easy manufacturing of the barrier layer 40, thereby reducing the manufacturing cost of the semiconductor device 10.

[0133] (1-6) The protruding portion 28a of the second portion 28 of the field plates 25e to 25h is positioned to overlap with the guard rings 25a to 25d when viewed from the z direction. The intermediate portion 41 of the barrier layer 40 is interposed between the protruding portion 28a of the field plates 25e to 25h and the guard rings 25a to 25d. This protects the portion of the intermediate insulating film 39 that is formed on the guard rings 25a to 25d and is covered by the protruding portion 28a of the field plates 25e to 25h.

[0134] (1-7) A method for manufacturing the semiconductor device 10 comprises the steps of: forming an insulating film 38A and an intermediate insulating film 39 on both the drift layer 33 and the guard rings 25a to 25d in the outer peripheral region 12; forming a barrier layer 40 having a smaller diffusion coefficient than the intermediate insulating film 39 on the surface 39s of the intermediate insulating film 39; forming field plates 25e to 25h including a first portion 27 provided within the opening 39c of the intermediate insulating film 39 and a second portion 28 having a protruding portion 28a that protrudes laterally from the first portion 27 and overlaps with both the intermediate insulating film 39 and the barrier layer 40; and forming a passivation film 13 that covers both the barrier layer 40 and the field plates 25e to 25h. With this configuration, the same effects as in (1-1) can be obtained.

[0135] [Second Embodiment] Referring to Figures 21 to 25, the semiconductor device 10 of the second embodiment will be described. In this embodiment, the arrangement position of the barrier layer 40 is different. In the following description, the differences from the semiconductor device 10 of the first embodiment will be described in detail, and components common to the semiconductor device 10 of the first embodiment will be denoted by the same reference numerals and their descriptions will be omitted.

[0136] (Configuration of a semiconductor device) The configuration of the semiconductor device 10 of this embodiment will be described with reference to Figures 21 and 22. Figure 21 shows the cross-sectional structure of a part of the FLR portion 25 of the outer peripheral region 12. Although not shown, the placement positions of the barrier layer 40 in the gate fingers 23A, 23B and the equipotential ring 26 are the same as the placement positions of the barrier layer 40 in the FLR portion 25. Note that, for convenience, some or all of the hatching of the components of the semiconductor device 10 is omitted in Figures 21 and 22.

[0137] As shown in Figure 21, in the outer peripheral region 12, the barrier layer 40 is formed on the surface 38s of the insulating film 38, which is the surface of the insulating film 38A, and is covered by the intermediate insulating film 39. In other words, the barrier layer 40 can be said to be sandwiched between the insulating film 38A and the intermediate insulating film 39. Alternatively, the intermediate insulating film 39 can be said to be formed on top of the insulating film 38A. The intermediate insulating film 39 is covered by the passivation film 13. For this reason, in this embodiment, the barrier layer 40 is not in contact with the passivation film 13.

[0138] In this embodiment, the open end of the barrier layer 40 is formed to conform to the shape of the open end of the opening 38c of the insulating film 38A. More specifically, the open end of the insulating film 38A has a curved portion 38j, similar to the first embodiment. The barrier layer 40 has a curved portion 42 that covers the curved portion 38j. The curved portion 42, similar to the curved portion 38j of the insulating film 38A, curves toward the substrate surface 30s of the semiconductor substrate 30 as it approaches the opening center of the barrier layer side opening 40c. The curved portion 42 of the barrier layer 40 is covered by the intermediate insulating film 39. Therefore, it can also be said that the intermediate insulating film 39 covers the curved portion 38j of the insulating film 38A.

[0139] The barrier layer 40 has an intermediate portion 41 which is the part that fits between the protrusion 28a of the field plate 25e and the guard ring 25a. In this embodiment, the intermediate portion 41 is the part of the barrier layer 40 that overlaps with both the protrusion 28a of the field plate 25e and the guard ring 25a when viewed from the z direction. In this embodiment, the intermediate portion 41 is provided at a position away from both the protrusion 28a and the guard ring 25a in the z direction. The intermediate portion 41 has a barrier layer-side opening 40c. Therefore, when viewed from the z direction, the intermediate portion 41 extends to the opening edge of the opening 38c of the insulating film 38A that inserts the first portion 27 of the field plate 25e. In other words, the intermediate portion 41 is in contact with the first portion 27. The barrier layer 40 also has an intermediate portion 41 for the other field plates 25f to 25h and guard rings 25b to 25d, similar to the first embodiment.

[0140] The barrier layer 40 is formed so as to extend beyond the guard rings 25a to 25d when viewed from the z direction. In other words, the barrier layer 40 covers the entirety of the guard rings 25a to 25d, except for the position where it overlaps with the first portion 27 of the field plates 25e to 25h when viewed from the z direction.

[0141] As shown in Figure 22, in the cell region 11, the barrier layer 40 is formed on the surface 38s of the insulating film 38, which forms the gate oxide film, and is covered by the intermediate insulating film 39. In other words, the barrier layer 40 is formed between the insulating film 38 and the intermediate insulating film 39 in the cell region 11. It can also be said that the barrier layer 40 is sandwiched in contact with both the insulating film 38 and the intermediate insulating film 39 in the cell region 11. The barrier layer 40 is formed along the shape of the surface 38s of the insulating film 38. It can also be said that the intermediate insulating film 39 is formed on top of the insulating film 38.

[0142] (Method of manufacturing semiconductor devices) The manufacturing method of the semiconductor device 10 of this embodiment will be described with reference to Figures 23 to 25. In the manufacturing method of the semiconductor device 10 of this embodiment, the order of steps for forming the barrier layer 840 is different from that of the manufacturing method of the semiconductor device 10 of the first embodiment. For this reason, the following description will explain the differences from the first embodiment and omit the description of the manufacturing steps that are common to the first embodiment.

[0143] As shown in Figure 23, in the manufacturing method of the semiconductor device 10 of this embodiment, the step of forming the barrier layer 840 is performed after the step of forming the base region 34 and the emitter region 36, and before the step of forming the intermediate insulating film 839. In other words, the step of forming the barrier layer 840 is performed after the step of forming the insulating films 838 and 838B. As a result, the barrier layer 840 is formed over the entire surface of the insulating film 838, for example by CVD. The barrier layer 840 is formed from the same material as the barrier layer 840 of the first embodiment. In this embodiment, the steps prior to the step of forming the base region 34 and the emitter region 36 are the same as in the first embodiment.

[0144] As shown in Figure 24, in the step of forming the intermediate insulating film 839, the intermediate insulating film 839 is formed over the entire surface 840s of the barrier layer 840, for example by CVD. In this embodiment, the step of forming the intermediate insulating film 839 corresponds to the "step of forming a second insulating film that covers the surface of the barrier layer".

[0145] As shown in Figure 25, openings 861 to 863 are formed. Through the above steps, insulating films 38, 38A, an intermediate insulating film 39, and a barrier layer 40 are formed. The subsequent manufacturing steps are the same as those for the manufacturing method of the semiconductor device 10 in the first embodiment.

[0146] (Effects of the second embodiment) The semiconductor device of this embodiment provides the following advantages. (2-1) The semiconductor device 10 comprises insulating films 38, 38A, an intermediate insulating film 39 formed on the insulating films 38, 38A, a barrier layer 40 formed on the surface 38s of the insulating films 38, 38A and covered by the intermediate insulating film 39, and a passivation film 13 covering the intermediate insulating film 39.

[0147] In this configuration, the barrier layer 40 is positioned between the protrusions 28a of the field plates 25e to 25h and the guard rings 25a to 25d, so the barrier layer 40 is not formed on the surface side of the field plates 25e to 25h. Therefore, the formation of a stepped shape in the barrier layer 40 can be suppressed. Consequently, the occurrence of cracks in the barrier layer 40 can be suppressed, which in turn suppresses the insulating film 38 corresponding to the FLR portion 25 from being charged by external ions, thereby suppressing a decrease in the breakdown voltage of the FLR portion 25.

[0148] Furthermore, since the configuration of the barrier layer 40 for the emitter routing section 24 and gate fingers 23A, 23B is the same as the configuration of the barrier layer 40 for the FLR section 25, crack formation can also be suppressed in the barrier layer 40 for the emitter routing section 24 and gate fingers 23A, 23B.

[0149] (2-2) A method for manufacturing a semiconductor device comprises the steps of: forming an insulating film 38A that covers the surface of the drift layer 33 and the surfaces of the guard rings 25a to 25d; forming a barrier layer 40 having a smaller diffusion coefficient than the insulating film 38 on the surface 38s of the insulating film 38 of the insulating film 38A; forming an intermediate insulating film 39 that covers the surface 40s of the barrier layer 40; forming field plates 25e to 25h that include a first portion 27 provided in the barrier layer side opening 40c and the openings 39c, 38c, and a second portion 28 having a protruding portion 28a that protrudes laterally from the first portion 27 and overlaps with both the intermediate insulating film 39 and the barrier layer 40; and forming a passivation film 13 that covers both the intermediate insulating film 39 and the field plates 25e to 25h. With this configuration, the same effects as in (2-1) can be obtained.

[0150] [Third Embodiment] The semiconductor device 10 of the third embodiment will be described with reference to Figures 26 to 33. In this embodiment, the shape of the insulating film formed on the substrate surface 30s of the semiconductor substrate 30 is different. In the following description, the differences from the semiconductor device 10 of the first embodiment will be described in detail, and components common to the semiconductor device 10 of the first embodiment will be denoted by the same reference numerals and their descriptions will be omitted.

[0151] (Configuration of a semiconductor device) The configuration of the semiconductor device 10 in this embodiment will be described with reference to Figure 26. Note that, for convenience, the hatching of the components of the semiconductor device 10 is omitted in Figure 26.

[0152] As shown in Figure 26, a LOCOS oxide film 50 is formed on the substrate surface 30s of the semiconductor substrate 30 in place of the substrate-side insulating film 38B. In other words, in this embodiment, the insulating film 38A consists of a laminated structure of the LOCOS oxide film 50 and the insulating film 38. The LOCOS oxide film 50 has a surface 50s and a back surface 50r that face opposite each other in the z direction. The back surface 50r of the LOCOS oxide film 50 is in contact with the substrate surface 30s of the semiconductor substrate 30.

[0153] The LOCOS oxide film 50 has a thick film portion 51, a thin film portion 52, and a sloped portion 53. The thick film portion 51 is a portion of the LOCOS oxide film 50 that is relatively thick, and is provided, for example, between adjacent guard rings 25a to 25d. The thin film portion 52 is a portion of the LOCOS oxide film 50 that is relatively thin, and is provided, for example, in a position that overlaps with the guard rings 25a to 25d when viewed from the z direction. The inclined portion 53 is provided between the thick film portion 51 and the thin film portion 52 and is a portion that connects the thick film portion 51 and the thin film portion 52. On both sides of the front surface 50s and the back surface 50r, the inclined portion 53 is inclined such that the thickness of the LOCOS oxide film 50 increases from the thin film portion 52 toward the thick film portion 51.

[0154] The thick film portion 51 is formed to bite into the substrate surface 30s of the semiconductor substrate 30. As a result, the semiconductor substrate 30 has a recessed portion 30a formed in the substrate surface 30s. An opening 54 is formed in the thin film portion 52, penetrating the thin film portion 52 in the z direction. As a result, a portion of the guard rings 25a to 25d is exposed from the LOCOS oxide film 50. In other words, the area of ​​the guard rings 25a to 25d viewed from the z direction is larger than the area of ​​the opening 54. The configuration of the LOCOS oxide film 50 can be arbitrarily changed. In one example, the thin film portion 52 may be omitted from the LOCOS oxide film 50. In this case, the LOCOS oxide film 50 will have a configuration in which multiple oxide films consisting of a thick film portion 51 and an inclined portion 53 are provided spaced apart from each other.

[0155] In this embodiment, an insulating film 38 is formed on the surface 50s of the LOCOS oxide film 50. The insulating film 38 is laminated on the LOCOS oxide film 50 according to its shape. That is, the insulating film 38 is inclined along the shape of the inclined portion 53 of the LOCOS oxide film 50. In this embodiment, the insulating film 38 is formed over the entire surface 50s of the LOCOS oxide film 50. An intermediate insulating film 39 is formed on the surface 38s of the insulating film 38. Therefore, the intermediate insulating film 39 is formed to cover all of the thick film portion 51, thin film portion 52, and inclined portion 53 of the LOCOS oxide film 50. In this embodiment, the intermediate insulating film 39 has a two-layer laminated structure.

[0156] A barrier layer 40 is formed on the surface 39s of the intermediate insulating film 39. In this embodiment, the barrier layer 40 is formed along the shape of the surface 39s of the intermediate insulating film 39. The thickness of the barrier layer 40 is greater than or equal to the thickness of the thin film portion 52 of the LOCOS oxide film 50. Also, the thickness of the barrier layer 40 is less than the thickness of the thick film portion 51 of the LOCOS oxide film 50. Note that the thickness of the barrier layer 40 is arbitrary and may be less than, for example, the thickness of the thin film portion 52 of the LOCOS oxide film 50.

[0157] The field plate 25e includes a first portion 27 provided within the openings 54, 39c and the barrier layer side opening 40c, and a second portion 28 having a protruding portion 28a that protrudes outward from the first portion 27 and overlaps with the intermediate insulating film 39. The configuration of the first portion 27 and the second portion 28 is the same as in the first embodiment.

[0158] The barrier layer 40 has an intermediate portion 41 which is the part that fits between the protruding portion 28a of the field plate 25e and the guard ring 25a. In this embodiment, as in the first embodiment, the intermediate portion 41 is sandwiched between the protruding portion 28a of the field plate 25e and the intermediate insulating film 39. Therefore, it can also be said that the barrier layer 40 has a portion (intermediate portion 41) that is sandwiched between the intermediate insulating film 39 and the protruding portion 28a of the field plate 25e. The intermediate portion 41 has a barrier layer-side opening 40c through which the first portion 27 of the field plate 25e is inserted. Therefore, when viewed from the z direction, the intermediate portion 41 extends to the opening edge of the opening 39c of the intermediate insulating film 39 through which the first portion 27 of the field plate 25e is inserted. The barrier layer 40 also has an intermediate portion 41 for the other field plates 25f to 25h and guard rings 25b to 25d, as in the first embodiment.

[0159] (Method of manufacturing semiconductor devices) The manufacturing method of the semiconductor device 10 of this embodiment will be described with reference to Figures 27 to 33. In the manufacturing method of the semiconductor device 10 of this embodiment, the method of forming the insulating film formed on the substrate surface 830s of the semiconductor substrate 830 differs from that of the manufacturing method of the semiconductor device 10 of the first embodiment. For this reason, the following description will explain the differences from the first embodiment and omit the explanation of the manufacturing process common to the first embodiment. Also, for convenience, the manufacturing method of the semiconductor device 10 of this embodiment will mainly describe the manufacturing process of the FLR portion 25.

[0160] As shown in Figures 27 to 29, the manufacturing method of the semiconductor device 10 of this embodiment includes a step of forming a LOCOS oxide film 850. As shown in Figure 27, first, a semiconductor substrate 830 formed from a material containing Si is prepared. A drift layer 33 is formed on the semiconductor substrate 830. Next, an oxide film 851 is formed over the entire substrate surface 830s of the semiconductor substrate 830, for example by CVD. The oxide film 851 has, for example, a silicon oxide film (SiO2 film). Next, a mask 852 is formed over the entire surface 851s of the oxide film 851, for example by CVD. The mask 852 has, for example, a silicon nitride film (Si3N4 film).

[0161] Next, as shown in Figure 28, the mask 852 is selectively etched. This partially exposes the oxide film 851 from the mask 852. Thus, it can be said that the mask 852 is formed on a portion of the surface of the drift layer 33. Subsequently, as shown in Figure 29, the oxide film 851 is thermally grown. This increases the thickness of the portion of the oxide film 851 not covered by the mask 852. On the other hand, the thermal growth of the oxide film 851 is suppressed in the portion covered by the mask 852. As a result, the oxide film 851 becomes partially thicker. Through these steps, the LOCOS oxide film 850 is formed. Next, the mask 852 is removed.

[0162] As shown in Figure 30, the manufacturing method of the semiconductor device 10 of this embodiment includes a step of forming a p-type well region 834, which is a second conductivity type semiconductor region. Specifically, p-type impurities are selectively implanted into the substrate surface 830s of the semiconductor substrate 830. Subsequently, the p-type impurities are diffused by heat treatment of the semiconductor substrate 830. This forms the well region 834. In Figure 30, the well region 834 includes guard rings 25a to 25c.

[0163] As shown in Figure 31, the manufacturing method of the semiconductor device 10 of this embodiment includes a step of forming an insulating film 838 and an intermediate insulating film 839. The method for forming the insulating film 838 and the intermediate insulating film 839 is the same as in the first embodiment. The insulating film 838 is formed on the surface 851s of the oxide film 851. The intermediate insulating film 839 is formed on the surface 838s of the insulating film 838.

[0164] As shown in Figure 32, the manufacturing method of the semiconductor device 10 of this embodiment includes a step of forming a barrier layer 840. The step of forming the barrier layer 840 is the same as in the first embodiment. As shown in Figure 33, the manufacturing method of the semiconductor device 10 of this embodiment includes a step of forming an opening 863. The method of forming the opening 863 is the same as in the first embodiment. This forms the LOCOS oxide film 50, the insulating film 38, the intermediate insulating film 39, and the barrier layer 40. The subsequent steps are also the same as in the first embodiment. Furthermore, the semiconductor device 10 of this embodiment provides the same effects as in the first embodiment.

[0165] [Example of changes] The embodiments described above are illustrative of possible forms of semiconductor devices and methods for manufacturing semiconductor devices according to this disclosure, and are not intended to limit their forms. Semiconductor devices and methods for manufacturing semiconductor devices according to this disclosure may take forms different from those illustrated in the embodiments described above. One example is a form in which parts of the configuration of each embodiment are replaced, modified, or omitted, or a form in which new configurations are added to each embodiment. Furthermore, the following modifications can be combined with each other as long as they do not contradict each other technically. In the following modifications, parts common to each embodiment are denoted by the same reference numerals as in each embodiment, and their descriptions are omitted.

[0166] In the third embodiment, as shown in Figure 34, the barrier layer 40 may be formed on the surface 38s of the insulating film 38, similar to the second embodiment. In this case, the barrier layer 40 is sandwiched between the insulating film 38 and the intermediate insulating film 39. The barrier layer 40 is formed along the shape of the surface 38s of the insulating film 38. Note that in Figure 34, for convenience, the hatching of the components of the semiconductor device 10 is omitted.

[0167] In each embodiment, the termination structure that relaxes the surface electric field of the outer peripheral region 12 is not limited to the FLR portion 25. For example, as shown in Figure 35, the semiconductor device 10 may, instead of the FLR portion 25, have an annular second conductivity type semiconductor region 60 extending in a direction perpendicular to the z direction in the region between the gate electrode 22 and gate fingers 23A, 23B (both see Figure 2) and the equipotential ring 26 within the outer peripheral region 12. The semiconductor region 60 is larger than the width of each guard ring 25a to 25d (the dimension of each guard ring 25a to 25d in the direction perpendicular to the z direction). The dopant concentration of the semiconductor region 60 is, for example, p + The dopant concentration is lower than that of the molded contact region 34B or the base contact region 37. The dopant concentration of the semiconductor region 60 is equal to, for example, the dopant concentration of the guard rings 25a to 25d. Note that in Figure 35, for convenience, the hatching of the components of the semiconductor device 10 is omitted.

[0168] In the illustrated example, the width of the emitter routing portion 24 (the dimension of the emitter routing portion 24 in the direction perpendicular to the z-direction) is formed to be larger than the width of the emitter routing portion 24 in each embodiment. When viewed from the z-direction, a portion of the emitter routing portion 24 is formed to overlap with the semiconductor region 60.

[0169] Furthermore, in the illustrated example, the semiconductor region 60 extends to the region where the equipotential ring 26 is formed. Viewed from the z direction, the semiconductor region 60 extends to a position that overlaps with the equipotential ring 26. Thus, the semiconductor region 60 includes a region that overlaps with the emitter routing portion 24 when viewed from the z direction, a region that overlaps with the equipotential ring 26 when viewed from the z direction, and a region between the emitter routing portion 24 and the equipotential ring 26. With this configuration, the surface electric field in the outer peripheral region 12 is mitigated by the semiconductor region 60, thereby improving the breakdown voltage of the semiconductor device 10.

[0170] In each embodiment, the formation range of the barrier layer 40 can be arbitrarily changed. In one example, the barrier layer 40 may be omitted from the cell region 11. That is, the barrier layer 40 may be formed only in the outer peripheral region 12. Also, the barrier layer 40 may be omitted from at least one of the gate fingers 23A, 23B, the emitter routing portion 24, and the equipotential ring 26 in the outer peripheral region 12.

[0171] In each embodiment, the intermediate insulating film 39 was composed of a single layer, but it is not limited to this. The intermediate insulating film 39 may be configured by stacking multiple insulating films of different types. In each embodiment, the gate trenches 22A and emitter trenches 21A were arranged alternately, but this is not limited to this arrangement. The arrangement of the gate trenches 22A and emitter trenches 21A can be changed as desired.

[0172] In each embodiment, the semiconductor device 10 was provided with a gate trench 22A and an emitter trench 21A, but is not limited thereto. For example, the semiconductor device 10 may not be provided with an emitter trench 21A.

[0173] In each embodiment, the first portion 27 and the second portion 28 of the field plates 25e to 25h of the FLR section 25 may be formed integrally. In this case, the first portion 27 is formed from AlCu instead of tungsten (W). The emitter electrode 21, gate fingers 23A, 23B, and emitter routing section 24 can also be modified in the same way as the field plates 25e to 25h.

[0174] In each embodiment, the semiconductor device 10 may be a planar gate type IGBT instead of a trench gate type IGBT. In each embodiment, the semiconductor device 10 is embodied as an IGBT, but it is not limited to this, and the semiconductor device 10 may be, for example, a SiCMOSFET (metal-oxide-semiconductor field-effect transistor) or a SiMOSFET.

[0175] As used in this disclosure, the term “on / above” includes the meanings of “on / above” and “above / beyond” unless the context clearly indicates otherwise. Therefore, the expression “A is formed on B” is intended to mean that in this embodiment, A may be in contact with B and directly positioned on B, but as a modified example, A may be positioned above B without contacting B. In other words, the term “on / above” does not preclude structures in which other members are formed between A and B.

[0176] The z-direction used in this disclosure does not necessarily have to be vertical, nor does it have to coincide perfectly with the vertical. Therefore, the various structures described herein are not limited to the z-direction "up" and "down" being the same as the z-direction "up" and "down" being the same as the vertical. For example, the x-direction may be vertical, or the y-direction may be vertical.

[0177] [Note] The technical concepts that can be understood from each of the above embodiments and their respective modifications are described below. The reference numerals for the components of the embodiments corresponding to the components described in each appendix are shown in parentheses. These reference numerals are provided as examples to aid understanding, and the components described in each appendix should not be limited to those indicated by these reference numerals.

[0178] (Note 1) A cell region (11) in which multiple cells (11A) are formed, A semiconductor device (10) comprising an outer peripheral region (12) provided outside the cell region (11) so as to surround the cell region (11), The aforementioned outer peripheral region (12) is A first semiconductor layer (33) of the first conductivity type, A second semiconductor region (25a to 25d) of the second conductivity type partially formed in the first semiconductor layer (33), An insulating film (38A, 39) covering the surface (30s) of the first semiconductor layer (33) and the surface (30s) of the second semiconductor region (25a~25d), An opening (38c, 39c) is formed in the insulating film (38A, 39) and exposes a part of the surface (30s) of the second semiconductor region (25a~25d), An electrode portion (25e~25h) is provided so as to be in contact with the portion exposed by the aforementioned opening (38c, 39c), The device comprises a passivation film (13) provided so as to cover both the insulating film (38A, 39) and the electrode portion (25e~25h), The electrode portion (25e~25h) is The first portion (27) provided within the aforementioned openings (38c, 39c), The first portion (27) has a second portion (28) having a protruding portion (28a) that protrudes laterally and overlaps with the insulating film (38A, 39), The semiconductor device (10) includes a barrier layer (40) provided between the passivation film (13) and the first semiconductor layer (33), the barrier layer having a smaller diffusion coefficient than both the insulating film (38A, 39) and the passivation film (13). The barrier layer (40) has a portion that extends between the protruding portion (28a) and the second semiconductor region (25a to 25d). Semiconductor equipment.

[0179] (Note 2) The barrier layer (40) is formed on the surface (38s) of the insulating film (38A, 39), The barrier layer (40) has a portion sandwiched between the insulating film (38A, 39) and the protruding portion (28a). The semiconductor device described in Appendix 1.

[0180] (Note 3) The insulating film (38A, 39) is A first insulating film (38A) is formed on both the surface (30s) of the first semiconductor layer (33) and the surface (30s) of the second semiconductor region (25a~25d), A second insulating film (39) is laminated on the first insulating film (38A), It has, The barrier layer (40) is formed on the surface (39s) of the second insulating film (39) and is covered by the passivation film (13). Semiconductor device as described in Appendix 2.

[0181] (Note 4) The insulating film (38A, 39) is A first insulating film (38A) is formed on both the surface (30s) of the first semiconductor layer (33) and the surface (30s) of the second semiconductor region (25a~25d), A second insulating film (39) formed on the first insulating film (38A), It has, The barrier layer (40) is formed on the surface (38s) of the first insulating film (38A) and is covered by the second insulating film (39). The second insulating film (39) is covered by the passivation film (13). The semiconductor device described in Appendix 1.

[0182] (Note 5) The portion of the first insulating film (38A) that constitutes the opening (38c) is inclined toward the first semiconductor layer (33) as it approaches the opening (38c), The second insulating film (39) covers the portion of the first insulating film (38A) that constitutes the opening (38c). Semiconductor device as described in Appendix 3 or 4.

[0183] (Note 6) The barrier layer (40) has a barrier layer-side opening (40c) into which the first portion (27) is inserted. The inner surface (40d) that constitutes the barrier layer side opening (40c) and the inner surfaces (38d, 39d) of the insulating film (38A, 39) that constitute the openings (38c, 39c) are flush with each other. A semiconductor device as described in any one of the appendices 1 to 5.

[0184] (Note 8) Viewed from the thickness direction (z direction) of the first semiconductor layer (33), the barrier layer (40) is formed to extend beyond the outer edge of the second semiconductor region (25a to 25d). A semiconductor device as described in any one of the appendices 1 to 6.

[0185] (Note 8) The thickness of the barrier layer (40) is thinner than the thickness of the insulating film (38A, 39). A semiconductor device as described in any one of the appendices 1 to 7.

[0186] (Note 9) The cell region (11) is a region where a transistor is formed. The aforementioned first semiconductor layer (33), A gate oxide film (38) formed on the surface (30s) of the first semiconductor layer (33), The gate oxide film (38) comprises an intermediate insulating film (39) formed on the surface (38s) of the gate oxide film (38), The barrier layer (40) is formed on the surface (39s) of the intermediate insulating film (39). Semiconductor device as described in Appendix 2 or 3.

[0187] (Note 10) The cell region (11) is a region where a transistor is formed. The aforementioned first semiconductor layer (33), A gate oxide film (38) formed on the surface (30s) of the first semiconductor layer (33), The gate oxide film (38) is formed on an intermediate insulating film (39), and the intermediate insulating film (39) is formed on the gate oxide film (38). The barrier layer (40) is formed in the cell region (11) between the gate oxide film (38) and the intermediate insulating film (39). Semiconductor device as described in Appendix 4.

[0188] (Note 11) The outer peripheral region (12) has a second conductivity type semiconductor region (25a~25d, 60) for mitigating the surface electric field. A semiconductor device as described in any one of the appendices 1 to 10.

[0189] (Note 12) The insulating film (38A, 39) is a silicon oxide film. The passivation film (13) is an organic insulating film, The barrier layer (40) is a silicon nitride film. A semiconductor device as described in any one of the appendices 1 to 11.

[0190] (Note 13) A cell region (11) in which multiple cells (11A) are formed, A method for manufacturing a semiconductor device comprising: an outer peripheral region (12) provided outside the cell region (11) so as to surround the cell region (11), The process of forming a first semiconductor layer (33) of a first conductivity type in the outer peripheral region (12), A step of partially forming a second semiconductor region (834) of the second conductivity type in the first semiconductor layer (33), A step of forming insulating films (838B, 838, 839) that cover the surface (830s) of the first semiconductor layer (33) and the surface (830s) of the second semiconductor region (834), A step of forming a barrier layer (840) on the surface (839s) of the insulating film (839) having a smaller diffusion coefficient than the insulating films (838B, 838, 839), A step of forming openings (861-863) that penetrate both the insulating film (838B, 838, 839) and the barrier layer (840) and expose a part of the second semiconductor region (834), A step of forming an electrode portion (25e~25h) including a first portion (821) provided within the openings (861~863), and a second portion (822) having a protruding portion that protrudes laterally from the first portion (821) and overlaps with both the insulating film (838B, 838, 839) and the barrier layer (840), A method for manufacturing a semiconductor device, comprising the step of forming a passivation film that covers both the barrier layer (840) and the electrode portion.

[0191] (Note 14) The step of forming the aforementioned insulating film (838B, 838, 839) is: A step of forming a first insulating film (838B, 838) by thermal oxidation of the surface (830s) of the first semiconductor layer (33), The process includes the step of forming a second insulating film (839) on the surface of the first insulating film (838) by CVD, The method for manufacturing a semiconductor device as described in Appendix 13.

[0192] (Note 15) The step of forming the first insulating film (838B, 838) is: A step of forming a mask (852) on a part of the surface (830s) of the first semiconductor region (33), The process includes a step of oxidizing the portion of the surface (830s) of the first semiconductor region (33) that is exposed from the mask (852) to form an oxide film (851), The method for manufacturing a semiconductor device as described in Appendix 14.

[0193] (Note 16) The step of forming the first insulating film (838B) is as follows: A step of forming a first insulating layer by thermal oxidation of the surface (830s) of the first semiconductor layer (33), The process includes wet etching the first insulating layer, followed by dry etching. The method for manufacturing a semiconductor device as described in Appendix 14.

[0194] (Note 17) A cell region (11) in which multiple cells (11A) are formed, A method for manufacturing a semiconductor device (10) comprising an outer peripheral region (12) provided outside the cell region (11) so as to surround the cell region (11), The process of forming a first semiconductor layer (33) of a first conductivity type in the outer peripheral region (12), A step of partially forming a second semiconductor region (834) of the second conductivity type in the first semiconductor layer (33), A step of forming a first insulating film (838B, 838) that covers the surface (830s) of the first semiconductor layer (33) and the surface (830s) of the second semiconductor region (834), A step of forming a barrier layer (840) on the surface (838s) of the first insulating film (838) having a smaller diffusion coefficient than the first insulating film (838B, 838), A step of forming a second insulating film (839) that covers the surface (840s) of the barrier layer (840), A step of forming an opening (861) that penetrates the first insulating film (838B, 838), the second insulating film (839), and the barrier layer (840) to expose a part of the second semiconductor region (834), A step of forming an electrode portion (25e~25h) including a first portion (821) provided within the opening (861), and a second portion (822) having a protruding portion that protrudes laterally from the first portion (821) and overlaps with both the second insulating film (839) and the barrier layer (840), A method for manufacturing a semiconductor device, comprising the step of forming a passivation film (13) that covers both the second insulating film (839) and the electrode portion.

[0195] (Note 18) The step of forming the first insulating film (838B, 838) includes the step of thermally oxidizing the surface (830s) of the first semiconductor layer (33), The step of forming the second insulating film (839) includes the step of forming the second insulating film (839) on the surface (840s) of the barrier layer (840) by CVD. The method for manufacturing a semiconductor device as described in Appendix 17.

[0196] (Note 19) The step of forming the first insulating film (838B) is as follows: A step of forming a mask (852) on a part of the surface (830s) of the first semiconductor layer (33), The process includes a step of oxidizing the portion of the surface (830s) of the first semiconductor layer (33) that is exposed from the mask (852) to form an oxide film (851), The method for manufacturing a semiconductor device as described in Appendix 18.

[0197] (Note 20) The step of forming the first insulating film (838B) is as follows: A step of forming a first insulating layer by thermal oxidation of both the surface (830s) of the first semiconductor layer (33) and the surface (830s) of the second semiconductor region (834), The process includes wet etching the first insulating layer, followed by dry etching. The method for manufacturing a semiconductor device as described in Appendix 18. [Explanation of Symbols]

[0198] 10...Semiconductor device, 11...Cell region, 12...Peripheral region, 13...Passivation film, 23A, 23B...Gate finger, 23ba...First part, 23bb...Second part, 23bc...Protrusion, 24...Emitter routing part, 24a...First part, 24b...Second part, 24c...Protrusion, 25a~25d...Guard ring (Second semiconductor region of second conductivity type), 25e~25h...Field plate (Electrode part), 27...First part, 28...Second part, 28a...Protrusion, 33...Drift layer (First semiconductor region of first conductivity type), 38...Insulating film (Gate oxide film), 38A...Insulating film (First insulating film), 38s...Surface, 38a, 38c, 38g, 38p...Opening, 38d, 38h...Inner surface, 3 9...Intermediate insulating film (second insulating film), 39s...Surface, 39a,39c,39e,39g,39p,39u...Openings, 39b,39d,39f,39h,39q,39t...Inner surfaces, 40...Barrier layer, 40s...Surface, 40a,40c,40e,40g,40p,40u...Openings on the barrier layer side, 40b,40d,40f,40h,40q,4 0t...inner surface, 41...intermediate part, 50...LOCOS oxide film, 54...opening, 821...first part, 822...second part, 830...semiconductor substrate, 838...insulating film, 838s...surface, 839...intermediate insulating film, 839s...surface, 840...barrier layer, 840s...surface, 851...oxide film, 851s...surface, 852...mask, 861~863...opening.

Claims

1. A cell region in which multiple cells are formed, An outer peripheral region is provided outside the cell region so as to surround the cell region, A semiconductor device equipped with, The aforementioned cell region is A first semiconductor layer of the first conductivity type, Terminal gate and, An insulating film covering the surface of the gate electrode, Equipped with, The aforementioned semiconductor device is A barrier layer having a smaller diffusion coefficient than the insulating film is provided on the surface of the insulating film, A main electrode provided so as to cover both the insulating film and the barrier layer, A passivation film that overlaps with at least a portion of the barrier layer in a plan view, Equipped with, The insulating film comprises a plurality of first openings that penetrate the insulating film in the thickness direction of the first semiconductor layer, The barrier layer comprises a plurality of second openings that penetrate the barrier layer in the thickness direction and communicate with the plurality of first openings, The main electrode is embedded across the first and second openings which are in communication with each other. The angle formed by the inner surface of the first opening with respect to the thickness direction and the angle formed by the inner surface of the second opening communicating with the first opening with respect to the thickness direction are different from each other. Semiconductor equipment.

2. The first semiconductor layer comprises a second semiconductor region of a second conductivity type that is partially formed therein. The insulating film is A first insulating film formed on both the surface of the first semiconductor layer and the surface of the second semiconductor region, A second insulating film laminated on the first insulating film, It has, The barrier layer is formed on the surface of the second insulating film and is covered by the passivation film. The semiconductor device according to claim 1.

3. The thickness of the barrier layer is thinner than the thickness of the insulating film. The semiconductor device according to claim 1 or 2.

4. The aforementioned cell region is a region where a transistor is formed. The first semiconductor layer and, A gate oxide film formed on the surface of the first semiconductor layer, An intermediate insulating film formed on the surface of the gate oxide film, Equipped with, The barrier layer is formed on the surface of the intermediate insulating film. The semiconductor device according to claim 2.

5. The aforementioned outer peripheral region has a semiconductor region of a second conductivity type for mitigating the surface electric field. A semiconductor device according to any one of claims 1 to 4.

6. The insulating film is a silicon oxide film. The passivation film is an organic insulating film, The barrier layer is a silicon nitride film. The semiconductor device according to any one of claims 1 to 5.

7. The first semiconductor layer comprises a second semiconductor region of a second conductivity type that is partially formed therein. The insulating film covers the surface of the second semiconductor region. A semiconductor device according to any one of claims 1 to 6.

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