Multilayer ceramic capacitor

Abstract

To provide a multilayer ceramic capacitor that improves productivity by reducing chip transport failures. [Solution] A multilayer ceramic capacitor 10 comprising stacked dielectric layers, first and second internal electrode layers, and first and second external electrodes 30a and 30b, wherein dimension L is shorter than dimension W, and dimension T is shorter than dimension L. The first external electrode has a first covering portion 30a0 and first to fourth folded portions 30a1 to 30a4, and the second external electrode has a second covering portion 30b0 and fifth to eighth folded portions 30b1 to 30b4. The first folded portion has a first maximum thickness point 30aP, which is the region with the greatest thickness in the stacking direction, and the fifth folded portion has a second maximum thickness point 30bP, which is the region with the greatest thickness in the stacking direction, and the first maximum thickness point of the first folded portion and the second maximum thickness point of the fifth folded portion are located diagonally with respect to the center points of the first and second directions of the first main surface.

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor. [Background Art]

[0002] Conventionally, multilayer ceramic capacitors have been known as multilayer ceramic electronic components. A general multilayer ceramic capacitor includes a substantially rectangular parallelepiped multilayer body in which a dimension in the length direction is longer than a dimension in the width direction, and external electrodes are provided at both ends in the length direction of the multilayer body. On the other hand, in order to reduce ESL (equivalent series inductance), a so-called LW-reversed multilayer ceramic capacitor, in which the magnitude relationship between the length dimension and the width dimension of the multilayer body is reversed, is also known (see Patent Document 1 and Patent Document 2).

[0003] Furthermore, in recent years, as the mounting density of substrates has increased, the mounting area of multilayer ceramic capacitors has decreased. Accordingly, a PoP (Package on Package) mounting form has been adopted, and demand for multilayer ceramic capacitors mounted in an LSC (Land side Capacitor) type on the lower end portion of a substrate has been increasing. As such a multilayer ceramic capacitor mounted in the LSC type, a low-profile multilayer ceramic capacitor having a small thickness in the height direction is required. [Prior Art Literature] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2020-57753 [Patent Document 2] Japanese Patent Application Laid-Open No. 2020-61524 [Summary of the Invention] [Problems to be Solved by the Invention]

[0005] In the manufacturing process of multilayer ceramic capacitors (measurement process, visual inspection process, packaging process), when the contact area of ​​the chip with the transport part increases during chip transport by the equipment, the chip may stick to the transport part due to static electricity, etc., leading to a problem of decreased productivity (equipment utilization rate) due to chip transport malfunctions. In particular, multilayer ceramic capacitors with a thin thickness in the height direction, as described above, have a lighter chip weight, making this problem even more pronounced.

[0006] Therefore, the main objective of this invention is to provide a structure that can improve productivity by reducing the contact area of ​​the chips with the transport section during chip transport by equipment in the manufacturing process, thereby improving chip adhesion due to static electricity, etc., and reducing chip transport malfunctions. [Means for solving the problem]

[0007] The multilayer ceramic capacitor according to this invention comprises a laminate having a plurality of stacked dielectric layers and a plurality of internal electrode layers stacked on the dielectric layers, having a first and second surface facing the stacking direction, a third and fourth surface facing the first direction perpendicular to the stacking direction, and a fifth and sixth surface facing the second direction perpendicular to the stacking direction and the first direction, a first internal electrode layer disposed on the plurality of dielectric layers and drawn out to the third surface, a second internal electrode layer disposed on the plurality of dielectric layers and drawn out to the fourth surface, a first external electrode disposed on the third surface and connected to the first internal electrode layer, and a second external electrode disposed on the fourth surface and connected to the second internal electrode layer, wherein the dimension l of the laminate in the first direction is shorter than the dimension w of the laminate in the second direction, and the dimension t of the laminate in the stacking direction is shorter than the dimension l of the laminate in the first direction, and the first external electrode is located on the third surface The second external electrode has a covering portion, a first folded portion located on a part of the first surface, a second folded portion located on a part of the second surface, a third folded portion located on a part of the fifth surface, and a fourth folded portion located on a part of the sixth surface, and the second external electrode has a second covering portion located on the fourth surface, a fifth folded portion located on a part of the first surface, a sixth folded portion located on a part of the second surface, a seventh folded portion located on a part of the fifth surface, and the sixth surface A multilayer ceramic capacitor having an eighth folded portion located in part of the first main surface, wherein the first folded portion has a first maximum thickness point which is the region with the greatest thickness in the stacking direction, and the fifth folded portion has a second maximum thickness point which is the region with the greatest thickness in the stacking direction, and the first maximum thickness point of the first folded portion and the second maximum thickness point of the fifth folded portion are located diagonally with respect to the center points of the first and second directions of the first main surface.

[0008] According to the multilayer ceramic capacitor of the present invention, the dimension l of the laminate in the first direction is shorter than the dimension w of the laminate in the second direction, and the dimension t of the laminate in the stacking direction is shorter than the dimension l of the laminate in the first direction. Furthermore, the first folded portion has a first maximum thickness point, which is the region with the greatest thickness in the stacking direction, and the fifth folded portion has a second maximum thickness point, which is the region with the greatest thickness in the stacking direction. The first maximum thickness point of the first folded portion and the second maximum thickness point of the fifth folded portion are located diagonally with respect to the center points of the first and second directions of the first main surface. As a result, in the manufacturing process of the multilayer ceramic capacitor (measurement process, visual inspection process, packaging process), the contact area of ​​the multilayer ceramic capacitor with the transport part is reduced when the multilayer ceramic capacitor is transported by the equipment, thereby improving the adhesion of the multilayer ceramic capacitor due to static electricity, etc., and improving productivity (equipment utilization rate) due to transport problems of the multilayer ceramic capacitor. [Effects of the Invention]

[0009] According to this invention, in the manufacturing process, by reducing the contact area of ​​the chips with the transport section during chip transport by equipment, it is possible to improve chip adhesion due to static electricity, etc., and to provide a structure that can improve productivity by reducing chip transport malfunctions.

[0010] The above-mentioned objectives, other objectives, features, and advantages of this invention will become even clearer from the following description of embodiments for carrying out the invention, with reference to the drawings. [Brief explanation of the drawing]

[0011] [Figure 1] This is an external perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of this invention. [Figure 2] This is a plan view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. [Figure 3] This is a side view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. [Figure 4]It is a cross-sectional view taken along line IV-IV in FIG. 1. [Figure 5] It is a cross-sectional view taken along line V-V in FIG. 1. [Figure 6] It is a cross-sectional view taken along line VI-VI in FIG. 1. [Figure 7] It is an explanatory diagram of a manufacturing method showing the step of forming a base electrode layer. [Figure 8] It is an explanatory diagram of a manufacturing method showing the step of forming a maximum thickness portion. [Figure 9] It is an explanatory diagram for explaining the amount of deviation of the maximum thickness point at the folded portion from the second direction center line in an experimental example. MODE FOR CARRYING OUT THE INVENTION

[0012] 1. Multilayer Ceramic Capacitor A multilayer ceramic capacitor according to an embodiment of the present invention will be described.

[0013] FIG. 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 2 is a plan view showing an example of the multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 3 is a side view showing an example of the multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 1. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 1. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 1.

[0014] As shown in FIGS. 1 to 3, the multilayer ceramic capacitor 10 includes a rectangular parallelepiped multilayer body 12 and external electrodes 30 disposed at both end portions of the multilayer body 12.

[0015] The multilayer body 12 includes a plurality of stacked dielectric layers 14 and a plurality of internal electrode layers 16 stacked on the dielectric layers 14. The internal electrode layers 16 include a first internal electrode layer 16a and a second internal electrode layer 16b. Details of the first internal electrode layer 16a and the second internal electrode layer 16b will be described later.

[0016] The laminate 12 has a first surface 12a and a second surface 12b opposing each other in the lamination direction x, a third surface 12c and a fourth surface 12d opposing each other in a first direction y orthogonal to the lamination direction x, and a fifth surface 12e and a sixth surface 12f opposing each other in a second direction z orthogonal to the lamination direction x and the first direction y.

[0017] The laminate 12 has a rectangular parallelepiped shape, and it is preferable that corners and ridge portions of the laminate 12 are rounded. A corner is a portion where three surfaces of the laminate 12 intersect, and a ridge portion is a portion where two surfaces of the laminate 12 intersect. Further, unevenness or the like may be formed on part or all of the first surface 12a, the second surface 12b, the third surface 12c, the fourth surface 12d, and the fifth surface 12e and the sixth surface 12f.

[0018] Here, let the dimension of the laminate 12 in the first direction y be the l-dimension, the dimension of the laminate 12 in the second direction z be the w-dimension, and the dimension of the laminate 12 in the lamination direction x be the t-dimension. In this case, the dimensional relationship satisfies w>l>t.

[0019] The laminate 12 includes a capacitance forming portion 18, and a first outer layer portion 20a located on the first surface 12a side and a second outer layer portion 20b located on the second surface 12b side, which are arranged so as to sandwich the capacitance forming portion 18 in the lamination direction x.

[0020] In the capacitance forming portion 18, first internal electrode layers 16a and second internal electrode layers 16b are alternately laminated with dielectric layers 14 interposed therebetween.

[0021] The first outer layer portion 20a is an aggregate of a plurality of dielectric layers 14 located on the first surface 12a side of the laminate 12 and between the first surface 12a and the capacitance forming portion 18 closest to the first surface 12a. The second outer layer portion 20b is an aggregate of a plurality of dielectric layers 14 located on the second surface 12b side of the laminate 12 and between the second surface 12b and the capacitance forming portion 18 closest to the second surface 12b. Further, the region sandwiched between the first outer layer portion 20a and the second outer layer portion 20b is the capacitance forming portion 18.

[0022] The volume-forming section 18 is positioned in the center of the stacking direction x. More specifically, in the stacking direction x connecting the first surface 12a and the second surface 12b, the center position of the laminate 12 and the center position of the volume-forming section 18 are approximately the same.

[0023] As shown in Figure 5, the laminate 12 has side portions (W gaps) 26a and 26b located between the volume-forming portion 18 and the fifth surface 12e, and between the volume-forming portion 18 and the sixth surface 12f.

[0024] Furthermore, as shown in Figure 4, the laminate 12 is located between the volume-forming portion 18 and the third surface 12c, and between the volume-forming portion 18 and the fourth surface 12d, and has ends (L gaps) 27a, 27b of the laminate 12 that include the first extraction electrode portion 24a and the second extraction electrode portion 24b of the first internal electrode layer 16a.

[0025] The dielectric layer 14 can be made of a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as the ceramic material. Alternatively, a material may be used in which minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, or Ni compounds are added to the main components.

[0026] The thickness of the dielectric layer 14 is preferably 0.30 μm or more and 5.00 μm or less. Furthermore, the number of dielectric layers 14 to be stacked is preferably 10 or more and 200 or less. Note that this number of dielectric layers 14 is the sum of the number of dielectric layers 14 in the capacitance forming section 18 and the number of dielectric layers 14 in the first outer layer section 20a and the second outer layer section 20b.

[0027] As shown in Figures 4 and 5, the internal electrode layer 16 has a first internal electrode layer 16a and a second internal electrode layer 16b. The first internal electrode layer 16a and the second internal electrode layer 16b are alternately stacked with an inner dielectric layer 14a in between.

[0028] The first internal electrode layer 16a is arranged on a plurality of dielectric layers 14 and is located inside the laminate 12. The first internal electrode layer 16a has a first opposing electrode portion 22a facing the second internal electrode layer 16b, and a first leading electrode portion 24a located on one end side of the first internal electrode layer 16a, extending from the first opposing electrode portion 22a to the third surface 12c of the laminate 12. The end of the first leading electrode portion 24a is led out to the surface of the third surface 12c and exposed from the laminate 12. In other words, the end of the first leading electrode portion 24a is not exposed to the first surface 12a, the second surface 12b, the fourth surface 12d, the fifth surface 12e, and the sixth surface 12f. In detail, the end of the first internal electrode layer 16a is slightly recessed from the fourth surface 12d.

[0029] The shape of the first opposing electrode portion 22a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0030] The shape of the first lead-out electrode portion 24a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0031] The second internal electrode layer 16b is arranged on a plurality of dielectric layers 14 and is located inside the laminate 12. The second internal electrode layer 16b has a second opposing electrode portion 22b facing the first internal electrode layer 16a, and a second leading electrode portion 24b located on one end of the second internal electrode layer 16b, extending from the second opposing electrode portion 22b to the fourth surface 12d of the laminate 12. The end of the second leading electrode portion 24b is led out to the surface of the fourth surface 12d and exposed from the laminate 12. In other words, the end of the second leading electrode portion 24b is not exposed to the first surface 12a and the second surface 12b, the third surface 12c, and the fifth surface 12e and the sixth surface 12f. In detail, the end of the second internal electrode layer 16b is slightly recessed from the third surface 12c.

[0032] The shape of the second opposing electrode portion 22b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0033] The shape of the second lead-out electrode portion 24b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0034] The width of the second opposing electrode portion 22b of the second internal electrode layer 16b and the width of the second leading electrode portion 24b of the second internal electrode layer 16b may be the same, or one of them may be narrower.

[0035] The number of first internal electrode layers 16a is not particularly limited, but is preferably, for example, 1 to 100. Similarly, the number of second internal electrode layers 16b is not particularly limited, but is preferably, for example, 1 to 100. Therefore, the total number of first internal electrode layers 16a and second internal electrode layers 16b is preferably 2 to 200.

[0036] The thickness of the first internal electrode layer 16a is not particularly limited, but is preferably, for example, 0.30 μm or more and 3.00 μm or less. Similarly, the thickness of the second internal electrode layer 16b is not particularly limited, but is preferably, for example, 0.30 μm or more and 3.00 μm or less.

[0037] The first internal electrode layer 16a and the second internal electrode layer 16b can be made of appropriate conductive materials such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ag-Pd alloys. In particular, when Cu is the main component, low loss characteristics (i.e., high Q characteristics) can be obtained due to its low conductivity.

[0038] By including a Sn layer between the first internal electrode layer 16a and the second internal electrode layer 16b and the dielectric layer 14, electric field concentration at the interface between the internal electrode layer and the ceramic layer can be mitigated, leading to improved high-temperature load reliability.

[0039] (external electrode) External electrodes 30 are arranged on the third surface 12c and the fourth surface 12d of the laminate 12, as shown in Figures 1 to 3.

[0040] The external electrode 30 includes a base electrode layer 32 containing a metal component and glass, and a plating layer 34 disposed on the surface of the base electrode layer 32.

[0041] The external electrode 30 has a first external electrode 30a and a second external electrode 30b.

[0042] The first external electrode 30a is positioned on the third surface 12c side. The first external electrode 30a is also connected to the first internal electrode layer 16a. The first external electrode 30a is positioned on the third surface 12c and has a first covering portion 30a0 that covers the first internal electrode layer 16a exposed on the third surface 12c, a first folded portion 30a1 that extends from the first covering portion 30a0 and is located in part of the first surface 12a, a second folded portion 30a2 that extends from the first covering portion 30a0 and is located in part of the second surface 12b, a third folded portion 30a3 that extends from the first covering portion 30a0 and is located in part of the fifth surface 12e, and a fourth folded portion 30a4 that extends from the first covering portion 30a0 and is also located in part of the sixth surface 12f.

[0043] The second external electrode 30b is positioned on the fourth surface 12d. The second external electrode 30b is also connected to the second internal electrode layer 16b. The second external electrode 30b is positioned on the fourth surface 12d and has a second covering portion 30b0 that covers the first internal electrode layer 16a exposed on the fourth surface 12d, a fifth folded portion 30b1 extending from the second covering portion 30b0 and located in part of the first surface 12a, a sixth folded portion 30b2 extending from the second covering portion 30b0 and located in part of the second surface 12b, a seventh folded portion 30b3 extending from the second covering portion 30b0 and located in part of the fifth surface 12e, and an eighth folded portion 30b4 extending from the second covering portion 30b0 and also located in part of the sixth surface 12f.

[0044] The first external electrode 30a has a first maximum thickness point 30aP in the first folded portion 30a1 located on the first surface 12a side, which is the region with the greatest thickness in the stacking direction x. The first maximum thickness point 30aP of the first folded portion 30a1 located on the first surface 12a side is located on the fifth surface 12e side of the first folded portion 30a1.

[0045] The second external electrode 30b has a second maximum thickness point 30bP in the fifth folded portion 30b1 located on the first surface 12a side, which is the region with the greatest thickness in the stacking direction x. The second maximum thickness point 30bP of the fifth folded portion 30b1 located on the first surface 12a side is located on the sixth surface 12f side of the fifth folded portion 30b1.

[0046] The first external electrode 30a has a minimum thickness point in a region defined by excluding the area within 10% of the dimension of the first folded portion 30a1 in the second direction z from both ends of the first folded portion 30a1 in the second direction z.

[0047] The second external electrode 30b has a minimum thickness point in a region defined by excluding the area within 10% of the dimension of the fifth folded portion 30b1 in the second direction z from both ends of the fifth folded portion 30b1 in the second direction z.

[0048] As shown in Figure 2, the first maximum thickness point 30aP of the first folded portion 30a1 and the second maximum thickness point 30bP of the fifth folded portion 30b1 are located diagonally with respect to the center point CP of the first direction y and the second direction z of the first surface 12a.

[0049] The first maximum thickness point 30aP of the first folded portion 30a1 is preferably located on the fifth surface 12e side with respect to the center of the second direction z of the first folded portion 30a1. The second maximum thickness point 30bP of the fifth folded portion 30b1 is preferably located on the sixth surface 12f side with respect to the center of the second direction z of the fifth folded portion 30b1.

[0050] Preferably, the first maximum thickness point 30aP of the first folded portion 30a1 is located outside a range of ±10% of the length in the second direction z from the center of the second direction z of the first folded portion 30a1. Also, preferably, the second maximum thickness point 30bP of the fifth folded portion 30b1 is located outside a range of ±10% of the length in the second direction z from the center of the second direction z of the fifth folded portion 30b1.

[0051] The ratio of the thickness of the first maximum thickness point 30aP of the first folded portion 30a1 to the thickness of the minimum thickness point of the first folded portion 30a1 is preferably 1.4 or more and 2.5 or less. Furthermore, the ratio of the thickness of the second maximum thickness point 30bP of the fifth folded portion 30b1 to the thickness of the minimum thickness point of the fifth folded portion 30b1 is preferably 1.4 or more and 2.5 or less.

[0052] With the above configuration, in the manufacturing process of multilayer ceramic capacitors, particularly in the measurement process, visual inspection process, and packaging process, the contact area of ​​the chip with the transport part during chip transport by the equipment is reduced, thereby improving chip adhesion due to static electricity, etc., and improving productivity (equipment utilization rate) due to chip transport malfunctions.

[0053] Here, the thickness of the first maximum thickness point 30aP of the first folded portion 30a1 and the thickness of the second maximum thickness point 30bP of the fifth folded portion 30b1 are measured as follows. Using a laser displacement meter, the positions of the first maximum thickness point 30aP of the first external electrode 30a and the second maximum thickness point 30bP of the second external electrode 30b are determined.

[0054] The thickness of the first maximum thickness point 30aP of the first external electrode 30a is determined by reading the height position of the first maximum thickness point 30aP and the height position of the surface of the laminate 12 from the laser displacement graph of the LT surface containing the first maximum thickness point 30aP. The difference between the read height position of the first maximum thickness point 30aP of the first external electrode 30a and the height position of the surface of the laminate 12 is defined as the magnitude of the thickness of the first maximum thickness point 30aP of the first external electrode 30a. The thickness of the second maximum thickness point 30bP of the second external electrode 30b is determined by reading the height position of the second maximum thickness point 30bP and the height position of the surface of the laminate 12 from the laser displacement graph of the LT surface containing the second maximum thickness point 30bP. The difference between the read height position of the second maximum thickness point 30bP of the second external electrode 30b and the height position of the surface of the laminate 12 is defined as the magnitude of the thickness of the second maximum thickness point 30bP of the second external electrode 30b.

[0055] Here, the thickness of the minimum thickness point of the first folded portion 30a1 and the thickness of the minimum thickness point of the fifth folded portion 30b1 are measured as follows. Using a laser displacement meter, the position of the minimum thickness point on the first external electrode 30a is determined in the range excluding the area within 10% of the dimension of the first folded portion 30a1 in the second direction z from both ends of the first folded portion 30a1 in the second direction z. Similarly, the position of the minimum thickness point on the first external electrode 30a is determined in the range excluding the area within 10% of the dimension of the fifth folded portion 30b1 in the second direction z from both ends of the fifth folded portion 30b1 in the second direction z. The position of the minimum thickness point on the second external electrode 30b is specified within the range excluding the area within %.

[0056] Then, the thickness of the minimum thickness point of the first external electrode 30a is determined from the laser displacement graph, within the range excluding the area within 10% of the dimension of the second direction z of the first folded portion 30a1 from both ends of the second direction z of the first folded portion 30a1. The height position of the minimum thickness point of the first external electrode 30a and the height position of the surface of the laminate 12 are read. The difference between the read height position of the minimum thickness point of the first external electrode 30a and the height position of the surface of the laminate 12 is defined as the magnitude of the thickness of the minimum thickness point of the first external electrode 30a. The thickness of the minimum thickness point of the second external electrode 30b is located at a position half the length of the fifth folded portion 30b1 on the WT surface. The position of the minimum thickness point of the second external electrode 30b is identified from the laser displacement graph, within the range excluding the area within 10% of the dimension of the fifth folded portion 30b1 in the second direction z from both ends of the fifth folded portion 30b1 in the second direction z, and the height position of the surface of the laminate 12 is read. The difference between the read height position of the minimum thickness point of the second external electrode 30b and the height position of the surface of the laminate 12 is defined as the magnitude of the thickness of the minimum thickness point of the second external electrode 30b.

[0057] Furthermore, if the positions of the first maximum thickness point 30aP located in the first folded portion 30a1 and the second maximum thickness point 30bP located in the fifth folded portion 30b1 are diagonally opposite to the center point CP of the first direction y and the second direction z of the first surface 12a of the multilayer ceramic capacitor 10, the contact area of ​​the chip with the transport portion is reduced.

[0058] Furthermore, if there is a large difference in the thickness of the first folded portion 30a1 and the fifth folded portion 30b1 within their respective folded surfaces, the contact area of ​​the chip with the transport section of the equipment will be further reduced, and problems with chip transport will be further improved.

[0059] Within the laminate 12, capacitance is formed when the first opposing electrode portion 22a of the first internal electrode layer 16a and the second opposing electrode portion 22b of the second internal electrode layer 16b face each other via the dielectric layer 14. Therefore, capacitance can be obtained between the first external electrode 30a to which the first internal electrode layer 16a is connected and the second external electrode 30b to which the second internal electrode layer 16b is connected, resulting in the characteristics of a capacitor.

[0060] The external electrode 30 includes a base electrode layer 32 placed on the surface of the laminate 12 and a plating layer 34 placed so as to cover the base electrode layer 32.

[0061] The base electrode layer 32 has a first base electrode layer 32a and a second base electrode layer 32b.

[0062] The plating layer 34 has a first plating layer 34a and a second plating layer 34b.

[0063] In other words, the first external electrode 30a has a first base electrode layer 32a and a first plating layer 34a. The second external electrode 30b has a second base electrode layer 32b and a second plating layer 34b.

[0064] The first underlay electrode layer 32a is positioned on the surface of the third surface 12c of the laminate 12 and is formed to extend from the third surface 12c and cover a portion of each of the first surface 12a, the second surface 12b, the fifth surface 12e, and the sixth surface 12f. The second base electrode layer 32b is positioned on the surface of the fourth surface 12d of the laminate 12 and is formed to extend from the fourth surface 12d and cover a portion of each of the first surface 12a, the second surface 12b, the fifth surface 12e, and the sixth surface 12f.

[0065] The base electrode layer 32 includes at least one selected from a baked layer and a conductive resin layer, etc. The following describes the configurations when the base electrode layer 32 is the baked layer and the conductive resin layer described above.

[0066] (In the case of a baked-on layer) The baked layer contains a glass component and a metal component. The glass component of the baked layer contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal component of the baked layer contains at least one selected from, for example, Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The baked layer may consist of multiple layers. The baked layer is obtained by applying a conductive paste containing the glass component and the metal component to the laminate 12 and baking it. The baked layer may be obtained by simultaneously baking the laminate chip having the internal electrode layer 16 and the dielectric layer 14 and the conductive paste applied to the laminate chip, or by baking the laminate chip having the internal electrode layer 16 and the dielectric layer 14 to obtain the laminate 12, and then applying the conductive paste to the laminate 12 and baking it. Furthermore, when firing a laminated chip having an internal electrode layer 16 and a dielectric layer 14 and a conductive paste applied to the laminated chip simultaneously, it is preferable to form the firing layer by firing a material with a dielectric material added instead of a glass component.

[0067] The thickness of the first underlay electrode layer 32a located on the third surface 12c in the first direction y connecting the third surface 12c and the fourth surface 12d in the central part of the lamination direction x is preferably 10 μm or more and 40 μm or less. Furthermore, the thickness of the second underlay electrode layer 32b located on the fourth surface 12d in the first direction y connecting the third surface 12c and the fourth surface 12d at the center of the lamination direction x is preferably 10 μm or more and 40 μm or less.

[0068] When the first base electrode layer 32a is provided on a portion of the first surface 12a and a portion of the second surface 12b, and on a portion of the fifth surface 12e and a portion of the sixth surface 12f, the thickness in the lamination direction x connecting the first surface 12a and the second surface 12b at the center of the first direction y connecting the third surface 12c and the fourth surface 12d of the first base electrode layer 32a located on the first surface 12a and the second surface 12b is preferably, for example, 3 μm or more and 30 μm or less. Furthermore, the thickness in the second direction z connecting the fifth surface 12e and the sixth surface 12f at the center of the first direction y connecting the third surface 12c and the fourth surface 12d of the first base electrode layer 32a located on the fifth surface 12e and the sixth surface 12f is preferably, for example, 3 μm or more and 30 μm or less.

[0069] Furthermore, when a second base electrode layer 32b is provided on a part of the first surface 12a and a part of the second surface 12b, and a part of the fifth surface 12e and a part of the sixth surface 12f, the thickness in the lamination direction x connecting the first surface 12a and the second surface 12b at the center of the first direction y connecting the third surface 12c and the fourth surface 12d of the second base electrode layer 32b located on the first surface 12a and the second surface 12b is preferably, for example, 3 μm or more and 30 μm or less. Moreover, the thickness in the second direction z connecting the fifth surface 12e and the sixth surface 12f at the center of the first direction y connecting the third surface 12c and the fourth surface 12d of the second base electrode layer 32b located on the fifth surface 12e and the sixth surface 12f is preferably, for example, 3 μm or more and 30 μm or less.

[0070] (In the case of a conductive resin layer) The conductive resin layer may be arranged on top of the baking layer so as to cover it, or it may be arranged directly on the laminate 12 without a baking layer. Furthermore, the conductive resin layer may completely cover the baking layer, or it may cover only a portion of it. In addition, there may be multiple conductive resin layers.

[0071] The conductive resin layer contains a thermosetting resin and a metal. Because the conductive resin layer contains a thermosetting resin, it is more flexible than a baked layer consisting of, for example, a plated film or a baked conductive paste. Therefore, even if the multilayer ceramic capacitor 10 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer functions as a buffer layer, preventing cracks in the multilayer ceramic capacitor 10.

[0072] The metals that can be included in the conductive resin layer include Ag, Cu, Ni, Sn, Bi, or alloys containing these metals. Alternatively, metal powder with an Ag coating on its surface can be used. When using metal powder with an Ag coating, it is preferable to use Cu, Ni, Sn, Bi, or alloys thereof as the metal powder. The reason for using Ag conductive metal powder is that Ag has the lowest resistivity among metals, making it suitable for electrode materials; and because Ag is a noble metal, it does not oxidize and has high weather resistance. Furthermore, it allows for the use of less expensive base metals while maintaining the above-mentioned properties of Ag.

[0073] Furthermore, the metals included in the conductive resin layer can be Cu or Ni that have been treated to prevent oxidation. Additionally, metal powders coated with Sn, Ni, or Cu can be used as the metals included in the conductive resin layer. When using metal powders coated with Sn, Ni, or Cu, it is preferable to use Ag, Cu, Ni, Sn, Bi, or alloys thereof as the metal powder.

[0074] The metals contained in the conductive resin layer are primarily responsible for the conductivity of the conductive resin layer. Specifically, conductive fillers come into contact with each other, forming an electrical pathway within the conductive resin layer.

[0075] The metal contained in the conductive resin layer can be spherical, flattened, or otherwise, but it is preferable to use a mixture of spherical and flattened metal powders.

[0076] As the resin for the conductive resin layer, various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin can be used. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins.

[0077] Furthermore, it is preferable that the conductive resin layer contains a curing agent along with the thermosetting resin. When epoxy resin is used as the base resin, various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds can be used as curing agents for the epoxy resin.

[0078] The thickest part of the conductive resin layer is preferably, for example, 5 μm to 40 μm.

[0079] The plating layer 34 is positioned to cover the underlying electrode layer 32.

[0080] The plating layer 34 includes, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc.

[0081] The plating layer 34 may be formed from multiple layers. In this case, the plating layer 34 preferably has a two-layer structure consisting of Ni plating and Sn plating. The Ni plating layer is used to prevent the underlying electrode layer 32 from being corroded by the solder when mounting the multilayer ceramic capacitor 10. The Sn plating layer is used to improve the wettability of the solder when mounting the multilayer ceramic capacitor 10, thereby facilitating mounting. The thickness of each layer of the plating layer 34 is preferably 1 μm or more and 6 μm or less.

[0082] The dimension in the first direction y of the multilayer ceramic capacitor 10, which includes the laminate 12, the first external electrode 30a, and the second external electrode 30b, is defined as dimension L. The dimension in the stacking direction x of the multilayer ceramic capacitor 10, which includes the laminate 12, the first external electrode 30a, and the second external electrode 30b, is defined as dimension T. The dimension in the second direction z of the multilayer ceramic capacitor 10, which includes the laminate 12, the first external electrode 30a, and the second external electrode 30b, is defined as dimension W. The dimensions of the multilayer ceramic capacitor 10 are as follows: the L dimension in the first direction y is 0.30 mm to 0.80 mm; the W dimension in the second direction z is 0.60 mm to 1.60 mm; and the T dimension in the stacking direction x is 0.10 mm to 0.60 mm. The dimensions of the multilayer ceramic capacitor 10 can also be measured using a microscope.

[0083] In the multilayer ceramic capacitor 10 shown in Figure 1, when the dimension of the laminate 12 in the first direction y is denoted as dimension l, the dimension of the laminate 12 in the second direction z is denoted as dimension w, and the dimension of the laminate 12 in the stacking direction x is denoted as dimension t, the dimensional relationship is w>l>t. The first external electrode 30a has a first maximum thickness point 30aP, which is the region with the greatest thickness in the stacking direction x, at the first folded portion 30a1 located on the first surface 12a side. The second external electrode 30b has a second maximum thickness point 30bP, which is the region with the greatest thickness in the stacking direction x, at the fifth folded portion 30b1 located on the first surface 12a side. The first maximum thickness point 30aP of the first folded portion 30a1 and the second maximum thickness point 30bP of the fifth folded portion 30b1 are located diagonally with respect to the center point CP of the first direction y and the second direction z of the first surface 12a. As a result, in the manufacturing process of the multilayer ceramic capacitor 10 (measurement process, visual inspection process, packaging process), the contact area of ​​the multilayer ceramic capacitor 10 with the transport section during transport by the equipment is reduced, thereby improving the adhesion of the multilayer ceramic capacitor 10 due to static electricity, etc., and potentially improving productivity (equipment utilization rate) due to transport problems of the multilayer ceramic capacitor 10.

[0084] Furthermore, in the multilayer ceramic capacitor 10 shown in Figure 1, if the ratio of the thickness of the first maximum thickness point 30aP of the first folded portion 30a1 to the thickness of the minimum thickness point of the first folded portion 30a1 is 1.4 or more and 2.5 or less, and the ratio of the thickness of the second maximum thickness point 30bP of the fifth folded portion 30b1 to the thickness of the minimum thickness point of the fifth folded portion 30b1 is 1.4 or more and 2.5 or less, then a large difference in the folded surface reduces the contact area of ​​the multilayer ceramic capacitor 10 with the equipment transport section, thereby further improving transport problems of the multilayer ceramic capacitor 10.

[0085] 2. Manufacturing method of multilayer ceramic capacitors Next, a method for manufacturing a multilayer ceramic capacitor 10 according to an embodiment of this invention will be described.

[0086] First, a dielectric sheet for the dielectric layer and a conductive paste for the internal electrode layer are prepared. The dielectric sheet and the conductive paste for the internal electrode layer contain a binder and a solvent. The binder and solvent may be known substances.

[0087] A conductive paste for the internal electrode layer is printed onto the dielectric sheet in a predetermined pattern, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the pattern for the first internal electrode layer formed on it, and a dielectric sheet with the pattern for the second internal electrode layer formed on it.

[0088] More specifically, a gravure printing plate can be prepared for printing the first internal electrode layer and the second internal electrode layer, and each internal electrode layer of the present invention can be printed.

[0089] Next, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form a portion that will become the second outer layer 20b on the second surface 12b side. Then, a portion that will become the capacitance forming section 18 is formed by alternately stacking sheets with printed first internal electrode layers and sheets with printed second internal electrode layers on the portion that will become the second outer layer 20b. Next, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked on the portion that will become the capacitance forming section 18 to form a portion that will become the first outer layer 20a on the first surface 12a side. This completes the production of the laminated sheet.

[0090] Next, the laminated sheets are pressed in the lamination direction using means such as hydrostatic pressing to produce a laminated block.

[0091] Next, the laminated block is cut to a predetermined size, thereby cutting out the laminated chips. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or other methods.

[0092] The laminated chips that have been cut out are then fired to produce the laminated body 12. The firing temperature depends on the materials of the dielectric layer 14 and the internal electrode layer 16, but is preferably between 900°C and 1400°C.

[0093] (base electrode layer) Next, a first base electrode layer 32a of the first external electrode 30a is formed on the third surface 12c of the laminate 12 obtained by firing, and a second base electrode layer 32b of the second external electrode 30b is formed on the fourth surface 12d of the laminate 12. In this embodiment, the first base electrode layer 32a and the second base electrode layer 32b are formed using the DIP method so as to extend not only to the third surface 12c and the fourth surface 12d, but also to a part of the first surface 12a, a part of the second surface 12b, a part of the fifth surface 12e, and a part of the sixth surface 12f.

[0094] When forming a baked layer as the base electrode layer 32, a conductive paste containing glass and metal components is applied, and then a baking process is performed to form the baked layer as the base electrode layer 32. The temperature of the baking process at this time is preferably 700°C to 900°C. In this embodiment, the base electrode layer 32 is formed of a baked layer.

[0095] The method for forming the base electrode layer 32 will be described below with reference to Figure 7.

[0096] First, the fired laminate 12 is fixed with its third surface 12c facing upwards, and its fourth surface 12d side is fixed to the adhesive surface 40a of the first holding jig 40, which is equipped with an adhesive layer. An unsintered first base electrode layer 60a is formed by immersing the third surface 12c of the laminate 12 vertically into a paste tank 50 in which conductive paste 60 has been formed to a certain thickness using a blade or the like on a metal surface plate 52. Next, the third surface 12c, after the conductive paste 60 has been applied, is pressed against the adhesive surface 42a of the second holding jig 42, which has an adhesive layer with higher adhesive strength than the adhesive layer of the first holding jig 40, thereby transferring the fired laminate 12 to the second holding jig 42. In this way, the laminate is fixed to the second holding jig 42 with the fourth surface 12d facing upwards. The conductive paste 60 is applied to the fourth surface 12d in the same manner as the conductive paste 60 is applied to the third surface 12c. This forms an unsintered second base electrode layer 60b.

[0097] Next, an example of a method for forming the maximum thickness portions diagonally on the first folded portion 30a1 of the first external electrode 30a and the fifth folded portion 30b1 of the second external electrode 30b will be described.

[0098] As shown in Figure 8, the coating apparatus 80 at the maximum thickness comprises a slit plate 82, a closing member 86, and a pressing member 88, and the laminate 70 on which the unsintered base electrode layer is formed is held by a holding plate 90.

[0099] The slit plate 82 has one main surface 82a and the other main surface 82b facing each other at a predetermined distance apart. The side of the slit plate 82 with the one main surface 82a is the side on which the laminate 70, on which the unsintered base electrode layer is formed, is placed. On the side of the slit plate 82 with the one main surface 82a, there are a number of slits 84a having a width corresponding to the width to which the conductive paste 62 should be applied to the laminate 12. On the side of the slit plate 82 with the other main surface 82b, there is a cavity 84b that is wider than the slits 84a and is filled with the conductive paste 62, defining a space that communicates with the space in the slits 84a. Such a slit plate 82 is made of, for example, an iron-based metal such as stainless steel or a rigid body such as ceramic.

[0100] The closing member 86 is positioned on the other main surface 82b side of the slit plate 82 to close the opening of the cavity 84b. The closing member 86 is made of an elastic material such as silicone rubber, and its thickness is about 5 mm or less. It is preferable that the closing member 86 is joined to the slit plate 82 so as to be in close contact and integrated with it.

[0101] The pressing member 88 has a projection 88a formed at a position facing the cavity 84b of the slit plate 82. The projection 88a provided on the pressing member 88 has a width that is less than or equal to the width of the cavity 84b.

[0102] Next, with reference to Figure 8, a method for forming a baked layer using the coating apparatus 80 at the maximum thickness will be described.

[0103] First, the coating device 80 for the thickest part is prepared, and the conductive paste 62 is filled into the slits 84a and cavities 84b of the slit plate 82.

[0104] Then, conductive paste 62 is filled into a cavity 84b having a slit 84a of a certain width on its upper surface. In order to align the orientation of the laminate 70 after the formation of the unsintered base electrode layer in a certain direction, the laminate 70 is held by the holding plate 90. The position of the laminate 70 held by the holding plate 90, which is shifted from the center line in the second direction z toward the fifth surface 12e, is aligned with the position of the slit 84a, and the third surface 12c, which has been formed after the unsintered base electrode layer has been created, is lowered to a height that contacts the surface of one main surface 82a of the slit plate 82.

[0105] Next, the conductive paste 62 filled in the cavity 84b of the slit plate 82 is pushed up by the pressing member 88 using air pressure or the like, and the conductive paste 62 is pushed out from the slit 84a to the surface. The conductive paste 62 pushed out from the slit 84a is applied to predetermined positions on the third surface 12c and the first surface 12a of the unsintered first base electrode layer 60a formed on the third surface 12c side, forming the first maximum thickness portion 62a. Similarly, the conductive paste 62 pushed out from the slit 84a is applied to predetermined positions on the fourth surface 12d and the first surface 12a of the unsintered second base electrode layer 60b formed on the fourth surface 12d side, forming the second maximum thickness portion 62b.

[0106] Here, by transferring the third surface 12c to the surface of the platen, the excess conductive paste 62 adhering to the third surface 12c is scraped off, and by transferring the fourth surface 12d to the surface of the platen, the excess conductive paste 62 adhering to the fourth surface 12d is scraped off. In this way, a laminate 72 is obtained in which an unsintered base electrode layer and a maximum thickness portion are formed.

[0107] Next, if necessary, plating is applied to the surface of the base electrode layer to form a plating layer. In this embodiment, two plating layers are formed on the surface of the base electrode layer. Specifically, a Ni plating layer and a Sn plating layer are formed on the base electrode layer. Electrolytic plating is preferred as the plating process. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating.

[0108] As described above, the multilayer ceramic capacitor 10 according to this embodiment is manufactured.

[0109] 3. Experimental Examples Next, in order to confirm the effect of the multilayer ceramic capacitor according to the present invention as described above, experimental samples were prepared according to the manufacturing method described above, as shown in Figure 9, by changing the amount of deviation (deviation rate) from the center line l0 in the second direction z of the first and fifth folded parts, and by changing the ratio of the maximum thickness point to the minimum thickness point of the first and fifth folded parts. Experiments were then conducted to check the equipment failure rate and the number of tombstone defects that occurred during substrate mounting.

[0110] (1) Specifications of the multilayer ceramic capacitor fabricated as a sample for the experimental example Using the manufacturing method according to the above embodiment, multilayer ceramic capacitors, which are samples numbered 1 to 13, were fabricated. • Structure of a multilayer ceramic capacitor: Multilayer ceramic capacitor shown in Figure 1 • Dimension of the first direction of the multilayer ceramic capacitor: 0.50 mm • Dimension of the multilayer ceramic capacitor in the second direction: 1.00 mm • Dimensions in the stacking direction of multilayer ceramic capacitors: 0.20 mm • Dielectric layer thickness: 1.00 μm • Thickness of the internal electrode layer: 0.70 μm • Number of first internal electrode layers: 43 • Number of layers in the second internal electrode layer: 42 • Thickness of the first outer layer: 30 μm • Thickness of the second outer layer: 30 μm L-gap dimension: 100 μm • W-gap dimension: 100 μm • Plating layer Formation of a two-layer structure consisting of a Ni plating layer and a Sn plating layer. Ni plating layer thickness: approximately 3 μm Sn plating layer thickness: approximately 5 μm

[0111] As a comparative example, a sample was prepared in which the maximum thickness point of the first folded portion and the maximum thickness point of the fifth folded portion were located approximately in the center of the second direction z in each folded portion. As an example, a sample was prepared in which the point of maximum thickness of the first folded portion and the point of maximum thickness of the fifth folded portion are located diagonally with respect to the center points of the first direction y and the second direction z of the first main surface. In addition, samples were prepared in which the ratio of the maximum thickness point to the minimum thickness point of the first and fifth folded sections was varied, and samples were prepared in which the amount of deviation of the first and fifth folded sections from the center point in the second direction z was varied.

[0112] (2) Point of maximum thickness (2-1) How to confirm the position of the point of maximum thickness Using a laser displacement meter (KEYENCE Corporation, model number VK-X1000), the position of the point of maximum thickness was determined at the first folded portion of the first external electrode and the fifth folded portion of the second external electrode. (2-2) Method for measuring the thickness at the point of maximum thickness The thickness of the first external electrode at its maximum thickness point was determined by reading the height position of the maximum thickness point and the height position of the laminate surface from the laser displacement graph of the LT surface containing the maximum thickness point. The difference between the height position of the maximum thickness point of the first external electrode and the height position of the laminate surface was defined as the magnitude of the thickness of the first external electrode at its maximum thickness point. The thickness of the second external electrode at its maximum thickness point was determined by reading the height position of the maximum thickness point and the height position of the laminate surface from the laser displacement graph of the LT surface containing the maximum thickness point. The difference between the height position of the maximum thickness point of the second external electrode and the height position of the laminate surface was defined as the magnitude of the thickness of the second external electrode at its maximum thickness point.

[0113] (3) Minimum thickness point (3-1) Method for confirming the position of the minimum thickness point Using a laser displacement meter (KEYENCE, model VK-X1000), the position of the minimum thickness point on the first external electrode was determined within the range excluding the area within 10% of the dimension of the first folded portion in the second direction z from both ends of the first folded portion in the second direction z. Similarly, the position of the minimum thickness point on the second external electrode was determined within the range excluding the area within 10% of the dimension of the fifth folded portion in the second direction z from both ends of the fifth folded portion in the second direction z. (3-2) Method for measuring the thickness of the point of minimum thickness The thickness of the minimum thickness point of the first external electrode was determined from the laser displacement graph, within the range excluding the area within 10% of the dimension of the second direction z of the first folded portion from both ends of the second direction z of the first folded portion. The height position of the minimum thickness point and the height position of the laminate surface were read. The difference between the read height position of the minimum thickness point of the first external electrode and the height position of the laminate surface was defined as the magnitude of the thickness of the minimum thickness point of the first external electrode. The thickness of the minimum thickness point of the second external electrode was determined at a position half the length of the fifth folded portion on the WT surface. The height position of the minimum thickness point of the second external electrode was read from the laser displacement graph, within the range excluding the area within 10% of the dimension of the fifth folded portion in the second direction z from both ends of the fifth folded portion in the second direction z. The difference between the read height position of the minimum thickness point of the second external electrode and the height position of the laminate surface was defined as the magnitude of the thickness of the minimum thickness point of the second external electrode.

[0114] (4) Method for checking for equipment malfunctions We investigated the frequency of equipment malfunctions in a taping machine where samples would stick to the transport surface due to static electricity during linear feeder transport, causing chip transport to stall and preventing samples from being inserted into the measurement terminals. 2 million samples were used for the investigation.

[0115] (5) Method for evaluating the occurrence of tombstone defects during circuit board mounting A glass epoxy substrate with a thickness of 1.6 mm was soldered using Sn-3.0Ag-0.5Cu solder paste in a reflow oven. The peak temperature of the reflow oven was set to 250°C (240°C or higher: 10 seconds, 220°C or higher: 60 seconds), and the oven was kept in an air atmosphere. After soldering, the appearance was checked, and if one of the external electrodes was floating away from the solder on the substrate electrode, it was determined to be a tombstone defect. 100 chips were used for the check.

[0116] (6) Results Table 1 shows the equipment failure rate and the number of tombstone defects during substrate mounting when the ratio of the maximum thickness point to the minimum thickness point of the first and fifth folded sections is changed for sample numbers 1 to 8.

[0117] Furthermore, Table 2 shows the equipment failure rate and the number of tombstone defects during substrate mounting when the position of the first and fifth folded sections from the center of the second direction z is changed for samples 9 through 13.

[0118] [Table 1]

[0119] [Table 2]

[0120] According to samples 1 and 2, when the ratio fell below 1.4, the contact area of ​​the chips with the transport surface increased, leading to an increased rate of equipment malfunctions. According to samples 7 and 8, when the ratio exceeded 2.5, the tilt of the chip relative to the substrate surface increased during substrate mounting, the distance between the substrate surface and the chip increased, and tombstone defects occurred during substrate mounting.

[0121] In sample number 9, the positions of the maximum thickness points of the first and fifth folded sections from the center of the second direction z were shifted in the same direction of the second direction z. This increased the contact area of ​​the chip during equipment transport, resulting in equipment malfunction. In samples 10 and 11, the displacement of the fifth folded portion, or the maximum thickness point of the first and fifth folded portions, from the center in the second direction z was small. This increased the chip contact area during equipment transport, resulting in equipment malfunction. In samples 12 and 13, the positional displacement from the center in the second direction z of the maximum thickness point of the fifth fold, or the first and fifth folds, was large. As a result, the position of the maximum thickness point overlapped with the chip corner shape, increasing the chip contact area during equipment transport and causing equipment malfunction.

[0122] Based on the evaluation results above, it was confirmed that, particularly for samples 3 through 6, reducing the contact area of ​​the chip with the transport unit during chip transport by the equipment in the manufacturing process of multilayer ceramic capacitors (measurement process, visual inspection process, and packaging process) improves chip adhesion due to static electricity, etc., and thus improves productivity (equipment utilization rate) due to chip transport malfunctions. Furthermore, it was confirmed that the maximum thickness point of the first folded portion and the maximum thickness point of the fifth folded portion are located diagonally to the center point of the chip in the second direction z, thereby reducing the chip contact area with the transport section. Furthermore, it was confirmed that the significant difference in thickness between the first and fifth folded sections on the folded surface reduces the chip contact area with the equipment transport section, thereby further improving chip transport malfunctions.

[0123] As described above, embodiments of the present invention are disclosed in the above description, but the present invention is not limited thereto.

[0124] In other words, various modifications can be made to the embodiments described above with respect to the mechanism, shape, material, quantity, position or arrangement, etc., without departing from the scope of the technical idea and objectives of the present invention, and these modifications are included in the present invention. [Explanation of Symbols]

[0125] 10 Multilayer ceramic capacitors 12-layer structure 12a First face 12b Second face 12c Third side 12d Fourth face 12e Fifth side 12f Sixth face 14 Dielectric layer 16 Internal electrode layer 16a First internal electrode layer 16b Second internal electrode layer 18 Capacity forming part 20a First outer layer 20b Second outer layer 22 Counter electrode section 22a First counter electrode portion 22b Second counter electrode section 24a First extraction electrode section 24b Second extraction electrode section 26a, 26b Side 27a, 27b ends 30 External electrode 30a First external electrode 30a0 First covering portion 30a1 First folded section 30a2 Second folded section 30a3 Third folded section 30a4 Fourth fold 30aP First point of maximum thickness 30b Second external electrode 30b0 Second coating portion 30b1 Fifth fold 30b2 Sixth fold 30b3 Seventh fold 30b4 Eighth fold 30bP Second point of maximum thickness 32 Base electrode layer 32a First underlay electrode layer 32b Second base electrode layer 34 Plating layer 34a First plating layer 34b Second plating layer 40 First holding fixture 40a Adhesive surface 42 Second retaining fixture 42a Adhesive side 50 Paste tanks 52 Surface plate 60, 62 Conductive paste 60a Unsintered first base electrode layer 60b Unsintered second base electrode layer 62a Unsintered first maximum thickness portion 62b Unsintered second maximum thickness portion 70 Laminate with an unsintered under electrode layer 72 Laminate with the maximum thickness portion formed in the unsintered section 80 Coating device 82 Slit plate 82a One main surface 82b Other main surface 84a Slit 84b Cavity 86 Closing member 88 Pressing member 88a protrusion 90 Holding Plates CP center point x stacking direction y First direction z Second direction

Claims

1. A laminate comprising a plurality of stacked dielectric layers and a plurality of internal electrode layers stacked on the dielectric layers, having a first surface and a second surface facing each other in the stacking direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction, A first internal electrode layer is arranged on the plurality of dielectric layers and is drawn out to the third surface, A second internal electrode layer is arranged on the plurality of dielectric layers and is drawn out to the fourth surface, A first external electrode is disposed on the third surface and connected to the first internal electrode layer, A second external electrode is disposed on the fourth surface and connected to the second internal electrode layer, Equipped with, The dimension l of the laminate in the first direction is shorter than the dimension w of the laminate in the second direction, and the dimension t of the laminate in the stacking direction is shorter than the dimension l of the laminate in the first direction. The first external electrode is, The first covering portion located on the third surface, A first folded portion located on a part of the first surface, A second folded portion located on a part of the second surface, A third folded portion located on a part of the fifth surface, A fourth folded portion located on a part of the sixth surface, It has, The second external electrode is, The second covering portion located on the fourth surface, A fifth folded portion located on a part of the first surface, A sixth folded portion located on a part of the second surface, A seventh folded portion located on a part of the fifth surface, An eighth folded portion located on a part of the sixth surface, It has, The first folded portion has a first maximum thickness point, which is the region with the greatest thickness in the stacking direction. The fifth folded portion has a second maximum thickness point, which is the region with the greatest thickness in the stacking direction. A multilayer ceramic capacitor in which the first maximum thickness point of the first folded portion and the second maximum thickness point of the fifth folded portion are located diagonally with respect to the center points of the first and second directions of the first main surface.

2. The first point of maximum thickness of the first folded portion is located on the fifth surface side with respect to the center of the first folded portion in the second direction, The multilayer ceramic capacitor according to claim 1, wherein the second maximum thickness point of the fifth folded portion is located on the sixth surface side with respect to the center of the second method of the fifth folded portion.

3. The first point of maximum thickness of the first folded portion is located within a range of ±10% of the length in the second direction from the center of the first folded portion in the second direction. The multilayer ceramic capacitor according to claim 2, wherein the second maximum thickness point of the fifth folded portion is located outside a range of ±10% of the length in the second direction from the center of the fifth folded portion in the second direction.

4. The first point of maximum thickness of the first folded portion is located in a range that excludes the area within 10% of the length in the second direction from both ends of the first folded portion in the second direction. The multilayer ceramic capacitor according to claim 3, wherein the second maximum thickness point of the fifth folded portion is located in a range excluding the area from both ends of the fifth folded portion in the second direction to within 10% of the length in the second direction.

5. The minimum thickness point is located in a region specified by excluding an area within 10% of the dimension of the first folded portion in the second direction from both ends of the first folded portion in the second direction, The fifth folded portion has a minimum thickness point in a region defined by excluding an area within 10% of the dimension of the fifth folded portion in the second direction from both ends in the second direction, The ratio of the maximum thickness point of the first folded portion to the minimum thickness point of the first folded portion is 1.4 or more and 2.5 or less. The multilayer ceramic capacitor according to claim 4, wherein the ratio of the maximum thickness point of the fifth folded portion to the minimum thickness point of the fifth folded portion is 1.4 or more and 2.5 or less.

6. The dimension in the first direction including the laminate, the first external electrode, and the second external electrode is 0.20 mm or more and 0.80 mm or less. The dimensions of the second method, which includes the laminate, the first external electrode and the second external electrode, are 0.40 mm or more and 1.60 mm or less, according to claim 5.

7. The first internal electrode layer and the second internal electrode layer are mainly composed of Cu, The multilayer ceramic capacitor according to any one of claims 1 to 6, wherein the dielectric layer is mainly composed of a ceramic material containing at least one of Ca, Sr, Zr, and Ti.

Images