Semiconductor equipment

Abstract

To provide a semiconductor device that can suppress the effects of applying voltages that undergo rapid changes. [Solution] The semiconductor device A10 comprises a first semiconductor element 11 and a first lead 31 having a first island portion 311 on which the first semiconductor element 11 is mounted. The first semiconductor element 11 comprises a first substrate 110, a first functional portion 115 including a first upper winding 115a and a first lower winding 115b located between the first upper winding 115a and the first substrate 110 in the thickness direction z, and a first laminated structure 117 including a portion interposed between the first upper winding 115a and the first lower winding 115b. The semiconductor device A10 comprises a first insulating portion interposed between the first island portion 311 and the first functional portion 115.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device. [Background Art]

[0002] Patent Document 1 discloses an example of a conventional semiconductor device. The semiconductor device disclosed in said document includes an insulating element. The insulating element has two coils. In the insulating element, inductive coupling of the two coils enables transmission of an electrical signal in an insulated state. [Prior Art Documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Unexamined Patent Publication No. 2024-020625

[0004] [Summary] When a voltage accompanied by a steep change such as a surge voltage is applied to a semiconductor device, the internal structure may be adversely affected.

[0005] The present disclosure has been conceived in view of the foregoing circumstances, and an object thereof is to provide a semiconductor device capable of suppressing the influence caused by application of a voltage accompanied by a steep change.

[0006] A semiconductor device provided by the present disclosure includes a first semiconductor element, and a first lead having a first island portion on which said first semiconductor element is mounted, said first semiconductor element includes a first semiconductor substrate, a first functional portion including a first upper winding and a first lower winding positioned between said first upper winding and said first semiconductor substrate in a thickness direction, and a first stacked structure including a portion interposed between said first upper winding and said first lower winding, and the semiconductor device further includes a first insulating portion interposed between said first island portion and said first functional portion. [Brief Description of the Drawings]

[0007] [Figure 1]Figure 1 is a plan view showing a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a plan view of Figure 1, with the sealing resin indicated by dashed lines. [Figure 3] Figure 3 is a front view showing a semiconductor device according to the first embodiment. [Figure 4] Figure 4 is a left side view showing a semiconductor device according to the first embodiment. [Figure 5] Figure 5 is a right side view showing a semiconductor device according to the first embodiment. [Figure 6] Figure 6 is a cross-sectional view along the line VI-VI in Figure 2. [Figure 7] Figure 7 is an enlarged cross-sectional view of a key part, which is a magnified view of a portion of Figure 6. [Figure 8] Figure 8 is a cross-sectional view along the line VIII-VIII in Figure 2. [Figure 9] Figure 9 is a cross-sectional view of a key part showing the internal structure of one of the multiple semiconductor elements (insulating element) of the semiconductor device according to the first embodiment. [Figure 10] Figure 10 is a plan view showing a semiconductor device according to a first modification of the first embodiment, in which the sealing resin is indicated by dashed lines. [Figure 11] Figure 11 is a cross-sectional view along the line XI-XI in Figure 10. [Figure 12] Figure 12 is an enlarged cross-sectional view of a key part, which is a magnified view of a portion of Figure 11. [Figure 13] Figure 13 is a cross-sectional view showing a semiconductor device according to a second modification of the first embodiment. [Figure 14] Figure 14 is a cross-sectional view showing a semiconductor device according to a third modification of the first embodiment. [Figure 15] Figure 15 is a cross-sectional view showing a semiconductor device according to a second embodiment. [Figure 16] Figure 16 is a cross-sectional view showing a semiconductor device according to a first modified example of the second embodiment. [Figure 17] Figure 17 is a plan view showing a semiconductor device according to the third embodiment. [Figure 18]FIG. 18 is a diagram showing a sealing resin by an imaginary line in the plan view of FIG. 17. [Figure 19] FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 18. [Figure 20] FIG. 20 is an enlarged cross-sectional view of a principal part in which a part of FIG. 19 is enlarged. [Figure 21] FIG. 21 is a cross-sectional view of a principal part showing the internal structure of two (two insulating elements) among a plurality of semiconductor elements of a semiconductor device according to a third embodiment. [Figure 22] FIG. 22 is a plan view showing a semiconductor device according to a fourth embodiment, in which a sealing resin is shown by an imaginary line. [Figure 23] FIG. 23 is an enlarged cross-sectional view of a principal part in which a part of a cross section taken along line XXIII-XXIII in FIG. 22 is enlarged. [Figure 24] FIG. 24 is a plan view showing a semiconductor device according to a fifth embodiment, in which a sealing resin is shown by an imaginary line. [Figure 25] FIG. 25 is an enlarged cross-sectional view of a principal part in which a part of a cross section taken along line XXV-XXV in FIG. 24 is enlarged.

[0008] [Detailed Description] Preferred embodiments of the semiconductor device, the method of designing a semiconductor device, and the method of manufacturing a semiconductor device of the present disclosure will be described below with reference to the drawings. In the following description, identical or similar components are denoted by the same reference numerals, and redundant description thereof is omitted.

[0009] In this disclosure, "object A is formed on object B" and "object A is formed on object B" include, unless otherwise specified, "object A is directly formed on object B" and "object A is formed on object B with another object interposed between object A and object B." Similarly, "object A is located on object B" and "object A is located on object B" include, unless otherwise specified, "object A is directly located on object B" and "object A is located on object B with another object interposed between object A and object B." Similarly, "object A is located on object B" includes, unless otherwise specified, "object A is located on object B in contact with object B" and "object A is located on object B with another object interposed between object A and object B." Furthermore, "object A overlaps with object B when viewed in a certain direction" includes, unless otherwise specified, "object A overlaps with all of object B" and "object A overlaps with a part of object B." Also, "object A (or its material) contains material C" includes "object A (or its material) consists of material C" and "the main component of object A (or its material) is material C." Furthermore, "a surface A faces a certain direction B (one side or the other side)" is not limited to cases where the angle of surface A with respect to direction B is 90°, but also includes cases where surface A is inclined with respect to direction B. Furthermore, "a surface A is perpendicular to surface B" is not limited to cases where the angle of surface A with respect to surface B is 90°, but also includes cases where surface A is inclined with respect to surface B.

[0010] Figures 1 to 9 show a semiconductor device A10 according to a first embodiment. As shown in these figures, the semiconductor device A10 includes a first semiconductor element 11, a second semiconductor element 12, a first control element 13, a second control element 14, a conductive support 3, a plurality of connection members 4, and a sealing resin 5. The conductive support 3 includes a plurality of first leads 31, a plurality of second leads 32, a plurality of leads 33, and a plurality of leads 34, and the plurality of connection members 4 includes a plurality of wires 41, 42, 44 to 47.

[0011] In the present disclosure, description is given with reference to a thickness direction z, a first direction x, and a second direction y that are orthogonal to each other. The thickness direction z corresponds to the thickness direction of each of the first semiconductor element 11, the second semiconductor element 12, the first control element 13, the second control element 14, the conductive support 3, and the sealing resin 5. One side in the thickness direction z may be referred to as upper, and the other side as lower. Note that descriptions such as "upper", "lower", "upward", "downward", "upper surface", and "lower surface" indicate the relative positional relationship of each component or the like in the thickness direction z, and are not necessarily terms that define the relationship with the direction of gravity. In addition, in the following description, "plan view" refers to a view when viewed along the thickness direction z.

[0012] The semiconductor device A10 is, for example, surface-mounted on a wiring board of industrial equipment and an inverter device such as an electric vehicle or a hybrid vehicle. The semiconductor device A10 controls the switching operation of a switching element such as an IGBT or a MOSFET. As can be understood from FIG. 1 and FIGS. 3 to 5, the package format of the semiconductor device A10 is SOP (Small Outline Package). However, the package format of the semiconductor device A10 is not limited to SOP.

[0013] The first semiconductor element 11, the second semiconductor element 12, the first control element 13, and the second control element 14 are the core elements of the semiconductor device A10. Each of the first semiconductor element 11, the second semiconductor element 12, the first control element 13, and the second control element 14 is composed of individual elements. In the first direction x, the first semiconductor element 11 is located between the first control element 13 and the second control element 14. In a plan view, each of the first semiconductor element 11, the second semiconductor element 12, the first control element 13, and the second control element 14 has a rectangular shape with the second direction y as its longer side. Note that the plan view shapes of the first semiconductor element 11, the second semiconductor element 12, the first control element 13, and the second control element 14 are not limited to the illustrated examples.

[0014] The first control element 13 is a controller (control element) for a gate driver that drives switching elements such as IGBTs and MOSFETs. The first control element 13 includes a circuit that converts a control signal input from an ECU or the like into a PWM control signal, a transmitting circuit for transmitting the PWM control signal to the first semiconductor element 11, and a receiving circuit that receives an electrical signal from the first semiconductor element 11.

[0015] As shown in Figure 6, the first control element 13 has a main surface 13a and a back surface 13b. The main surface 13a and the back surface 13b are separated in the thickness direction z. The main surface 13a is the upper surface of the first control element 13, and the back surface 13b is the lower surface of the first control element 13. The back surface 13b faces the first lead 31.

[0016] As shown in Figures 2 and 6, the first control element 13 has a plurality of pads 131. The plurality of pads 131 are provided on the main surface 13a (the surface facing the same direction as the mounting surface 311a of the first island portion 311 of the first lead 31, which will be described later). The composition of each of the plurality of pads 131 includes, for example, aluminum (Al).

[0017] The second control element 14 is a gate driver (driving element) for driving the switching element. The second control element 14 includes a receiving circuit for receiving a PWM control signal, a circuit for driving the switching element based on the PWM control signal, and a transmitting circuit for transmitting an electrical signal to the first control element 13. The electrical signal may be, for example, an output signal from a temperature sensor located near the motor.

[0018] As shown in Figure 6, the second control element 14 has a main surface 14a and a back surface 14b. The main surface 14a and the back surface 14b are separated in the thickness direction z. The main surface 14a is the upper surface of the second control element 14, and the back surface 14b is the lower surface of the second control element 14. The back surface 14b faces the second lead 32.

[0019] As shown in Figures 2 and 6, the second control element 14 has a plurality of pads 141. The plurality of pads 141 are provided on the main surface 14a (the surface facing the same direction as the mounting surface 321a of the second island portion 321 of the second lead 32, which will be described later). The composition of each of the plurality of pads 141 includes, for example, aluminum.

[0020] The first semiconductor element 11 is an insulating element for transmitting PWM control signals and other electrical signals in an isolated state. The first semiconductor element 11 is of the inductive type. An example of an inductive type first semiconductor element 11 is an isolated transformer.

[0021] As shown in Figures 6 to 9, the first semiconductor element 11 has a main surface 11a and a back surface 11b. The main surface 11a and the back surface 11b are separated in the thickness direction z. The main surface 11a is the upper surface of the first semiconductor element 11, and the back surface 11b is the lower surface of the first semiconductor element 11. The back surface 11b faces the first lead 31.

[0022] The first semiconductor element 11 includes a first functional section 115. The first functional section 115 has multiple sets of first upper windings 115a and first lower windings 115b, with each set consisting of a first upper winding 115a and a first lower winding 115b. That is, the first semiconductor element 11 has multiple first upper windings 115a and multiple first lower windings 115b. Figures 7 and 9 show one set of the multiple sets of first upper windings 115a and first lower windings 115b. For example, multiple sets of first upper windings 115a and first lower windings 115b are arranged along the longitudinal direction (second direction y) of the first semiconductor element 11. A set of first upper windings 115a and first lower windings 115b are spaced apart in the thickness direction z and face each other in the thickness direction z. In this embodiment, a pair of first upper windings 115a and first lower windings 115b are each wound in a spiral shape in a planar configuration. The pair of first upper windings 115a and first lower windings 115b are magnetically coupled. The first control element 13 transmits electrical signals in an insulated state by inductively coupling the first upper winding 115a and the first lower winding 115b in each pair of first upper windings 115a and first lower windings 115b.

[0023] As shown in Figures 2, 6, and 7, the first semiconductor element 11 has a plurality of pads 111, 112. Each of the plurality of pads 111, 112 is provided on the main surface 13a. As shown in Figure 7, each pad 111 is conductive to one of the plurality of first lower windings 115b, and each pad 112 is conductive to one of the plurality of first upper windings 115a. The composition of each of the plurality of pads 111, 112 includes, for example, aluminum. As shown in Figures 2, 6, and 7, each of the plurality of pads 111 is joined to one of the plurality of wires 42, and each of the plurality of pads 112 is joined to one of the plurality of wires 41.

[0024] As shown in Figures 7 and 9, the first semiconductor element 11 includes a first substrate 110, a protective film 1141, a passivation film 1142, a coil protective film 1143, a first stacked structure 117, and a wiring portion 118.

[0025] In this embodiment, the first substrate 110 includes an insulating material and constitutes the first insulating portion of the present disclosure. Examples of insulating materials include glass, SiO2, ceramic, and resin. In this example, the first substrate 110 includes glass and may be a glass substrate.

[0026] The first laminated structure 117 is formed on the first substrate 110. As shown in Figure 9, the first laminated structure 117 includes a plurality of first insulating layers 1171. The plurality of first insulating layers 1171 are laminated on the upper surface of the first substrate 110. Except for the bottommost first insulating layer 1171 that is in contact with the upper surface of the first substrate 110, each of the plurality of first insulating layers 1171 consists of a laminated structure with an etching stopper film below and an interlayer insulating film above. The bottommost first insulating layer 1171 consists only of an interlayer insulating layer. As the etching stopper film, for example, a SiN film (silicon nitride film), SiC film (silicon carbide film), SiCN film, etc. (silicon carbonitride film) can be used, and as the interlayer insulating film, for example, an SiO2 film (silicon oxide film) can be used. The dimension of the plurality of first insulating layers 1171 in the thickness direction z is not limited in any way, but for example it is 2.4 μm. The thickness of each of the multiple first insulating layers 1171 may be the same or different.

[0027] The first upper winding 115a and the first lower winding 115b are formed on different first insulating layers 1171 in the first laminated structure 117, and face each other with one or more first insulating layers 1171 in between. In the illustrated example, the first lower winding 115b is formed on the fourth first insulating layer 1171 from the first substrate 110, and the first upper winding 115a is formed on the 15th first insulating layer 1171, with 10 layers of first insulating layers 1171 in between it and the first lower winding 115b. Note that the number of first insulating layers 1171 is not limited to the illustrated example and can be appropriately changed, for example, depending on the magnitude of the voltage applied to each pad 111 and each pad 112. The more first insulating layers 1171 there are between the first upper winding 115a and the first lower winding 115b, the higher the dielectric breakdown voltage of the first semiconductor element 11, but the thicker the first semiconductor element 11 (dimension z in the thickness direction) becomes. On the other hand, the fewer first insulating layers 1171 there are between the first upper winding 115a and the first lower winding 115b, the lower the dielectric breakdown voltage of the first semiconductor element 11, but the thinner the first semiconductor element 11 (dimension z in the thickness direction) becomes.

[0028] The wiring section 118 electrically connects a plurality of pads 111, 112 with the first upper winding 115a and the first lower winding 115b. The wiring section 118 includes a plurality of through-wirings 1181 and lead-out wirings 1182. As shown in Figure 9, each of the plurality of through-wirings 1181 penetrates one or more first insulating layers 1171 in the thickness direction z. In the example shown in Figure 9, the plurality of through-wirings 1181 include those connecting pads 111 and lead-out wirings 1182, those connecting lead-out wirings 1182 and the first lower winding 115b, and those connecting pad 112 and the first upper winding 115a. The lead-out wirings 1182 are formed on the bottommost first insulating layer 1171. The lead-out wirings 1182 form part of the conductive path between pad 111 and the first lower winding 115b.

[0029] As shown in Figure 9, the protective film 1141 is laminated on the first laminated structure 117. The passivation film 1142 is laminated on the protective film 1141, as shown in Figure 9. The coil protective film 1143 is on the passivation film 1142 and selectively covers the region directly above the first upper winding 115a, as shown in Figure 9. As can be seen from Figure 9, the protective film 1141, the passivation film 1142, and the coil protective film 1143 have pad openings formed to expose each pad 111 and each pad 112. The protective film 1141 contains, for example, SiO2 and has a thickness of about 150 nm. The passivation film 1142 contains, for example, SiN and has a thickness of about 1000 nm. The coil protective film 1143 contains, for example, polyimide and has a thickness of about 4000 nm. The constituent materials and thicknesses of the protective film 1141, passivation film 1142, and coil protective film 1143 are not limited to the examples described above.

[0030] The structure of the first semiconductor element 11 is not limited to the examples described above. For example, the first upper winding 115a and the first lower winding 115b are not limited to being wound planarly around a single first insulating layer 1171, but may be wound three-dimensionally across multiple first insulating layers 1171. However, in order to suppress an increase in the thickness of the first semiconductor element 11, it is preferable that the first upper winding 115a and the first lower winding 115b are each wound planarly around a single first insulating layer 1171.

[0031] In semiconductor device A10, the second control element 14 requires a higher power supply voltage than the power supply voltage required for the first control element 13. Therefore, a potential difference is generated between the first control element 13 and the second control element 14. Thus, the first circuit, which includes the first control element 13 as a component, and the second circuit, which includes the second control element 14 as a component, are insulated from each other by the first semiconductor element 11. The components of the first circuit include the first control element 13, a first lead 31 and multiple leads 33, multiple wires 42, 44, 46, and a part of the first semiconductor element 11 (each pad 111 and each first lower winding 115b, etc.). The components of the second circuit include the second control element 14, a second lead 32 and multiple leads 34, multiple wires 41, 45, 47, and a part of the first semiconductor element 11 (each pad 112 and each first upper winding 115a, etc.). The first and second circuits have relatively different potentials. In semiconductor device A10, the potential of the second circuit is higher than that of the first circuit. Furthermore, the first semiconductor element 11 relays the mutual signals between the first and second circuits. For example, in inverter devices for electric vehicles and hybrid vehicles, the voltage applied to the ground of the first control element 13 is around 0V, while the voltage applied to the ground of the second control element 14 can transiently exceed 600V. Depending on the specifications of the inverter device, the voltage applied to the ground of the second control element 14 can exceed 3750V.

[0032] The conductive support 3 constitutes a conductive path between the first semiconductor element 11, the second semiconductor element 12, the first control element 13, the second control element 14, and the wiring board on which the semiconductor device A10 is mounted. The conductive support 3 is obtained, for example, from the same lead frame, as will be described in detail later. The lead frame is made of, for example, copper or a copper alloy, but may be made of other metallic materials. As described above, the conductive support 3 has a first lead 31, a second lead 32, a plurality of leads 33, and a plurality of leads 34.

[0033] As shown in Figures 1 and 2, the first lead 31 and the second lead 32 are positioned apart from each other in the first direction x. In the semiconductor device A10, the first semiconductor element 11 and the first control element 13 are mounted on the first lead 31, and the second control element 14 is mounted on the second lead 32.

[0034] As shown in Figure 2, the first lead 31 includes a first island portion 311 and two terminal portions 312.

[0035] As shown in Figures 6 and 7, the first island portion 311 has a mounting surface 311a facing one direction (upward) in the thickness direction z. As shown in Figure 7, the first semiconductor element 11 is bonded to the mounting surface 311a via a first conductive bonding material 119, and the first control element 13 is bonded via a conductive bonding material 139. The first substrate 110 of the first semiconductor element 11 is at approximately the same potential as the first island portion 311 via the first conductive bonding material 119. Each of the first conductive bonding materials 119 and 139 is, for example, solder, metal paste, or sintered metal. The first island portion 311 is covered with a sealing resin 5. In the illustrated example, the first island portion 311 is rectangular in plan view. The thickness of the first island portion 311 is, for example, 100 μm or more and 300 μm or less.

[0036] As shown in Figures 2, 6, and 7, the first island portion 311 has a plurality of through holes 313. Each of the multiple through holes 313 penetrates the first island portion 311 in the thickness direction z and extends along the second direction y. In a plan view, at least one of the multiple through holes 313 is located between the first semiconductor element 11 and the first control element 13. The multiple through holes 313 are arranged along the second direction y. Unlike the illustrated example, the first island portion 311 does not necessarily have to have a plurality of through holes 313.

[0037] As shown in Figure 2, the two terminal portions 312 extend from both sides of the first island portion 311 in the second direction y. The two terminal portions 312 are located apart from each other in the second direction y. At least one of the two terminal portions 312 is connected to the ground of the first control element 13 via one of the plurality of wires 46. Each of the two terminal portions 312 has a covered portion 312a and an exposed portion 312b. The covered portion 312a is connected to the first island portion 311 and is covered by the sealing resin 5. The exposed portion 312b is connected to the covered portion 312a and is exposed from the sealing resin 5. In plan view, the exposed portion 312b extends along the first direction x. As shown in Figure 3, when viewed in the second direction y, the exposed portion 312b is bent in a gull-wing shape. The surface of the exposed portion 312b may be plated, for example, with tin (Sn).

[0038] As shown in Figure 2, the second lead 32 has a second island portion 321 and two terminal portions 322.

[0039] As shown in Figures 6 and 7, the second island portion 321 has a mounting surface 321a facing one side (upwards) in the thickness direction z. As shown in Figure 7, the second control element 14 is bonded to the mounting surface 321a via a conductive bonding material 149. Each second conductive bonding material 129 and conductive bonding material 149 is, for example, solder, metal paste, or sintered metal. The second island portion 321 is covered with a sealing resin 5. In the illustrated example, the second island portion 321 is rectangular in plan view. The thickness of the second island portion 321 is, similar to the first island portion 311, for example, 100 μm to 300 μm.

[0040] As shown in Figure 2, the two terminal portions 322 extend from both sides of the second island portion 321 in the second direction y. The two terminal portions 322 are located apart from each other in the second direction y. At least one of the two terminal portions 322 is connected to the ground of the second control element 14 via one of the plurality of wires 47. Each of the two terminal portions 322 has a covered portion 322a and an exposed portion 322b. The covered portion 322a is connected to the second island portion 321 and is covered by the sealing resin 5. The exposed portion 322b is connected to the covered portion 322a and is exposed from the sealing resin 5. In plan view, the exposed portion 322b extends along the first direction x. As shown in Figure 3, when viewed in the second direction y, the exposed portion 322b is bent in a gull-wing shape. The surface of the exposed portion 322b may be tin-plated, for example.

[0041] As shown in Figures 1 and 2, the multiple leads 33 are positioned in the first direction x on the opposite side of the second island portion 321 of the second lead 32 from the first island portion 311 of the first lead 31. The multiple leads 33 are arranged along the second direction y. At least one of the multiple leads 33 is conductive to the first control element 13 via one of the multiple wires 44. The multiple leads 33 include multiple (six in the illustrated example) intermediate leads 33A and two side leads 33B. The two side leads 33B are located one on each side of the multiple intermediate leads 33A in the second direction y. Each of the two side leads 33B is positioned in the second direction y between one of the two terminal portions 312 of the first lead 31 and the intermediate lead 33A closest to that terminal portion 312.

[0042] As shown in Figures 2 and 6, each of the multiple leads 33 (multiple intermediate leads 33A and two side leads 33B) has a covering portion 331 and an exposed portion 332. The covering portion 331 is covered with a sealing resin 5. In the illustrated example, the dimension of each covering portion 331 of the two side leads 33B in the first direction x is greater than the dimension of each covering portion 331 of the multiple intermediate leads 33A in the first direction x. As shown in Figures 2 and 6, the exposed portion 332 is connected to the covering portion 331 and is exposed from the sealing resin 5. In plan view, the exposed portion 332 extends along the first direction x. As can be seen from Figures 2 to 4, when viewed along the second direction y, the exposed portion 332 is bent in a gull-wing shape. The shape of the exposed portion 332 is equal to the shape of the exposed portion 312b of each terminal portion 312 of the first lead 31. The surface of the exposed portion 332 may be tin-plated, for example.

[0043] The shape, arrangement, and number of the multiple leads 33 are not limited to the illustrated example. For example, there may be fewer or more leads 33 than in the illustrated example (eight). Also, for example, some of the multiple leads 33 may be positioned outward from either of the two terminal portions 312 of the first lead 31.

[0044] As shown in Figures 1 and 2, the multiple leads 34 are located in the first direction x on the opposite side of the multiple leads 33 from the first island portion 311 of the first lead 31. The multiple leads 34 are arranged along the second direction y. At least one of the multiple leads 34 is conductive to the second control element 14 via one of the multiple wires 45. The multiple leads 34 include multiple (six in the illustrated example) intermediate leads 34A and two side leads 34B. The two side leads 34B are located one on each side of the multiple intermediate leads 34A in the second direction y. In the second direction y, one of the two terminal portions 322 of the second lead 32 is located between one of the two side leads 34B and the intermediate lead 34A closest to that side lead 34B.

[0045] As shown in Figures 2 and 6, each of the multiple leads 34 (multiple intermediate leads 34A and two side leads 34B) has a covering portion 341 and an exposed portion 342. The covering portion 341 is covered with a sealing resin 5. In the illustrated example, the dimension in the first direction x of each covering portion 341 of the two side leads 34B is greater than the dimension in the first direction x of each covering portion 341 of the multiple intermediate leads 34A. As shown in Figures 2 and 6, the exposed portion 342 is connected to the covering portion 341 and is exposed from the sealing resin 5. In plan view, the exposed portion 342 extends along the first direction x. As can be understood from Figures 2, 3 and 5, when viewed along the second direction y, the exposed portion 342 is bent in a gull-wing shape. The shape of the exposed portion 342 is equal to the shape of each exposed portion 322b of the two terminal portions 322 of the second lead 32. The surface of the exposed portion 342 may be tin-plated, for example.

[0046] The shape, arrangement, and number of the multiple leads 34 are not limited to the illustrated example. For example, there may be fewer or more leads 34 than in the illustrated example (eight). Also, for example, the two side leads 34B may each be located between one of the two terminal portions 322 of the second lead 32 and the intermediate lead 34A that is closest to that terminal portion 322 in the second direction y.

[0047] Each of the multiple connecting members 4 provides electrical conductivity between two parts that are separated from each other. As described above, the multiple connecting members 4 include multiple wires 41, 42, 44-47. The multiple connecting members 4 may be bonding ribbons or plate-shaped metal members instead of multiple wires 41, 42, 44-47 (bonding wires).

[0048] Each of the multiple wires 41, 42, 44-47 contains a metallic material, which is copper or a copper alloy (for example, a palladium-copper alloy). In other words, each of the multiple wires 41, 42, 44-47 is a copper wire. Each of the multiple wires 41, 42, 44-47 may also consist of a core material (for example, containing copper) and a surface layer (for example, palladium) covering the core material. In this embodiment, the multiple wires 42, 44-47 may not consist of copper or a copper alloy as the metallic material, but may also consist of gold, aluminum, or silver.

[0049] Each of the multiple wires 41 is joined to one of the multiple pads 112 of the first semiconductor element 11 and one of the multiple pads 141 of the second control element 14, as shown in Figures 2 and 7. Each wire 41 provides electrical conductivity between the first semiconductor element 11 and the second control element 14. The multiple wires 41 are arranged along the second direction y. In a plan view, each of the multiple wires 41 straddles the first island portion 311 of the first lead 31 and the second island portion 321 of the second lead 32.

[0050] As shown in Figure 7, each of the multiple wires 41 includes two joints 411, 412 and a loop 413. In each wire 41, the joint 411 is bonded to one of the multiple pads 112. The joint 412 is bonded to one of the multiple pads 141. The loop 413 connects the two joints 411, 412. The loop 413 curves upward from the joint 411 in the thickness direction z and extends toward the joint 412. The loop 413 has a rising section 413a. The rising section 413a is the part of the loop 413 that connects to the joint 411 and rises in the thickness direction z. In the illustrated example (see Figure 7), the rising section 413a extends along the thickness direction z. Each wire 41 is formed, for example, by ball bonding, and is first bonded to one of the multiple pads 112 and second bonded to one of the multiple pads 141. Unlike this example, each wire 41 may be formed by other methods such as wedge bonding. If each wire 41 is formed by wedge bonding, the shape of the joint 411 will be approximately the same as the shape of the joint 412.

[0051] Each of the multiple wires 42 is joined to one of the multiple pads 111 of the first semiconductor element 11 and one of the multiple pads 131 of the first control element 13, as shown in Figures 2 and 7. Each wire 42 provides electrical conductivity between the first semiconductor element 11 and the first control element 13. The multiple wires 42 are arranged along the second direction y. As shown in Figure 7, in this embodiment, the highest point of wire 42 in the thickness direction z is lower than the highest point of wire 41 in the thickness direction z (located closer to the main surface 11a of the first semiconductor element 11 with respect to the thickness direction z).

[0052] As shown in Figure 7, each of the multiple wires 42 includes two joints 421, 422 and a loop 423. In each wire 42, joint 421 is bonded to one of the multiple pads 111. Joint 422 is bonded to one of the multiple pads 131. The loop 423 connects the two joints 421, 422. The loop 423 curves upward from joint 421 in the thickness direction z and extends toward joint 422. The loop 423 has a rising section 423a. The rising section 423a is the part of the loop 423 that connects to joint 421 and rises in the thickness direction z. In the illustrated example (see Figure 7), the rising section 423a extends along the thickness direction z. Each wire 42 is formed, for example, by ball bonding, and is first bonded to one of the multiple pads 111 and second bonded to one of the multiple pads 131. Unlike this example, each wire 42 may be formed by other methods, such as wedge bonding. If each wire 42 is formed by wedge bonding, the shape of the joint 421 will be approximately the same as the shape of the joint 422.

[0053] Each of the multiple wires 44 is connected to one of the multiple pads 131 of the first control element 13 and to the covering portion 331 of one of the multiple leads 33, as shown in Figure 2. Each wire 44 provides electrical conductivity between the first control element 13 and one of the multiple leads 33.

[0054] Each of the multiple wires 45 is connected to one of the multiple pads 141 of the second control element 14 and to the covering portion 341 of one of the multiple leads 34, as shown in Figure 2. Each wire 45 provides electrical conductivity between the second control element 14 and one of the multiple leads 34.

[0055] Each of the multiple wires 46 is connected to one of the multiple pads 131 of the first control element 13 and to the covering portion 312a of one of the two terminal portions 312, as shown in Figure 2. Each of the multiple wires 46 provides electrical conductivity between the first control element 13 and the first lead 31. Note that the number of wires 46 is not limited to multiple; it may be just one.

[0056] Each of the multiple wires 47 is connected to one of the multiple pads 141 of the second control element 14 and to the covering portion 322a of one of the two terminal portions 322, as shown in Figure 2. Each of the multiple wires 47 provides electrical conductivity between the second control element 14 and the second lead 32. Note that the number of multiple wires 47 is not limited to multiple; it may be just one.

[0057] As shown in Figure 1, the encapsulating resin 5 covers the first semiconductor element 11, the first control element 13 and the second control element 14, a part of the conductive support 3 and a plurality of connecting members 4. The encapsulating resin 5 has electrical insulating properties. The encapsulating resin 5 insulates the components of the first circuit (e.g., the first lead 31) and the components of the second circuit (e.g., the second lead 32) from each other. The encapsulating resin 5 is made of a material including, for example, a black epoxy resin. In the illustrated example, the encapsulating resin 5 is rectangular in plan view.

[0058] As shown in Figures 2 to 5, the sealing resin 5 has a top surface 51, a bottom surface 52, a pair of side surfaces 53, and a pair of side surfaces 54.

[0059] As shown in Figures 3 to 5, the top surface 51 and the bottom surface 52 are located apart from each other in the thickness direction z. The top surface 51 and the bottom surface 52 face opposite each other in the thickness direction z. Each of the top surface 51 and the bottom surface 52 is substantially flat.

[0060] As shown in Figures 3 to 5, the pair of sides 53 are connected to the top surface 51 and the bottom surface 52, and are located apart from each other in the first direction x. From one of the pair of sides 53 located on the side 53 on the first direction x, the exposed portions 312b of the two terminal portions 312 (first leads 31) and the exposed portions 332 of the multiple leads 33 are exposed. From the other side 53 located on the first direction x, the exposed portions 322b of the two terminal portions 322 (second leads 32) and the exposed portions 342 of the multiple leads 34 are exposed.

[0061] As shown in Figures 3 to 5, each of the pair of sides 53 includes an upper section 531, a lower section 532, and an intermediate section 533. The upper section 531 has one side in the thickness direction z connected to the top surface 51 and the other side in the thickness direction z connected to the intermediate section 533. The upper section 531 is inclined with respect to the top surface 51. The lower section 532 has one side in the thickness direction z connected to the bottom surface 52 and the other side in the thickness direction z connected to the intermediate section 533. The lower section 532 is inclined with respect to the bottom surface 52. The intermediate section 533 has one side in the thickness direction z connected to the upper section 531 and the other side in the thickness direction z connected to the lower section 532. The in-plane direction of the intermediate section 533 is the thickness direction z and the second direction y. In plan view, the intermediate section 533 is located outward from the top surface 51 and the bottom surface 52. From the intermediate portion 533 of the pair of sides 53, the exposed portions 312b of the two terminal portions 312 (first lead 31), the exposed portions 322b of the two terminal portions 322 (second lead 32), the exposed portions 332 of the multiple leads 33, and the exposed portions 342 of the multiple leads 34 are exposed.

[0062] As shown in Figures 3 to 5, the pair of sides 54 are connected to the top surface 51 and the bottom surface 52, and are located apart from each other in the second direction y. As shown in Figure 1, the first lead 31, the second lead 32, the multiple leads 33 and the multiple leads 34 are located apart from the pair of sides 54.

[0063] As shown in Figures 3 to 5, each of the pair of sides 54 includes an upper section 541, a lower section 542, and an intermediate section 543. The upper section 541 has one side in the thickness direction z connected to the top surface 51 and the other side in the thickness direction z connected to the intermediate section 543. The upper section 541 is inclined with respect to the top surface 51. The lower section 542 has one side in the thickness direction z connected to the bottom surface 52 and the other side in the thickness direction z connected to the intermediate section 543. The lower section 542 is inclined with respect to the bottom surface 52. The intermediate section 543 has one side in the thickness direction z connected to the upper section 541 and the other side in the thickness direction z connected to the lower section 542. The in-plane direction of the intermediate section 543 is the thickness direction z and the second direction y. In plan view, the intermediate section 543 is located outward from the top surface 51 and the bottom surface 52.

[0064] The operation and effects of semiconductor device A10 are as follows:

[0065] When semiconductor device A10 is used in industrial equipment, for example, it is required to be less susceptible to the effects of voltages that change rapidly, such as surge voltages, when applied. For example, unlike in this embodiment, if the first substrate 110 is made of a conductive material, a fault mode may occur in which a rapid voltage is applied to the first island portion 311, causing a short circuit from the first island portion 311 through the first substrate 110 to the first upper winding 115a. Since the path from the first island portion 311 through the first substrate 110 does not include wires, etc., voltages that change rapidly can easily act on it, making it easy to cause a short circuit in the first laminated structure 117. According to semiconductor device A10, a first insulating portion (first substrate 110) is provided interposed between the first island portion 311 and the first functional portion 115. This makes it possible to reduce the effect of voltages that change rapidly from the first island portion 311 through the first substrate 110 on the first laminated structure 117. Therefore, the effects of applying voltages that undergo rapid changes can be suppressed.

[0066] In semiconductor device A10, the first semiconductor element 11 has a first substrate 110 which serves as a first insulating portion. The first substrate 110 occupies most of the thickness direction z of the first semiconductor element 11. By having this first substrate 110 constitute the first insulating portion, the effects of applying a voltage that undergoes abrupt changes can be suppressed more reliably.

[0067] Other embodiments and modifications of the semiconductor device of the present disclosure are described below. The configurations of the parts in each embodiment and each modification are interchangeable to the extent that no technical inconsistencies arise.

[0068] Figures 10 to 12 show a semiconductor device A11 according to a first modification of the first embodiment. The semiconductor device A11 differs from the semiconductor device A10 in the following respect: In the semiconductor device A11, the first semiconductor element 11 is mounted on the second lead 32 (second island portion 321) rather than the first lead 31 (first island portion 311). For the sake of ease of understanding, in the description of the semiconductor device A11, the lead and island portion on which the first substrate 110 is mounted are referred to as the second lead 32 and the second island portion 321, but in this modification, the second lead 32 and the second island portion 321 correspond to the first lead and the first island portion in the technical concept of this disclosure.

[0069] In semiconductor device A11, as shown in Figures 10 to 12, the first semiconductor element 11 is bonded to the second island portion 321 by a first conductive bonding material 119.

[0070] In semiconductor device A11, as shown in Figures 10 to 12, each wire 42 provides electrical conductivity between the first semiconductor element 11 and the first control element 13. The junction 411 of each wire 41 is joined to one of the multiple pads 112 of the first semiconductor element 11, and the junction 412 of each wire 41 is joined to one of the multiple pads 131 of the first control element 13. Also in semiconductor device A11, as shown in Figures 10 to 12, each wire 42 provides electrical conductivity between the first semiconductor element 11 and the second control element 14. The junction 421 of each wire 42 is joined to one of the multiple pads 111 of the first semiconductor element 11, and the junction 422 of each wire 42 is joined to one of the multiple pads 141 of the second control element 14. As shown in Figures 10 to 12, in semiconductor device A11, in a plan view, the multiple pads 112 are arranged on the side where the first control element 13 is located relative to the multiple pads 111, and the multiple pads 111 are arranged on the side where the second control element 14 is located relative to the multiple pads 112.

[0071] As can be seen from this modified example, the arrangement of the first semiconductor element 11 and the first control element 13 and the second control element 14 in the semiconductor device of this disclosure is not limited in any way.

[0072] Figure 13 shows a semiconductor device A12 according to a second modification of the first embodiment. In semiconductor device A12, the first substrate 110 differs from the example described above. In this modification, the first substrate 110 includes a semiconductor layer 1100, an insulating layer 1101, and a semiconductor layer 1102.

[0073] The semiconductor layer 1100 may contain a semiconductor such as Si (silicon) and may be thicker than the insulating layer 1101 and the semiconductor layer 1102. The insulating layer 1101 contains an insulating material such as SiO2. The semiconductor layer 1102 contains a semiconductor such as Si (silicon). The semiconductor layer 1100 and the semiconductor layer 1102 are located on both sides of the insulating layer 1101. Such a first substrate 110 is referred to as, for example, an SOI (Silicon on Insulator) substrate.

[0074] As can be seen from this modified example, the specific configuration of the first substrate 110 constituting the first insulating portion is not limited in any way.

[0075] Figure 14 shows a semiconductor device A13 according to a third modification of the first embodiment. In the semiconductor device A13, the first substrate 110 includes a semiconductor layer 1100, an insulating layer 1101, and a bonding layer 1103. The semiconductor layer 1100 includes a semiconductor such as Si (silicon). The insulating layer 1101 includes an insulating material such as glass, SiO2, ceramics, or resin. The bonding layer 1103 is a layer that bonds the insulating layer 1101 and the semiconductor layer 1100.

[0076] As can be seen from this modified example, the specific configuration of the first substrate 110 constituting the first insulating portion is not limited in any way.

[0077] Figure 15 shows a semiconductor device A20 according to a second embodiment. In this embodiment, the configuration of the first insulating part differs from that of the embodiment described above.

[0078] In this embodiment, the first semiconductor element 11 is bonded to the first island portion 311 by a first insulating bonding material 16. The first insulating bonding material 16 is insulating and is, for example, an adhesive mainly composed of resin. In this embodiment, the first substrate 110 may be made of a conductive material.

[0079] This embodiment makes it possible to suppress the effects of applying voltages that change rapidly. According to this embodiment, a general first semiconductor element 11 that does not have a first insulating portion can be used.

[0080] Figure 16 shows a semiconductor device A21 according to a first modified example of the second embodiment. The semiconductor device A21 includes a first insulating plate material 17. The first insulating plate material 17 constitutes a first insulating portion.

[0081] The first insulating board material 17 includes, for example, an insulating layer 170, a metal layer 171, and a metal layer 172. The insulating layer 170 includes, for example, an insulating material such as glass, SiO2, ceramics, or resin. The metal layers 171 and 172 are located on both sides of the insulating layer 170 and are, for example, metal plating layers. The first insulating board material 17 is joined to the first semiconductor element 11 (first substrate 110) and the first island portion 311 by the first conductive bonding material 119.

[0082] As can be seen from this modified example, various configurations can be adopted for the first insulating section.

[0083] Figures 17 to 21 show a semiconductor device A30 according to the third embodiment. The semiconductor device A30 differs from semiconductor devices A10 and A11 in the following respect: The semiconductor device A30 further comprises a second semiconductor element 12.

[0084] The second semiconductor element 12, like the first semiconductor element 11, is an insulating element for transmitting PWM control signals and other electrical signals in an isolated state. In a plan view, the second semiconductor element 12 has a rectangular shape with the second direction y as its longer side, but the plan view shape of the second semiconductor element 12 is not limited to a rectangle. The second semiconductor element 12 is electrically connected between the first semiconductor element 11 and the second control element 14. In the first direction x, the second semiconductor element 12 is positioned between the first semiconductor element 11 and the second control element 14. In the semiconductor device A30, the first circuit including the first control element 13 and the second circuit including the second control element 14 are insulated from each other by the first semiconductor element 11 and the second semiconductor element 12.

[0085] The second semiconductor element 12 is mounted on the second island portion 321 (second lead 32) together with the second control element 14. The second semiconductor element 12 is bonded to the mounting surface 321a of the second island portion 321 via the second conductive bonding material 129. As a result, the second substrate 120 of the second semiconductor element 12 is at approximately the same potential as the second island portion 321 via the second conductive bonding material 129. The second conductive bonding material 129 is, for example, solder, metal paste, or sintered metal.

[0086] As shown in Figures 19 to 21, the second semiconductor element 12 has a main surface 12a and a back surface 12b. The main surface 12a and the back surface 12b are separated in the thickness direction z. The main surface 12a is the upper surface of the second semiconductor element 12, and the back surface 12b is the lower surface of the second semiconductor element 12. The back surface 12b faces the second lead 32.

[0087] The second semiconductor element 12 includes a second functional section 125. The second functional section 125 has multiple sets of second upper windings 125a and second lower windings 125b, with each set consisting of a second upper winding 125a and a second lower winding 125b. That is, the second semiconductor element 12 has multiple second upper windings 125a and multiple second lower windings 125b. Figure 20 shows one set of the multiple sets of second upper windings 125a and second lower windings 125b. For example, multiple sets of second upper windings 125a and second lower windings 125b are arranged along the longitudinal direction (second direction y) of the second semiconductor element 12. A set of second upper windings 125a and second lower windings 125b are spaced apart in the thickness direction z and face each other in the thickness direction z. In this embodiment, a pair of second upper windings 125a and second lower windings 125b are each wound in a spiral shape in a planar configuration. The pair of second upper windings 125a and second lower windings 125b are magnetically coupled. The second semiconductor element 12 transmits electrical signals in an insulated state by inductively coupling the second upper windings 125a and second lower windings 125b in each pair of second upper windings 125a and second lower windings 125b.

[0088] As shown in Figures 18 to 21, the second semiconductor element 12 has a plurality of pads 121 and 122. Each of the plurality of pads 121 and 122 is provided on the main surface 12a. As shown in Figure 20, each pad 121 is conductive to one of the plurality of second lower windings 125b, and each pad 122 is conductive to one of the plurality of second upper windings 125a. The composition of each of the plurality of pads 121 and 122 includes, for example, aluminum. As shown in Figures 18 and 20, each of the plurality of pads 121 is joined to one of the plurality of wires 43, and each of the plurality of pads 122 is joined to one of the plurality of wires 41.

[0089] As shown in Figures 20 and 21, the second semiconductor element 12 includes a second substrate 120, a protective film 1241, a passivation film 1242, a coil protective film 1243, a second stacked structure 127, and a wiring section 128.

[0090] In this embodiment, the second substrate 120 includes an insulating material and constitutes the second insulating portion of the disclosure. Examples of insulating materials include glass, SiO2, ceramic, and resin. In this example, the second substrate 120 includes glass and may be a glass substrate. The second substrate 120 can have various configurations similar to those of the first substrate 110 described above. Furthermore, in the semiconductor device A30, components corresponding to the first insulating bonding material 16, the first insulating board material 17, etc. in the above embodiment may constitute the second insulating portion.

[0091] The second laminated structure 127 is formed on the second substrate 120. As shown in Figure 21, the second laminated structure 127 includes a plurality of second insulating layers 1271. The plurality of second insulating layers 1271 are laminated on the upper surface of the second substrate 120. Except for the bottommost second insulating layer 1271 that is in contact with the upper surface of the second substrate 120, each of the plurality of second insulating layers 1271 has a laminated structure consisting of an etching stopper film below and an interlayer insulating film above. The bottommost second insulating layer 1271 consists only of an interlayer insulating layer. For example, a SiN film, SiC film, SiCN film, etc. can be used as the etching stopper film, and for example, an SiO2 film can be used as the interlayer insulating film. The dimension z in the thickness direction of the plurality of second insulating layers 1271 is not limited in any way, but for example it is 2.4 μm. The thickness of each of the plurality of second insulating layers 1271 may be the same or different.

[0092] The second upper winding 125a and the second lower winding 125b are formed on different second insulating layers 1271 in the second laminated structure 127, and face each other with one or more second insulating layers 1271 in between. In the illustrated example, the second lower winding 125b is formed on the fourth second insulating layer 1271 from the second substrate 120, and the second upper winding 125a is formed on the eleventh second insulating layer 1271, with six second insulating layers 1271 in between it and the second lower winding 125b. Note that the number of second insulating layers 1271 is not limited to the illustrated example and can be appropriately changed, for example, depending on the magnitude of the voltage applied to each pad 121 and each pad 122. The more second insulating layers 1271 there are between the second upper winding 125a and the second lower winding 125b, the higher the dielectric breakdown voltage of the second semiconductor element 12 can be, but the thickness of the second semiconductor element 12 (dimension in the thickness direction z) will increase. On the other hand, the fewer second insulating layers 1271 there are between the second upper winding 125a and the second lower winding 125b, the lower the dielectric breakdown voltage of the second semiconductor element 12, but the thickness of the second semiconductor element 12 (dimension in the thickness direction z) can be reduced. In this embodiment, considering the relationship between the dielectric breakdown voltage of the second semiconductor element 12 and the thickness of the second semiconductor element 12 (suppression of its increase), it is preferable that the number of layers of the second insulating layer 1271 between the second upper winding 125a and the second lower winding 125b be 4 to 6. Furthermore, the dimension in the thickness direction z of the multiple second insulating layers 1271 between the second upper winding 125a and the second lower winding 125b (i.e., the separation distance along the thickness direction z between the second upper winding 125a and the second lower winding 125b) is not limited in any way, but for example it is 9.6 μm or more and 14.4 μm or less. This example dimension (9.6 μm or more and 14.4 μm or less) corresponds, for example, to the case where the dimension in the thickness direction z of each second insulating layer 1271 between the second upper winding 125a and the second lower winding 125b is 2.4 μm and the number of layers of the second insulating layer 1271 between the second upper winding 125a and the second lower winding 125b is 4 or more and 6 or less.

[0093] In this embodiment, the number of layers of the first insulating layer 1171 in the first semiconductor element 11 is equivalent to the number of layers of the second insulating layer 1271 in the second semiconductor element 12. Specifically, the first lower winding 115b is formed on the fourth layer of the first insulating layer 1171 from the first substrate 110, and the first upper winding 115a is formed on the eleventh layer of the first insulating layer 1171, with six layers of the first insulating layer 1171 in between it and the first lower winding 115b. Therefore, the number of first insulating layers 1171 between the pair of first upper windings 115a and first lower windings 115b in semiconductor device A30 is less than the number of first insulating layers 1171 between the pair of first upper windings 115a and first lower windings 115b in semiconductor device A10. In this embodiment, considering the relationship between the dielectric breakdown voltage of the first semiconductor element 11 and the thickness of the first semiconductor element 11 (and suppression of its thickness increase), it is preferable that the number of layers of the first insulating layer 1171 between the first upper winding 115a and the first lower winding 115b be 4 to 6. Furthermore, the dimension of the multiple first insulating layers 1171 between the first upper winding 115a and the first lower winding 115b in the thickness direction z (i.e., the separation distance between the first upper winding 115a and the first lower winding 115b along the thickness direction z) is not limited in any way, but for example, it is 9.6 μm to 14.4 μm. This example of dimensions (9.6 μm to 14.4 μm) corresponds, for example, to the case where the dimension in the thickness direction z of each first insulating layer 1171 between the first upper winding 115a and the first lower winding 115b is 2.4 μm, and the number of layers of the first insulating layer 1171 between the first upper winding 115a and the first lower winding 115b is 4 to 6.

[0094] The wiring section 128 electrically connects the multiple pads 121 and 122 with the second upper winding 125a and the second lower winding 125b. The wiring section 128 includes multiple through-wirings 1281 and lead-out wirings 1282. As shown in Figure 21, each of the multiple through-wirings 1281 penetrates one or more second insulating layers 1271 in the thickness direction z. In the example shown in Figure 21, the multiple through-wirings 1281 include those connecting the pad 121 to the lead-out wiring 1282, those connecting the lead-out wiring 1282 to the second lower winding 125b, and those connecting the pad 122 to the second upper winding 125a. The lead-out wiring 1282 is formed on the bottommost second insulating layer 1271. The lead-out wiring 1282 forms part of the conductive path between the pad 121 and the second lower winding 125b.

[0095] The protective film 1241 is laminated on the second laminated structure 127, as shown in Figure 21. The passivation film 1242 is laminated on the protective film 1241, as shown in Figure 21. The coil protective film 1243 is on the passivation film 1242 and selectively covers the region directly above the second upper winding 125a, as shown in Figure 21. As can be seen from Figure 21, the protective film 1241, the passivation film 1242, and the coil protective film 1243 have pad openings formed to expose each pad 121 and each pad 122. The protective film 1241 contains, for example, SiO2 and has a thickness of about 150 nm. The passivation film 1242 contains, for example, SiN and has a thickness of about 1000 nm. The coil protective film 1243 contains, for example, polyimide and has a thickness of about 4000 nm. The constituent materials and thicknesses of the protective film 1241, passivation film 1242, and coil protective film 1243 are not limited to the examples described above.

[0096] The structure of the second semiconductor element 12 is not limited to the examples described above. For example, the second upper winding 125a and the second lower winding 125b are not limited to being wound planarly around a single second insulating layer 1271, but may be wound three-dimensionally across multiple second insulating layers 1271. However, in order to suppress an increase in the thickness of the second semiconductor element 12, it is preferable that the second upper winding 125a and the second lower winding 125b are each wound planarly around a single second insulating layer 1271.

[0097] In semiconductor device A30, each of the multiple wires 41 is joined to one of the multiple pads 112 of the first semiconductor element 11 and one of the multiple pads 122 of the second semiconductor element 12, as shown in Figures 18 to 20. In this embodiment, the multiple wires 41 provide electrical conductivity between the first semiconductor element 11 and the second semiconductor element 12. The junction 411 of each wire 41 is joined to one of the multiple pads 112 of the first semiconductor element 11, and the junction 412 of each wire 41 is joined to one of the multiple pads 122 of the second semiconductor element 12.

[0098] In the semiconductor device A30, the multiple connecting members 4 include multiple wires 43. Each of the multiple wires 43 is joined to one of the multiple pads 121 of the second semiconductor element 12 and one of the multiple pads 141 of the second control element 14, as shown in Figures 18 to 20. Each wire 43 provides electrical conductivity between the second semiconductor element 12 and the second control element 14. The multiple wires 43 are arranged along the second direction y.

[0099] As shown in Figure 20, each of the multiple wires 43 includes two joints 431, 432 and a loop 433. In each wire 43, joint 431 is bonded to one of the multiple pads 121. Joint 432 is bonded to one of the multiple pads 141. The loop 433 connects the two joints 431, 432. The loop 433 curves upward from joint 431 in the thickness direction z and extends toward joint 432. The loop 433 has a rising section 433a. The rising section 433a is the part of the loop 433 that connects to joint 431 and rises in the thickness direction z. Each wire 43 is formed, for example, by ball bonding, with first bonding to one of the multiple pads 121 and second bonding to one of the multiple pads 141. Unlike this example, each wire 43 may be formed by other methods such as wedge bonding. When each wire 43 is formed by wedge bonding, the shape of the joint 431 will be approximately the same as the shape of the joint 432.

[0100] The conductive support 3 of semiconductor device A30 differs from the conductive support 3 of semiconductor device A10 in the following respects. Firstly, the number of multiple leads 33 and the number of multiple leads 34 are each six. Secondly, all of the multiple leads 34 are sandwiched between the two terminal portions 322 of the second lead 32 in the second direction y. Note that the shape, size, and arrangement of the conductive support 3 of semiconductor device A30 are not limited to the illustrated example. For example, the second island portion 321 may have a through hole that penetrates in the thickness direction z, similar to the first island portion 311 of semiconductor device A10. This through hole is formed, for example, between the second semiconductor element 12 and the second control element 14.

[0101] In semiconductor device A30, a third circuit is provided that is at an intermediate potential between the potential of the first circuit and the potential of the second circuit, by electrically insulating the first circuit and the second circuit with a first semiconductor element 11 and a second semiconductor element 12 (two insulating elements). In other words, semiconductor device A30 includes a third circuit in addition to the first and second circuits. In this embodiment, the third circuit includes a part of the first semiconductor element 11 (each first upper winding 115a and each pad 112, etc.), a part of the second semiconductor element 12 (each second upper winding 125a and each pad 122, etc.), and a plurality of wires 41. In a configuration where the potential of the second circuit is higher than the potential of the first circuit, the potential of the third circuit is higher than the potential of the first circuit and lower than the potential of the second circuit. In this embodiment, the first semiconductor element 11 and the second semiconductor element 12 are configured similarly, and they equally share and insulate the voltage difference between the first circuit and the second circuit. Therefore, the potential of the third circuit is half the potential difference between the first and second circuits. Unlike this example, the potential of the third circuit may be biased towards either the potential of the first circuit or the potential of the second circuit, relative to half the potential difference between the first and second circuits.

[0102] According to this embodiment, the effects of applying a voltage that undergoes a rapid change can be suppressed on the first semiconductor element 11 and the second semiconductor element 12. The first insulating part that contributes to the protection of the first semiconductor element 11 and the second insulating part that contributes to the protection of the second semiconductor element 12 may have the same configuration as the first insulating part, or they may have different configurations. As for the specific configuration of the second insulating part, various configurations of the first insulating part described above may be appropriately adopted.

[0103] Figures 22 and 23 show a semiconductor device A40 according to the fourth embodiment. The semiconductor device A40 differs from the semiconductor device A30 in the following respect: The semiconductor device A40 does not have a first control element 13 and a second control element 14. Note that the connections of the multiple wires 42 and multiple wires 43 are examples and are not limited to the example shown in Figure 22, and can be appropriately changed depending on the configuration of the first semiconductor element 11 and the second semiconductor element 12.

[0104] In semiconductor device A40, multiple wires 42 are connected to one of the multiple pads 111 and to one of the two terminal portions 312 (covering portion 312a) of the first lead 31 or to one of the multiple leads 33, thereby creating electrical conductivity between them. In other words, multiple wires 42 create electrical conductivity between the first semiconductor element 11 and either the first lead 31 or the multiple leads 33.

[0105] In semiconductor device A40, multiple wires 43 are connected to one of the multiple pads 121 and to one of the two terminal portions 322 (covering portion 322a) of the second lead 32 or to one of the multiple leads 34, thereby creating electrical conductivity between them. In other words, multiple wires 43 create electrical conductivity between the second semiconductor element 12 and either the second lead 32 or the multiple leads 34.

[0106] In semiconductor device A40, for example, a first control element 13 is arranged on the wiring board on which semiconductor device A40 is mounted, and the first control element 13 can be electrically connected to a first semiconductor element 11 via the wiring board and a plurality of leads 33. Also, a first lead 31 can conduct to the ground of the first circuit including the first control element 13 via the wiring board. Similarly, a second control element 14 is arranged on the wiring board on which semiconductor device A40 is mounted, and the second control element 14 can be electrically connected to a second semiconductor element 12 via the wiring board and a plurality of leads 34. Also, a second lead 32 can conduct to the ground of the second circuit including the second control element 14 via the wiring board. In such a configuration, semiconductor device A40 (the first semiconductor element 11 and the second semiconductor element 12) can be used to isolate the first circuit (the circuit including the first control element 13) from the second circuit (the circuit including the second control element 14).

[0107] This embodiment makes it possible to suppress the effects of applying a voltage that involves abrupt changes on the first semiconductor element 11 and the second semiconductor element 12. As can be seen from this embodiment, in a configuration comprising the first semiconductor element 11 and the second semiconductor element 12, there is no limitation on whether or not the first control element 13 and the second control element 14, or both, are included.

[0108] Figures 24 and 25 show a semiconductor device A50 according to the fifth embodiment. The semiconductor device A50 differs from the semiconductor device A40 in the following respects. First, the first semiconductor element 11 of the semiconductor device A50 includes a functional unit 116 in addition to the first functional unit 115. Second, the second semiconductor element 12 of the semiconductor device A50 includes a functional unit 126 in addition to the second functional unit 125. Note that the connections of the multiple wires 42 and multiple wires 43 are examples and are not limited to the example shown in Figure 24, and can be appropriately changed depending on the configuration of the first semiconductor element 11 and the second semiconductor element 12.

[0109] The functional unit 116 functions as the first control element 13 (i.e., the control element). The functional unit 116 may be formed on, for example, the first substrate 110. The functional unit 116 is conductive to the first functional unit 115 inside the first semiconductor element 11. In the example shown in Figure 25, the functional unit 116 is conductive to the first lower winding 115b. In this example, multiple pads 111 are conductive to the functional unit 116, and multiple pads 112 are conductive to the first functional unit 115 (first upper winding 115a). The first semiconductor element 11 of the semiconductor device A50 has a configuration in which the control element and the insulating element are integrated into a single chip.

[0110] The functional unit 126 functions as the second control element 14 (i.e., the driving element). The functional unit 126 may be formed on, for example, the second substrate 120. The functional unit 126 is electrically connected to the second functional unit 125 inside the second semiconductor element 12. In the example shown in Figure 25, the functional unit 126 is electrically connected to the second lower winding 125b. In this example, multiple pads 121 are electrically connected to the functional unit 126, and multiple pads 122 are electrically connected to the second functional unit 125 (second upper winding 125a). The second semiconductor element 12 of the semiconductor device A50 has a configuration in which the driving element and the insulating element are integrated into a single chip.

[0111] In the semiconductor device A50 configured in this way, the first circuit including the functional part 116 of the first semiconductor element 11 and the second circuit including the functional part 126 of the second semiconductor element 12 are isolated from each other by the first functional part 115 of the first semiconductor element 11 and the second functional part 125 of the second semiconductor element 12.

[0112] This embodiment makes it possible to suppress the effects of applying a voltage that undergoes a rapid change on the first semiconductor element 11 and the second semiconductor element 12. As can be understood from this embodiment, in a configuration comprising the first semiconductor element 11 and the second semiconductor element 12, and the first control element 13 and the second control element 14, it is not limited in whether each is configured as a separate chip or whether they are configured as an integrated chip.

[0113] The semiconductor device relating to this disclosure is not limited to the embodiments described above. The specific configuration of each part of the semiconductor device relating to this disclosure can be modified in various ways. For example, the semiconductor device relating to this disclosure includes embodiments relating to the following appendices. Examples of each component in the following appendices are shown in parentheses using the reference numerals from the embodiments (including modified examples) described above, but are not limited thereto.

[0114] [Note 1] First semiconductor element (11), The first lead (31) has a first island portion (311) on which the first semiconductor element (11) is mounted, The first semiconductor element (11) includes a first substrate (110), a first functional portion (115) including a first upper winding (115a) and a first lower winding (115b) located between the first upper winding (115a) and the first substrate (110) in the thickness direction (z), and a first laminated structure (117) including a portion interposed between the first upper winding (115a) and the first lower winding (115b). A semiconductor device (A10) comprising a first insulating portion interposed between the first island portion (311) and the first functional portion (115). [Note 2] The semiconductor device (A10) described in Appendix 1, wherein the first insulating portion is the first substrate (110) containing an insulating material. [Note 3] The first substrate (110) is a semiconductor device (A10) as described in Appendix 2, which includes glass. [Note 4] The first substrate (110) is a semiconductor device (A12) as described in Appendix 2, comprising two semiconductor layers (1100, 1102) and an insulating layer (1101) interposed between the two semiconductor layers (1100, 1102). [Note 5] The semiconductor device (A13) described in Appendix 2 includes a semiconductor layer (1100) and an insulating layer (1101), and a bonding layer (1103) that joins the semiconductor layer (1100) and the insulating layer (1101). [Note 6] The first semiconductor element (11) and the first island portion (311) are joined together by a first insulating bonding material (16), The semiconductor device (A20) described in Appendix 1, wherein the first insulating bonding material (16) is the first insulating portion. [Note 7] The first semiconductor element (11) and the first island portion (311) are interposed by a first insulating plate material (17), The semiconductor device (A21) described in Appendix 1, wherein the first insulating plate material (17) is the first insulating part. [Note 8] The semiconductor device (A21) described in Appendix 7, wherein the first insulating board material (17) includes an insulating layer (170) and two metal layers (171, 172) individually disposed on both sides of the insulating layer (170). [Note 9] A semiconductor device (A10) according to any one of the appendices 1 to 8, comprising a semiconductor element (13) mounted on the first island portion (311) and connected to the first semiconductor element (11). [Note 10] A second semiconductor element (12) connected to the first semiconductor element (11), The second lead (32) is mounted on the second semiconductor element (12) and has a second island portion (321) that is separated from the first island portion (311), The second semiconductor element (12) includes a second semiconductor substrate (120), a second functional portion (125) including a second upper winding (125a) and a second lower winding (125b) located between the second upper winding (125a) and the second semiconductor substrate (120) in the thickness direction (z), and a second laminated structure (127) including a portion interposed between the second upper winding (125a) and the second lower winding (125b). A semiconductor device (A30) according to any one of appendices 1 to 8, comprising a second insulating portion interposed between the second island portion (321) and the first functional portion (115). [Note 11] The semiconductor device (A30) described in Appendix 10, wherein the first upper winding (115a) and the second upper winding (125a) are electrically connected. [Note 12] A semiconductor device (A30) as described in Appendix 10 or 11, comprising a first control element (13) mounted on the first island portion (311) and electrically connected to the first lower winding (115b). [Note 13] The semiconductor device (A50) described in Appendix 12, wherein the first semiconductor element (11) and the first control element (13) are configured as a single element. [Note 14] A semiconductor device (A30) according to any one of appendices 10 to 13, comprising a second control element (14) mounted on the second island portion (321) and electrically connected to the second lower winding (125b). [Note 15] The semiconductor device (A50) described in Appendix 14, wherein the second semiconductor element (12) and the second control element (14) are configured as a single element. [Explanation of Symbols]

[0115] A10, A11, A12, A13, A20, A21, A30, A40, A50: Semiconductor equipment 3: Conductive support 4: Connecting member 5: Sealing resin 11: First semiconductor element 11a: Main surface 11b: Back side 12: Second semiconductor element 12a: Main surface 12b: Reverse side 13: First control element 13a: Main surface 13b: Back side 14: Second control element 14a: Main surface 14b: Reverse side 16: First insulating bonding material 17: First insulating board material 31: First lead 32: Second lead 33: Lead 33A: Intermediate lead 33B: Side lead 34: Lead 34A: Intermediate lead 34B: Side lead 41, 42, 43, 44, 45, 46, 47: Wire 51:Top surface 52: Bottom 53: Side view 54: Side view 110: First board 111: Pad 112: Pad 115: First Functional Unit 115a: First upper winding 115b: First lower winding 116: Functional section 117: First Laminated Structure 118:Wiring section 119: First conductive bonding material 120: Second board 121: Pad 122: Pad 125: Second Functional Unit 125a: Second upper winding 125b: Second lower winding 126: Functional parts 127: Second layered structure 128:Wiring section 129: Second conductive bonding material 131: Pad 139: Conductive bonding material 141: Pad 149: Conductive bonding material 170: Insulating layer 171,172: Metal layer 311: First Island Section 311a: Mounting surface 312:Terminal section 312a: Covering part 312b: Exposed part 313: Through hole 321: Second Island Section 321a: Mounting surface 322:Terminal section 322a: Covering part 322b:Exposed part 331: Covering part 332 :Exposed part 341: Covering part 342 :Exposed part 411: Joint 412: Joint 413: Loop section 413a: Rising section 421: Joint 422: Joint 423: Loop section 423a: Rising section 431: Joint 432: Joint 433: Loop section 433a: Rising section 531: Top 532: Lower part 533: Middle section 541: Top 542: Lower part 543: Middle section 1100: Semiconductor layer 1101: Insulating layer 1102: Semiconductor layer 1103: Bonding layer 1141 :Protective film 1142: Passivation membrane 1143: Coil protective film 1171: First insulating layer 1181: Through-hole wiring 1182: Output wiring 1241 :Protective film 1242: Passivation membrane 1243: Coil protective film 1271: Second insulating layer 1281: Through-hole wiring 1282: Output wiring C: Material x :1st direction y: Second direction z: thickness direction

Claims

1. First semiconductor device, A first lead having a first island portion on which the first semiconductor element is mounted, The first semiconductor element comprises a first substrate, a first functional portion including a first upper winding and a first lower winding located between the first upper winding and the first substrate in the thickness direction, and a first laminated structure including a portion interposed between the first upper winding and the first lower winding. A semiconductor device comprising a first insulating portion interposed between the first island portion and the first functional portion.

2. The semiconductor device according to claim 1, wherein the first insulating portion is the first substrate containing an insulating material.

3. The semiconductor device according to claim 2, wherein the first substrate includes glass.

4. The semiconductor device according to claim 2, wherein the first substrate includes two semiconductor layers and an insulating layer interposed between the two semiconductor layers.

5. The semiconductor device according to claim 2, wherein the first substrate includes a semiconductor layer and an insulating layer, and a bonding layer that joins the semiconductor layer and the insulating layer.

6. The first semiconductor element and the first island portion are joined together by a first insulating bonding material, The semiconductor device according to claim 1, wherein the first insulating bonding material is the first insulating portion.

7. The first semiconductor element and the first island portion are interposed between them, The semiconductor device according to claim 1, wherein the first insulating plate material is the first insulating portion.

8. The semiconductor device according to claim 7, wherein the first insulating board material includes an insulating layer and two metal layers individually disposed on both sides of the insulating layer.

9. The semiconductor device according to claim 1, comprising a semiconductor element mounted on the first island portion and connected to the first semiconductor element.

10. A second semiconductor element connected to the first semiconductor element, The second lead comprises a second island portion on which the second semiconductor element is mounted and which is separated from the first island portion, The second semiconductor element comprises a second semiconductor substrate, a second functional portion including a second upper winding and a second lower winding located between the second upper winding and the second semiconductor substrate in the thickness direction, and a second laminated structure including a portion interposed between the second upper winding and the second lower winding. The semiconductor device according to claim 1, further comprising a second insulating portion interposed between the second island portion and the first functional portion.

11. The semiconductor device according to claim 10, wherein the first upper winding and the second upper winding are electrically connected.

12. The semiconductor device according to claim 10, comprising a first control element mounted on the first island portion and electrically connected to the first lower winding.

13. The semiconductor device according to claim 12, wherein the first semiconductor element and the first control element are configured as a single element.

14. The semiconductor device according to claim 10, comprising a second control element mounted on the second island portion and electrically connected to the second lower winding.

15. The semiconductor device according to claim 14, wherein the second semiconductor element and the second control element are configured as a single element.

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