Received clock recovery device, receiver, and received clock recovery method

Abstract

This invention provides an information processing device that enables secure configuration updates even for standalone devices that do not have a network connection. [Solution] The receiving clock recovery device receives a series of digital sampling data D(k-1 / 2), D(k-1), and D(k-3 / 2) sampled in response to an input signal at a sampling frequency determined based on the receiving clock, and includes a determination means for determining whether the frequency of the receiving clock is higher or lower than the frequency of the transmitting clock using D(k-1 / 2), D(k-1), and D(k-3 / 2) when D(k-1 / 2) and D(k-3 / 2) are approximately the same, and a correction means for correcting the phase difference of the receiving clock with respect to the transmitting clock using the determination result from the determination means.

Description

[Technical Field]

[0001] The present invention relates to a reception clock recovery device, a receiver, and a reception clock recovery method. [Background Art]

[0002] In recent years, with the rapid development of communication infrastructure, there has been a demand for increased capacity of core networks. To meet this demand, digital coherent optical transmission systems have been developed. In particular, the Dual Polarization Quadrature Phase Shift Keying (DP-QPSK) scheme has been widely adopted. On the other hand, for a digital coherent optical transmission system to operate effectively, clock recovery processing that extracts an accurate clock signal from a digital signal received by a receiver and samples the digital signal using the clock signal is important.

[0003] Patent Document 1 discloses a digital coherent receiver including a clock recovery unit that extracts a clock signal from a digital signal output from a chromatic dispersion compensation unit and performs identification and regeneration of the digital signal using the clock signal. [Prior Art Documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Unexamined Patent Publication No. 2016-208115 [Summary of the Invention] [Problem to be Solved by the Invention]

[0005] By the way, in a state where there is an offset with a period exceeding the feedback loop time between the received signal and the reception-side sampling clock, it may not be possible to appropriately determine whether the frequency of the reception clock relative to the transmission clock is higher or lower from the reception data sampled by analog-to-digital conversion on the reception side.

[0006] The purpose of this disclosure is to provide a received clock recovery device, a receiver, and a received clock recovery method that solve the above-mentioned problems. [Means for solving the problem]

[0007] A receiving clock recovery device according to one aspect of the present disclosure includes a determination means that receives a series of digital sampling data D(k-1 / 2), D(k-1), and D(k-3 / 2) sampled with respect to an input signal at a sampling frequency determined based on a receiving clock, and determines whether the frequency of the receiving clock is higher or lower than the frequency of the transmitting clock using D(k-1 / 2), D(k-1), and D(k-3 / 2) when D(k-1 / 2) and D(k-3 / 2) are substantially the same.

[0008] A receiver according to one aspect of this disclosure includes the aforementioned receiving clock recovery device.

[0009] A receiving clock recovery method for a receiving clock recovery device according to one aspect of the present disclosure includes inputting continuous digital sampling data D(k-1 / 2), D(k-1), and D(k-3 / 2) sampled at a sampling frequency determined based on the receiving clock to an input signal, determining whether the frequency of the receiving clock is higher or lower than the frequency of the transmitting clock using D(k-1 / 2), D(k-1), and D(k-3 / 2) when D(k-1 / 2) and D(k-3 / 2) are approximately the same, and correcting the phase difference of the receiving clock with respect to the transmitting clock using the determination result. [Effects of the Invention]

[0010] According to the above embodiment, it becomes possible to appropriately determine whether the frequency of the received clock is higher or lower than the frequency of the transmitted clock from the received data obtained by sampling the input signal. [Brief explanation of the drawing]

[0011] [Figure 1]This figure shows the basic configuration of a transmitting and receiving system including a transmitter and receiver according to one embodiment of the present disclosure. [Figure 2] This diagram shows a detailed configuration of the clock phase detection unit. [Figure 3] This diagram shows the configuration of the PID control unit in detail. [Figure 4] This figure shows the digital sampling data D(k-1 / 2), D(k-1), and D(k-3 / 2) for the analog signal input from the optical coherent receiver. 1. [Figure 5A] This figure shows the digital sampling data D(k-1 / 2), D(k-1), and D(k-3 / 2) for the analog signal input from the optical coherent receiver. [Figure 5B] This figure shows the digital sampling data D(k-1 / 2), D(k-1), and D(k-3 / 2) for the analog signal input from the optical coherent receiver. [Figure 6A] This figure shows the digital sampling data D(k-1 / 2), D(k-1), and D(k-3 / 2) for the analog signal input from the optical coherent receiver. [Figure 6B] This figure shows the digital sampling data D(k-1 / 2), D(k-1), and D(k-3 / 2) for the analog signal input from the optical coherent receiver. [Figure 7] This is a diagram illustrating the high / low determination process in the judgment unit. [Figure 8] This diagram illustrates the operation of the phase error calculation unit within the clock phase detection unit. [Figure 9] This diagram illustrates the operation of the phase error calculation unit within the clock phase detection unit. [Figure 10] This diagram illustrates the operation of the phase error calculation unit within the clock phase detection unit. [Figure 11] This diagram illustrates the operation of the phase error calculation unit within the clock phase detection unit. [Figure 12] This is a flowchart showing the operation of the receive clock recovery device. [Figure 13] FIG. 1 is a diagram showing the minimum configuration of a clock recovery device according to an embodiment of the present invention. DETAILED DESCRIPTION OF EMBODIMENTS

[0012] Hereinafter, a receiver including a reception clock recovery device according to an embodiment of the present disclosure will be described with reference to the drawings. FIG. 1 is a diagram showing a basic configuration of a transmission / reception system including a transmitter and a receiver according to an embodiment. As shown in FIG. 1, the transmission / reception system includes a transmitter 100 and a receiver 200, and a transmission line 30 is provided between the transmitter 100 and the receiver 200.

[0013] The transmitter 100 includes a transmission clock unit 101, a frame generation unit 102, a signal generation unit 103, and an optical coherent transmission unit 104. The receiver 200 includes an optical coherent reception unit 201, an ADC unit 202, an equalization unit 203, a polarization separation unit 204, a frequency offset compensation unit 205, a phase offset compensation unit 206, a decoding unit 207, a clock phase detection unit 300, a PID control unit 400, and a reception clock generation unit 208.

[0014] In the transmitter 100, a transmission clock unit 101 generates a transmission clock used on the transmission side. The transmission clock unit 101 also supplies the generated transmission clock to a frame generation unit 102, a signal generation unit 103, and other unillustrated functional units in the transmitter. The frame generation unit 102 frames transmission data and outputs the framed data to the signal generation unit 103. The signal generation unit 103 converts the framed data into an analog signal and outputs the analog signal to an optical coherent transmission unit 104. The present disclosure is described with a polarization-multiplexed Quadrature Phase Shift Keying (QPSK) modulation scheme. In this case, the four signals output from the signal generation unit 103 are an X-polarized I signal (XI), an X-polarized Q signal (XQ), a Y-polarized I signal (YI), and a Y-polarized Q signal (YQ). These signals are obtained by converting binary data received from the frame generation unit 102 into four constellation points corresponding to 45 degrees, 135 degrees, 225 degrees, and 315 degrees. The optical coherent transmission unit 104 performs optical modulation using the four received signals, and outputs the modulated signal to a transmission path 30.

[0015] In the receiver 200, an optical coherent reception unit 201 causes an optical signal received from a transmission path 30 to interfere with a light source in the optical coherent reception unit 201, and converts the interfered optical signal into an electrical signal. The converted electrical signal is output to an ADC unit 202. Since the present disclosure adopts the polarization-multiplexed QPSK modulation scheme, the optical coherent reception unit 201 outputs an X'-polarized I signal (X'I), an X'-polarized Q signal (X'Q), a Y'-polarized I signal (Y'I), and a Y'-polarized Q signal (Y'Q).

[0016] The ADC unit 202, an analog-to-digital converter, samples each of the four signals from the optical coherent receiver unit 201 in synchronization with the received clock shared by the received clock generation unit 208. The sampled data is converted from analog signals to digital signals and output to the equalization unit 203 and the clock phase detection unit 300. The digitally converted data consists of four signals: X'I, X'Q, Y'I, and Y'Q. The clock used for sampling is twice the symbol rate, and 2x oversampling is performed. The converted digital signals are output to the equalization unit 203 and the clock phase detection unit 300.

[0017] The equalization unit 203 compensates for the degradation of the received signal waveform caused by bandwidth limiting in the optical coherent transmitter 104 and optical coherent receiver 201 and transmission of the coherent optical signal in the transmission line 30, using an FIR (Finite Impulse Response) filter or the like. The polarization separation unit 204 corrects the polarization rotation in the transmission line 30, separates the X-polarized signal and Y-polarized signal generated on the transmitting side, and outputs them to the frequency offset compensation unit 205. The polarization separation method is performed by the CMA (Coherent Multi-Carrier Access) method or the like. The frequency offset compensation unit 205 performs frequency offset compensation processing on the polarization-separated signal and outputs it to the phase offset compensation unit 206. The phase offset compensation unit 206 performs phase offset compensation processing on the frequency offset-compensated signal. This compensates for the slope of the constellation, and the signal is plotted at four points, for example, 45 degrees, 135 degrees, 225 degrees, and 315 degrees. The phase-offset compensated signal is output to the decoding unit 207. The decoding unit 207 makes a determination on the constellation of the frequency-offset compensated and phase-offset compensated signals and performs decoding. As a result, the data from the transmitting side is decoded and output to the subsequent functional unit.

[0018] The clock phase detection unit 300 performs phase difference detection processing between the transmit clock and the receive clock for each of the four signals input from the ADC unit 202, and outputs the result as a phase error (PHERR) to the PID control unit 400. The PID control unit 400 generates PID control values ​​(Proportional, Integral, Derivative: P [proportional control], I [integral control], D [derivative control]) according to the phase error. In this embodiment, the control value is the frequency setting value and is output to the subsequent receive clock generation unit 208. The receive clock generation unit 208 generates a clock according to the frequency setting value input from the PID control unit 400 and supplies it to the ADC unit 202.

[0019] Figure 2 is a diagram showing the configuration of the clock phase detection unit 300 in detail. The clock phase detection unit 300 consists of four phase error calculation units 320, 321, 322, and 323, which correspond to the input signals X'I, X'Q, Y'I, and Y'Q from the ADC unit 202, respectively. Note that the configuration of the phase error calculation units 320, 321, 322, and 323 is the same. Below, the configuration of the phase error calculation unit will be explained using the phase error calculation unit 320 as an example.

[0020] The phase error calculation unit 320 includes T-delay units 301 and 302 that delay the input signal by one symbol time T, T / 2-delay units 303 and 304 that delay the input signal by half a period of time, addition units 305 and 306, multiplication units 307, 308, and 309, determination unit 310, and squaring unit 311. The T-delay units 301 and 302 are processing units that output the input signal after holding it for a time T. The T / 2-delay units 303 and 304 are processing units that output the input signal after holding it for a time T / 2. The T-delay unit 301 outputs data D(k-1), which is one symbol time delayed from the input data D(k) from the ADC unit 202, to the addition units 305 and 306, the T-delay unit 302, the T / 2-delay unit 304, and the determination unit 310. The determination unit 310 outputs D(k-1) as DIN2. The T / 2 delay unit 303 outputs data D(k-1 / 2), which is delayed by 1 / 2 symbol time from the input data D(k) from the ADC unit 202, to the multiplication unit 307 and the determination unit 310. Note that D(k-1 / 2) is output to the determination unit 310 as DCP1.

[0021] The adder 305 adds the input data D(k) from the ADC 202 and the output data D(k-1) from the T delay 301 with a negative sign and outputs it to the multiplier 307. The multiplier 307 multiplies the output of the adder 305 and the output of the T / 2 delay 303 and outputs it as error 1 (ERR1) to the determination 310.

[0022] The T-delay unit 302 outputs data D(k-2), which is obtained by delaying the output D(k-1) of the T-delay unit 301 by one symbol time, to the adder 306 and the determination unit 310. D(k-2) is output to the determination unit 310 as DIN3.

[0023] The T / 2 delay unit 304 outputs data D(k-3 / 2), which is obtained by delaying the output D(k-1) of the T delay unit 301 by 1 / 2 symbol time, to the multiplication unit 308 and the determination unit 310. The determination unit 310 outputs D(k-3 / 2) as DCP2.

[0024] The adder 306 adds the output D(k-1) from the T delay unit 301 and the output data D(k-2) from the T delay unit 302 with a negative sign and outputs it to the multiplier 308. The multiplier 308 multiplies the output of the adder 306 and the output of the T / 2 delay unit 304 and outputs it as error 2 (ERR2) to the determination unit 310.

[0025] The determination unit 310 receives the input data D(k) from the ADC unit 202 as DIN1, and receives ERR1 from the multiplication unit 307, DCP1 from the T / 2 delay unit 303, DIN2 from the T delay unit 301, DIN3 from the T delay unit 302, DCP2 from the T / 2 delay unit 304, and ERR2 from the multiplication unit 308 to determine whether the frequency of the received clock is higher or lower than the frequency of the transmitted clock. The result of the frequency high or low determination is output to the multiplication unit 309 as +1 if it is higher and -1 if it is lower. In addition, the phase error ERR1 is output as ERR_d to the squaring unit 311.

[0026] The squaring unit 311 squares the phase error ERR_d and outputs the positive phase error value to the multiplication unit 309. The multiplication unit 309 multiplies the value of the determination result of the determination unit 310, which is +1 or -1, with the positive phase error value from the squaring unit 311, and outputs the result as the phase error PHERR to the PID control unit 400. The four phase errors output from the phase error calculation units 320 to 323 that constitute the clock phase detection unit 300 are denoted as PHERR_XI, PHERR_XQ, PHERR_YI, and PHERR_YQ, respectively.

[0027] Figure 3 is a diagram showing the configuration of the PID control unit 400 in detail. The PID control unit 400 consists of adders 401 and 402, a filter 403, a differential D control unit 404, an integral I control unit 405, multipliers 406, 407, and 408, and a control value generation unit 409.

[0028] The adder 401 adds the four phase errors (PHERR_XI to PHERR_YQ) from the phase error calculation units 320 to 323 that constitute the clock phase detection unit 300 and outputs the result to the filter unit 403. The filter unit 403 removes noise from the phase errors input from the adder 401 and outputs the result to the multiplier 406, the differential D control unit 404, and the integral I control unit 405. The filter unit 403 is, for example, a low-pass filter. The differential D control unit 404 calculates the differential value (slope) of the noise-removed phase error and outputs it to the multiplier 407. The integral I control unit 405 calculates the integral value of the noise-removed phase error and outputs it to the multiplier 408.

[0029] The multiplier 406 multiplies the denoised phase error by the gain coefficient Kp and outputs it to the adder 402. This output becomes the proportional term of the PID control. The multiplier 407 multiplies the derivative value of the phase error output from the differential D control unit 404 by the gain coefficient Kd and outputs it to the adder 402. This output becomes the derivative term of the PID control. The multiplier 408 multiplies the integral value of the phase error output from the integral I control unit 405 by the gain coefficient Ki and outputs it to the adder 402. This output becomes the integral term of the PID control. The adder 402 adds the outputs of the multipliers 406, 407, and 408 and outputs the adjusted value to the control value generation unit 409. The control value generation unit 409 adds the input adjusted value to the current control value and outputs it to the receive clock generation unit 208. In this disclosure, the control value will be referred to as the frequency setting value in the following explanation.

[0030] Next, we will explain the basic method for determining the high or low frequency of the received clock relative to the transmitted clock, based on the sampled consecutive digital sampling data D(k-1 / 2), D(k-1), D(k-3 / 2) for the analog signal input from the optical coherent receiver 201. Figures 4, 5A, 5B, 6A, and 6B show the relationship between the analog signal input from the optical coherent receiver 201 and the consecutive digital sampling data D(k-1 / 2), D(k-1), D(k-3 / 2) sampled according to the received clock. Here, the analog signal input from the optical coherent receiver 201 is conveniently assumed to be a sine wave. In each figure, the digital value of the sampling point at sampling time k-1 is denoted as D(k-1), and the digital values ​​of the sampling points before and after it are denoted as D(k-1 / 2) and D(k-3 / 2). The difference between sampling times (k-1 / 2) and (k-1) is approximately 1 / 2 symbol time, and the difference between sampling times (k-1) and (k-3 / 2) is approximately 1 / 2 symbol time.

[0031] Figure 4 shows a state where D(k-1 / 2) and D(k-3 / 2) are approximately the same (nearly the same), and there is no phase error between the transmitted and received clocks. That is, both D(k-1 / 2) and D(k-3 / 2) are approximately zero. Here, whether or not they are approximately the same (nearly the same) is determined based on the level of the received signal. More specifically, if the absolute value of the difference between D(k-1 / 2) and D(k-3 / 2) is less than or equal to a predetermined threshold, it is determined that they are approximately the same (nearly the same). Here, the predetermined threshold is set, for example, as α times the maximum value of the received signal level. The value α is, for example, a preset value of 0.1 or less.

[0032] Figures 5A and 5B show a state where D(k-1 / 2) and D(k-3 / 2) are approximately equal, indicating that the received clock frequency is higher than the transmitted clock frequency. Specifically, as shown in Figure 5A, if the values ​​of D(k-1 / 2), D(k-1), and D(k-3 / 2) are all positive, or as shown in Figure 5B, if the values ​​of D(k-1 / 2), D(k-1), and D(k-3 / 2) are all negative, it is determined that the received clock frequency is higher than the transmitted clock frequency.

[0033] Figures 6A and 6B show a state where D(k-1 / 2) and D(k-3 / 2) are approximately the same, and the received clock is lower than the transmitted clock. That is, as shown in Figure 6A, if the values ​​of D(k-1 / 2) and D(k-3 / 2) are negative and the value of D(k-1) is positive, or as shown in Figure 6B, if the values ​​of D(k-1 / 2) and D(k-3 / 2) are positive and the value of D(k-1) is negative, it is determined that the frequency of the received clock is lower than the frequency of the transmitted clock.

[0034] Note that in Figures 4, 5A, 5B, 6A, and 6B, DCP1 = D(k-1 / 2) DIN = D(k-1) DCP2 = D(k-3 / 2) In this case, when DCP1 and DCP2 are approximately the same, the values ​​of DCP1, DIN, and DCP2 are used to determine whether the frequency of the received clock is higher or lower than that of the transmitted clock.

[0035] As a basic operation, the phase error calculation unit 320 determines whether the frequency of the received clock is higher or lower than the frequency of the transmitted clock using the determination method shown in Figures 4, 5A, 5B, 6A, and 6B. In addition to the above basic operation, the phase error calculation unit 320 further adds a configuration that allows clock recovery even when the offset clock frequency, which is the difference between the frequency of the transmitted clock and the frequency of the received clock, is large, by determining whether the frequency of the received clock is higher or lower than the frequency of the transmitted clock. To this end, the phase error calculation unit 320 uses five consecutive digital sampling data sets, including the consecutive digital sampling data sets D(k) and D(k-2), in addition to the consecutive digital sampling data sets D(k-1 / 2), D(k-1), and D(k-3 / 2), to determine whether the frequency of the received clock is higher or lower than the frequency of the transmitted clock. Note that the difference between sampling times (k) and (k-1 / 2) is 1 / 2 symbol time, and the difference between sampling times (k-3 / 2) and (k-2) is also 1 / 2 symbol time. The operation of the phase error calculation unit 320 using five consecutive digital sampling data points will be explained below with reference to a diagram.

[0036] Figures 7 to 11 are diagrams illustrating the operation of the phase error calculation unit 320 within the clock phase detection unit 300. Since the same processing is performed for each of the four digital signals X'I, X'Q, Y'I, and Y'Q output from the ADC unit 202, the explanation will proceed using the case where the X'I signal is as shown in Figure 8 as an example. The analog signal X'I 506 in Figure 8 represents the analog signal input to the ADC unit 202 from the optical coherent receiver unit 201. Sampling points D501, 502, 503, 504, and 505 illustrate the values ​​sampled by the ADC unit 202. The sampling point at sampling time k is denoted as D(k), and the sampling point at sampling time k-1 is denoted as D(k-1). As mentioned above, the difference between sampling times k and k-1 is 1 symbol time, and the difference between sampling time k and k-1 / 2 is 1 / 2 symbol time. The symbol time is determined by the modulation scheme and the received clock. In this embodiment, each sampling point becomes digital sampling data sampled at a sampling rate of 1 / 2 symbol time determined by the receiving clock. That is, the digital sampling data is data sampled at a sampling rate that is oversampled by twice the symbol rate, as described above. If there is a phase error in the receiving clock relative to the transmitting clock, the receiver 200 can sample the received signal at an appropriate sampling rate by correcting the phase difference of the receiving clock relative to the transmitting clock. As a result, the receiver 200 can accurately decode the transmitted signal by sampling at an appropriate sampling rate.

[0037] When the sampling point D(k) at sampling time k is input to the phase error calculation unit 320, the signals DIN1, ERR1, DCP1, DIN2, DIN3, DCP2, and ERR2 input to the determination unit 310 can be expressed using the following formulas with respect to the sampling point D.

[0038] DIN1 = D(k)...Equation 1 ERR1 = D(k-1 / 2)*{ D(k)-D(k-1)} Formula 2 DCP1 = D(k-1 / 2)...Equation 3 DIN2 = D(k-1)...Equation 4 DIN3 = D(k-2)...Equation 5 DCP2 = D(k-3 / 2)...Equation 6 ERR2 = D(k-3 / 2)*{ D(k-1)-D(k-2)} Formula 7 The determination unit 310 performs the determination process shown in Figure 7 when DCP1 and DCP2 are approximately the same. Here, the determination of whether or not they are "approximately the same" is as described above.

[0039] Point A500 is an example of a determination where the sign of sampling point D(k) is negative and the received clock frequency is higher than the transmitted clock frequency (Sample freq > signal Freq). The sign after processing with equations 1 to 7 is as follows.

[0040] DIN1 = negative, ERR1 = negative, DCP1 = positive, DIN2 = positive, DIN3 = negative, DCP2 = positive, ERR2 = positive Based on the input above, the judgment in Figure 7 results in a high / low determination of "+1". Note that this determination result is "+1" if the received clock frequency is higher than the transmitted clock frequency, and "-1" if it is lower.

[0041] Point B510 in Figure 9 is an example of a determination where the sign of sampling point D(k) is positive and the received clock frequency is higher than the transmitted clock frequency (Sample freq > signal Freq), and the sign after processing with Equations 1 to 7 is as follows.

[0042] DIN1 = positive, ERR1 = negative, DCP1 = negative, DIN2 = negative, DIN3 = positive, DCP2 = negative, ERR2 = positive Based on the input above, the judgment in Figure 7 results in a high / low determination of "+1".

[0043] Next, point C600 in Figure 10 is an example of determining the case where the sign of the sampling point D(k) is negative and the received clock frequency is lower than the transmitted clock frequency (Sample freq < signal Freq), and the sign after processing with Equations 1 to 7 is as follows.

[0044] DIN1 = negative, ERR1 = positive, DCP1 = negative, DIN2 = positive, DIN3 = negative, DCP2 = negative, ERR2 = negative Based on the input above, the judgment in Figure 7 results in a high / low determination of "-1".

[0045] In Figure 11, point D610 is an example of a determination where the sign of sampling point D(k) is positive and the received clock frequency is lower than the transmitted clock frequency (Sample freq < signal Freq). The sign after processing with Equations 1 to 7 is as follows.

[0046] DIN1 = positive, ERR1 = positive, DCP1 = positive, DIN2 = negative, DIN3 = positive, DCP2 = positive, ERR2 = negative Based on the input above, the judgment in Figure 7 results in a high / low determination of "-1".

[0047] The determination unit 310 updates the determination result when DCP1 and DCP2 are approximately the same, and maintains the determination result otherwise. The determination unit 310 outputs the calculated value of ERR1 as ERR1_d to the squaring unit 311. The squaring unit 311 squares the input phase error ERR1_d to make the sign of the phase error positive and outputs it to the multiplication unit 309. The multiplication unit 309 multiplies the square of the phase error ERR1_d by "+1" or "-1" of the determination result to reflect the high or low frequency determination result of the determination unit 310 in the phase error and outputs it to the PID control unit 400.

[0048] As described above, the phase error calculation units 320 to 323 within the clock phase detection unit 300 operate. The determination unit 310 of the phase error calculation units 320 to 323 may be configured using hardware logic or implemented by software processing using a general-purpose processor.

[0049] By the way, referring to Figure 7, it can be seen that when DCP1 and DCP2 are approximately the same, if the value of ERR1 is negative, the judgment result is determined to be "+1", and if the value of ERR1 is positive, the judgment result is determined to be "-1". In other words, when DCP1 and DCP2 are approximately the same, the phase error calculation units 320 to 323 can obtain a judgment result based on whether the value of ERR1 is positive or negative. In this case, since it is not necessary to calculate ERR2, the phase error calculation units 320 to 323 may perform the judgment using four consecutive digital sampling data D(k), D(k-1 / 2), D(k-1), and D(k-3 / 2).

[0050] Similarly, when DCP1 and DCP2 are approximately the same, the phase error calculation units 320-323 can determine a result based on whether the value of ERR2 is positive or negative. In this case, since it is not necessary to calculate ERR1, the phase error calculation units 320-323 may perform the determination using four consecutive digital sampling data D(k-1 / 2), D(k-1), D(k-3 / 2), and D(k-2). In this case, the phase error calculation units 320-323 may also determine the phase error as the value obtained by multiplying the square of ERR2 by the determination result.

[0051] Furthermore, the phase error calculation units 320-323 are: ERR1 = D(k-1 / 2)*{ D(k)-D(k-1)} Formula 2 ERR2 = D(k-3 / 2)*{ D(k-1)-D(k-2)} Formula 7 This is how it is calculated. The phase error calculation units 320-323 then calculate this. ERR1 = D(k-1 / 2)*{ D(k-1)-D(k)} ··· Formula 2' ERR2 = D(k-3 / 2)*{ D(k-2)-D(k-1)} ...Equation 7' If calculated in this way, the determination may be made in a manner inverse to the cases of Equation 2 and Equation 7, such that the sign of ERR1 and the determination result based on the sign of ERR1 are positive. That is, when using Equation 2', the determination unit 310 determines the result to be "+1" if the value of ERR1 is positive when DCP1 and DCP2 are approximately the same, and determines the result to be "-1" if the value of ERR1 is negative. Also, when using Equation 7', the determination unit 310 determines the result to be "+1" if the value of ERR2 is negative when DCP1 and DCP2 are approximately the same, and determines the result to be "-1" if the value of ERR2 is positive.

[0052] In this disclosure, the DP-QPSK modulation scheme was used as an example, and therefore the ADC unit 202 outputs four digital signals. However, if polarization multiplexing is not performed, the phase error calculation unit 320 may be used for two outputs. Also, in this explanation, the DP-QPSK modulation scheme was used as an example, and an example was shown where four phase error calculation units 320 to 323 are provided for the four digital signals output from the ADC unit 202. However, if the circuit size needs to be reduced, the phase error calculation unit may be provided for one to three of the four digital signals. Furthermore, even for received signals other than QPSK modulation, if the patterns shown in Figures 8 to 11 can be detected, a determination of whether the received clock frequency is higher or lower than the transmitted clock frequency may be made.

[0053] Furthermore, the determination process in the determination unit 310 was performed when DCP1 and DCP2 were approximately the same. In addition to this condition, the absolute values ​​of the digital data of DIN1, DIN2, and DIN3 were used. |DIN1|> THdin & |DIN2|> THdin &|DIN3|> THdin The determination unit 310 may perform a determination process when the condition is met. Here, THdin is an absolute threshold value, which may be changed dynamically according to the level of the received signal, or it may be operated with a fixed value.

[0054] Alternatively, a filter unit can be added between the ADC unit 202 and the clock phase detection unit 300 in Figure 2. This improves noise immunity by applying a low-pass filter to the digital signal output from the ADC unit 202, enabling the determination of whether the received clock frequency is higher or lower than the transmitted clock frequency.

[0055] In the receiver 200, the clock phase detection unit 300 functions as a determination means for determining whether the frequency of the received clock is higher or lower than that of the transmitted clock. Furthermore, the PID control unit 400 and the received clock generation unit 208 function as correction means for correcting the phase difference of the received clock relative to the transmitted clock using the phase error obtained using the determination result from the determination means. These determination means and correction means constitute a received clock recovery device. The receiver 200 is configured as a transmitter equipped with this received clock recovery device.

[0056] Figure 12 is a flowchart showing the operation of the receive clock recovery device. The determination means of the receive clock recovery device receives input digital sampling data, which includes consecutive digital sampling data D(k-1 / 2), D(k-1), and D(k-3 / 2) sampled with respect to the input signal (step S10).

[0057] The determination means determines whether D(k-1 / 2) and D(k-3 / 2) are approximately the same (step S20). If they do not match (step S10: No), the determination means retains the previous determination result and receives the next sampling data input (step S10).

[0058] If they match (Step S10: Yes), the input sampling data is used to determine whether the frequency of the received clock is higher or lower than the frequency of the transmitted clock (Step S30).

[0059] The correction means of the received clock recovery device corrects the phase difference of the received clock with respect to the transmitted clock using the phase error obtained using the determination result of the determination means (step S40).

[0060] The operation of the received clock recovery device involves repeating steps S10 to S40 in response to the input signal. Note that the input of digital sampling data in step S10 may be four consecutive digital sampling data, including D(k-1 / 2), D(k-1), and D(k-3 / 2), or five consecutive digital sampling data. In this case, the determination of whether the frequency of the received clock is high or low relative to the transmitted clock and the calculation of the phase error are as described above.

[0061] In the embodiment of this disclosure described above, the receiver 200 can determine whether the received clock frequency is high or low relative to the transmitted clock frequency from five sample points, even when the frequency offset is large, thus enabling clock recovery. Furthermore, stable clock recovery is possible even when the frequency offset is large. Moreover, since complex calculations are not required, the circuit size is small and low power consumption is possible.

[0062] Figure 13 is a diagram showing the minimum configuration of a received clock recovery device 700 according to one embodiment of the present invention. The received clock recovery device 700 comprises a determination means 710 and a correction means 720. The determination means 710 receives continuous digital sampling data D(k-1 / 2), D(k-1), and D(k-3 / 2) sampled at a sampling frequency determined based on the received clock in response to the input signal, and uses D(k-1 / 2), D(k-1), and D(k-3 / 2) when D(k-1 / 2) and D(k-3 / 2) are approximately identical to determine whether the frequency of the received clock is higher or lower than that of the transmitted clock. The correction means 720 corrects the phase difference of the received clock with respect to the transmitted clock using the determination result from the determination means 710.

[0063] Although the present disclosure has been described above with reference to embodiments, the present disclosure is not limited to the embodiments described above. Various modifications to the structure and details of the present disclosure are possible, as can be understood by those skilled in the art within the scope of the present disclosure. Furthermore, each embodiment can be combined in any way that suits the context of the present disclosure.

[0064] Some or all of the above embodiments may also be described as follows, but are not limited to the following:

[0065] (Note 1) A determination means that inputs consecutive digital sampling data D(k-1 / 2), D(k-1), and D(k-3 / 2) sampled at a sampling frequency determined based on the received clock in relation to the input signal, and uses D(k-1 / 2), D(k-1), and D(k-3 / 2) when D(k-1 / 2) and D(k-3 / 2) are approximately identical to determine whether the frequency of the received clock is higher or lower than the frequency of the transmitted clock. A correction means for correcting the phase difference of the received clock with respect to the transmitted clock using the determination result of the determination means, A receiving clock recovery device equipped with the following features.

[0066] (Note 2) The determination means determines that the frequency of the receiving clock is higher than the frequency of the transmitting clock if the values ​​of D(k-1 / 2), D(k-1), and D(k-3 / 2) are all positive or all negative, and determines that the frequency of the receiving clock is lower than the frequency of the transmitting clock in all other cases. The receiving clock recovery device described in Appendix 1.

[0067] (Note 3) The determination means receives four consecutive digital sampling data D(k), D(k-1 / 2), D(k-1), D(k-3 / 2) or D(k-1 / 2), D(k-1), D(k-3 / 2), D(k-2) as input, and uses the four digital sampling data when D(k-1 / 2) and D(k-3 / 2) are approximately identical to determine whether the frequency of the received clock is higher or lower than the frequency of the transmitted clock. The receiving clock recovery device described in Appendix 1.

[0068] (Note 4) The determination means receives five consecutive digital sampling data D(k), D(k-1 / 2), D(k-1), D(k-3 / 2), and D(k-2), and uses the five digital sampling data when D(k-1 / 2) and D(k-3 / 2) are approximately identical to determine whether the frequency of the received clock is higher or lower than the frequency of the transmitted clock. The receiving clock recovery device described in Appendix 1.

[0069] (Note 5) The determination means determines whether the frequency of the receiving clock is higher or lower than the frequency of the transmitting clock based on the sign of the value of D(k-1 / 2)*{D(k)-D(k-1)} and / or the sign of the value of D(k-3 / 2)*{D(k-1)-D(k-2)}. The receiving clock recovery device described in Appendix 4.

[0070] (Note 6) The determination means determines that the frequency of the receiving clock is higher than the frequency of the transmitting clock if the value of D(k-1 / 2)*{D(k)-D(k-1)} is negative, and determines that the frequency of the receiving clock is lower than the frequency of the transmitting clock if the value is positive. A received clock recovery device as described in any one of the items 3 to 5 of the appendix.

[0071] (Note 7) The determination means determines that the frequency of the receiving clock is higher than the frequency of the transmitting clock if the value of D(k-3 / 2)*{D(k-1)-D(k-2)} is positive, and determines that the frequency of the receiving clock is lower than the frequency of the transmitting clock if the value is negative. A received clock recovery device as described in any one of the items 3 to 5 of the appendix.

[0072] (Note 8) The determination means sets the determination value to +1 when it is determined to be high and -1 when it is determined to be low, and outputs a value obtained by multiplying the square of the value of D(k-1 / 2)*{D(k)-D(k-1)} by the determination value as the phase error value. The correction means corrects the phase difference of the received clock with respect to the transmitted clock using the phase error value. The receiving clock recovery device described in Appendix 6.

[0073] (Note 9) A receiver equipped with a receive clock recovery device as described in any one of the appendices 1 to 7.

[0074] (Note 11) The input signal is sampled with a sampling frequency determined based on the received clock, and a series of digital sampled data D(k-1 / 2), D(k-1), D(k-3 / 2) are input. When D(k-1 / 2) and D(k-3 / 2) are approximately the same, the values ​​of D(k-1 / 2), D(k-1), and D(k-3 / 2) are used to determine whether the frequency of the received clock is higher or lower than that of the transmitted clock. The phase difference between the transmitted clock and the received clock is corrected using the determination result. A method for recovering the received clock of a received clock recovery device, including the following.

[0075] (Note 12) If the values ​​of D(k-1 / 2), D(k-1), and D(k-3 / 2) are all positive or all negative, it is determined that the frequency of the receiving clock is higher than that of the transmitting clock; otherwise, it is determined that the frequency of the receiving clock is lower than that of the transmitting clock. The received clock recovery method described in Appendix 11.

[0076] (Note 13) Four consecutive digital sampling data sets D(k), D(k-1 / 2), D(k-1), D(k-3 / 2) or D(k-1 / 2), D(k-1), D(k-3 / 2), D(k-2) are input, and the frequency of the received clock relative to the transmitted clock is determined using the four digital sampling data sets when D(k-1 / 2) and D(k-3 / 2) are approximately identical. Determination means, The received clock recovery method described in Appendix 11.

[0077] (Note 14) Five consecutive digital sampling data sets D(k), D(k-1 / 2), D(k-1), D(k-3 / 2), and D(k-2) are input, and the frequency of the received clock relative to the transmitted clock is determined using the five digital sampling data sets where D(k-1 / 2) and D(k-3 / 2) are approximately identical. The received clock recovery method described in Appendix 11.

[0078] (Note 15) Based on the sign of the value of D(k-1 / 2)*{D(k)-D(k-1)} and / or the sign of the value of D(k-3 / 2)*{D(k-1)-D(k-2)}, the frequency of the received clock relative to the transmitted clock is determined. The received clock recovery method described in Appendix 14.

[0079] (Note 16) If the value of D(k-1 / 2)*{D(k)-D(k-1)} is negative, it is determined that the frequency of the receiving clock is higher than that of the transmitting clock; if it is positive, it is determined that the frequency of the receiving clock is lower than that of the transmitting clock. The received clock recovery method described in any one of the appendices 13 to 15.

[0080] (Note 17) If the value of D(k-3 / 2)*{D(k-1)―D(k-2)} is positive, it is determined that the frequency of the receiving clock is higher than that of the transmitting clock; if it is negative, it is determined that the frequency of the receiving clock is lower than that of the transmitting clock. The received clock recovery method described in any one of the appendices 13 to 15.

[0081] (Note 18) If the value is determined to be high, the judgment value is set to +1, and if it is determined to be low, the judgment value is set to -1. The value obtained by multiplying the square of the value of D(k-1 / 2)*{D(k)-D(k-1)} by the judgment value is output as the phase error value. The phase difference between the received clock and the transmitted clock is corrected using the aforementioned phase error value. The receive clock recovery method described in Appendix 16. [Explanation of Symbols]

[0082] 100 Transmitters 101 Transmitting Clock Section 102 Frame generation unit 103 Signal generation unit 104 Optical Coherent Transmitter 121 Power line communication transceiver 122 Communication Content Verification Unit 200 Receiver 201 Optical Coherent Receiver 202 ADC section 203 Equalization section 204 Polarization Separation Unit 205 Frequency Offset Compensation Section 206 Phase offset compensation section 207 Decoding section 208 Received Clock Generation Unit 300 Clock phase detection unit 301,302 T delay section 303,304 T / 2 delay section 304 to DCP2 delay section 305,306 Addition section 307, 308, 309 Multiplication part 310 Judgment section 311 Squared section 320 Phase Error Calculation Unit 321 Phase Error Calculation Unit 322 Phase Error Calculation Unit 323 Phase Error Calculation Unit 400 PID control unit 401,402 Addition section 403 Filter section 404 Differential D Control Section 405 Integral I Control Unit 406, 407, 408 Multiplication part 409 Control Value Generation Unit

Claims

1. A determination means that inputs consecutive digital sampling data D(k-1 / 2), D(k-1), and D(k-3 / 2) sampled at a sampling frequency determined based on the received clock in relation to the input signal, and uses D(k-1 / 2), D(k-1), and D(k-3 / 2) when D(k-1 / 2) and D(k-3 / 2) are approximately the same to determine whether the frequency of the received clock is higher or lower than the frequency of the transmitted clock, A correction means for correcting the phase difference of the received clock with respect to the transmitted clock using the determination result of the determination means, A receiving clock recovery device equipped with the following features.

2. The determination means determines that the frequency of the receiving clock is higher than the frequency of the transmitting clock if the values ​​of D(k-1 / 2), D(k-1), and D(k-3 / 2) are all positive or all negative, and determines that the frequency of the receiving clock is lower than the frequency of the transmitting clock in all other cases. The received clock recovery device according to claim 1.

3. The determination means receives four consecutive digital sampling data D(k), D(k-1 / 2), D(k-1), D(k-3 / 2) or D(k-1 / 2), D(k-1), D(k-3 / 2), D(k-2) as input, and uses the four digital sampling data when D(k-1 / 2) and D(k-3 / 2) are approximately identical to determine whether the frequency of the received clock is higher or lower than the frequency of the transmitted clock. The received clock recovery device according to claim 1.

4. The determination means receives five consecutive digital sampling data D(k), D(k-1 / 2), D(k-1), D(k-3 / 2), and D(k-2) as input, and uses the five digital sampling data when D(k-1 / 2) and D(k-3 / 2) are approximately identical to determine whether the frequency of the received clock is higher or lower than the frequency of the transmitted clock. The received clock recovery device according to claim 1.

5. The determination means determines whether the frequency of the receiving clock is higher or lower than the frequency of the transmitting clock based on the sign of the value of D(k-1 / 2) * {D(k) - D(k-1)} and / or the sign of the value of D(k-3 / 2) * {D(k-1) - D(k-2)}. The received clock recovery device according to claim 4.

6. The determination means determines that the frequency of the receiving clock is higher than the frequency of the transmitting clock if the value of D(k-1 / 2)*{D(k)-D(k-1)} is negative, and determines that the frequency of the receiving clock is lower than the frequency of the transmitting clock if the value is positive. A received clock recovery device according to any one of claims 3 to 5.

7. The determination means determines that the frequency of the receiving clock is higher than the frequency of the transmitting clock if the value of D(k-3 / 2)*{D(k-1)-D(k-2)} is positive, and determines that the frequency of the receiving clock is lower than the frequency of the transmitting clock if the value is negative. A received clock recovery device according to any one of claims 3 to 5.

8. The determination means sets the determination value to +1 when it is determined to be high and -1 when it is determined to be low, and outputs a value obtained by multiplying the square of the value of D(k-1 / 2)*{D(k)-D(k-1)} by the determination value as the phase error value. The correction means corrects the phase difference of the received clock with respect to the transmitted clock using the phase error value. The received clock recovery device according to claim 6.

9. A receiver comprising a receive clock recovery device according to any one of claims 1 to 5.

10. The input signal is sampled at a sampling frequency determined based on the received clock, and a series of digital sampled data D(k-1 / 2), D(k-1), and D(k-3 / 2) are input. When D(k-1 / 2) and D(k-3 / 2) are approximately the same, the values ​​of D(k-1 / 2), D(k-1), and D(k-3 / 2) are used to determine whether the frequency of the received clock is higher or lower than that of the transmitted clock. The phase difference between the received clock and the transmitted clock is corrected using the determination result. A method for recovering the received clock of a received clock recovery device, including the following.

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