Semiconductor memory device and method for manufacturing a semiconductor memory device

Abstract

Activating impurities in the source wire. [Solution] The semiconductor memory device of the embodiment comprises a laminate in which a plurality of first conductive layers and a plurality of first insulating layers are alternately stacked one layer at a time; a pillar extending within the laminate in the stacking direction of the laminate and including a semiconductor layer having an upper end protruding from the laminate; a plate-like portion adjacent to the pillar, extending within the laminate in a first direction intersecting the stacking direction and the stacking direction, and including a second conductive layer having an upper end protruding from the laminate; and a first layer positioned above the laminate, covering the upper end of the semiconductor layer and the upper end of the plate-like portion, and mainly composed of a semiconductor, wherein the plate-like portion has a void at its upper end.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device and a method of manufacturing a semiconductor memory device. Background Art

[0002] In a semiconductor memory device such as a three-dimensional nonvolatile memory, pillars penetrating through a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked are formed. In this process, laser light or the like may be irradiated from above the semiconductor memory device to activate impurities in the source line connected to the upper end portions of the pillars. However, impurities in the source line may not be sufficiently activated around the pillars adjacent to other members or the like. Prior Art Documents Patent Documents

[0003] Patent Document 1 United States Patent Application Publication No. 2021 / 217768 Patent Document 2 Japanese Unexamined Patent Publication No. 2023-510877 Summary of Invention Problem to be Solved by Invention

[0004] An object of one embodiment is to provide a semiconductor memory device capable of activating impurities in a source line and a method of manufacturing the semiconductor memory device. Means for Solving the Problem

[0005] The semiconductor memory device of the embodiment comprises: a laminate in which a plurality of first conductive layers and a plurality of first insulating layers are alternately stacked one layer at a time; a pillar extending within the laminate in the stacking direction of the laminate and including a semiconductor layer having an upper end protruding from the laminate; a plate-like portion adjacent to the pillar, extending within the laminate in a first direction intersecting the stacking direction and the stacking direction, and including a second conductive layer having an upper end protruding from the laminate; and a first layer disposed above the laminate, covering the upper end of the semiconductor layer and the upper end of the plate-like portion, and mainly composed of a semiconductor, wherein the plate-like portion has a void at its upper end. [Brief explanation of the drawing]

[0006] [Figure 1] A diagram showing a schematic configuration example of a semiconductor memory device according to an embodiment. [Figure 2] A cross-sectional view showing an example of the configuration of a semiconductor memory device according to the embodiment. [Figure 3] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 4] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 5] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 6] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 7] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 8] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 9] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 10] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 11] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 12] A diagram sequentially illustrating part of the steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 13] A diagram sequentially illustrating part of the steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 14] A diagram sequentially illustrating part of the steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 15] A diagram illustrating a method for forming a source line of a semiconductor memory device according to a comparative example. [Figure 16] A diagram sequentially illustrating part of the steps of a method for manufacturing a semiconductor memory device according to Modification 1 of the embodiment. [Figure 17] A diagram sequentially illustrating part of the steps of a method for manufacturing a semiconductor memory device according to Modification 1 of the embodiment. [Figure 18] A diagram sequentially illustrating part of the steps of a method for manufacturing a semiconductor memory device according to Modification 1 of the embodiment. [Figure 19] A diagram sequentially illustrating part of the steps of a method for manufacturing a semiconductor memory device according to Modification 1 of the embodiment. [Figure 20] A diagram sequentially illustrating part of the steps of a method for manufacturing a semiconductor memory device according to Modification 2 of the embodiment. [Figure 21] A diagram sequentially illustrating part of the steps of a method for manufacturing a semiconductor memory device according to Modification 2 of the embodiment. [Figure 22] A diagram sequentially illustrating part of the steps of a method for manufacturing a semiconductor memory device according to Modification 2 of the embodiment. [Figure 23] A cross-sectional view illustrating an example configuration of a semiconductor memory device according to Modification 3 of the embodiment. [Figure 24] A diagram sequentially illustrating part of the steps of a method for manufacturing a semiconductor device according to Modification 3 of the embodiment. [Figure 25] A diagram sequentially illustrating part of the steps of a method for manufacturing a semiconductor device according to Modification 3 of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiments. In addition, constituent elements in the following embodiments include those that can be easily conceived by those skilled in the art or those that are substantially the same.

[0008] (Configuration Example of Semiconductor Memory Device) FIG. 1 is a diagram showing a schematic configuration example of a semiconductor memory device 1 according to an embodiment. More specifically, FIG. 1(a) is a cross-sectional view taken along the X direction of the semiconductor memory device 1, and FIG. 1(b) is a schematic plan view showing the layout of the semiconductor memory device 1.

[0009] However, hatching is omitted in FIG. 1(a) in consideration of the visibility of the drawing. In addition, in FIG. 1(a), components that do not necessarily exist in the same cross section are shown, and some upper-layer wirings and the like are omitted.

[0010] In addition, in this specification, both the X direction and the Y direction are directions along the surface orientation of a word line WL, and the X direction and the Y direction are orthogonal to each other. The electrical lead-out direction of the word line WL may be referred to as a first direction, and this first direction is a direction along the X direction. A direction intersecting the first direction may be referred to as a second direction, and this second direction is a direction along the Y direction. However, since the semiconductor memory device 1 may include manufacturing errors, the first direction and the second direction are not necessarily orthogonal to each other.

[0011] As shown in FIG. 1(a), the semiconductor memory device 1 includes, in order from the lower side of the drawing, a semiconductor substrate SB, a peripheral circuit CBA, one or more select gate lines SGD, a plurality of word lines WL, one or more select gate lines SGS, a source line SL, an electrode film EL, and the like.

[0012] In this specification, the side where the source line SL is arranged with respect to the plurality of word lines WL and select gate lines SGD, SGS is defined as the upper side of the semiconductor memory device 1. That is, the source side of the semiconductor memory device 1 is the upper side, and the drain side is the lower side.

[0013] The semiconductor substrate SB is, for example, a silicon substrate. Peripheral circuits CBA, including transistors TR and wiring, are arranged on the surface of the semiconductor substrate SB, and the entire surface is covered with an insulating layer 40. Above the semiconductor substrate SB on which the peripheral circuits CBA are arranged, multiple word lines WL and selection gate lines SGD, SGS, which are entirely covered with an insulating layer 50, are arranged.

[0014] As shown in Figures 1(a) and 1(b), a memory area MR is located in the center of multiple word lines WL in the X direction, and stepped areas SR are located at both ends of the multiple word lines WL in the X direction. These memory areas MR and stepped areas SR are divided into multiple regions by multiple plate-shaped contacts LI that penetrate the multiple word lines WL and extend in a direction along the X direction.

[0015] Furthermore, the area located between adjacent plate-shaped contacts LI in the Y direction, and including the memory area MR and the step area SR, is called the block area BLK. As will be described later, the memory area MR contains multiple memory cells that hold data non-volatilely, and the block area BLK described above serves as the unit for erasing this data.

[0016] Furthermore, between adjacent plate-shaped contacts LI in the Y direction, multiple isolation layers SHE are arranged, extending in the direction along the X direction and penetrating the selected gate line SGD. These multiple isolation layers SHE extend in the direction along the X direction throughout the entire memory area MR, and also reach a portion of the stepped area SR at both ends in the X direction.

[0017] Multiple pillars PL are arranged in the memory area MR. The multiple pillars PL penetrate multiple word lines WL and selection gate lines SGD, SGS, with one end protruding into the source line SL.

[0018] A metal layer TS is positioned further above the source wire SL. Above the metal layer TS, an electrode film EL is positioned via an insulating layer 60. The electrode film EL is entirely covered by an insulating layer 70, except for the pad region PD located in the peripheral region PR, which is located outside the X direction of the word wire WL, etc. The insulating layer 70 has a structure in which layers such as a silicon oxide layer, a silicon nitride layer, and a polyimide layer are stacked from the bottom.

[0019] The electrode film EL is connected to the source wire SL and the through-contact C3 by a plug PG or the like that penetrates the insulating layer 60. The through-contact C3 is provided in the peripheral region PR and penetrates the insulating layer 50 that covers the word WL and the like, and the insulating layer 40 that covers the peripheral circuit CBA, and is connected to the semiconductor substrate SB on which the peripheral circuit CBA is located.

[0020] From outside the semiconductor memory device 1, the semiconductor substrate SB is controlled to a predetermined potential via the pad area PD and through-contact C3. Furthermore, power and signals from the outside are supplied to the semiconductor memory device 1 via the pad area PD.

[0021] Multiple memory cells are formed at the intersection of the pillar PL and the word line WL. As a result, the semiconductor memory device 1 is configured as a three-dimensional non-volatile memory in which memory cells are arranged three-dimensionally in the memory region MR, for example.

[0022] In the stepped region SR, there is a stepped section SP where multiple word lines WL and selection gate lines SGD and SGS are processed in a stepped manner and terminated. The aforementioned isolation layer SHE extends from the memory region MR to the portion of the stepped region SR where the selection gate line SGD is processed in a stepped manner. As a result, within a single block region BLK, the selection gate line SGD is separated into multiple regions. In other words, the isolation layer SHE penetrates the portion below the multiple word lines WL, thereby dividing these portions into multiple patterns of selection gate line SGD.

[0023] Each terrace section, composed of multiple word lines WL and select gate lines SGD and SGS, has a contact CC that extends upward through the insulating layer 50 and connects to the word lines WL and select gate lines SGD and SGS of each layer.

[0024] In word lines WL and select gate lines SGS, one contact CC is connected per layer. In select gate lines SGD, one contact CC is connected per layer, for each section separated by the isolation layer SHE.

[0025] Here, within a single block region BLK, multiple contacts CC are positioned on one side of the stair regions SR on either side in the X direction. Also, looking at one side in the X direction, for example, multiple contacts CC are positioned every two block regions BLK.

[0026] In other words, in the example shown in Figure 1(b), in the block region BLK at the very top of the page, multiple contact CCs are located in the stair region SR on the left side of the page, among the stair regions SR at both ends in the X direction. Furthermore, in the block region BLK one level below and two levels below the above block region BLK, multiple contact CCs are located in the stair region SR on the right side of the page, among the stair regions SR at both ends in the X direction. Moreover, in the block region BLK at the very bottom of the page, multiple contact CCs are again located in the stair region SR on the left side of the page.

[0027] Therefore, as shown in Figure 1(a), the respective contact CCs of the stair region SR at both ends in the X direction belong to different block regions BLK and are not actually located in the same cross-section.

[0028] These contact CCs allow individual stacked word lines WLs to be drawn out. More specifically, these contact CCs apply write voltages and read voltages to memory cells included in the memory region MR at the center of multiple word lines WLs, via word lines WLs located at the same height as the memory cells.

[0029] In this embodiment, the semiconductor memory device 1 is constructed by bonding together an insulating layer 40 covering the peripheral circuit CBA and an insulating layer 50 covering the word lines WL, etc. Thus, the insulating layers 40 and 50 function as bonding layers. Furthermore, by bonding the insulating layers 40 and 50, the electrode pads placed on the surfaces of these insulating layers 40 and 50 are connected to each other, thereby electrically connecting the peripheral circuit CBA, the contact CC, the multiple word lines WL and the selection gate lines SGS, SGD, and the pillar PL.

[0030] The application of a predetermined voltage from contact CC to the memory cell is controlled by the peripheral circuit CBA, which is electrically connected to these components. In this way, the peripheral circuit CBA controls the electrical operation of the memory cell.

[0031] Next, a detailed example of the configuration of the semiconductor memory device 1 will be described using Figure 2. Figure 2 is a cross-sectional view showing an example of the configuration of the semiconductor memory device 1 according to the embodiment.

[0032] More specifically, Figure 2(a) is a cross-sectional view along the Y direction in the memory region MR of the semiconductor memory device 1. In Figure 2(a), the structure above the insulating layer 60 and below the insulating layer 52, which will be described later, are omitted.

[0033] Figure 2(b) is an enlarged cross-sectional view of pillar PL at the height of word line WL. Figure 2(c) is an enlarged cross-sectional view of pillar PL at the height of selected gate lines SGD and SGS.

[0034] As shown in Figure 2(a), below the insulating layer 60, in order from the side of the insulating layer 60, are the metal layer TS, the barrier metal layer BM, and the source wires SLa and SLp.

[0035] The insulating layer 60 is, for example, a silicon oxide layer. The metal layer TS is, for example, a tungsten layer, and functions as the source wire metal of the semiconductor memory device 1 in addition to the source wires SLa and SLp below. The barrier metal layer BM is, for example, at least one of a titanium layer, a titanium nitride layer, a tantalum layer, or a tantalum nitride layer, and suppresses the diffusion of tungsten atoms from the metal layer TS to the surrounding components.

[0036] The source lines SLa and SLp are, for example, polycrystalline semiconductor layers such as polysilicon layers, and are doped with N-type impurities containing at least one of arsenic or phosphorus. In addition to functioning as a source line, the source line SLp also functions as a stopper layer during pillar PL formation in the manufacturing process of the semiconductor memory device 1 described later.

[0037] Below the source wire SLp, a laminate LM is arranged, in which multiple word wires WL and multiple insulating layers OL are alternately stacked one layer at a time. The laminate LM consists of a laminate LMa located below the source wire SLp and a laminate LMb located further below the laminate LMa.

[0038] The LMa laminate has selection gate lines SGS1 and SGS0 above the uppermost word line WL, starting from the source line SLp side. These selection gate lines SGS1 and SGS0 are the selection gate lines on the source side.

[0039] The laminate LMb has selection gate lines SGD1 and SGD0 located below the bottommost word line WL, starting from the bottommost word line WL side. These selection gate lines SGD1 and SGD0 are the drain-side selection gate lines.

[0040] However, the number of word line WL and selective gate line SGS,SGD layers included in the laminate LM is arbitrary. Therefore, the laminate LM may have one or more selective gate lines SGS,SGD each, or three or more each. The multiple word line WL and selective gate lines SGS,SGD may be, for example, tungsten layers or molybdenum layers, and the multiple insulating layers OL may be, for example, silicon oxide layers.

[0041] Below the laminate LM, insulating layers 52 and 53 are arranged in order from the LM side. These insulating layers 52 and 53 constitute a part of the insulating layer 50 (see Figure 1(a)) described above.

[0042] As described above, the multiple plate-shaped contacts LI extend in directions along the lamination direction and the X direction of the laminate LM. More specifically, the plate-shaped contacts LI penetrate the laminate LM and the source wire SLp. The source wire SLa above the source wire SLp covers the upper end of the plate-shaped contact LI extending above the source wire SLp with approximately equal thickness. As a result, the upper surface of the source wire SLa may have irregularities in accordance with the shape of the upper end of the plate-shaped contact LI.

[0043] Each of these plate-shaped contacts LI has a conductive layer 24, such as a tungsten layer, and insulating layers 54n and 54 that cover the side walls of the conductive layer 24 in order from the conductive layer 24 side. The insulating layer 54 also covers the upper end of the conductive layer 24 that protrudes into the source wire SLa. Furthermore, the conductive layer 24, which is positioned between the insulating layers 54n and 54 and serves as the core material of the plate-shaped contact LI, contains a void VD at its upper end. In other words, the void VD at the upper end of the plate-shaped contact LI is covered on its side walls and upper surface by the conductive layer 24 and the insulating layer 54 in that order.

[0044] The insulating layer 54 is, for example, a silicon oxide layer. The insulating layer 54n is an insulating layer containing a different material from the insulating layer 54 and has etching selectivity with respect to the insulating layer 54. As an example, the insulating layer 54n is a silicon nitride layer. The conductive layer 24 is, for example, a tungsten layer.

[0045] Furthermore, the plate-shaped contact LI may have a tapered shape in which its width in the Y direction increases from the upper end to the lower end, for example. Alternatively, the plate-shaped contact LI may have a bowing shape in which its width in the Y direction is maximum at a predetermined position between the upper end and the lower end.

[0046] Among the multiple plate-shaped contacts LI, one or more isolation layers SHE extend along the X-direction to the lower part of the laminate LM between adjacent plate-shaped contacts LI in the Y-direction. In the example shown in Figure 2(a), the isolation layer SHE penetrates the aforementioned selection gate lines SGD0 and SGD1 and reaches the insulating layer OL adjacent to the selection gate line SGD1 in the lamination direction. As a result, the selection gate lines SGD0 and SGD1 are divided into multiple sections.

[0047] Furthermore, between adjacent plate-shaped contacts LI in the Y direction, multiple pillars PL extend through the laminate LM in the stacking direction. More specifically, these pillars PL extend from the bottom insulating layer OL of the laminate LM through the laminate LM in the stacking direction, penetrating the laminate LM and the source wire SLp. As a result, of the channel layer CN and memory layer ME that constitute the pillar PL, the channel layer CN protrudes above the source wire SLp.

[0048] The source line SLa above the source line SLp covers the upper end of the channel layer CN, which is part of the pillar PL extending above the source line SLp, with approximately equal thickness. As a result, the upper surface of the source line SLa may have irregularities that conform to the shape of the upper end of the channel layer CN of the pillar PL.

[0049] Furthermore, the barrier metal layer BM, which is positioned even higher above the source line SLa, also extends along the upper end of the channel layer CN of the plate-shaped contact LI and pillar PL mentioned above, via the source line SLa.

[0050] Multiple pillars PL are arranged, for example, in a staggered pattern when viewed from the stacking direction of the laminate LM. Each pillar PL has a cross-sectional shape in the direction along the layering direction of the laminate LM, i.e., along the XY plane, such as a circular, elliptical, or oval shape.

[0051] Furthermore, the pillar PL has a tapered shape in the portion that penetrates the laminate LMa and the portion that penetrates the laminate LMb, where the diameter and cross-sectional area increase from the upper layer side to the lower layer side. Alternatively, the pillar PL has a bowing shape in the portion that penetrates the laminate LMa and the portion that penetrates the laminate LMb, where the diameter and cross-sectional area are maximized at a predetermined position between the upper layer side and the lower layer side.

[0052] Furthermore, the pillar PL comprises a core layer CR which serves as the core material, a channel layer CN which covers the sidewalls of the core layer CR, a memory layer ME which covers the sidewalls of the channel layer CN, and a cap layer CP which is positioned at the lower end of the pillar PL.

[0053] Of these core layer CR, channel layer CN, and memory layer ME, the memory layer ME penetrates the stack LM and source line SLp. Furthermore, the core layer CR and channel layer CN penetrate the stack LM and source line SLp, and their upper ends protrude into the source line SLa.

[0054] In other words, the portion of the channel layer CN that protrudes into the source line SLa is not covered by the memory layer ME, and the channel layer CN is in direct contact with the source line SLa. As a result, the channel layer CN is electrically connected to the metal layer TS via the source line SLa.

[0055] The cap layer CP, located at the lower end of pillar PL, connects the channel layer CN to the plug CH, which extends through the bottom insulating layer OL of the laminate LM and the insulating layer 52 below it. The plug CH connects the bit wire BL, located in the insulating layer 53, to pillar PL, located in the laminate LM. The bit wire BL extends downward along the Y direction so as to intersect with the drawing direction of the word wire WL.

[0056] As shown in Figures 2(b) and 2(c), the memory layer ME has a stacked structure including a block insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN, in that order from the outer periphery of the pillar PL. The charge storage layer CT of the memory layer ME is, for example, a silicon nitride layer. The block insulating layer BK, the tunnel insulating layer TN, and the core layer CR of the memory layer ME are, for example, silicon oxide layers. The channel layer CN and the cap layer CP are, for example, polycrystalline semiconductor layers such as polysilicon layers.

[0057] Furthermore, at least the portion of the channel layer CN that protrudes into the source line SLa may contain N-type impurities of the same type as those doped into the source lines SLp and SLa, such as arsenic or phosphorus.

[0058] As shown in Figure 2(b), with the above configuration, memory cells MC are formed in the portions of the pillar PL side surface that face each word line WL. Data is written to and read from the memory cells MC by applying a predetermined voltage from the word line WL.

[0059] As shown in Figure 2(c), selection gate STD is formed on the side of pillar PL where it faces selection gate lines SGD0 and SGD1. Additionally, selection gate STS is formed on the side of pillar PL where it faces selection gate lines SGS0 and SGS1, which are lower than the word line WL.

[0060] By applying predetermined voltages to the selection gate lines SGD and SGS, respectively, the selection gates STD and STS can be turned on or off, thereby selecting or deselecting the memory cell MC of the pillar PL to which the selection gates STD and STS belong.

[0061] (Method of manufacturing semiconductor memory devices) Next, the manufacturing method of the semiconductor memory device 1 according to the embodiment will be described using Figures 3 to 14. Figures 3 to 14 are diagrams illustrating, in order, some of the steps of the manufacturing method of the semiconductor memory device 1 according to the embodiment. More specifically, Figures 3 to 14 show a cross-section along the Y direction of the region that will later become the memory region MR.

[0062] In the following explanation, the direction in which the side of the support substrate SS or semiconductor substrate SB, which will be described later, that undergoes various processing will be oriented will be considered the upper side of the semiconductor memory device 1 during manufacturing. In other words, the upper side of the drawing below is the upper side of the semiconductor memory device 1 during manufacturing, and the lower side of the drawing below is the lower side of the semiconductor memory device 1 during manufacturing.

[0063] As shown in Figure 3(a), a support substrate SS is prepared. As the support substrate SS, a semiconductor substrate such as a silicon substrate, an insulating substrate such as a ceramic substrate, or a conductive substrate can be used.

[0064] Subsequently, the components that will later become the source wire SL, the laminate LM, and the pillar PL are formed on the upper surface of the support substrate SS. These formation processes are carried out in a state where the vertical direction is reversed compared to the examples in Figures 1 and 2 described above.

[0065] First, an insulating layer 51 and a semiconductor layer TSC are formed on the support substrate SS in that order. The semiconductor layer TSC is a polycrystalline semiconductor layer such as an undoped polysilicon layer, and a portion of it will later become the source line SLp.

[0066] Furthermore, a laminate LMsa is formed on the semiconductor layer TSC by alternately stacking multiple insulating layers NL and multiple insulating layers OL one layer at a time. The insulating layer NL is, for example, a silicon nitride layer and functions as a sacrificial layer that will later be replaced by a conductive material to become a word line WL or a selected gate line SGS.

[0067] Although not shown in the diagram, in a portion of the laminated LMsa, the insulating layer NL and insulating layer OL are processed in a stepped manner. This processing can be achieved by repeatedly slimming the mask pattern of the photoresist layer, etc., and etching the insulating layer NL and insulating layer OL of the laminated LMsa.

[0068] Specifically, a mask pattern is formed on the upper surface of the laminated LMsa, and the insulating layer NL and insulating layer OL in the exposed areas are etched away one layer at a time. Then, the edges of the mask pattern are receded by treatment with oxygen plasma or the like, exposing the upper surface of the laminated LMsa, and the insulating layer NL and insulating layer OL are etched away one layer at a time again. By repeating this process multiple times, a laminated LMsa with a stepped shape at both ends in the X direction is formed.

[0069] Subsequently, the stepped shape at both ends in the X direction is covered with a portion of the insulating layer 50 (see Figure 1(a)) described above.

[0070] As shown in Figure 3(b), multiple memory holes MHa are formed in the stacked LMsa in the stacking direction. At this time, the semiconductor layer TSC below the stacked LMsa functions as a stopper layer. Therefore, the multiple memory holes MHa penetrate the stacked LMsa and reach a predetermined depth in the semiconductor layer TSC. These memory holes MHa are the portions that later penetrate the stacked LMa of the pillar PL.

[0071] As shown in Figure 3(c), these memory holes MHa are filled with a sacrificial layer 26 such as a CVD-carbon layer. This forms a pillar PLc in which multiple memory holes MHa are filled with the sacrificial layer 26.

[0072] As shown in Figure 4(a), the laminate LMsa is covered, and a laminate LMsb is formed by alternately stacking multiple insulating layers NL and multiple insulating layers OL one layer at a time. The insulating layers NL of the laminate LMsb function as sacrificial layers that are later replaced by conductive layers to become word lines WL or selected gate lines SGD.

[0073] Although not shown in the diagram, a portion of the laminate LMsb is processed in a stepwise manner, altering the insulating layer NL and insulating layer OL. This processing can be achieved by repeatedly performing the same steps as the processing for the laminate LMsa described above: slimming the mask pattern of the photoresist layer, etc., and etching the insulating layer NL and insulating layer OL of the laminate LMsb.

[0074] At this time, the uppermost step of the stair section formed on the laminated LMsa and the lowermost step of the stair section formed on the laminated LMsb are brought into close proximity to form a stair shape that extends continuously from the lower layer of the laminated LMsa to the upper layer of the laminated LMsb. As a result, the laminated LMsa and LMsb are formed with a stair region SR having a stair shape extending from the laminated LMsa to the laminated LMsb, with the stair region SR formed at both ends in the X direction.

[0075] Subsequently, the stepped shape at both ends in the X direction is further covered with a portion of the insulating layer 50 (see Figure 1(a)) described above.

[0076] As shown in Figure 4(b), multiple memory holes MHb are formed that penetrate the laminate LMsb and connect to multiple pillars PLc that have already been formed within the laminate LMsa. The memory holes MHb are the parts of pillar PL that will later penetrate the laminate LMb.

[0077] As shown in Figure 5(a), the sacrificial layer 26 is removed from the pillar PLc at the bottom of the memory hole MHb. As a result, multiple memory holes MH are formed, each with a memory hole MHa opening at the bottom of multiple memory holes MHb, penetrating the laminates LMsb and LMsa and reaching a predetermined depth of the source wire SL.

[0078] Furthermore, if the sacrificial layer 26 filled inside the pillar PLc is a CVD-carbon layer or the like, the sacrificial layer 26 can be removed from these pillar PLc all at once when the mask pattern used to form the memory holes MHb in Figure 4(b) above is removed by ashing using oxygen plasma or the like.

[0079] As shown in Figure 5(b), a memory layer ME is formed on the sidewall and bottom surface of the memory hole MH, in the order of block insulating layer BK, charge storage layer CT, and tunnel insulating layer TN (see Figures 2(b) and 2(c)), starting from the sidewall side of the memory hole MH. The memory layer ME is also formed on the top surface of the laminate LMsb.

[0080] Furthermore, the channel layer CN and core layer CR are formed in this order within the memory hole MH via the memory layer ME. As a result, the channel layer CN is formed on the memory layer ME that covers the sides and bottom of the memory hole MH, and the core layer CR fills the center of the memory hole MH. The channel layer CN and core layer CR are also formed in this order on the upper surface of the laminate LMsb via the memory layer ME.

[0081] Furthermore, the channel layer CN at this point is not doped with impurities and may be in an amorphous state, such as an amorphous silicon layer.

[0082] As shown in Figure 6(a), the core layer CR, channel layer CN, and memory layer ME formed on the upper surface of the laminate LMsb are removed by etch-back along with a portion of the insulating layer OL of the uppermost layer of the laminate LMsb, and the core layer CR is recessed to a predetermined depth of the memory hole MH to form a depression DN at the upper end of the memory hole MH.

[0083] As shown in Figure 6(b), a cap layer CP is formed in the recess DN at the upper end of the memory hole MH. At this point, the cap layer CP may be in an amorphous state, such as an amorphous silicon layer.

[0084] As shown in Figure 7(a), the etch-back of the core layer CR, channel layer CN, and memory layer ME formed on the upper surface of the laminated LMsb increases the thickness of the insulating layer OL on the top layer of the laminated LMsb. This forms a pillar PL whose upper end is embedded in the insulating layer OL on the top layer of the laminated LMsb. However, at this point, the memory layer ME covers the channel layer CN at the lower end of the pillar PL.

[0085] As shown in Figure 7(b), a slit ST is formed that penetrates the laminates LMsb and LMsa and reaches a predetermined depth in the semiconductor layer TSC. The slit ST also extends along the X direction within the laminates LMsa and LMsb.

[0086] As shown in Figure 8(a), a solvent for removing the insulating layer NL, such as thermal phosphoric acid, is introduced into the laminates LMsa and LMsb through the slit ST to remove the insulating layer NL of the laminates LMsa and LMsb. This forms laminates LMga and LMgb having multiple gap layers GP from which the insulating layer NL between insulating layers OL has been removed.

[0087] Laminates LMga and LMgb, which contain multiple gap layers GP, have a fragile structure. Multiple pillars PL support these fragile laminates LMga and LMgb. This prevents the insulating layer OL remaining in the laminate from bending, and prevents the laminate LMga and LMgb from deforming or collapsing.

[0088] As shown in Figure 8(b), a conductive material raw material gas, such as tungsten or molybdenum, is injected into the interior of the laminates LMga and LMgb through the slit ST, and the gap layer GP of the laminates LMga and LMgb is filled with the conductive material to form multiple word lines WL, etc. This forms a laminate LM containing laminates LMa and LMb, in which multiple word lines WL, etc. and multiple insulating layers OL are alternately stacked one layer at a time.

[0089] As described above, the process of forming the word line WL from the insulating layer NL is also called the replacement process.

[0090] As shown in Figure 9(a), an insulating layer 54 is formed to cover the side walls and bottom surface of the slit ST. At this time, the insulating layer 54 is formed to be thicker than the insulating layer 54 that will ultimately be present in the semiconductor memory device 1.

[0091] As shown in Figure 9(b), the insulating layer 54 covering the sidewall of the slit ST is reduced in thickness to a predetermined thickness. This process can be carried out, for example, by dry etching using isotropic conditions. As a result, an insulating layer 54 is formed in which the portion covering the bottom surface of the slit ST is thickened. At this time, it is preferable that the upper surface of the insulating layer 54 on the bottom surface of the slit ST is located below the height of the word line WL of the lowest layer in the subsequent laminate LMa, and that the insulating layer 54 on the bottom surface of the slit ST has a thickness such that it reaches, for example, the bottom surface of the laminate LMsa.

[0092] As shown in Figure 10(a), an insulating layer 54n is formed to cover the side walls and bottom surface of the slit ST via the insulating layer 54.

[0093] As shown in Figure 10(b), the insulating layer 54n at the bottom of the slit ST is removed by dry etching or the like, partially exposing the insulating layer 54.

[0094] As shown in Figure 11(a), while maintaining the selectivity ratio with the insulating layer 54n, the insulating layer 54 exposed at the lower end of the insulating layer 54n is removed by wet etching or the like to form a void VD at the lower end of the slit ST. At this time, the wet etching conditions are adjusted so that the side walls and bottom surface of the void VD are covered with the insulating layer 54 without completely removing the insulating layer 54 in the void VD portion.

[0095] Furthermore, if the insulating layer 54 is a silicon oxide layer and the insulating layer 54n is a silicon nitride layer, diluted hydrofluoric acid (DHF: Dolute Hydrogen Fluoride) or the like can be used as the wet etching solution.

[0096] As described above, the thickness of the insulating layer 54 at the bottom of the slit ST is adjusted so that it is located below the height of the word line WL of the lowermost layer of the later laminate LMa. Therefore, the void VD is also located below the height of the word line WL of the lowermost layer.

[0097] As shown in Figure 11(b), a conductive layer 24 is formed by filling the slit ST with a tungsten layer or the like. At this time, low coverage deposition conditions are used so that the void VD at the lower end of the slit ST is not filled.

[0098] As a result, a plate-shaped contact LI is formed.

[0099] As shown in Figure 12(a), a separation layer SHE is formed on the upper side of the laminate LM. More specifically, a groove is formed that penetrates one or more conductive layers, including the uppermost conductive layer of the laminate LMb, and an insulating layer 56 is filled into the groove, thereby forming a separation layer SHE that divides the conductive layer on the upper side of the laminate LM into a pattern of selected gate lines SGD.

[0100] Although not shown in the diagram, multiple contact points CC are formed from the upper side of the staircase area SR, reaching the word lines WL and selection gate lines SGD and SGS that constitute each step of the staircase structure of the staircase area SR.

[0101] As shown in Figure 12(b), after forming an insulating layer 52 covering the laminate LM, plugs CH are formed that penetrate the uppermost insulating layer OL of the laminate LM and the insulating layer 52, and are connected to the cap layer CP at the upper end of the pillar PL. In addition, an insulating layer 53 is formed to cover the insulating layer 52, and bit wires BL are formed in the insulating layer 53 to which the individual plugs CH are connected.

[0102] Furthermore, the plug CH and bit wire BL may be formed collectively, for example, by using a dual damascene method.

[0103] Although not shown in the diagram, a peripheral circuit CBA is formed on a semiconductor substrate SB, which is separate from the support substrate SS on which the laminate LM is formed, and is covered with an insulating layer 40. Contacts, vias, wiring, etc. are formed in the insulating layer 40 to bring the peripheral circuit CBA to the surface of the insulating layer 40 and connect to electrode pads etc. formed on the upper surface of the insulating layer 40.

[0104] Furthermore, the support substrate SS and the semiconductor substrate SB are bonded together using their respective insulating layers 50 and 40, and the electrode pads within the insulating layers 50 and 40 are connected. These insulating layers 50 and 40 can be bonded together by activating them beforehand, for example, through plasma treatment. Additionally, after bonding the insulating layers 54 and 40, annealing treatment can be performed to connect the electrode pads within the insulating layers 50 and 40 by Cu-Cu bonding or the like.

[0105] As shown in Figure 13(a), from this point onward, various processes are performed on the support substrate SS, which is bonded to the semiconductor substrate SB in an inverted state. Therefore, in the following drawings, the portions of the pillar PL and plate-shaped contact LI that protrude into the semiconductor layer TSC are considered as the upper ends, and the process is shown from the upper end side of these pillar PL and plate-shaped contact LI.

[0106] Note that in the following drawings, only the upper ends of the pillar PL and plate-shaped contact LI are shown.

[0107] As shown in Figure 13(b), the support substrate SS is removed by cracking the interface between the insulating layer 51 and the support substrate SS. Furthermore, the insulating layer 51 in the memory region MR where the pillar PL and the like are formed is removed, and the semiconductor layer TSC is removed while leaving a predetermined layer thickness. As a result, in the memory region MR, the upper ends of the pillar PL and plate-shaped contact LI protrude upward through the thinned semiconductor layer TSC.

[0108] Furthermore, the memory layer ME is removed from the portion of the pillar PL that protrudes above the semiconductor layer TSC. This exposes the upper end of the channel layer CN of the pillar PL above the semiconductor layer TSC. At this time, a portion of the insulating layer 54 of the plate-shaped contact LI may also be removed. However, since the insulating layer 54 is thicker than the memory layer ME, it will not be completely removed. When forming the insulating layer 54 in the process shown in Figure 9(a) above, a stopper layer such as a silicon nitride layer may be formed in the insulating layer 54 separately from the insulating layer 54n to protect the inner insulating layer 54.

[0109] As shown in Figure 13(c), the semiconductor layer TSC is sequentially subjected to implantation treatments, such as phosphorus, to dopage the semiconductor layer TSC with N-type impurities. At this time, the upper end of the channel layer CN may also be doped with impurities. By doping with impurities such as phosphorus, the entire semiconductor layer TSC and at least the upper end of the channel layer CN become amorphous semiconductor layers such as amorphous silicon layers.

[0110] As shown in Figure 13(d), a semiconductor layer AMR is formed over the semiconductor layer TSC. The semiconductor layer AMR is an amorphous semiconductor layer such as an amorphous silicon layer, and is formed to absorb laser light and be used as a heat source during the subsequent annealing process with laser light, and it will later become the source line SLa.

[0111] As shown in Figure 14(a), impurities such as arsenic are doped into the semiconductor layer AMR and the upper end of the channel layer CN of the pillar PL.

[0112] As shown in Figure 14(b), laser light is irradiated onto the semiconductor layer AMR and the upper end of the channel layer CN of the pillar PL. As the laser light to be irradiated, for example, a laser light with a wavelength of 540 nm, such as a green laser, can be used.

[0113] In this process, an amorphous semiconductor layer, such as the AMR semiconductor layer, absorbs laser light and functions as a heat source. As a result, the AMR semiconductor layer is heated by the laser light, and the heat from the AMR semiconductor layer is transferred to the TSC semiconductor layer, allowing the TSC semiconductor layer to be annealed. As described above, when using a laser light with a wavelength of 540 nm, the TSC semiconductor layer can be heated to, for example, approximately 1100°C.

[0114] This annealing process, utilizing the heat of laser light, allows the amorphous semiconductor layer TSC, which has been doped with impurities, to become polycrystalline, and also activates the N-type impurities doped into the semiconductor layer TSC. Furthermore, the heat from the semiconductor layer AMR is also transferred to the upper end of the channel layer CN of the pillar PL, causing the amorphous channel layer CN and the originally amorphous semiconductor layer AMR to also become polycrystalline.

[0115] As a result, source lines SLp and SLa, which are N-doped polysilicon layers, are formed from the semiconductor layers TSC and AMR, respectively.

[0116] As shown in Figure 14(c), a barrier metal layer BM is formed to cover the source wire SLa.

[0117] As shown in Figure 14(d), a metal layer TS is formed to cover the barrier metal layer BM.

[0118] Subsequently, an insulating layer 60 is formed on the metal layer TS, and a plug PG is formed that penetrates the insulating layer 60. An electrode film EL is also formed in the insulating layer 60 and connected to the plug PG, and an insulating layer 70 is formed to cover the electrode film EL. Furthermore, an opening is made in the insulating layer 70 to expose a part of the electrode film EL, forming a pad region PD.

[0119] The semiconductor memory device 1 of the embodiment is manufactured as described above.

[0120] (Overview) Semiconductor memory devices such as three-dimensional non-volatile memory may be manufactured by forming peripheral circuits including transistors and other components, and laminates including word lines and pillar PLs, on separate substrates, and then bonding these substrates together.

[0121] Furthermore, source wires connected to pillars may be formed from the back side of the support substrate that supports the laminate after the substrates have been bonded together. In this case, the source wires are doped with N-type impurities and activated by annealing using laser light. Figure 15 shows the process at this time.

[0122] Figure 15 shows a method for forming the source line of a semiconductor memory device according to a comparative example.

[0123] The state of the semiconductor memory device in the comparative example shown in Figure 15(a) corresponds to the state shown in Figure 13(d) of the embodiment described above.

[0124] As shown in Figure 15(a), on the upper surface of the semiconductor substrate to which the peripheral circuit and the laminate are bonded, a pillar PLx having a channel layer CNx with its upper end protruding above the thinned semiconductor layer TSCx, a plate-shaped contact LIx having a conductive layer 24x with its upper end protruding above the thinned semiconductor layer TSCx, and a semiconductor layer AMRx covering these are formed.

[0125] In contrast, the plate-shaped contact LIx of the comparative example does not have the aforementioned void VD at its upper end, and the conductive layer 24x is filled throughout the entire plate-shaped contact LIx.

[0126] As shown in Figure 15(b), impurities such as phosphorus are doped into the semiconductor layer TSCx and the upper end of the channel layer CNx of the pillar PLx. As a result, the entire semiconductor layer TSCx and the upper end of the channel layer CNx become amorphous.

[0127] As shown in Figure 15(c), impurities such as arsenic are doped into the semiconductor layer AMRx and the upper end of the channel layer CNx of the pillar PLx, and then laser light is irradiated onto them.

[0128] As a result, the semiconductor layer AMRx is heated by the laser light, and the heat from the semiconductor layer AMRx is further transferred to the semiconductor layer TSCx and the upper end of the channel layer CNx of the pillar PLx, causing these semiconductor layers AMRx, TSCx and channel layer CNx to undergo annealing. Consequently, the semiconductor layers AMRx and TSCx become polycrystalline, and impurities within these semiconductor layers AMRx and TSCx are activated.

[0129] However, as shown in Figure 15(d), in the comparative example semiconductor memory device, impurities in the source line SLx may not be sufficiently activated around the pillar PLx adjacent to the plate-shaped contact LIx.

[0130] This is because the heat generated by the laser light is dissipated to the conductive layer 24x of the plate-shaped contact LIx. As a result, the temperature of the semiconductor layers AMRx, TSCx, etc., decreases in the vicinity of the plate-shaped contact LIx, and it is thought that impurities cannot be activated.

[0131] Therefore, the heat from the laser beam is suppressed from being dissipated into the conductive layer 24x. The configuration is such that the thermal conductivity of the upper end of the plate-shaped contact LIx is lower than when the conductive layer 24x is present.

[0132] According to the semiconductor memory device 1 of the embodiment, a plate-shaped contact LI including a conductive layer 24 is located adjacent to the pillar PL, extending within the laminate LM in the direction along the X direction and in the stacking direction of the laminate LM, and having an upper end protruding from the laminate LM; and a source line SLa mainly composed of semiconductor is disposed above the laminate LM and covers the upper end of the channel layer CN of the pillar PL and the upper end of the plate-shaped contact LI, wherein the plate-shaped contact LI has a void VD at its upper end.

[0133] The void VD at the upper end of the plate-shaped contact LI functions as an excellent heat insulating material. This suppresses the dissipation of heat from the laser beam into the conductive layer 24 of the plate-shaped contact LI. Therefore, the source wires SLp and SPa can be sufficiently heated to activate impurities in the source wires SLp and SPa.

[0134] According to the semiconductor memory device 1 of this embodiment, the plate-shaped contact LI has an insulating layer 54 that covers the side walls and top surface of the plate-shaped contact LI and separates the conductive layer 24 from the source wire SLa. This prevents electrical contact between the conductive layer 24 of the plate-shaped contact LI and the source wire SLa.

[0135] According to the semiconductor memory device 1 of this embodiment, the plate-shaped contact LI further has an insulating layer 54n inside the insulating layer 54, covering the sidewall of the conductive layer 24 and containing a different material from the insulating layer 54. This allows the sidewall of the slit SL to be protected by the insulating layer 54n by taking a selectivity ratio with respect to the insulating layer 54n when etching away the insulating layer 54 to form a void VD at the upper end of the plate-shaped contact LI.

[0136] In the semiconductor memory device 1 of this embodiment, the void VD of the plate-shaped contact LI is located above the select gate line SGS1 of the uppermost layer of the laminate LM. This ensures sufficient strength of the plate-shaped contact LI and suppresses chipping when the semiconductor memory device 1 is fragmented. Furthermore, even if the void VD of the plate-shaped contact LI is extended to below the height of the select gate line SGS1, the select gate line SGS1 itself has heat dissipation properties and therefore does not contribute to suppressing heat dissipation from the laser light.

[0137] (Variation 1) In the above embodiment, the insulating layer 54 on the bottom surface of the slit ST was made thicker, and this was removed by wet etching or the like to form a void VD at the lower end of the plate-shaped contact LI. However, the method for forming a void in a plate-shaped contact is not limited to this.

[0138] In the following modified embodiment 1, other methods for forming a void in the plate-shaped contact will be described using Figures 16 to 19.

[0139] Figures 16 to 19 illustrate, in order, a part of the method for manufacturing a semiconductor memory device according to a modified example 1 of the embodiment. More specifically, Figures 16 to 19 show a cross-section along the Y direction of the region that will later become the memory area, similar to Figures 3 to 14 of the embodiment described above.

[0140] In Figures 16 to 19, components similar to those in the embodiments described above are denoted by the same reference numerals, and their descriptions may be omitted. Furthermore, Figures 16 to 19 primarily illustrate a method for forming a void VDa in a plate-shaped contact LIa.

[0141] Figure 16(a) shows the state after the replacement of the insulating layer NL has been completed and the laminate LM having multiple word lines WL, etc., has been formed. In other words, Figure 16(a) corresponds to Figure 9(a) of the embodiment described above.

[0142] As shown in Figure 16(a), when replacing the laminate LM, the slit STa of Modified Example 1 is formed such that its reach in the semiconductor layer TSC is shallower than that of the slit ST in the above-described embodiment. However, it is preferable that the reach of the slit STa is greater than or equal to the thickness of the semiconductor layer TSC that will ultimately remain as a source line SLp in the semiconductor memory device of Modified Example 1.

[0143] Furthermore, after replacing the laminate LM, an insulating layer 54 is formed to cover the sidewalls and bottom surface of the slit STa. At this time, the insulating layer 54 is formed to have approximately the same thickness as the insulating layer 54 that will ultimately be present in the semiconductor memory device of Modified Example 1.

[0144] As shown in Figure 16(b), an insulating layer 54n is formed to cover the side walls and bottom surface of the slit ST via the insulating layer 54.

[0145] As shown in Figure 17(a), the insulating layers 54n, 54 on the bottom surface of the slit ST are removed by dry etching or the like, exposing the semiconductor layer TSC from the bottom surface of the slit ST.

[0146] As shown in Figure 17(b), while maintaining the selectivity ratio with respect to the insulating layer 54n, the semiconductor layer TSC exposed at the lower end of the insulating layer 54n is removed by wet etching or the like, forming a void VDa at the lower end of the slit STa. Since the insulating layer 54n is, for example, a silicon nitride layer and the semiconductor layer TSC is, for example, a silicon layer, it is possible to maintain etching selectivity even between these different materials.

[0147] As described above, because the original slit STa has a shallow reach, the height of the upper end of the void VDa at the lower end of the slit STa does not need to reach the lower surface of the laminate LM, and the void VDa may be smaller in size than, for example, the void VD in the above embodiment.

[0148] As shown in Figure 18(a), a conductive layer 24 is formed by filling the slit STa with a tungsten layer or the like. At this time, low coverage deposition conditions are used so that the void VDa at the lower end of the slit STa is not filled.

[0149] As a result, the plate-shaped contact LIa of Modified Example 1 is formed. However, in this case, the conductive layer 24 covering the void VDa at the lower end of the plate-shaped contact LIa is not covered by an insulating layer 54 or the like, and is in direct contact with the semiconductor layer TSC.

[0150] As shown in Figure 18(b), a separation layer SHE is formed on the upper side of the laminate LM, insulating layers 52 and 53 are formed to cover the laminate LM, a plug CH is formed which is connected to the cap layer CP, and a bit wire BL is formed which is connected to the plug CH.

[0151] Furthermore, the support substrate SS and the semiconductor substrate SB on which the peripheral circuit CBA is formed are bonded together.

[0152] As shown in Figure 19(a), various processes are then performed on the support substrate SS, which is bonded to the semiconductor substrate SB in an inverted state. Note that in Figure 19, only the upper ends of the pillar PL and plate-shaped contact LIa are shown.

[0153] As shown in Figure 19(b), the support substrate SS and the insulating layer 51 are removed, the semiconductor layer TSC is removed leaving a predetermined layer thickness, and the memory layer ME is removed from the upper end of the pillar PL that protrudes above the semiconductor layer TSC.

[0154] At this time, the upper end of the plate-shaped contact Lia that protrudes above the semiconductor layer TSC is covered with a conductive layer 24, such as a tungsten layer, in the void VDa, and is therefore hardly affected by the removal process of the memory layer ME from the upper end of the pillar PL. Also, as described above, since the slit STa depth is greater than or equal to the thickness of the semiconductor layer TSC after thickness reduction, the sidewall of the plate-shaped contact Lia is covered with the insulating layer 54 up to the portion that penetrates the semiconductor layer TSC.

[0155] As shown in Figure 19(c), an insulating layer 54a, such as a silicon oxide layer, is formed on the upper end of the plate-shaped contact LIa, covering the conductive layer 24 that is exposed and covers the void VDa. This prevents electrical conductivity between the conductive layer 24 of the plate-shaped contact LIa and the semiconductor layer AMR when the semiconductor layer AMR covering the upper ends of the plate-shaped contact LIa and pillar PL is formed thereafter.

[0156] However, the formation of the insulating layer 54a may be performed before the process of removing the memory layer ME from the upper end of the pillar PL described above. In this case, it is preferable to form the insulating layer 54a thickly so that the insulating layer 54a is not completely removed when the memory layer ME is removed.

[0157] Subsequently, the same process as shown in Figures 13(c) to 14(d) of the above-described embodiment is performed. That is, the semiconductor layer TSC is doped with impurities such as phosphorus, a semiconductor layer AMR is formed to cover the plate-shaped contact LIa and the upper end of the pillar PL, the semiconductor layer AMR and the upper end of the pillar PL are doped with impurities such as arsenic, and the entire upper surface of the laminate LM is irradiated with laser light.

[0158] As shown in Figure 19(d), a barrier metal layer BM is then formed to cover the source wire SLa, and a metal layer TS is formed to cover the barrier metal layer BM.

[0159] Furthermore, the same processing as in the above embodiment will be continued thereafter.

[0160] Based on the above, the semiconductor memory device of Modification 1 is manufactured.

[0161] The semiconductor memory device of Modification 1 provides the same effects as the embodiment described above.

[0162] (Modification 2) Next, a semiconductor memory device of modified embodiment 2 will be described using Figures 20 to 22. In modified embodiment 2, yet another method for forming a void in the plate-shaped contact will be described.

[0163] Figures 20 to 22 illustrate, in order, a part of the manufacturing method of a semiconductor memory device according to a modified example 2 of the embodiment. More specifically, Figures 20 to 22 show a cross-section along the Y direction of the region that will later become the memory area, similar to Figures 3 to 14 of the above-described embodiment.

[0164] In Figures 20 to 22, components similar to those in the above-described embodiments are denoted by the same reference numerals, and their descriptions may be omitted. Figures 20 to 22 mainly illustrate a method for forming a void VDb in a plate-shaped contact LIb.

[0165] Figure 20(a) shows the state after the replacement of the insulating layer NL has been completed and the laminate LM having multiple word lines WL, etc., has been formed. In other words, Figure 20(a) corresponds to Figure 9(a) of the embodiment described above.

[0166] As shown in Figure 20(a), when replacing the laminate LM, the slit ST of the modified example 2 is formed such that the depth reached in the semiconductor layer TSC is approximately the same as that of the slit ST of the embodiment described above.

[0167] Furthermore, after replacing the laminate LM, an insulating layer 54 is formed to cover the sidewalls and bottom surface of the slit ST. In this case as well, the insulating layer 54 is formed to have approximately the same thickness as the insulating layer 54 that will ultimately be present in the semiconductor memory device of Modified Example 2.

[0168] As shown in Figure 20(b), a sacrificial layer 27, such as an amorphous silicon layer, is formed on the bottom surface of the slit ST via the insulating layer 54.

[0169] As shown in Figure 21(a), an insulating layer 54n is formed to cover the side walls and bottom surface of the slit ST via the insulating layer 54 and the sacrificial layer 27.

[0170] As shown in Figure 21(b), the insulating layer 54n at the bottom of the slit ST is removed by dry etching or the like to expose the sacrificial layer 27.

[0171] As shown in Figure 22(a), while maintaining the selectivity ratio with respect to the insulating layer 54n, the sacrificial layer 27 exposed at the lower end of the insulating layer 54n is removed by wet etching or the like, forming a void VDb at the lower end of the slit ST. Since the insulating layer 54n is, for example, a silicon nitride layer and the sacrificial layer 27 is, for example, an amorphous silicon layer, it is possible to maintain etching selectivity even between these different materials.

[0172] As shown in Figure 22(b), a conductive layer 24 is formed by filling the slit ST with a tungsten layer or the like. At this time, low coverage deposition conditions are used so that the void VDb at the lower end of the slit ST is not filled.

[0173] As a result, the plate-shaped contact LIb of modified example 2 is formed.

[0174] Subsequently, the processes shown in Figure 12 and later of the above-described embodiment are carried out.

[0175] Based on the above, the semiconductor memory device of Modification 2 is manufactured.

[0176] The semiconductor memory device of Modified Example 2 provides the same effects as the embodiment described above.

[0177] (Variation 3) Next, a semiconductor memory device 2 of the third modified embodiment will be described using Figures 23 to 25. The third modified embodiment differs from the above-described embodiment in that the plate-shaped contact does not have a gap. In the following drawings, components similar to those in the above-described embodiment are denoted by the same reference numerals, and their descriptions may be omitted.

[0178] Figure 23 is a cross-sectional view showing an example of the configuration of a semiconductor memory device 2 according to a modified example of the embodiment 3. More specifically, Figure 23 is a cross-sectional view along the Y direction in the memory region MR of the semiconductor memory device 2.

[0179] As shown in Figure 23, the semiconductor memory device 2 of the modified example 3 includes a plate-shaped contact LIc instead of the plate-shaped contact LI of the above-described embodiment. The plate-shaped contact LIc comprises an insulating layer 54 covering the side walls and top surface of the plate-shaped contact LIc, an insulating layer 54c filled inside the plate-shaped contact LIc, and a conductive layer 24c interposed between the insulating layers 54 and 54c covering the top surface of the plate-shaped contact LIc and positioned at the upper end of the plate-shaped contact LIc.

[0180] More specifically, the insulating layer 54 has a thicker layer in the portion covering the upper surface of the plate-shaped contact LIc than in the portion covering the side walls of the plate-shaped contact LIc. The conductive layer 24c is positioned between the insulating layer 54 covering the upper surface of the plate-shaped contact LIc and the insulating layer 54c, at the height of the uppermost layer of the laminate LM, the selectable gate wire SGS1. The thickness of the conductive layer 24c is approximately the same as the thickness of the selectable gate wire SGS1.

[0181] The insulating layers 54 and 54c are silicon oxide layers, etc., and the conductive layer 24c is a tungsten layer, etc.

[0182] Thus, the plate-shaped contact LIc of Modification 3 has a thin conductive layer 24c at its upper end. In other words, the volume of the conductive layer 24c is smaller than that of the conductive layer 24 in the plate-shaped contact LI of the above embodiment. As a result, the heat of the laser light is suppressed from being dissipated to the conductive layer 24c, and the conductive layer 24c plays a role solely in reflecting the laser light. The laser light reflected by the conductive layer 24c returns to the semiconductor layer AMR during laser irradiation, promoting further heat generation in the semiconductor layer AMR.

[0183] Figures 24 and 25 show the method for forming the plate-shaped contact LIc described above.

[0184] Figures 24 and 25 illustrate, in sequence, a part of the procedure for manufacturing the semiconductor memory device 2 according to the modified embodiment 3. More specifically, Figures 24 and 25 show a cross-section along the Y direction of the region that will later become the memory area, similar to Figures 3 to 14 of the above-described embodiment.

[0185] Figures 24 and 25 primarily illustrate a method for forming voids VDb in the plate-shaped contact LIb.

[0186] Figure 24(a) shows the state after the replacement of the insulating layer NL has been completed and the laminate LM having multiple word lines WL, etc., has been formed. In other words, Figure 24(a) corresponds to Figure 9(a) of the embodiment described above.

[0187] As shown in Figure 24(a), when replacing the laminate LM, the slit ST of Modified Example 3 is formed such that the depth reached in the semiconductor layer TSC is approximately the same as that of the slit ST of the above-described embodiment.

[0188] Furthermore, after replacing the laminate LM, an insulating layer 54 is formed to cover the side walls and bottom surface of the slit ST. At this time, the insulating layer 54 is thickened in the portion covering the bottom surface of the slit ST using the same method as in the embodiment described above.

[0189] As shown in Figure 24(b), a conductive layer 24 is formed to cover the side walls and bottom surface of the slit ST via an insulating layer 54.

[0190] As shown in Figure 25(a), the conductive layer 24 covering the sidewall of the slit ST is removed to form a conductive layer 24c remaining on the bottom surface of the slit ST. This process can be carried out, for example, by dry etching using isotropic conditions.

[0191] As shown in Figure 25(b), the void created at the top of the slit ST is filled with an insulating layer 54c.

[0192] As a result, the plate-shaped contact Lic of modified example 3 is formed.

[0193] Subsequently, the processes shown in Figure 12 and later of the above-described embodiment are carried out.

[0194] Based on the above, the semiconductor memory device 2 of the modified example 3 is manufactured.

[0195] According to the semiconductor memory device 2 of Modified Example 3, a plate-shaped contact LIc is provided, which is located adjacent to the pillar PL, extends within the laminate LM in the direction along the X direction and in the stacking direction of the laminate LM, and includes a conductive layer 24 having an upper end protruding from the laminate LM; and a source line SLa, which is positioned above the laminate LM and covers the upper end of the channel layer CN of the pillar PL and the upper end of the plate-shaped contact LIc, and is mainly composed of semiconductor, wherein the plate-shaped contact LIc has a conductive layer 24c at the height of the selectable gate line SGS1 of the uppermost layer of the laminate LM.

[0196] This suppresses the dissipation of heat from the laser beam to the conductive layer 24c. In addition, the conductive layer 24c reflects the laser beam to the semiconductor layer AMR, thereby promoting the heat generation of the semiconductor layer AMR.

[0197] The semiconductor memory device 2 of the modified example 3 also provides the same effects as the embodiments described above.

[0198] (Other variations) In the embodiments and variations 1 to 3 described above, the semiconductor memory device is provided with a stacked LM having a 2-tier structure in which two stacked LMa and LMb are stacked vertically. However, the configuration of the stacked structure is not limited to 2 tiers; it may be 1 tier or 3 tiers or more.

[0199] Furthermore, in the embodiments and variations 1 to 3 described above, the stair region SR is positioned at both ends of the laminate LM in the X direction. However, the stair region may be positioned in the center of the laminate in the X direction, and the memory region MR may be positioned at both ends in the X direction.

[0200] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0201] 1,2...semiconductor memory device, 24,24c...conductive layer, 27...sacrificial layer, 54,54a,54c,54n...insulating layer, AMR,TSC...semiconductor layer, CN...channel layer, CR...core layer, LM,LMa,LMb,LMga,LMgb,LMsa,LMsb...laminated structure, MC...memory cell, ME...memory layer, MR...memory area, NL,OL...insulating layer, PL...pillar, SGD,SGS...selection gate line, SLa,SLp...source line, VD,VDa,VDb...void, WL...word line.

Claims

1. A laminate in which multiple first conductive layers and multiple first insulating layers are alternately stacked one layer at a time, A pillar including a semiconductor layer that extends within the laminate in the stacking direction of the laminate and has an upper end portion that protrudes from the laminate, A plate-like portion including a second conductive layer having an upper end portion protruding from the laminate, extending within the laminate in a first direction intersecting the lamination direction and the lamination direction at a position adjacent to the pillar, The laminate is positioned above the laminate and covers the upper end of the semiconductor layer and the upper end of the plate-like portion, and comprises a first layer mainly composed of a semiconductor, The plate-like portion is The upper end has a gap, Semiconductor memory device.

2. The plate-like portion is The plate-like portion has a second insulating layer that covers the side walls and top surface and separates the second conductive layer from the first layer. The aforementioned semiconductor layer is Connected to the first layer mentioned above, The semiconductor memory device according to claim 1.

3. The plate-like portion is The second insulating layer is further provided with a third insulating layer inside the second insulating layer, covering the sidewall of the second conductive layer and containing a material different from the second insulating layer. The semiconductor memory device according to claim 2.

4. The aforementioned void portion is Among the plurality of first conductive layers, the uppermost first conductive layer is located above the first conductive layer. The semiconductor memory device according to claim 1.

5. A laminate in which multiple first conductive layers and multiple first insulating layers are alternately stacked one layer at a time, A pillar including a semiconductor layer that extends within the laminate in the stacking direction of the laminate and has an upper end portion that protrudes from the laminate, A plate-like portion having an upper end protruding from the laminate, extending within the laminate in a first direction intersecting the lamination direction and at a position adjacent to the pillar, Displaced above the laminate, covering the upper end of the semiconductor layer and the upper end of the plate-like portion, the first layer comprises a semiconductor as its main component. The plate-like portion is Among the plurality of first conductive layers, the laminate has a second conductive layer at the height of the uppermost first conductive layer. Semiconductor memory device.

6. A laminate is formed in which multiple first conductive layers and multiple first insulating layers are alternately stacked one layer at a time; a pillar extending within the laminate in the stacking direction of the laminate and including a semiconductor layer having an upper end protruding from the laminate; and a plate-like portion adjacent to the pillar, having a second conductive layer extending within the laminate in a first direction intersecting the stacking direction and the stacking direction, and having an upper end protruding from the laminate. Displaced above the laminate, covering the upper end of the semiconductor layer and the upper end of the plate-like portion, a first layer mainly composed of semiconductor material is formed. A first conductive impurity is injected into the first layer, and the entire laminate including the first layer is irradiated with laser light. The formation of the plate-like portion is To form slits extending within the laminate in the first direction and the lamination direction, To form a second insulating layer covering the side wall of the slit, A third insulating layer is formed to cover the side wall of the slit via the second insulating layer, The second and third insulating layers protect the side walls of the slit, while forming a gap at the upper end of the slit. This includes forming the second conductive layer within the slit while leaving the aforementioned void portion intact. A method for manufacturing semiconductor memory devices.

7. The formation of the aforementioned void is The second insulating layer is formed by covering the upper surface together with the side walls of the slit, and thickening the portion that covers the upper surface. This includes removing the thickened portion of the second insulating layer while protecting the second insulating layer covering the side wall of the slit with the third insulating layer. The method for manufacturing a semiconductor memory device according to claim 6.

8. The formation of the aforementioned void is The second insulating layer is formed to cover the upper surface together with the side walls of the slit, A sacrificial layer is formed on the second insulating layer in the portion that covers the upper surface of the slit. This includes removing the sacrificial layer that is exposed at the upper end of the third insulating layer covering the side wall of the slit, The method for manufacturing a semiconductor memory device according to claim 6.

9. A second layer, mainly composed of semiconductor material, is formed on the upper surface of the aforementioned laminate. The formation of the aforementioned slit is This includes forming the slit that penetrates the laminate in the stacking direction and reaches into the second layer, The formation of the aforementioned void is This includes removing the second layer exposed from the upper end of the slit, The formation of the second conductive layer is This includes covering the side walls and upper surface of the void with the second conductive layer while leaving the void intact. The formation of the plate-like portion is This includes removing the second layer while leaving a predetermined thickness, so that the upper end of the plate-like portion, including the void covered by the second conductive layer together with the semiconductor layer, protrudes above the second layer. The formation of the first layer is The second conductive layer covering the aforementioned void is covered with a fourth conductive layer, This includes covering the upper end of the plate-like portion covered with the fourth conductive layer with the first layer, The method for manufacturing a semiconductor memory device according to claim 6.

10. The laminate having the pillar is formed above the first substrate, Before forming the first layer described above, A second substrate is prepared on which peripheral circuits contributing to the electrical operation of the pillar are formed. The first substrate and the second substrate are bonded together and the first substrate is removed. The method for manufacturing a semiconductor memory device according to claim 6.

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