Information processing device and information processing system

Abstract

To perform sparse vector operations efficiently and accurately on a small hardware scale. [Solution] The information processing device is connected to a first wire and each of a plurality of second wires, and comprises a plurality of strings that perform dot product calculations of first data and second data consisting of a plurality of bits, each of the plurality of strings has a plurality of transistors connected in series, each of the plurality of transistors is set to a threshold voltage corresponding to the first data, and a voltage corresponding to the second data is applied to each gate of the plurality of transistors via the corresponding second wire, and two or more bits in each of the first data and the second data are valid values ​​other than 0, and each of the plurality of strings flows a current through the first wire corresponding to the dot product value of the first data containing different valid values ​​and the second data containing different valid values.

Description

[Technical Field]

[0001] One embodiment of the present invention relates to an information processing apparatus and an information processing system. [Background Art]

[0002] Natural language processing requires analyzing the meaning of sentences containing a huge number of vocabularies and words. When natural language processing is performed by software, it takes a considerable amount of time to obtain a result. Accordingly, studies have been underway to implement natural language processing by hardware.

[0003] When each vocabulary constituting a sentence handled in natural language processing is represented by a vector, the number of dimensions of the vector is set to the number of vocabularies, and words included in the vocabulary are set to element positions of the vector, the number of words is overwhelmingly smaller than the number of vocabularies, resulting in a sparse vector in which the frequency of elements of each vector being non-zero is extremely low. Storing such sparse vectors in a semiconductor memory device and performing inner product calculation by hardware enables analogy determination between vocabularies. However, storing a huge number of sparse vectors in a semiconductor memory device results in low calculation efficiency and is a factor that unnecessarily consumes hardware resources and electric power. [Prior Art Literature] [Patent Literature]

[0004] [Patent Literature 1] U.S. Patent Application Publication No. 2022 / 0075843 Specification [Patent Literature 2] U.S. Patent Application Publication No. 2023 / 0221956 Specification [Patent Literature 3] U.S. Patent Application Publication No. 2021 / 0150313 Specification [Brief Summary of the Invention] [Problem to be Solved by the Invention]

[0005] Therefore, one embodiment of the present invention provides an information processing device and an information processing system that can perform sparse vector operations efficiently and accurately on a small hardware scale. [Means for solving the problem]

[0006] To solve the above problems, according to one embodiment of the present invention, a plurality of strings are connected to a first wire and to a plurality of second wires, and each string is connected to a plurality of second wires, and the strings perform an inner product operation between a first data consisting of a plurality of bits and the second data, Each of the aforementioned strings has multiple transistors connected in series, A threshold voltage corresponding to the first data is set for each of the aforementioned plurality of transistors. A voltage corresponding to the second data is applied to the gate of each of the plurality of transistors via the corresponding second wiring. The first data and the second data each have two or more bits that are valid values ​​other than 0. Each of the plurality of strings sends a current through the first wiring corresponding to the dot product of the first data containing different valid values ​​and the second data containing different valid values. An information processing device is provided. [Brief explanation of the drawing]

[0007] [Figure 1] This diagram illustrates an example where the number of dimensions of a vector is the number of words in a vocabulary, and each word in the vocabulary is identified by the position of the vector element. [Figure 2A] This diagram illustrates an example of converting a 1024-bit sparse vector to a 10-bit compressed vector. [Figure 2B] This figure shows a second example of converting a sparse vector, where at least two bits out of 1024 are 1, into a 10-bit compressed vector. [Figure 3] A circuit diagram showing an example of strings used in dot product operations. [Figure 4] A diagram showing the first and second transistors within a string. [Figure 5] This diagram shows the relationship between the threshold voltage and gate voltage of the first and second transistors. [Figure 6] A flowchart illustrating the procedure for a key-query matching search process performed by an information processing device according to one embodiment. [Figure 7] Figures 7A, 7B, and 7C show the input and output information of the string. [Figure 8] This diagram shows the relationship between the threshold voltage distribution and gate voltage of each transistor that makes up the string. [Figure 9] A diagram showing the correspondence between the number of dimensions and the number of cells required. [Figure 10] A diagram illustrating an example of performing an inner product operation using strings. [Figure 11A] A diagram showing the values ​​of the query (Q1, Q2) and key (K1, K2) that are input and set in two strings 1. [Figure 11B] Schematic diagram of two strings 1 into which the queries (Q1, Q2) and keys (K1, K2) are input and set in Figure 11A. [Figure 12A] This diagram shows the values ​​of the queries (Q1, Q2, Q3) and keys (K1, K2, K3) that are input and set in the three strings 1. [Figure 12B] Circuit diagram of three strings 1 into which the queries (Q1, Q2, Q3) and keys (K1, K2, K3) are input and set in Figure 12A. [Figure 13] A diagram showing combinations of compressed vectors, each containing exactly one valid value. [Figure 14] A circuit diagram of multiple strings composed of multiple memory cell transistors within a memory cell array. [Figure 15A] This diagram shows the values ​​of the queries (Q1, Q2) and keys (K1, K2) that are input and set in the two strings related to the first example. [Figure 15B] Circuit diagrams of two strings relating to the first example in Figure 15A where the queries (Q1, Q2) and keys (K1, K2) are input and set. [Figure 16A] The diagram shows the values ​​of the queries (Q1, Q2) and keys (K1, K2) that are input and set in the two strings related to the second example. [Figure 16B] A circuit diagram of two strings according to a second example, in which queries (Q1, Q2) and keys (K1, K2) of FIG. 16A are input and set. [Figure 17A] A diagram showing values of queries (Q1, Q2) and keys (K1, K2) input and set to two strings according to a third example. [Figure 17B] A circuit diagram of two strings according to a third example, in which queries (Q1, Q2) and keys (K1, K2) of FIG. 17A are input and set. [Figure 18A] A diagram showing values of queries (Q1, Q2) and keys (K1, K2) input and set to two strings according to a fourth example. [Figure 18B] A circuit diagram of two strings according to a fourth example, in which queries (Q1, Q2) and keys (K1, K2) of FIG. 18A are input and set. [Figure 19] A diagram showing a correspondence relationship between all numbers of dimensions of a key and a query, and the number of valid values included in the key and the query. [Figure 20] FIG. 20A, FIG. 20B, and FIG. 20C are diagrams showing memory areas including strings reserved from a memory cell array according to the number of valid values included in each sparse vector of a key and a query. [Figure 21A] A diagram illustrating an example in which an inner product operation is performed in a time-division manner by using a limited number of strings a plurality of times. [Figure 21B] A diagram showing a more specific example of FIG. 21A. [Figure 22] A block diagram showing a schematic configuration of an information processing system including an information processing apparatus according to an embodiment. DESCRIPTION OF EMBODIMENTS

[0008] Hereinafter, embodiments of an information processing apparatus and an information processing system will be described with reference to the drawings. The following description focuses on main components of the information processing apparatus and the information processing system, however, the information processing apparatus and the information processing system may include components and functions that are not illustrated or described. The following description does not exclude such components or functions that are not illustrated or described.

[0009] Figure 1 shows an example where each word in an arbitrary sentence to be analyzed in natural language processing is represented by a vector, the number of dimensions of the vector is the number of words in the vocabulary, and each word in the vocabulary is identified by the position of the vector element. In Figure 1, an example is shown where if only the second element from the left of a vector representing a certain word is 1, it represents "dog," and if only the fifth element from the left of the same vector is 1, it represents "cat." The number of elements in the vector in Figure 1 is, for example, 1024. In such a vector with a large number of elements, a vector in which at most one element is 1 is called a sparse vector.

[0010] Since sparse vectors are identified by the position of their 1s, they can be converted into compressed vectors that represent the positions of the 1s in the sparse vector. For example, if we convert a sparse vector to a 10-bit compressed vector and do not define the compressed vector "0000000000", then a 1022-bit sparse vector can be converted to a 10-bit compressed vector.

[0011] Figure 2A shows the first example of converting a sparse vector, where up to one bit out of 1022 bits is 1, into a 10-bit compressed vector. In the first example in Figure 2A, if all elements of the sparse vector are zero, it is converted into the compressed vector "0000000001". If only the first element of the sparse vector is 1, it is converted into the compressed vector "0000000010". If only the second element of the sparse vector is 1, it is converted into the compressed vector "0000000011".

[0012] Similarly, as the position of the 1 element in the sparse vector increases, the 10-bit compression bits are increased by one bit from the lower bits to the higher bits. As a result, if only the 1021st element of the sparse vector is 1, it is converted to the compressed vector "1111111110". If only the 1022nd element of the sparse vector is 1, it is converted to the compressed vector "1111111111".

[0013] Figure 2B shows a second example of converting a sparse vector, where two or more bits out of 1022 are 1, into a 10-bit compressed vector. If the first and third elements of the sparse vector are 1, it is converted into two compressed vectors "0000000010" and "0000000100". If the first and fifth elements of the sparse vector are 1, it is converted into two compressed vectors "0000000010" and "0000000110". If the third and fifth elements of the sparse vector are 1, it is converted into two compressed vectors "0000000100" and "0000000110". If the fifth and seventh elements of the sparse vector are 1, it is converted into two compressed vectors "0000000110" and "0000001000". If the 5th, 7th, and 9th elements of a sparse vector are 1, it is converted into three compressed vectors: "0000000110", "0000001000", and "0000001010".

[0014] In this way, by converting a sparse vector into a compressed vector that represents the position of element 1 in the sparse vector, the number of elements in the sparse vector can be reduced to approximately 1 / 10.

[0015] By performing the dot product operation on two sparse vectors, it is possible to determine whether each element of the two sparse vectors is identical based on the dot product value. In this specification, when performing the dot product operation on two sparse vectors, the two sparse vectors are converted into two compressed vectors, and the dot product operation is performed on the two compressed vectors. The dot product operation on two compressed vectors can be performed using a string of transistors connected in cascode. In this specification, a cascode connection of multiple transistors is sometimes referred to as a series connection.

[0016] Figure 3 is a circuit diagram showing an example of a string used in dot product calculations. String 1 shown in Figure 3 is, for example, part of a memory cell array in a semiconductor memory device.

[0017] Here, semiconductor memory devices refer to non-volatile memories such as NAND flash memory, ReRAM (Resistive Random Access Memory), and PCM (Phase-Change Memory). Alternatively, the semiconductor memory devices mentioned above may be volatile memories such as DRAM (Dynamic RAM) or SRAM (Static RAM). This specification mainly describes an example using string 1 made of NAND flash memory, but string 1 may be constructed using semiconductor memory devices other than NAND flash memory.

[0018] String 1, shown in Figure 3, has multiple transistors connected in a cascode configuration. Figure 3 shows an example of String 1 having a cascode-connected first transistor Tr1 and a second transistor Tr2. In addition to the first transistor Tr1 and the second transistor Tr2, String 1 can be constructed by connecting any number of transistors in a cascode configuration.

[0019] One end of string 1 is connected to the bit line (first wiring) BL. Different word lines (second wiring) WL1 and WL2 are connected to the gates of the first and second transistors Tr1 and Tr2 in string 1, respectively. In this specification, multiple word lines WL1, WL2, etc., may be collectively referred to as word line WL.

[0020] Multiple transistors within string 1 store data supplied via the bit line BL, with the word line WL connected to their respective gates set to a predetermined potential level. For example, in the case of string 1 of a NAND flash memory, each transistor within string 1 stores a charge corresponding to the data in a floating gate or charge storage film. Storing data in a transistor changes its threshold voltage. A change in the transistor's threshold voltage changes the gate potential level at which the transistor turns on.

[0021] Among the multiple transistors in each string 1, the first transistor Tr1 and the second transistor Tr2 are used to store a key K consisting of multiple bits. In this embodiment, it is assumed that each bit of key K is multi-valued data, but first, an example where each bit of key K is binary (0 or 1) will be explained using Figure 3.

[0022] The value of each bit of key K is stored in a first transistor Tr1 and a second transistor Tr2 in separate strings 1. The first transistor Tr1 in each string 1 stores the value of the corresponding bit of key K, and the second transistor Tr2, which is cascode-connected to the first transistor Tr1, stores a value that is the complement of the value of the corresponding bit of key K. The complement value is the bit-inverted data. For example, if the first transistor Tr1 stores 0, the second transistor Tr2 stores 1. In this specification, the multi-bit key K is referred to as the first data, and the complement data of key K is referred to as the second data.

[0023] In this specification, when we say that the first transistor Tr1 stores 0, we mean that the threshold voltage of the first transistor Tr1 is set to 0. In practice, the threshold voltage of the first transistor Tr1 is set to a potential level corresponding to 0, but for the sake of simplicity, this specification describes it as the threshold voltage being set to 0.

[0024] Among the multiple transistors in String 1, the third data and fourth data are supplied to the two word lines WL1 and WL2 connected to the gates of the first transistor Tr1 and the second transistor Tr2, respectively. The third data and fourth data each consist of multiple bits, and the fourth data is the complement of the third data. That is, the fourth data is the data obtained by inverting each bit of the third data. Each bit of the third and fourth data is assumed to be multi-level data with potential levels of three or more values, but first, we will explain the example where each bit of the third and fourth data is binary (0 or 1). The third data is the corresponding bit of query Q. Each bit of query Q is supplied by a different word line.

[0025] The information processing device according to this embodiment determines whether a query Q input from an external source matches a key K stored in a plurality of strings 1 by performing an inner product operation, and outputs the result of the inner product operation via a bit line BL.

[0026] Query Q and key K each consist of multiple bits, and are compared bit by bit using the corresponding first transistor Tr1 and second transistor Tr2. In this specification, key K is referred to as the first data, and query Q as the third data. Data that has a complement relationship with the first data is referred to as the second data, and data that has a complement relationship with the third data is referred to as the fourth data.

[0027] As described above, the corresponding bits of key K (first data) stored in the first transistor Tr1 and the corresponding bits of key / K (second data) stored in the second transistor Tr2 are complementary to each other. For example, if the corresponding bit of key K is "0", then the corresponding bit of key / K is "1". In this way, since the corresponding bits of the first and second data, which are complementary to each other, are written to the first transistor Tr1 and the second transistor Tr2, the threshold voltages of the first transistor Tr1 and the second transistor Tr2 will be different values. In this specification, the threshold voltage of the first transistor Tr1 is called the first threshold voltage, and the threshold voltage of the second transistor Tr2 is called the second threshold voltage.

[0028] String 1 may contain multiple sets of transistors, each consisting of a first transistor Tr1 and a second transistor Tr2, connected in series. In this case, threshold voltages that are complementary to each other are set for the first transistor Tr1 and second transistor Tr2 within the same set, based on the first data, and voltages that are complementary to each other are applied to the gates of the first transistor Tr1 and second transistor Tr2 within the same set, based on the second data.

[0029] More specifically, the first transistor Tr1 and the second transistor Tr2 of the same pair are set with threshold voltages corresponding to the corresponding bit value of the first data and its inverted bit value, and the gates of the first transistor Tr1 and the second transistor Tr2 of the same pair are each supplied with voltages corresponding to the corresponding bit value of the second data and its inverted bit value.

[0030] Figure 3 shows an example where each bit of query Q and key K is binary data. However, simply comparing the binary data of each bit only allows for a simple comparison of binary data. Recent non-volatile memories have increased their storage capacity by enabling the storage of multi-level data (three or more levels) within the memory cell. By utilizing such a non-volatile memory capable of storing multi-level data, it becomes possible to compare query Q and key K even when each bit of query Q and key K is multi-level data, thereby expanding the scope of application of the information processing device according to this embodiment.

[0031] Figure 4 shows the first transistor Tr1 and the second transistor Tr2 in string 1 when each bit of query Q and key K is a 2-bit, 4-value multi-level data. In this case, each bit of query Q and key K can take on four different potential levels, each consisting of two bits. The key K stored in the first transistor Tr1 (the first threshold voltage of the first transistor Tr1) and the key / K stored in the second transistor Tr2 (the second threshold voltage of the second transistor Tr2) are complementary to each other. If the first threshold voltage of the first transistor Tr1 is K, then the second threshold voltage of the second transistor Tr2 is 3-K.

[0032] Similarly, the query Q input to the gate of the first transistor Tr1 and the query / Q input to the gate of the second transistor Tr2 are complementary to each other. Therefore, if we denote the query Q input to the gate of the first transistor Tr1 as Q, then the query / Q input to the gate of the second transistor Tr2 can be expressed as 3-Q.

[0033] Figure 5 shows the relationship between the threshold voltage and gate voltage of the first transistor Tr1 and the second transistor Tr2. The first threshold voltage of the first transistor Tr1 in each string 1 is a value corresponding to the multi-level data of the corresponding bit of key K input via the bit line BL. Because there is some variation in the voltage level of the threshold voltage for each transistor, the potential level of the first threshold voltage of the first transistor Tr1 fluctuates within a predetermined range, as shown in Figure 5. This range of variation is called the threshold voltage distribution. The first transistor Tr1 turns on when the potential level of query Q input to the gate of the first transistor Tr1 is greater than this threshold voltage distribution, and turns off when it is less than the threshold voltage distribution. The same applies to the second transistor Tr2.

[0034] From Figures 4 and 5, the first transistor Tr1 and the second transistor Tr2 are both turned on only when both equations (1) and (2) below are satisfied.

[0035] Q≧K …(1) 3-Q≧3-K …(2) By rearranging equation (2), we obtain equation (3).

[0036] Q ≤ K …(3) The condition that satisfies both equation (1) and equation (3) is expressed by equation (4).

[0037] Q=K …(4) Thus, both the first transistor Tr1 and the second transistor Tr2 within each string 1 are turned on only when the multi-valued data of the corresponding bits of query Q and key K match.

[0038] An information processing device according to one embodiment applies natural language processing to sentences used by humans in daily life to generate the aforementioned sparse vectors, and converts the generated sparse vectors into compressed vectors. The compressed vectors represent the words contained in the vocabulary, and the compressed vectors are used to learn the vocabulary and words contained in various sentences. Since learning requires handling a vast amount of text, it may be performed on a cloud server or the like, which is set up separately from the information processing device. Based on the learning results, keys for queries are generated. The keys are, for example, information that represents words.

[0039] Figure 6 is a flowchart showing the procedure for key-query matching search processing performed by an information processing device according to one embodiment. Figures 7A, 7B, and 7C, included in Figure 7, show string input and output information.

[0040] In one embodiment, the information processing device sets threshold voltages for a plurality of transistors constituting string 1 based on keys obtained through learning (step S1). Figure 7A shows an example of setting thresholds corresponding to keys for each string 1. Each string includes a first transistor for which thresholds corresponding to keys key[0], key[1], etc. are set, and a second transistor for which thresholds corresponding to the complements of keys key[0], key[1], etc., / key[0], / key[1], etc. are set. In this drawing, the complement of a key or query is indicated by a bar above the key or query symbol, while in this specification, it is indicated by a slash before the symbol. The threshold voltages corresponding to keys set for each transistor remain fixed until the keys are updated through relearning.

[0041] Next, the information processing device inputs a query corresponding to an externally input question to each gate of the multiple transistors constituting string 1 via a word line (step S2). As a result, each transistor compares the gate voltage corresponding to the query with the threshold voltage corresponding to the key. Figure 7B shows an example where query query[0] etc. is supplied to the gate of each first transistor constituting string 1, and / query[0] etc. is supplied to the gate of each second transistor. When the gate voltage and threshold voltage match in all transistors constituting string 1, current flows through string 1 as shown in Figure 7C (step S3). If there is even one transistor in string 1 whose gate voltage and threshold voltage do not match, no current flows through string 1. The information processing device determines that the query and key match if current flows through string 1, and determines that the query and key do not match if no current flows through string 1.

[0042] Figure 8 shows the relationship between the threshold voltage distribution and gate voltage of each transistor constituting String 1. The upper part of Figure 8 shows the relationship between the threshold voltage distribution and gate voltage of the first transistor in String 1, and the lower part of Figure 8 shows the relationship between the threshold voltage distribution and gate voltage of the second transistor, which is in a complementary relationship with the first transistor in String 1.

[0043] Figure 8 shows an example where the query matches when the key is A. As shown in Figure 8, when the query and key match, the gate voltages of the first and second transistors are set to be greater than the threshold voltage. As a result, both the first and second transistors turn on, and current flows through string 1.

[0044] Figure 9 shows the correspondence between the number of dimensions and the number of required cells for compressed vectors (sparse vectors) and uncompressed vectors (uncompressed vectors). Figure 9 illustrates the correspondence W1 for binary compressed vectors, W2 for quaternary compressed vectors, W3 for binary uncompressed vectors, and W4 for quaternary uncompressed vectors. The number of required cells refers to the number of transistors that make up string 1 necessary to perform the dot product operation.

[0045] As shown in Figure 9, compressed vectors exhibit a smaller increase in the number of required cells relative to the increase in dimension compared to uncompressed vectors. Furthermore, for compressed vectors, quaternary vectors exhibit a smaller increase in the number of required cells relative to the increase in dimension compared to binary vectors. For uncompressed vectors, the number of required cells increases proportionally to the increase in dimension, and the rate of increase in the number of required cells relative to the increase in dimension is greater for quaternary vectors than for binary vectors.

[0046] Thus, compressed vectors allow for the inner product operation of sparse vectors to be performed with fewer cells than uncompressed vectors, and furthermore, the inner product operation can be performed more efficiently through multi-level processing.

[0047] Figure 10 shows an example of performing an inner product operation using string 1. Figure 10 shows an example where each transistor Tr0 to Tr9 constituting string 1 stores binary values. String 1 in Figure 10 has string section 1p and string section 1q connected in series. The same number of transistors Tr0 to Tr9 are cascode-connected to string section 1p and string section 1q. The threshold voltage and gate voltage of each transistor Tr0 to Tr9 in string section 1p and each transistor Tr0 to Tr9 in string section 1q are in a complement relationship.

[0048] Figure 10 shows an example in which the keys corresponding to the compressed vector "0000000101", obtained by compressing a sparse vector whose fourth element is 1, are set to the threshold voltages of each transistor Tr0 to Tr9 of string 1, and the queries corresponding to the compressed vector "0000000101" are applied to the gates of each transistor Tr0 to Tr9 of string 1.

[0049] More specifically, each transistor Tr0 to Tr9 in string section 1p is set to a threshold voltage corresponding to the compression vector "0000000101", and each transistor Tr0 to Tr9 in string section 1q is set to a threshold voltage corresponding to "1111111010", which is the complement of the compression vector "0000000101". In addition, a voltage corresponding to the compression vector "0000000101" is applied to the gates of each transistor Tr0 to Tr9 in string section 1p via a word line, and a voltage corresponding to "1111111010", which is the complement of the compression vector "0000000101", is applied to the gates of each transistor Tr0 to Tr9 in string section 1q.

[0050] Current flows through string section 1p and string section 1q only if the query and key match.

[0051] In this specification, elements that are 1 in a sparse vector are referred to as significant values. A sparse vector does not necessarily contain at most one significant value; it may contain two or more significant values. When a sparse vector contains two or more significant values, the correct dot product may not be obtained for string 1 in Figure 10.

[0052] Figures 11A and 11B illustrate an example of performing a dot product operation between two compressed vectors, each containing two valid values, using two parallel-connected strings 1. Figure 11A shows the values ​​of the query (Q1, Q2) and key (K1, K2) input to and set in the two strings 1. Figure 11B is a circuit diagram of the two strings 1 to which the query (Q1, Q2) and key (K1, K2) from Figure 11A are input and set. The compressed vector contains multiple bits that represent the bit positions of the valid values ​​in binary in a sparse vector, which contains bits that are 0 for all but the valid values. A threshold voltage corresponding to the valid value of one of the compressed vectors corresponding to the key is set for each transistor Tr0 to Tr9 of the two strings 1. In addition, a voltage corresponding to the valid value of the other compressed vector corresponding to the query is applied to the gates of each transistor Tr0 to Tr9 of the two strings 1 via a word line. In Figure 11B, the two strings 1 are connected in series: a first transistor sequence where the query is input to the gate and the key is set as the threshold voltage, and a second transistor sequence where the complement of the query is input to the query and the key's complement is set as the threshold voltage. However, the notation for the second transistor sequence is omitted in Figure 11B. Similarly, in Figures 12 to 19, which will be described later, the notation for the second transistor sequence in each string 1 is also omitted.

[0053] In Figure 11B, the two parallel-connected strings 1 are called the first string 1a and the second string 1b. Figure 11A shows an example where the two valid values ​​(K1, K2) of one compressed vector corresponding to the key are (1, 3), and the two valid values ​​(Q1, Q2) of the other compressed vector corresponding to the query are (3, 5). In this case, since both the key and the query contain valid values ​​= 3, current should flow through string 1 in principle. However, as shown in Figure 11B, there are cases where no current flows through string 1.

[0054] Figure 11B shows an example where (Q1, K1) is compared in the first string 1a and (Q2, k2) is compared in the second string 1b. In this example, a threshold voltage corresponding to the effective value K1=1 is set for each transistor Tr0 to Tr9 in the first string 1a, and a threshold voltage corresponding to the effective value K2=3 is set for each transistor Tr0 to Tr9 in the second string 1b. In addition, a voltage corresponding to the effective value Q1=3 is applied to the gates of each transistor Tr0 to Tr9 in the first string 1a, and a voltage corresponding to the effective value Q2=5 is applied to the gates of each transistor Tr0 to Tr9 in the second string 1b.

[0055] In Figure 11B, in the first string 1a, the compressed vector corresponding to the sparse vector with key=1 is compared with the compressed vector corresponding to the sparse vector with query=3. Since the key and query do not match, no current flows through the first string 1a. Similarly, in the second string 1b, the compressed vector corresponding to the sparse vector with key=3 is compared with the compressed vector corresponding to the sparse vector with query=5. Since the key and query do not match, no current flows through the second string 1b.

[0056] Thus, when performing an inner product operation on two sparse vectors, each containing multiple valid values, one might consider using multiple strings 1 to compare the query and the key. However, the result of the inner product operation will change depending on which threshold voltage corresponds to which valid value for each transistor in each string 1, and which voltage corresponding to which valid value is applied to the gate of each transistor in each string 1. This could lead to situations where the inner product operation between the two sparse vectors is not performed correctly.

[0057] Figures 12A and 12B illustrate an example of performing a dot product operation between two compressed vectors corresponding to two sparse vectors, each containing two valid values, using three parallel-connected strings 1. Figure 12A shows the values ​​of the queries (Q1, Q2, Q3) and keys (K1, K2, K3) that are input to and set in the three strings 1. Figure 12B is a circuit diagram of the three strings 1 to which the queries (Q1, Q2, Q3) and keys (K1, K2, K3) of Figure 12A are input and set.

[0058] Figure 12A shows an example where one compressed vector corresponding to the key has three valid values ​​(K1, K2, K3) which are (3, 5, 5), and the other compressed vector corresponding to the query has three valid values ​​(Q1, Q2, Q3) which are (1, 1, 3). In this case, since both the key and the query contain valid values ​​= 3, current should flow through string 1 in principle. However, as shown in Figure 12B, there are cases where current does not flow through string 1.

[0059] In the following, the three parallel-connected strings 1 in Figure 12B will be referred to as the first to third strings 1a, 1b, and 1c. Figure 12B shows an example where (Q1, K1) is compared in the first string 1a, (Q2, K2) is compared in the second string 1b, and (Q3, K3) is compared in the third string 1c. In this example, a threshold voltage corresponding to the effective value K1=3 is set for each transistor in the first string 1a, and a threshold voltage corresponding to the effective value K2=5 is set for each transistor in the second string 1b and the third string 1c. In addition, in the example in Figure 12B, a voltage corresponding to the effective value Q1=1 is applied to the gates of each transistor in the first string 1a and the second string 1b, and a voltage corresponding to the effective value Q2=3 is applied to the gates of each transistor in the third string 1c.

[0060] In Figure 12B, in the first string 1a, the compressed vector corresponding to the sparse vector with key=3 is compared with the compressed vector corresponding to the sparse vector with query=1. Since the key and query do not match, no current flows through the first string 1a. Similarly, in the second string 1b, the compressed vector corresponding to the sparse vector with key=5 is compared with the compressed vector corresponding to the sparse vector with query=1. Since the key and query do not match, no current flows through the second string 1b. Furthermore, in the third string 1c, the compressed vector corresponding to the sparse vector with key=5 is compared with the compressed vector corresponding to the sparse vector with query=3. Since the key and query do not match, no current flows through the third string 1c.

[0061] As shown in Figures 11B and 12B, when performing the dot product operation of two compressed vectors corresponding to two sparse vectors each containing two significant values ​​using three or fewer strings 1, there is a risk that the correct dot product value cannot be calculated.

[0062] Figure 13 shows the combinations of compressed vectors containing one valid value each, when the sparse vector contains one to three valid values. As shown in Figure 13, when the sparse vector contains one valid value, there is one combination of two compressed vectors corresponding to the key and query, and the correct dot product value can be obtained with one string 1. When the sparse vector contains two valid values, there are 2 × 2 = 4 combinations of two compressed vectors corresponding to the key and query, and the correct dot product value can be obtained with four strings 1. There are 3 × 3 = 9 combinations of three compressed vectors corresponding to the key and query, and the correct dot product value can be obtained with nine strings 1.

[0063] Thus, when a sparse vector contains n significant values ​​(where n is an integer greater than or equal to 1), the number of string 1s required to obtain the correct dot product is n squared.

[0064] The number of valid values ​​in a sparse vector can be determined, for example, by learning the valid values ​​contained in a large number of sparse vectors obtained through natural language processing. Since this learning requires enormous computational power, it may be performed on a different device (e.g., a server) from the information processing device according to one embodiment, and the valid values ​​and key information obtained through learning may be input to the information processing device according to one embodiment.

[0065] In one embodiment, the information processing device reserves strings 1 on a memory cell array, each containing a number of strings 1 equal to the square of the number of valid values, based on the valid values ​​included in a sparse vector. The strings 1 can be configured using, for example, a memory cell array of non-volatile memory such as NAND flash memory, and a memory area containing strings 1 equal to the square of the number of valid values ​​is reserved from the memory cell array.

[0066] In one embodiment of the information processing device, when performing a key-query matching search, a number of strings 1 corresponding to the number of valid values ​​contained in the two sparse vectors, the key and the query, are allocated on the memory cell array. For each of these strings 1, a matching search is performed for all combinations of the compressed vector for the key and the compressed vector for the query, each containing different valid values. These strings 1 are connected to a common bit line, and current flows through the strings 1 where the key and query match. Therefore, the key-query matching search result can be obtained by the current flowing from all the strings 1 to the bit line.

[0067] Figure 14 is a circuit diagram of multiple strings 1, which are composed of multiple memory cell transistors (hereinafter simply referred to as transistors) within a memory cell array. For example, when performing a dot product operation on two sparse vectors, each containing two valid values, four strings 1 are required. Therefore, in Figure 14, a memory area containing four strings 1 connected to a single bit line is treated as one block, and the dot product operation is performed for each block. In the block shown in Figure 14, multiple bit lines are arranged, and four strings 1 are connected to each bit line. In addition, multiple strings 1 corresponding to multiple blocks are connected to each bit line.

[0068] The current flowing through each of the four strings 1 in the same block flows through the corresponding bit line. Each bit line is connected to a sense amplifier (S / A). The sense amplifier determines whether the key and query match based on the current flowing through each bit line. For example, when performing a dot product operation on two sparse vectors, each containing two valid values, if both valid values ​​match between the query corresponding to one sparse vector and the key corresponding to the other sparse vector, twice the current flows through the bit line compared to when only one of the two valid values ​​matches. If neither of the two valid values ​​matches, no current flows through the bit line. In this way, the sense amplifier can determine how many valid values ​​of the key and query match based on the current flowing through the bit line.

[0069] Figures 15A to 18B show the first to fourth examples of the dot product operation between two compressed vectors corresponding to two sparse vectors, each containing two valid values. In the first to fourth examples, 2 x 2 = 4 strings 1 (hereinafter referred to as the first to fourth strings 1a to 1d) are prepared, the threshold voltage of each transistor in each string 1 is set based on one compressed vector corresponding to the key, and the voltage corresponding to the other compressed vector corresponding to the query is applied to the gate of each transistor in each string 1. More specifically, a match search is performed on the four strings 1 for all combinations of two compressed vectors for keys, each containing one different valid value, and two compressed vectors for queries, each containing one different valid value. In Figures 15 to 18, it is assumed that each transistor in each string 1 stores binary values.

[0070] In the first example shown in Figures 15A and 15B, the key and query have valid values ​​of 3 and 512, respectively. This is denoted herein as (Q1,Q2)=(3,512) and (K1,K2)=(3,512). Figure 15A shows the values ​​of the query (Q1,Q2) and key (K1,K2) input to and set in the two strings 1 in the first example. Figure 15B is a circuit diagram of the two strings 1 in the first example, to which the query (Q1,Q2) and key (K1,K2) of Figure 15A are input and set. As shown in Figure 15A, in the first example, since both the key and the query have two valid values, all possible combinations of key and query are (Q1,K1)=(3,3), (Q1,K2)=(3,512), (Q2,K1)=(512,3), and (Q2,K2)=(512,512).

[0071] In the first example, the first string 1a compares (Q1,K1)=(3,3), the second string 1b compares (Q2,K2)=(3,512), the third string 1c compares (Q2,K1)=(512,3), and the fourth string 1d compares (Q2,K2)=(512,512).

[0072] As shown in Figure 15B, in the first example, a threshold voltage corresponding to key K1=3 is set for each transistor in the first string 1a, and a voltage corresponding to query Q1=3 is applied to the gate of each transistor in the first string 1a. Similarly, a threshold voltage corresponding to key K1=512 is set for each transistor in the second string 1b, and a voltage corresponding to query Q1=3 is applied to the gate of each transistor in the second string 1b. Furthermore, a threshold voltage corresponding to key K1=3 is set for each transistor in the third string 1c, and a voltage corresponding to query Q1=512 is applied to the gate of each transistor in the third string 1c. Finally, a threshold voltage corresponding to key K1=512 is set for each transistor in the fourth string 1d, and a voltage corresponding to query Q1=512 is applied to the gate of each transistor in the fourth string 1d.

[0073] In the first example, the key and query match in both the first string 1a and the fourth string 1d, so current flows through both the first string 1a and the fourth string 1d. In the second string 1b and the third string 1c, the key and query do not match, so no current flows through the second string 1b and the third string 1c. Therefore, the bit line connecting the first to fourth strings 1a to 1d carries approximately twice the current flowing through either the first string 1a or the second string 1b.

[0074] In the second example in Figure 16, the key has valid values ​​3 and 255, and the query has valid values ​​3 and 512. This is denoted herein as (Q1,Q2)=(3,512) and (K1,K2)=(3,255). Figure 16A shows the values ​​of the query (Q1,Q2) and key (K1,K2) input to and set in the two strings 1 in the second example. Figure 16B is a circuit diagram of the two strings 1 in the second example to which the query (Q1,Q2) and key (K1,K2) in Figure 16A are input and set. As shown in Figure 16A, in the second example, since both the key and the query have two valid values, all possible combinations of key and query are (Q1,K1)=(3,3), (Q1,K2)=(3,255), (Q2,K1)=(512,3), and (Q2,K2)=(512,255).

[0075] In the second example, the first string 1a compares (Q1,K1)=(3,3), the second string 1b compares (Q1,K2)=(3,255), the third string 1c compares (Q2,K1)=(512,3), and the fourth string 1d compares (Q2,K2)=(512,255).

[0076] As shown in Figure 16B, in the second example, a threshold voltage corresponding to key K1=3 is set for each transistor in the first string 1a, and a voltage corresponding to query Q1=3 is applied to the gate of each transistor in the first string 1a. Similarly, a threshold voltage corresponding to key K1=255 is set for each transistor in the second string 1b, and a voltage corresponding to query Q1=3 is applied to the gate of each transistor in the second string 1b. Furthermore, a threshold voltage corresponding to key K1=3 is set for each transistor in the third string 1c, and a voltage corresponding to query Q1=512 is applied to the gate of each transistor in the third string 1c. Finally, a threshold voltage corresponding to key K1=255 is set for each transistor in the fourth string 1d, and a voltage corresponding to query Q1=512 is applied to the gate of each transistor in the fourth string 1d.

[0077] In the second example, the key and query match in the first string 1a, so current flows through the first string 1a. In the second to fourth strings 1d, the key and query do not match, so no current flows through the second to fourth strings 1d. Therefore, the bit line connecting the first to fourth strings 1a to 1d will have the same current flowing through it as the current flowing through the first string 1a.

[0078] In the third example in Figure 17, the keys have valid values ​​3 and 512, and the queries have valid values ​​512 and 771. In this specification, this is denoted as (Q1,Q2)=(512,771) and (K1,K2)=(3,512). Figure 17A shows the values ​​of the queries (Q1,Q2) and keys (K1,K2) that are input to and set in the two strings 1 in the third example. Figure 17B is a circuit diagram of the two strings 1 in the third example in which the queries (Q1,Q2) and keys (K1,K2) in Figure 17A are input to and set. As shown in Figure 17A, in the third example, since both the key and the query have two valid values, all possible combinations of key and query are (Q1,K1)=(512,3), (Q1,K2)=(512,512), (Q2,K1)=(771,3), and (Q2,K2)=(771,512).

[0079] In the third example, the first string 1a compares (Q1,K1)=(512,3), the second string 1b compares (Q1,K2)=(512,512), the third string 1c compares (Q2,K1)=(771,3), and the fourth string 1d compares (Q2,K2)=(771,512).

[0080] As shown in Figure 17B, in the third example, a threshold voltage corresponding to key K1=3 is set for each transistor in the first string 1a, and a voltage corresponding to query Q1=512 is applied to the gate of each transistor in the first string 1a. Similarly, a threshold voltage corresponding to key K1=512 is set for each transistor in the second string 1b, and a voltage corresponding to query Q1=512 is applied to the gate of each transistor in the second string 1b. Furthermore, a threshold voltage corresponding to key K1=3 is set for each transistor in the third string 1c, and a voltage corresponding to query Q1=771 is applied to the gate of each transistor in the third string 1c. Finally, a threshold voltage corresponding to key K1=512 is set for each transistor in the fourth string 1d, and a voltage corresponding to query Q1=771 is applied to the gate of each transistor in the fourth string 1d.

[0081] In the third example, the key and query match in the second string 1b, so current flows through the second string 1b. In the first, third, and fourth strings 1d, the keys and queries do not match, so no current flows through the first, third, and fourth strings 1d. Therefore, the bit line connecting the first to fourth strings 1a to 1d flows with the current that flows through the second string 1b.

[0082] In the fourth example in Figure 18, the keys have valid values ​​255 and 767, and the queries have valid values ​​3 and 512. This is denoted herein as (Q1,Q2)=(3,512) and (K1,K2)=(255,767). Figure 18A shows the values ​​of the queries (Q1,Q2) and keys (K1,K2) that are input to and set in the two strings 1 in the fourth example. Figure 18B is a circuit diagram of the two strings 1 in the fourth example, to which the queries (Q1,Q2) and keys (K1,K2) in Figure 18A are input to and set. As shown in Figure 18A, in the fourth example, since both the key and the query have two valid values, all possible combinations of key and query are (Q1,K1)=(3,255), (Q1,K2)=(3,767), (Q2,K1)=(512,255), and (Q2,K2)=(512,767).

[0083] In the fourth example, the first string 1a compares (Q1,K1)=(3,255), the second string 1b compares (Q1,K2)=(3,767), the third string 1c compares (Q2,K1)=(512,255), and the fourth string 1d compares (Q2,K2)=(512,767).

[0084] As shown in Figure 18B, in the fourth example, a threshold voltage corresponding to key K1=255 is set for each transistor in the first string 1a, and a voltage corresponding to query Q1=3 is applied to the gate of each transistor in the first string 1a. Similarly, a threshold voltage corresponding to key K1=767 is set for each transistor in the second string 1b, and a voltage corresponding to query Q1=3 is applied to the gate of each transistor in the second string 1b. Furthermore, a threshold voltage corresponding to key K1=255 is set for each transistor in the third string 1c, and a voltage corresponding to query Q1=512 is applied to the gate of each transistor in the third string 1c. Finally, a threshold voltage corresponding to key K1=767 is set for each transistor in the fourth string 1d, and a voltage corresponding to query Q1=512 is applied to the gate of each transistor in the fourth string 1d.

[0085] In the fourth example, since the key and query do not match in any of the first to fourth strings 1a to 1d, no current flows through any of the first to fourth strings 1a to 1d.

[0086] As shown in the first to fourth examples in Figures 15A to 18B, when performing a dot product operation on two compressed vectors corresponding to two sparse vectors each containing two valid values, four strings 1 are provided. By performing the dot product operation on each string 1 for all combinations of two keys (two compressed vectors) and two queries (two compressed vectors) each containing one valid value, current corresponding to the dot product value of the two keys and two queries can be passed through the bit lines to which the four strings 1 are connected.

[0087] Figure 19 shows the correspondence between the total number of dimensions of the key and query and the number of valid values ​​contained in the key and query. In Figure 19, the horizontal axis represents the number of dimensions of the sparse vectors of the key and query, and the vertical axis represents the number of valid values ​​contained in the sparse vectors that can be used for dot product operations. Figure 19 illustrates the correspondence W5 when the dot product operation is performed on the key and query as sparse vectors, and the correspondence W6 when the dot product operation is performed on the key and query as compressed vectors.

[0088] When performing the dot product operation between a key and a query using sparse vectors, the number of valid values ​​does not increase even if the number of dimensions increases, as shown in correspondence W5. In contrast, when converting sparse vectors to compressed vectors and performing the dot product operation between the key and the query, as shown in correspondence W6, the number of valid values ​​can increase accordingly as the number of dimensions increases, allowing dot product operations to be performed between sparse vectors containing more valid values.

[0089] The correspondence W6 can be expressed by the following equation (1). In equation (1), dim is the total number of dimensions, and yenable is the number of significant values ​​for which the dot product operation can be performed correctly.

number

[0090] As described above, in the information processing device according to one embodiment, the number of strings 1 used for the dot product operation changes depending on the number of valid values ​​contained in the key and query sparse vectors. Specifically, a memory area containing strings 1 equal to the square of the number of valid values ​​is allocated from the memory cell array.

[0091] Figures 20A, 20B, and 20C, included in Figure 20, show the memory areas containing string 1 allocated from the memory cell array, depending on the number of valid values ​​in each sparse vector of the key and query. When there is one valid value, the dot product operation can be performed in a memory area containing one string 1, as shown in Figure 20A. When there are two valid values, the dot product operation can be performed in a memory area containing 2 × 2 = 4 string 1s, as shown in Figure 20B. When there are three valid values, the dot product operation can be performed in a memory area containing 3 × 3 = 9 string 1s, as shown in Figure 20C.

[0092] Thus, the more significant values ​​there are, the larger the memory area required for the dot product operation becomes. As a method to reduce the memory area, one can use a limited number of strings 1 multiple times and perform the dot product operation using time-sharing.

[0093] Figures 21A and 21B illustrate an example of performing a dot product operation in time division multiple times using a limited number of strings 1. For example, the number of strings 1 is equal to the number of valid values ​​included in the key's sparse vector. For instance, if the key's sparse vector contains three valid values, three strings 1 (the first to third strings 1a, 1b, and 1c) are provided. Each string 1 corresponds to each valid value. For example, if the three valid values ​​in the key's sparse vector are the first to third valid values, the threshold voltage of each transistor in the first string 1a is set based on the compressed vector corresponding to the sparse vector containing only the first valid value. Similarly, the threshold voltage of each transistor in the second string 1b is set based on the compressed vector corresponding to the sparse vector containing only the second valid value. Furthermore, the threshold voltage of each transistor in the third string 1c is set based on the compressed vector corresponding to the sparse vector containing only the third valid value.

[0094] Assume that the query's sparse vector contains three valid values, and these valid values ​​are designated as the 4th to 6th valid values.

[0095] In the first dot product operation shown in Figure 21A, a voltage corresponding to the compressed vector that corresponds to the sparse vector containing only the fourth significant value is applied to the gates of the transistors in the first to third strings 1a, 1b, and 1c. As a result, the sum of the currents flowing through the first to third strings 1a, 1b, and 1c flows through the bit line. The sense amplifier stores the current flowing through the bit line as the result of the first dot product operation.

[0096] In the second dot product operation shown in Figure 21A, a voltage corresponding to the compressed vector that corresponds to the sparse vector containing only the fifth significant value is applied to the gates of the transistors 1a, 1b, and 1c in the first to third strings. As a result, the sum of the currents flowing through the first to third strings 1a, 1b, and 1c flows through the bit line. The sense amplifier stores the current flowing through the bit line as the result of the second dot product operation.

[0097] In the third dot product operation shown in Figure 21A, a voltage corresponding to the compressed vector that corresponds to the sparse vector containing only the sixth significant value is applied to the gates of the transistors 1a, 1b, and 1c in the first to third strings. As a result, the sum of the currents flowing through the first to third strings 1a, 1b, and 1c flows through the bit line. The sense amplifier stores the current flowing through the bit line as the result of the third dot product operation.

[0098] The sense amplifier calculates the dot product value based on the sum of the currents flowing through the bit lines during the first three passes.

[0099] Figure 21B shows a more detailed example of Figure 21A. In Figure 21B, an example is shown where the key has a first significant value K1=5, a second significant value K2=7, and a third significant value K3=9, and the query has a fourth significant value Q1=1, a fifth significant value Q2=5, and a sixth significant value Q3=6.

[0100] In the first dot product operation shown in Figure 21B, a voltage corresponding to the compressed vector that corresponds to the sparse vector containing only the fourth significant value Q1=1 is applied to the gates of the transistors in the first to third strings 1a, 1b, and 1c. As a result, the sum of the currents flowing through the first to third strings 1a, 1b, and 1c flows through the bit line. In this case, since the query and key do not match in any of the first to third strings 1a, 1b, and 1c, no current flows through the bit line.

[0101] In the second dot product operation shown in Figure 21B, a voltage corresponding to the compressed vector that corresponds to the sparse vector containing only the fifth significant value Q2=5 is applied to the gates of the transistors in the first to third strings 1a, 1b, and 1c. As a result, the sum of the currents flowing through the first to third strings 1a, 1b, and 1c flows through the bit line. In this case, the query K1=5 and key Q2=5 of the first string 1a match, so current flows through the first string 1a and the bit line.

[0102] In the third dot product operation shown in Figure 21B, a voltage corresponding to the compressed vector that corresponds to the sparse vector containing only the sixth significant value Q3=6 is applied to the gates of the transistors in the first to third strings 1a, 1b, and 1c. As a result, the sum of the currents flowing through the first to third strings 1a, 1b, and 1c flows through the bit line. In this case, since the query and key do not match in any of the first to third strings 1a, 1b, and 1c, no current flows through the bit line.

[0103] As shown above, in the examples in Figures 21A and 21B, the dot product operation between the key and the query can be performed using only the number of strings 1 corresponding to the number of valid values ​​in the sparse key vector, thus significantly reducing the number of strings 1 used in the dot product operation.

[0104] Figures 20, 21A, and 21B show examples of allocating memory areas for a number of string1s corresponding to the number of valid values. However, regardless of the number of valid values, it is also possible to allocate multiple memory areas for a predetermined number of string1s.

[0105] Figure 22 is a block diagram showing the schematic configuration of an information processing system 11 equipped with an information processing device 10 according to one embodiment. The information processing system 11 comprises the information processing device 10 according to one embodiment, a control device (control unit) 12, and a processing device 13. The information processing device 10 and the control device 12 constitute a memory system.

[0106] The control device 12 converts the input question into a query and generates an answer to the question based on the dot product value obtained by the information processing device 10.

[0107] Questions and answers are, for example, sentences or texts containing words and vocabulary that people use in everyday life.

[0108] The processing unit 13 performs natural language processing on a vast number of sentences containing words and vocabulary to generate a large number of sparse vectors, and learns the number of valid values ​​and keys contained in the sparse vectors. Since the learning of the processing unit 13 may require a great deal of computational power, for example, a server device accessible via a network from the information processing unit 10 may be used as the processing unit 13.

[0109] The processing unit 13 inputs a compressed vector corresponding to the learned key sparse vector and the number of valid values ​​included in the learned sparse vector to the information processing unit 10.

[0110] The information processing device 10 includes a memory cell array 2, a row selection circuit 3, a sense amplifier / column selection circuit 4, a controller 5, a data input / output buffer (acquisition unit) 6, a complement generation circuit 7, a multiplexer (MUX) 8, and a valid value storage unit 9.

[0111] As described above, the memory cell array 2 has multiple strings 1 connected to the same bit line BL. Note that the memory cell array 2 may have multiple bit lines BL. In this case, each bit line BL has multiple strings 1 similar to those in Figure 1. Each string 1 has a first transistor Q1 and a second transistor Q2, similar to those in Figure 1, and a word line WL, set to a potential level corresponding to the query Q, is connected to the gates of the first transistor Q1 and the second transistor Q2.

[0112] As shown in Figure 1, each string 1 may have multiple transistors in cascode connection in addition to the first transistor Q1 and the second transistor Q2. These multiple transistors are set to the ON state when reading the current from string 1.

[0113] The row selection circuit 3 sets the potential level of the word line WL connected to the gates of the first transistor Q1 and the second transistor Q2, in accordance with instructions from the controller 5 and an externally supplied query Q.

[0114] The data input / output buffer 6 acquires key K from the processing unit 13 and, according to instructions from the controller 5, supplies the acquired key K to the complement generation circuit 7 and the multiplexer 8. The complement generation circuit 7 inverts key K bit by bit from the data input / output buffer 6 to generate the complement data of key K. The multiplexer 8, according to instructions from the controller 5, selects either key K from the data input / output buffer 6 or the complement data of key K generated by the complement generation circuit 7 and supplies it to the sense amplifier / column selection circuit 4. The row selection circuit 3, where the address (query) is input, may also be equipped with a similar complement generation circuit 7 and multiplexer. The multiplexer 8, according to instructions from the controller 5, selects either the key input from the processing unit 13 via the data input / output buffer 6 or the key's complement data generated by the complement generation circuit 7 and inputs it to the sense amplifier / column selection circuit 4. The controller 5 also supplies the query input from the control device 12 via the data input / output buffer 6 and the query's complement data generated by the complement generation circuit 7 to the row selection circuit 3.

[0115] The sense amplifier / column selection circuit 4 supplies the key K or complement data output from the multiplexer 8 to the bit line BL. The sense amplifier / column selection circuit 4 also senses the current flowing from string 1 to the bit line.

[0116] The controller 5 calculates the dot product value based on the current sensed by the sense amplifier / column selection circuit 4. Based on the dot product value, the controller 5 performs a match search to determine whether the query and key match. Alternatively, the controller 5 performs an approximate nearest neighbor search between the query and key based on the dot product value. The result of the match search or approximate nearest neighbor search is sent to the control device 12.

[0117] The control device 12 generates and outputs an answer to the question based on the results of a match search or approximate nearest neighbor search.

[0118] The valid value storage unit 9 stores the valid values ​​contained in the learned sparse vector input from the processing unit 13. As described above, the controller 5 reserves a memory area from the memory cell array for the square of the valid values ​​stored in the valid value storage unit 9, which is the size of the string 1, for the dot product operation.

[0119] The processing unit 13 may also input the square of the valid value to the information processing unit 10. In this case, the valid value storage unit 9 stores the square of the valid value.

[0120] As described above, in the information processing device 10 according to one embodiment, when each of the two sparse vectors, the key and the query, contains multiple valid values, a number of strings 1 corresponding to the number of valid values ​​are reserved on the memory cell array, and a string dot product operation is performed using the reserved strings 1 for all combinations of multiple compressed vectors containing one valid value each of the key and multiple compressed vectors containing one valid value each of the query. This allows the dot product value to be calculated correctly even if the sparse vectors of the key and query contain multiple valid values.

[0121] [Item 1] It is connected to a first wire and also to a plurality of second wires, and comprises a plurality of strings that perform an inner product operation between a first data consisting of multiple bits and a second data, Each of the aforementioned strings has multiple transistors connected in series, A threshold voltage corresponding to the first data is set for each of the aforementioned plurality of transistors. A voltage corresponding to the second data is applied to the gate of each of the plurality of transistors via the corresponding second wiring. The first data and the second data each have two or more bits that are valid values ​​other than 0. Each of the plurality of strings sends a current through the first wiring corresponding to the dot product of the first data containing different valid values ​​and the second data containing different valid values. Information processing device. [Item 2] The sum of the currents flowing through the aforementioned multiple strings flows through the first wiring as the dot product value. The information processing device described in item 1. [Item 3] The aforementioned plurality of transistors include a plurality of sets, each consisting of a first transistor and a second transistor. For the same pair of first and second transistors, threshold voltages that are complementary to each other are set based on the first data. A voltage that is complementary to the other based on the second data is applied to the gates of the first and second transistors of the same pair. An information processing device as described in item 1 or 2. [Item 4] The first transistor and the second transistor of the same pair are set to the threshold voltage corresponding to the corresponding bit value of the first data and its inverted bit value. A voltage corresponding to the bit value of the second data and its inverted bit value is applied to the gates of the first and second transistors of the same pair. The information processing device described in item 3. [Item 5] The number of strings is corresponding to the number of significant values. An information processing device as described in any one of items 1 through 4. [Item 6] The first data and the second data include the same number of the aforementioned significant values, The information processing device described in item 5. [Item 7] The number of strings is n squared, where n is an integer greater than or equal to 2. Information processing device as described in item 5 or 6. [Item 8] From the memory cell array, a number of memory areas for the multiple strings corresponding to the number of valid values ​​are allocated. The dot product of the first data and the second data is obtained with a single current flow through the plurality of strings. An information processing device as described in any one of items 5 through 7. [Item 9] From the memory cell array, a predetermined number of memory areas for the plurality of strings are allocated, regardless of the number of valid values. The dot product of the first data and the second data is obtained with a single current flow through the plurality of strings. An information processing device as described in any one of items 5 through 7. [Item 10] The plurality of strings cause current to flow through the first wiring according to the multiple dot product values ​​of all combinations of the first data for a number of the valid values ​​and the second data for a number of the valid values. An information processing device as described in any one of items 5 through 9. [Item 11] From the memory cell array, a number of memory areas for the multiple strings corresponding to the number of valid values ​​are allocated. The dot product of the first data and the second data is obtained by summing the currents that flow through the plurality of strings in multiple steps. An information processing device as described in any one of items 1 through 6. [Item 12] From the memory cell array, a number of memory areas for the multiple strings corresponding to the number of valid values ​​are allocated. The dot product of the first data and the second data is obtained by the sum of the currents flowing through the plurality of strings multiple times. The information processing device described in item 11. [Item 13] From the memory cell array, memory areas for the plurality of strings equal to the number of valid values ​​are allocated. The information processing device described in item 12. [Item 14] Each of the plurality of transistors is set to a threshold voltage corresponding to the effective value, which is different for each of the plurality of strings. A voltage corresponding to the effective value, which is common to the plurality of transistors and differs for each iteration, is applied to the gate of each of the plurality of transistors. The information processing device described in item 12 or 13. [Item 15] The first data and the second data are compressed vectors containing multiple bits that represent the bit positions of the significant values ​​in binary in a sparse vector containing bits that are 0 except for the significant values. An information processing device as described in any one of items 1 through 14. [Item 16] The first wiring is a bit line, The second wire is a word wire, Having a non-volatile memory having the plurality of strings, An information processing device as described in any one of items 1 through 15. [Item 17] The aforementioned non-volatile memory is NAND flash memory. The information processing device described in item 16. [Item 18] An information processing device described in any one of items 1 through 17, The system includes a control device that converts an input question into the second data and generates an answer to the question based on the dot product value obtained by the information processing device, The aforementioned information processing device is An acquisition unit that acquires the first data, the number of strings to be used, and the second data, A control unit that performs a match search or approximate neighbor search of the first data and the second data based on the dot product value of the first data and the second data, Information processing system.

[0122] The aspects of this disclosure are not limited to the individual embodiments described above, but include various modifications that a person skilled in the art could conceive, and the effects of this disclosure are not limited to those described above. In other words, various additions, modifications, and partial deletions are possible, as long as they do not depart from the conceptual idea and spirit of this disclosure derived from the claims and their equivalents. [Explanation of Symbols]

[0123] 1 String, 1a First String, 1b Second String, 1c Third String, 1d Fourth String, 1p, 1p String Section, 2 Memory Cell Array, 3 Row Selection Circuit, 4 Column Selection Circuit, 5 Controller, 6 Data Input / Output Buffer, 7 Complement Generation Circuit, 8 Multiplexer, 9 Effective Value Storage Section, 10 Information Processing Unit, 11 Information Processing System, 12 Control Device, 13 Processing Unit

Claims

1. It comprises multiple strings, each connected to a first wire and a plurality of second wires, which perform an inner product operation between a first data and a second data consisting of multiple bits, Each of the aforementioned strings has multiple transistors connected in series, A threshold voltage corresponding to the first data is set for each of the plurality of transistors. A voltage corresponding to the second data is applied to the gate of each of the plurality of transistors via the corresponding second wiring. The first data and the second data each have two or more bits that are valid values ​​other than zero. Each of the plurality of strings sends a current through the first wiring corresponding to the dot product of the first data containing different valid values ​​and the second data containing different valid values. Information processing device.

2. The sum of the currents flowing through the plurality of strings flows through the first wiring as the dot product value. The information processing apparatus according to claim 1.

3. The plurality of transistors includes a plurality of sets, each set consisting of a first transistor and a second transistor. For the same pair of first and second transistors, threshold voltages that are complementary to each other are set based on the first data. A voltage that is complementary to the other based on the second data is applied to the gates of the first and second transistors of the same pair. The information processing apparatus according to claim 1.

4. The first transistor and the second transistor of the same pair are set to the threshold voltage corresponding to the corresponding bit value of the first data and its inverted bit value. A voltage corresponding to the bit value of the second data and its inverted bit value is applied to the gates of the first and second transistors of the same pair. The information processing apparatus according to claim 3.

5. The number of strings is corresponding to the number of significant values. The information processing apparatus according to claim 1.

6. The first data and the second data include the same number of the aforementioned valid values, The information processing apparatus according to claim 5.

7. The number of strings is n squared, where n is an integer greater than or equal to 2. The information processing apparatus according to claim 5.

8. From the memory cell array, a number of memory areas for the multiple strings corresponding to the number of valid values ​​are allocated. The dot product of the first data and the second data is obtained with a single current flow through the plurality of strings. The information processing apparatus according to claim 5.

9. From the memory cell array, a predetermined number of memory areas for the plurality of strings are allocated, regardless of the number of valid values. The dot product of the first data and the second data is obtained with a single current flow through the plurality of strings. The information processing apparatus according to claim 5.

10. The plurality of strings cause current to flow through the first wiring according to the multiple dot product values ​​of all combinations of the first data for a number of the valid values ​​and the second data for a number of the valid values. The information processing apparatus according to claim 5.

11. From the memory cell array, a number of memory areas for the multiple strings corresponding to the number of valid values ​​are allocated. The dot product of the first data and the second data is obtained by summing the currents that flow through the plurality of strings in multiple steps. The information processing apparatus according to claim 1.

12. From the memory cell array, a number of memory areas for the multiple strings corresponding to the number of valid values ​​are allocated. The dot product of the first data and the second data is obtained by the sum of the currents flowing through the plurality of strings multiple times. The information processing apparatus according to claim 11.

13. From the memory cell array, memory areas for the plurality of strings equal to the number of valid values ​​are allocated. The information processing apparatus according to claim 12.

14. Each of the plurality of transistors is set to a threshold voltage corresponding to the effective value, which is different for each of the plurality of strings. A voltage corresponding to the effective value, which is common to the plurality of transistors and differs for each iteration, is applied to the gate of each of the plurality of transistors. The information processing apparatus according to claim 12.

15. The first data and the second data are compressed vectors containing multiple bits that represent the bit positions of the significant values ​​in binary in a sparse vector containing bits that are 0 except for the significant values. The information processing apparatus according to claim 1.

16. The first wiring is a bit line, The second wiring is a word wire, Having a non-volatile memory having the plurality of strings, The information processing apparatus according to claim 1.

17. The aforementioned non-volatile memory is a NAND flash memory. The information processing apparatus according to claim 16.

18. An information processing device according to any one of claims 1 to 17, The system includes a control device that converts an input question into the second data and generates an answer to the question based on the dot product value obtained by the information processing device, The aforementioned information processing device is An acquisition unit that acquires the first data, the number of strings to be used, and the second data, A control unit that performs a match search or approximate neighbor search of the first data and the second data based on the dot product value of the first data and the second data, Information processing system.

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