Semiconductor equipment

Abstract

The present invention provides a semiconductor device that possesses barrier properties to solutions and electrical insulation (stability). [Solution] The present invention relates to a solution-gate FET transistor having graphene in the channel, wherein a first layer is formed on the outer periphery of the channel and on the source electrode and drain electrode, and a second layer is formed on the first layer, the first layer having better solution barrier properties than the second layer, and the second layer having better adhesion to the channel than the first layer.

Description

[Technical Field]

[0001] This invention relates to a semiconductor device. [Background technology]

[0002] Research and development of various sensors are underway, and sensors have become widely integrated into modern society, from industrial to medical applications, and even into ordinary households. Sensors are classified, for example, by their measurement target, signal conversion function, or constituent materials. Signal conversion functions can be broadly categorized into physical sensors, chemical sensors, or biosensors.

[0003] Among these, biosensors are measurement devices that mimic or directly utilize the excellent molecular recognition capabilities of living organisms, and are attracting attention due to their expected wide range of applications.

[0004] For example, biosensors using semiconductor devices such as field-effect transistors (FETs) have attracted attention in recent years because they can sense substances by utilizing the fact that the amount of charge in the channel changes according to the concentration of the target substance, and they allow for simple sensing. To enable sensing of even minute amounts, a technology that enables highly sensitive sensing is already known by using atomic layer materials such as graphene or fine fiber materials such as carbon nanotubes (CNTs) that have high field-effect mobility and a large surface area as the channel material.

[0005] Graphene field-effect transistors (GFETs), which use graphene as the channel, are expected to have various applications due to the unique properties of graphene. Graphene has attracted attention as a high-sensitivity sensor because it has ultra-high mobility more than 100 times that of silicon (Si), and its two-dimensional shape results in a large surface area-to-channel volume ratio. Furthermore, because it is composed solely of carbon and has good compatibility with biomolecules, it is particularly promising for applications in biosensing, such as biomolecules.

[0006] Patent Document 1 describes a semiconductor device in which the entire graphene transistor (at least the channel, source electrode, drain electrode, and wiring metal) is covered with a protective film. [Overview of the project] [Problems that the invention aims to solve]

[0007] However, because the above technology uses organic materials, if they are immersed in the solution being measured for a long time, moisture will penetrate the membrane due to the high water permeability of organic materials, causing membrane lifting or delamination. In addition, organic materials have low mechanical strength, making them prone to membrane lifting. Furthermore, because organic materials have low electrical insulation properties, they undergo significant electrical degradation when measured for extended periods while immersed in water.

[0008] The present invention has been made in view of the above, and aims to provide a semiconductor device that has barrier properties to solutions and electrical insulation properties. [Means for solving the problem]

[0009] To solve the above-mentioned problems and achieve the objective, the present invention provides a solution-gate FET transistor having graphene in the channel, wherein a first layer is formed on the outer periphery of the channel and on the source electrode and drain electrode, and a second layer is formed on the first layer, the first layer having better solution barrier properties than the second layer, and the second layer having better adhesion to the channel than the first layer. [Effects of the Invention]

[0010] According to the present invention, the material can have the effect of being both a barrier to the solution and an electrical insulator. [Brief explanation of the drawing]

[0011] [Figure 1-1]FIG. 1-1 is a diagram for explaining a graphene transistor that is an example of a semiconductor device according to the present embodiment. [Figure 1-2] FIG. 1-2 is a cross-sectional view schematically showing the layer configuration of a passivation layer of the graphene transistor according to the present embodiment. [Figure 2-1] FIG. 2-1 is a diagram showing an example in which a seed layer is introduced to facilitate deposition of an adhesion layer by ALD in a region including a graphene channel in the graphene transistor according to the present embodiment. [Figure 2-2] FIG. 2-2 is a diagram showing an example of ALD deposition rates on and outside a graphene channel. [Figure 3-1] FIG. 3-1 is a diagram for explaining a configuration in which a protective layer having a small difference in coefficient of thermal expansion from a substrate is also disposed on the lowermost layer to further relax the difference in coefficient of thermal expansion on the graphene channel in the graphene transistor according to the present embodiment. [Figure 3-2] FIG. 3-2 is a diagram for explaining an example in which an intermediate layer is inserted between an adhesion layer and a protective layer to further reduce the difference in coefficient of thermal expansion in the film thickness direction of a passivation film in the graphene transistor according to the present embodiment. [Figure 4-1] FIG. 4-1 is a diagram showing an example of a structure in which a protective layer and a stress relaxation layer are alternately stacked in a mille-feuille shape to improve barrier properties against a measurement solution. [Figure 4-2] FIG. 4-2 is a diagram showing an example of a structure in which a protective layer and a stress relaxation layer are alternately stacked in a mille-feuille shape to improve barrier properties against a measurement solution. [Figure 4-3] FIG. 4-3 is a diagram showing an example of a structure in which a protective layer and a stress relaxation layer are alternately stacked in a mille-feuille shape to improve barrier properties against a measurement solution. [Figure 4-4] FIG. 4-4 is a diagram showing an example of a structure in which a protective layer and a stress relaxation layer are alternately stacked in a mille-feuille shape to improve barrier properties against a measurement solution. [Figure 4-5] FIG. 4-5 is a diagram showing an example in which an adhesion layer and a stress relaxation layer are alternately stacked to improve the dispersibility of film stress. [Figure 5-1] FIG. 5-1 is a diagram for explaining an example of further relaxing the difference between the stress distribution in the film thickness direction of the passivation film and the coefficient of thermal expansion in the graphene transistor according to the present embodiment. [Figure 5-2] FIG. 5-2 is a diagram for explaining an example of further relaxing the difference between the stress distribution in the film thickness direction of the passivation film and the coefficient of thermal expansion in the graphene transistor according to the present embodiment. [Figure 6-1] FIG. 6-1 is a diagram for explaining an example of enhancing water resistance in the graphene transistor according to the present embodiment. [Figure 6-2] FIG. 6-2 is a diagram for explaining an example of enhancing water resistance in the graphene transistor according to the present embodiment. [Figure 6-3] FIG. 6-3 is a diagram for explaining an example of enhancing water resistance in the graphene transistor according to the present embodiment. [Figure 7-1] FIG. 7-1 is a diagram for explaining an example of improving the adhesiveness at the interface between the adhesion layer and the stress relaxation layer in the graphene transistor according to the present embodiment. [Figure 7-2] FIG. 7-2 is a diagram for explaining an example of improving the adhesiveness at the interface between the stress relaxation layer and the protective layer in the graphene transistor according to the present embodiment. [Figure 8] FIG. 8 is a diagram for explaining an example of improving the water repellency of the protective layer in the graphene transistor according to the present embodiment. [Figure 9-1] FIG. 9-1 is a diagram for explaining an example of enhancing water resistance in the graphene transistor according to the present embodiment. [Figure 9-2] FIG. 9-2 is a diagram for explaining an example of enhancing water resistance in the graphene transistor according to the present embodiment. [Figure 10] FIG. 10 is a diagram for explaining an example of further relaxing stress concentrated in the channel opening portion of the graphene transistor according to the present embodiment. [Figure 11]Figure 11 is a plan view and a cross-sectional view of the graphene transistor chip according to this embodiment, in which the gate electrode is placed on the chip. [Figure 12] Figure 12 is a diagram illustrating an example in which a gate electrode is placed on a graphene transistor chip according to this embodiment. [Modes for carrying out the invention]

[0012] The embodiments of the semiconductor device will be described in detail below with reference to the attached drawings.

[0013] Figure 1-1 is a diagram illustrating a graphene transistor, which is an example of a semiconductor device according to this embodiment. The graphene transistor according to this embodiment is an example of a solution-gate FET transistor having graphene in its channel. Specifically, the graphene transistor includes a graphene channel (an example of a channel) 3, a source electrode 4, a drain electrode 5, wiring metal 6, an adhesion layer 7 arranged to prevent peeling of the passivation film 789, a stress relaxation layer 8 arranged to ensure crack prevention and insulation of the passivation film 789, and a protective layer 9 arranged to prevent penetration of the solution to be measured (hereinafter also referred to as the measurement solution) 12 into the passivation film 789. In the following description, the adhesion layer 7, the stress relaxation layer 8, and the protective layer 9 are collectively referred to as the passivation film 789.

[0014] Here, the adhesion layer 7 is an example of a first layer formed on the outer periphery of the graphene channel 3, the source electrode 4, and the drain electrode 5. The protective layer 9 is an example of a second layer formed on the adhesion layer 7. The stress relaxation layer 8 is an example of a first intermediate layer formed between the adhesion layer 7 and the protective layer 9. Furthermore, the adhesion layer 7, the stress relaxation layer 8, and the protective layer 9 may be formed from insulating materials.

[0015] Furthermore, the adhesion layer 7 has superior solution barrier properties compared to the protective layer 9. Also, the protective layer 9 has better adhesion to the graphene channel 3 than the adhesion layer 7. In addition, the stress relaxation layer 8 may have residual stress in the opposite direction to the residual stress of the adhesion layer 7. Furthermore, the thermal expansion coefficient of the stress relaxation layer 8 may be a value between the thermal expansion coefficient of the adhesion layer 7 and the thermal expansion coefficient of the protective layer 9.

[0016] Furthermore, the graphene transistor includes a graphene channel 3, source and drain electrodes 4 and 5 connected to the graphene channel 3, a passivation film 789, and wiring metal 6 connected to the source and drain electrodes 4 and 5 and routed on the insulating film 2, in addition to a substrate 1 and the insulating film 2. However, the source and drain electrodes 4 and 5 connected to the graphene channel 3 and the wiring metal 6 routed on the source and drain electrodes 4 and 5 and the insulating film 2 may be made of the same metal.

[0017] In this embodiment, the graphene transistor can electrically sense the presence and concentration of the target substance 14 in the solution 12 by changing the current Ids flowing between the source electrode 4 and the drain electrode 5 when the receiving layer 10 captures the target substance 14.

[0018] The substrate 1 is not limited to conductive materials; flexible substrates such as PET (polyethylene terephthalate) and PEN (polyethylene naphthalate) can also be used. By forming graphene transistors on a flexible substrate 1, sensors utilizing graphene transistors can be formed on curved surfaces. For example, sensors that can be attached to the human body can be realized, which are extremely useful for sensing vital data.

[0019] Furthermore, by forming graphene transistors on a flexible substrate 1, it becomes possible to bring the sensor into close contact with the body, enabling accurate real-time detection of heart rate and muscle potential, as well as real-time sensing of body odor or bodily fluids such as sweat and tears. From this data, it may also be possible to understand health status and mood. If the substrate 1 is insulating, the insulating film 2 is not necessary.

[0020] The gate electrode 13 is not particularly limited as long as it is connected to the graphene channel 3 via the solution 12, and may be made of the same material as the source / drain electrodes 4, 5 or the wiring metal 6. Silver-silver chloride electrodes (Ag / AgCl), calomel electrodes, palladium-hydrogen electrodes (Pd / H2), etc., which have excellent stability and reproducibility of the electrode potential in the solution 12 are preferred.

[0021] The receptor layer 10 captures only the target substance 14 and does not capture other substances 15. The receptor layer 10 is appropriately selected according to the target substance 14. For example, if the target substance 14 is a molecule, the receptor layer 10 is preferably a corresponding molecular template. If the target substance 14 is an ion, the receptor layer 10 is preferably a corresponding ionophore. If the target substance 14 is an antigen such as a hormone, the receptor layer 10 is preferably a corresponding antibody. If the target substance 14 is a nucleic acid molecule, the receptor layer 10 is preferably a corresponding nucleic acid (DNA, RNA) aptamer. If the target substance 14 is an amino acid and a protein, the receptor layer 10 is preferably a corresponding peptide aptamer.

[0022] The dam material 11 seamlessly surrounds the opening region of the graphene channel 3 and the gate electrode 13, preventing the solution 12 containing the target substance 14 and non-target substance 15 from leaking out and spilling from the contact surface between the dam material 11 and the passivation membrane 789, and is positioned so that the solution 12 remains in the opening region of the graphene channel 3 for a certain period of time. It is preferable that the thickness be 1 mm or more to prevent the chemical solution (solution 12) from spilling. The dam material 11 may also be arranged in a double layer.

[0023] Furthermore, since the dam material 11 needs to completely immerse the opening region of the graphene channel 3 in the solution 12, it is preferable that the dam material 11 has water-repellent properties that prevent the solution 12 from spreading easily. Therefore, the dam material 11 is formed, for example, from silicone rubber. However, this is not necessarily required if the gate electrode 13 is connected to the graphene channel 3 via the solution 12.

[0024] Solution 12 is not particularly limited as long as it is a liquid capable of forming an electrical double layer, but a phosphate-buffered saline (PBS) or the like that can maintain a constant pH is preferred in order to ensure the characteristic stability of the graphene transistor.

[0025] Figure 1-2 is a schematic cross-sectional view showing the layer structure of the passivation layer 789 of the graphene transistor according to this embodiment. The adhesion layer 7 uses, for example, Al2O3, the stress relaxation layer 8 uses, for example, SiO2, and the protective layer 9 uses, for example, Si3N4.

[0026] The passivation film 789 is a laminated film comprising, in this order, an adhesion layer 7 which is an example of a first layer (film) to ensure adhesion to the substrate 1, a stress relaxation layer (insulating layer) 8 which is an example of a second layer (film), and a protective layer 9 which is an example of a third layer (film) to prevent penetration of the measurement solution 12.

[0027] The adhesion layer 7 is provided on the insulating film 2, on the outer periphery of the graphene channel 3, on the source and drain electrodes 4 and 5 connected to the graphene channel 3, and on the wiring metal 6 routed on the insulating film 2.

[0028] The adhesion layer 7 is provided on the insulating film 2, the outer periphery of the graphene channel 3, the source and drain electrodes 4 and 5 connected to the graphene channel 3, and the wiring metal 6 routed on the insulating film 2. This improves the adhesion of the entire passivation film 789 and prevents delamination from the underlying structure during immersion in solution. In particular, it is effective in achieving stable bonding with the entire passivation film 789 while taking advantage of the chemical properties and smoothness of the graphene surface.

[0029] Furthermore, the gas components contained within the graphene channel 3, as well as the gas components contained in the stress relaxation layer (insulating layer) 8 and protective layer 10, which are released due to the manufacturing of the graphene transistor, can be prevented from diffusing into the source and drain electrodes 4 and 5 and the wiring metal 6 routed on the insulating film 2. Therefore, in the region where the adhesion layer 7 is formed, the gas components released from the graphene transistor, the stress relaxation layer (insulating layer) 8 and protective layer 9 can be prevented from accumulating between these layers and the adhesion layer 7.

[0030] Most of the gas components contained within the graphene channel 3 are released when the adhesion layer 7 is formed on the graphene transistor surface, but some gas components remain. These remaining gas components are released from the graphene channel 3 when the graphene transistor is in use. The adhesion layer 7 absorbs some of the gas components remaining in the graphene channel 3, suppressing their release to the outside.

[0031] Materials that can form the adhesion layer 7 include oxides such as alumina (Al2O3), titanium oxide (TiO2), zinc oxide (ZnO), hafnium oxide (HfO2), and ZrO2. In particular, Al2O3 has good compatibility with graphene, and oxide-based materials can also ensure insulation, thus preventing interference with electronic properties such as an increase in leakage current to the date electrode 13 during solution immersion.

[0032] The thickness of the adhesion layer 7 can be designed as appropriate, preferably 10 nm to 40 nm, particularly preferably 15 nm to 35 nm, and even more preferably 10 nm to 20 nm. If the thickness of the adhesion layer 7 is within the above preferred range, it will suppress the occurrence of cracks in the adhesion layer 7 and allow it to perform its function as an adhesion layer 7.

[0033] In this embodiment, the thickness of the adhesion layer 7 refers to the thickness in the perpendicular direction at a predetermined surface position of the adhesion layer 7. The thickness of the adhesion layer 7 is, for example, the thickness measured at any point in the cross-section of the adhesion layer 7. If several measurements are taken at arbitrary locations in the cross-section of the adhesion layer 7, the average value of the thicknesses at these measurement points may be used. The thicknesses of the stress relaxation layer 8 and the protective layer 9 can also be measured in the same way as the adhesion layer 7.

[0034] The method for manufacturing the adhesion layer 7 is not particularly limited, and general film deposition methods such as vapor deposition, sputtering, and CVD can be used. However, it is more preferable that it be formed by atomic layer deposition (ALD). ALD is a vacuum film deposition technique that utilizes the self-regulating properties of atoms to deposit thin films one atomic layer at a time on the target of deposition: the insulating film 2, graphene channel 3, source / drain electrodes 4 and 5, and wiring metal 6. Compared to vapor deposition (CVD), ALD can form thin films with fewer film defects and can deposit films uniformly.

[0035] Furthermore, by selecting appropriate oxidizing agents and precursors, the thermal ALD method can be performed at film deposition temperatures of 100-200°C, effectively minimizing thermal damage to graphene. Additionally, because it does not use plasma, it minimizes plasma damage to graphene.

[0036] When using ALD to form an adhesion layer 7 in the region containing graphene channels 3, it is desirable to use an aluminum compound or a zirconia compound. This is because these materials have high vapor pressure and surface reactivity, and even for materials like graphene, which ideally do not have unbonded hands on the surface and are less prone to surface reactions in the first layer, rapid film formation is possible even at low temperatures (around 100°C).

[0037] The aluminum compound can be any gaseous component containing aluminum that can be vaporized; for example, trimethylaluminum (TMA), triethylaluminum (TEA), and trichloroaluminum can be used. The zirconia compound can be, for example, diethyl ketaneous zirconium (Zr(thd)4).

[0038] Any oxidizing agent capable of oxidizing aluminum compounds can be used, such as water vapor (H2O). Furthermore, when forming an adhesion layer 7 in the region containing graphene channels 3, water vapor may be used as the oxidizing agent only during the initial film formation phase, and then switched to ozone midway through. Using water vapor results in a higher film formation rate, making initial nucleation easier. Subsequently, using ozone results in fewer carbon atoms and impurities in the film, and because ozone reacts more readily at lower temperatures compared to water vapor, a high-density, good film can be formed even at temperatures of 100-200°C. In the case of zirconia compounds, it is preferable to use ozone instead of water vapor from the viewpoint of reaction stability.

[0039] The reaction temperature is preferably 150°C or lower. If water vapor is used as an oxidizing agent for only a few cycles during the initial film formation phase, the temperature is preferably 250°C or lower. Performing the reaction at this temperature helps to suppress thermal damage to the graphene channels 3.

[0040] The adhesion layer 7 not only ensures adhesion between the graphene channel 3, source / drain electrodes 4, 5, and wiring metal 6 and gas components, including oxygen and water vapor, generated from the stress relaxation layer 8 and protective layer 9, but also plays a role in preventing them from penetrating the graphene channel 3, source / drain electrodes 4, 5, and wiring metal 6 and causing adverse effects. For this reason, it is preferable that the adhesion layer 7 be formed to cover at least the area where the stress relaxation layer 8 and protective layer 9 are formed.

[0041] The stress relaxation layer 8 is provided on the entire surface, including the adhesion layer 7, except for the openings of the graphene channels 3. This layer functions as an intermediate layer that disperses film stress, improves the thermal stability of the film structure, suppresses film delamination and crack formation due to temperature changes, and enhances mechanical durability.

[0042] The thickness of the stress relaxation layer 8 can be designed as appropriate, preferably 5 nm to 70 nm, particularly preferably 10 nm to 60 nm, and even more preferably 15 nm to 45 nm. If the film thickness is too thin, the stress relaxation effect will be insufficient, and cracks and delamination will easily occur in the passivation film 789. If it is too thick, the overall film thickness of the device will increase, and the microfabrication process will become more complex. In particular, when the adhesion layer 7 is alumina deposited by the ALD method, it is desirable that the thickness be 5 times or more the thickness of the alumina. In the case of a graphene transistor without a stress relaxation layer 8, if alumina is used for the adhesion layer 7, tensile stress exists, and the passivation film 789 is prone to cracking. On the other hand, when SiO2 is used for the stress relaxation layer 8, compressive stress σ i Therefore, a stress t in the opposite direction exists with respect to the adhesion layer 7. i By combining materials and film thicknesses in which the following exists, the total stress sum σ of the passivation film 789 is obtained as shown in equation (1) below. tоtal It can be brought closer to zero. σ total =Σσ i ·t i =0···(1)

[0043] The stress relaxation layer 8 should preferably be made of a material with a thermal expansion coefficient intermediate between that of the adhesion layer 7 and the protective layer 9. This will alleviate the difference in thermal expansion coefficients and mechanical stress between the substrate 1 and the protective layer 9.

[0044] The stress relaxation layer 8 preferably contains, for example, silicon oxide (SiO2), aluminum nitride (AlN), silicon nitride (Si3N4), or zirconium oxide (ZrO2). Silicon oxide (SiO2) is particularly preferred because it has a low coefficient of thermal expansion and is stable as a thin film.

[0045] The method for manufacturing the stress relaxation layer 8 is not particularly limited, and general film deposition methods such as vapor deposition and sputtering can be used. However, it is preferable to deposit the film using the ALD method in order to control the film thickness to be thin and uniform.

[0046] It is preferable that the defect density of the stress relaxation layer 8 is greater than the defect density of the protective layer 9. If the stress relaxation layer 8 has a higher defect density than the protective layer 9, even if the protective layer 9 is formed on the surface of the stress relaxation layer 8, a portion of it will easily penetrate the surface of the stress relaxation layer 8, resulting in high adhesion. In addition, it will be easier to release the stress when the layers are laminated.

[0047] The defect density may be measured using a scanning electron microscope (SEM), optical microscope, or transmission electron microscope (TEM). The defect density is determined by calculating the number of voids per unit area of ​​the cross-section of the stress relaxation layer 8, based on images obtained by observing the cross-section of the stress relaxation layer 8 using an SEM, TEM, etc. Defects may be point defects, line defects, or surface defects.

[0048] Furthermore, the stress relaxation layer 8 also plays a role in suppressing adverse effects caused by gaseous components including oxygen and water vapor generated from the protective layer 9, as well as moisture and ions from the measurement solution that have permeated the protective film 9, entering the graphene channel 3, source and drain electrodes 4 and 5, and wiring metal 6. For this reason, it is preferable to form the stress relaxation layer 8 in the region where the protective layer 9 is formed.

[0049] The protective layer 9 is provided on at least the entire surface including the graphene transistor and the stress relaxation layer 8, thereby protecting the outer periphery of the internal graphene channel 3, source and drain electrodes 4 and 5, and wiring metal 6 from the measurement solution 12 and the environment, both physically and chemically. This prevents the ingress of the solution 12, suppresses metal corrosion, and improves device reliability during long-term use.

[0050] The thickness of the protective layer 9 can be designed as appropriate, preferably 10 nm to 500 nm, particularly preferably 20 nm to 4000 nm, and even more preferably 30 nm to 200 nm. If the film thickness is too thin, protection from moisture and chemicals contained in the solution 12 will be insufficient, shortening the lifespan of the device. If it is too thick, process costs will increase and electrical insulation performance will fluctuate significantly.

[0051] The material for the protective layer 9 is preferably, for example, silicon nitride (Si3N4), aluminum oxide (Al2O3), hafnium oxide (HfO2), or tantalum oxide (Ta2O5). Silicon nitride (Si3N4) is particularly preferred because it has high chemical resistance and insulating properties, as well as high durability in solution. In addition, a fluorinated polymer film (for example, a fluorinated alkylsilane that can be deposited by ALD) may be formed on the outermost layer to improve water repellency.

[0052] The method for manufacturing the protective layer 9 is not particularly limited, and general film formation methods such as vapor deposition and sputtering can be used. However, it is preferable to form the film by ALD in order to uniformly control the film thickness.

[0053] The following is an example of a multilayer film. Substrate 1 → Al2O3 (50nm) → SiO2 (100nm) → Si3N4 (100nm) tAl2O3<tSiO2,tSiO2> >tSi3N4 When Al2O3 is used for the adhesion layer 7, trimethylaluminum (TMA) can be used as a precursor. Since TMA is highly reactive with oxidizing agents such as ozone and water, it promotes interfacial reactions as an initial layer, improving interfacial adhesion with the graphene channel 3, source / drain electrodes 4 and 5, and wiring metal 6. When SiO2 is used for the stress relaxation layer 8, SiO2 has the effect of mitigating the difference in thermal expansion and dispersing stress. In addition, since SiO2 is chemically compatible with Al2O3 and Si3N4, it has the effect of improving adhesion.

[0054] When Si3N4 is used for the protective layer 9, its high water resistance and mechanical strength prevent the penetration of solution 12 and prevent unintended damage during measurement operations.

[0055] The openings in the passivation layer 789 are preferably formed using dry etching from the viewpoint of precise process control and reduction of contamination risk. On the other hand, since the graphene channel 3 readily reacts with plasma, the dry etching process cannot be used near the graphene channel 3. With this layered configuration, Si3N4→SiO2 can be etched simultaneously with the dry etching process of carbon tetrafluoride (CF4), and then Al2O3 can be wet-etched (using an etchant mixed with HF, H2SO4, HCl, HNO3, and H3PO4) to prevent plasma damage to the graphene channel 3 and perform processing with a lower contamination risk.

[0056] The reasons why ALD is preferable to CVD for forming the adhesion layer 7, stress relaxation layer 8, and protective layer 9 will be explained. Generally, when the adhesion layer 7, stress relaxation layer 8, and protective layer 9 are deposited by CVD, these layers tend to contain many impurities. Also, because CVD has a fast deposition rate (e.g., 10 nm / s to 15 nm / s), the layers become thick enough to affect the film stress characteristics, making it difficult to control the deposition of the adhesion layer 7 to a thickness of several tens of nanometers.

[0057] In contrast, ALD deposits the film atom by atom, resulting in a slower deposition rate than CVD. This reduces the likelihood of defects such as particles adhering to the interior or back surface of the passivation layer 789, thus producing fewer film defects compared to CVD. Furthermore, the coverage is better when the passivation layer 789 is formed using ALD than with CVD. Even if the graphene transistor has a conformal shape, the film can be deposited with a nearly uniform thickness that conforms to the shape of the graphene transistor.

[0058] When dissimilar materials such as the adhesion layer 7, stress relaxation layer 8, and protective layer 9 are used to cover the entire surface of dissimilar and irregularly shaped regions such as the graphene channel 3, source and drain electrodes 4 and 5, and wiring metal 6, it is difficult to control the film thickness of the adhesion layer 7, stress relaxation layer 8, and protective layer 9 to several tens of nanometers using CVD because the film thickness on the sides of the source and drain electrodes 4 and 5 becomes thinner and seams are more likely to occur. In contrast, ALD is a film deposition method that uses surface reactions, so even with a thin film of 1 nm, the film thickness of the adhesion layer 7, stress relaxation layer 8, and protective layer 9 can be made nearly uniform.

[0059] Figure 2-1 shows an example in which a seed layer 16 is introduced to facilitate the deposition of an adhesion layer 7 by ALD in the region including the graphene channel 3 in the graphene transistor according to this embodiment. Figure 2-2 shows an example of the ALD deposition rate on and off the graphene channel. In Figure 2-2, the vertical axis represents the film thickness, and the horizontal axis represents the number of ALD deposition cycles. Using ALD for deposition of the adhesion layer 7 has the effect of reducing plasma damage, thermal damage, and oxidizer damage to two-dimensional materials (graphene, TMDS, MoS2, etc.). However, there is a disadvantage in that ALD deposition does not proceed until physicoadsorption occurs probabilistically on the graphene channel 3, because ideally there are no unbonded hands on the graphene channel 3 that can undergo a surface reaction with the ALD precursor (see Figure 2-2).

[0060] The seed layer 16 is formed by depositing a few nanometers of the same material as the adhesion layer 7, such as alumina, using sputtering, vapor deposition, or PECVD. Alternatively, the seed layer 16 can also be obtained by using the same material as the adhesion layer 7, such as alumina, in the ALD method, using water as the oxidizing agent, at a low temperature of about 100°C, and extending the pulse and purge times to more than twice that of the adhesion layer 7 formation. Compared to deposition by sputtering or CVD, this method has the effect of reducing thermal and plasma damage to the substrate 1 and improving handling because the process up to the adhesion layer 7 can be carried out in the same apparatus.

[0061] The seed layer 16 can also be formed by forming a metal or semiconductor, which reacts with an oxidizing agent during ALD to form the same compound as the adhesion layer 16, by vacuum deposition or sputtering. For example, when the adhesion layer 7 is alumina, it can be obtained by depositing several nanometers of aluminum by vapor deposition.

[0062] When performing ALD, any material that reacts with an oxidizing agent such as water or ozone may be used as the seed layer 16 even if its oxide is not the same substance as the adhesion layer 7, like Ti, Ta, and the like. In particular, TiCl4, which is used as a titanium precursor, has high reactivity with oxidizing agents, so that the uniformity of the thickness of the seed layer 16 can be improved when a film is formed on graphene by ALD.

[0063] FIG. 3-1 is a diagram for explaining a configuration in which the protective layer 9, which has a small difference in coefficient of thermal expansion from the substrate 1, is also arranged in the lowermost layer to further alleviate the difference in coefficient of thermal expansion on the graphene channel 3 in the graphene transistor according to the present embodiment. That is, the protective layer 9 is an example of a protective layer formed on the outer periphery of the graphene channel 3 and on the source and drain electrodes 4 and 5.

[0064] Thin films formed by CVD and PVD generally contain impurities such as carbon and water immediately after deposition, so post-deposition annealing has the effects of relieving internal stress in the film, improving adhesion between stacked films or between the film and substrate, improving surface flatness, and improving insulating property and chemical stability by thermally decomposing impurities in the film. On the other hand, if annealing is performed at a high temperature, film peeling and cracks are likely to occur in stacked films due to the difference in coefficient of thermal expansion.

[0065] As an example, the coefficients of thermal expansion are Al2O3 (8.1×10 -6 K -1 ), SiO2 (0.5×10 -6 K -1 ), Si3N4 (2.8×10 -6 K -1 ), which are given as examples. By changing the stacking order such that the difference in coefficient of thermal expansion between the upper and lower layers, and between the substrate 1 and the adhesion layer 7 is reduced, there is an effect of reducing the risk of film peeling due to thermal expansion.

[0066] Figure 3-2 illustrates an example in which an intermediate layer 17 is inserted between the adhesion layer 7 and the stress relaxation layer 8 in order to further reduce the difference in thermal expansion coefficients in the film thickness direction of the passivation film 789 in the graphene transistor according to this embodiment. That is, the intermediate layer 17 is an example of a second intermediate layer formed between the adhesion layer 7 and the stress relaxation layer 8. In the case of a passivation film 789 with the configuration of substrate 1 → Al2O3 (50 nm) → SiO2 (100 nm) → Si3N4 (100 nm), for example, the intermediate layer 17 is HfO2 (thermal expansion coefficient: 5.9 × 10⁻⁶). -6 K -1 ), AlN(4.2×10 -6 K -1 ), silicon dioxide-aluminum oxide mixture (4.5-7.5 × 10 -6 K -1 ), SiOx silicon nitride-silicon oxide mixture (2.8~6.0 × 10 -6 K -1 ), tantalum oxide (6.5 × 10 -6 K -1 ), scandium oxide (6.1 × 10⁻⁶ -6 K -1 ) If the main concern is mitigating the difference in thermal expansion coefficients, the use of HfO2, AlN, and Al2O3-SiO2 is preferable; if insulation and adhesion are important, the use of ZrO2 or Ta2O5 is preferable; and if flexibility in the film deposition and etching processes is to be ensured, Al2O3-SiO2 and SiOx-SiN x Use is desirable.

[0067] The thickness of the intermediate layer 17 is preferably around 20-50 nm from the viewpoint of mitigating the difference in thermal expansion coefficients and stress relaxation. If the thickness is too thin or too thick, the stress relaxation effect will be insufficient, and cracks and delamination will easily occur in the passivation film 789.

[0068] The method for manufacturing the intermediate layer 17 is not particularly limited, and general film formation methods such as vapor deposition, sputtering, and CVD can be used. However, it is more preferable that it be formed by atomic layer deposition (ALD).

[0069] Figures 4-1 to 4-4 show an example of a structure in which a protective layer 9 and a stress relaxation layer 8 are alternately stacked in a mille-feuille-like fashion to improve the barrier properties against the measurement solution 12. That is, the protective layer 9 and the stress relaxation layer 8 are alternately stacked on the adhesion layer 7. By using the ALD method to alternately stack a highly water-resistant film (e.g., Si3N4) and a buffer film (e.g., SiO2) with a thickness of 10 nm or less, each material has different permeability, which complicates the entry paths of moisture and oxygen, thus improving the barrier properties against water and oxygen.

[0070] Furthermore, films that have high moisture barrier properties but are difficult to form uniformly (for example, SiN x By alternately depositing a uniform, low-defect film (e.g., Al2O3) with a thickness of 10 nm or less, defects such as pinholes generated during film formation are prevented from spreading in the film thickness direction, which has the effect of extending the lifespan of the passivation film 789 (see Figure 4-2).

[0071] Also, films with high mechanical strength and hardness (for example, SiN x By alternately stacking layers of film (e.g., SiO2) with mechanical strength, it is possible to prevent defects such as cracks caused by mechanical impact from propagating in the film thickness direction, thereby improving mechanical resistance (see Figure 4-3).

[0072] Furthermore, films that have excellent acid and alkali resistance but are difficult to form uniformly (for example, SiN x By alternately layering films that allow for uniform and low-defect deposition (e.g., Al2O3), the entry pathways for acids and alkalis become more complex, which further improves the barrier properties against acids and alkalis (see Figure 4-4).

[0073] Figure 4-5 shows an example of alternately stacking a protective layer 9 and a stress-relaxing layer 8 to improve the dispersion of film stress. By alternately stacking a stress-relaxing layer 8 (e.g., SiO2) with low compressive stress and a protective layer 9 (e.g., Al2O3) with high tensile stress, the stress distribution in the film thickness direction becomes more uniform.

[0074] Furthermore, other candidate materials such as ZrO2, HfO2, and TiO2 can also be applied. ZrO2 has higher barrier properties and heat resistance than Al2O3, thus enhancing resistance in higher temperature and humidity environments. HfO2, when used as a substitute for SiO2 (stress relaxation layer 8), has very high insulating properties and water resistance, thus further reducing leakage current from the wiring electrode 6 into the solution 12.

[0075] Figures 5-1 and 5-2 illustrate an example of further mitigating the difference in stress distribution and thermal expansion coefficient in the thickness direction of the passivation film 789 in the graphene transistor according to this embodiment. In Figure 5-2, the vertical axis represents the composition ratio, and the horizontal axis represents the film thickness. The graphene transistor according to this embodiment may also include an intermediate layer 7.5 (e.g., (Al2O3)x-(SiO2)1-x) made of materials constituting the adhesion layer 7 and the stress relaxation layer 8, and an intermediate layer 8.5 (e.g., (SiO2)x-(Si3N4)1-x) made of materials constituting the stress relaxation layer 8 and the protective layer 9.

[0076] The manufacturing method for the adhesion layer 7, intermediate layer 7.5, stress relaxation layer 8, intermediate layer 8.5, and protective layer 9 is more preferably carried out by atomic layer deposition (ALD).

[0077] The compositions of intermediate layers 7.5 and 8.5 are formed by controlling the pulse time and purge time of the precursor and oxidizer during film deposition of the adhesion layer 7, stress relaxation layer 8, and protective layer 9 using the ALD method, thereby changing the composition in the film thickness direction. As shown in Figure 5-2, the gradual change in the film composition ratio in the film thickness direction reduces the stress difference and the difference in thermal expansion coefficients between different materials at the interface, which helps to prevent delamination, splitting, and cracking.

[0078] Figure 6-1 illustrates an example of enhancing water resistance in a graphene transistor according to this embodiment. In the graphene transistor according to this embodiment, the adhesion to the substrate 1 is further enhanced by introducing a plasma-treated layer 17 at the substrate 1 interface. Before ALD treatment, the surface of the substrate 1 is subjected to plasma treatment or oxidation treatment to form a plasma-treated layer 17 with enhanced interfacial bonding. The formation of interfacial bonding between the plasma-treated layer 17 and the adhesion layer 7 has the effect of preventing water intrusion.

[0079] If substrate 1 is graphene, a wattage of 5-50W and a processing time of approximately 5 minutes are desirable because graphene reacts easily with plasma. In particular, if you want to protect the structure of the graphene as much as possible, a wattage of 10-20W and a processing time of 30-60 seconds are desirable.

[0080] Furthermore, oxygen plasma can introduce oxygen-containing functional groups (-OH,-COOH) to the surface, thus improving adhesion with the adhesion layer 7 containing oxides (e.g., Al2O3). Argon plasma cleans the surface by physically etching it without introducing chemical changes, thereby improving adhesion. Nitrogen and ammonia plasmas introduce nitrogen-containing functional groups (-NH) to the surface, thus improving adhesion with the adhesion layer containing nitrides (e.g., SiN x It has the effect of improving adhesion with )

[0081] Figure 6-2 illustrates an example of enhanced water resistance in a graphene transistor according to this embodiment. This embodiment improves the adhesion between the adhesion layer 7 and the stress relaxation layer 8 by introducing a plasma-treated layer 17 at the interface between the adhesion layer 7 and the stress relaxation layer 8.

[0082] If the stress relaxation layer 8 is an oxide such as SiO2, performing oxygen, carbon dioxide, or ozone plasma treatment will have the effect of improving adhesion because the ALD precursor forms a strong interfacial bond with the oxygen-containing groups (-OH, -COOH) of the plasma-treated layer 17.

[0083] Figure 6-3 illustrates an example of enhancing water resistance in a graphene transistor according to this embodiment. By introducing a plasma-treated layer 17 at the interface between the stress-relaxing layer 8 and the protective layer 9, the adhesion to the substrate 1 is further improved. If the protective layer 9 is a nitrogen-containing material such as SiN, performing nitrogen or ammonia plasma treatment will cause the ALD precursor to form a strong interfacial bond with the nitrogen-containing functional group (-NH) of the plasma-treated layer 17, thereby further improving adhesion.

[0084] Figure 7-1 illustrates an example of improving the adhesion at the interface between the adhesion layer 7 and the stress relaxation layer 8 in a graphene transistor according to this embodiment. In the graphene transistor according to this embodiment, the porous layer 18 may be formed on top of the adhesion layer 7. This increases the contact area between the adhesion layer 7 and the stress relaxation layer 8, thus further improving adhesion.

[0085] The porous layer 18 is formed by repeatedly forming layers of each material in small increments of a few nanometers using the ALD method, when the adhesion layer 7 is Al2O3 and the stress relaxation layer 8 is SiO2, and then immersing the layers in an etching solution containing H3PO4 and HF.

[0086] Figure 7-2 illustrates an example of improving the adhesion at the interface between the stress relaxation layer 8 and the protective layer 9 in a graphene transistor according to this embodiment. In the graphene transistor according to this embodiment, the porous layer 18 may be formed on top of the stress relaxation layer 8. This increases the contact area between the stress relaxation layer 8 and the protective layer 9, thus further improving adhesion.

[0087] The porous layer 18 can be formed by repeatedly forming each material in layers of a few nanometers using the ALD method, when the stress relaxation layer 8 is SiO2 and the protective layer 9 is Si3N4, and then immersing the layers in an etching solution containing HNO3 and HF.

[0088] Figure 8 illustrates an example of enhancing the water repellency of the protective layer 9 in a graphene transistor according to this embodiment. The graphene transistor according to this embodiment has a lotus structure layer 21 having a lotus structure on the protective layer 9. According to the Cassie model, in order to draw sufficient air into the grooves and increase the contact angle of the solution 12 due to surface tension, it is desirable that the height of the lotus structure layer 21 be about 1 to 10 μm and the pitch be about twice the height.

[0089] Furthermore, after the formation of the lotus structure layer 21, water-repellent chemicals (fluorine-containing silanes (e.g., CF3(CF2)5CH2CH2SiCl3), silicon compounds (e.g., ODTS or PDMS), or self-assembled monolayers (SAMs)) may be applied. These chemicals are immobilized by decontamination of the surface with oxidizing plasma or alcohol, followed by deposition, spin coating, or immersion processes, and then heat treatment as needed.

[0090] Furthermore, fluorine plasma treatment may be performed to further enhance water repellency. For plasma treatment with fluorine gas (e.g., CF4, C4F8, etc.), a plasma power of approximately 50-200W and a treatment time of approximately 20 seconds to 3 minutes are desirable to minimize surface damage to substrate 1. In addition, to improve surface stability, it is desirable to wash the surface with an inert gas (e.g., N2 or Ar) for approximately 1-9 minutes to remove excess fluorinated material. Fluorination has the effect of increasing the contact angle to 90-120 degrees.

[0091] Figure 9-1 illustrates an example of a graphene transistor according to this embodiment in which water resistance has been enhanced. In this embodiment, the graphene transistor may also be configured such that a getter material layer 22 is formed between the adhesion layer 7 and the stress relaxation layer 8 to prevent the diffusion of moisture to the substrate 1, source and drain electrodes 4 and 5, and wiring metal 6. The getter material layer 22 has the effect of reducing corrosion and performance degradation due to moisture, and improving operational stability in aqueous solution environments, by adsorbing moisture and chemical substances contained in the solution 12 that has penetrated the protective layer 9.

[0092] The getter layer 22 may contain one or more metals selected from the group of metals such as Ba, Ca, Mg, Ti, V, Zr, Nb, Mo, Ta, Th, and Ce. The getter layer 22 may also contain one or more metal alloys selected from the group of metal alloys such as Ba-Al, Zr-Al, Ag-Ti, and Zr-Ni. While pure metals offer higher adsorption capacity and the ability to adsorb impurities over a wider concentration range compared to alloys, they may be more susceptible to oxidation, resulting in a shorter lifespan. On the other hand, alloying allows for adjustment of oxidation resistance and adsorption capacity, and improves physical strength and uniformity during film formation.

[0093] The method for manufacturing the getter material layer 22 is not particularly limited, and general film formation methods such as vapor deposition and sputtering can be used. However, it is more preferable that it be formed by atomic layer deposition (ALD).

[0094] The thickness of the getter material layer 22 can be designed as desired, preferably 3 nm to 100 nm, particularly preferably 5 nm to 75 nm, and even more preferably 10 nm to 50 nm. If the film thickness is too thin, the adsorption capacity of moisture and chemical substances contained in the solution 12 that has penetrated the protective layer 9 will be insufficient, and if it is too thick, it will lead to increased stress, raising the risk of film delamination and cracking.

[0095] Figure 9-2 illustrates an example of enhanced water resistance in a graphene transistor according to this embodiment. In this embodiment, a getter material layer 22 is formed between the protective layer 9 and the stress relaxation layer 8 to prevent the diffusion of moisture to the substrate 1, source and drain electrodes 4 and 5, and wiring metal 6. Adsorption near the protective layer 9 reduces performance degradation due to corrosion and moisture in the short term and improves operational stability in aqueous solution environments.

[0096] Figure 10 illustrates an example of further mitigating the stress concentrated in the channel opening of the graphene transistor in this embodiment. In this embodiment, the graphene transistor may have tapers formed on the source and drain electrodes 4 and 5, the wiring metal 6, and the passivation film 789. This disperses the stress concentration around the edge near the opening of the graphene channel 3, which has the effect of preventing film delamination and cracking.

[0097] Figure 11 is a plan view and a cross-sectional view of the graphene transistor according to this embodiment, in which the gate electrode is arranged on the chip. The graphene transistor according to this embodiment has the effect of being miniaturized compared to Figure 1 because the gate electrode 13 is arranged on the chip (insulating film 2).

[0098] Figure 12 illustrates an example in which the gate electrode is placed on a chip of the graphene transistor according to this embodiment. In the graphene transistor according to this embodiment, when the gate electrode 13 is placed on a chip (insulating film 2), the dam material 11 may also be a sealed channel. Since the top of the dam material 11 is not open, it has the effect of preventing evaporation of the solution 12 during measurement. In addition, by transporting the solution 12 using a micropump or the like instead of manually, it has the effect of suppressing variations in the amount and rate of solution 12 input. As a result, it has the effect of suppressing variations in the time variation of the current-voltage characteristics of the solution gate transistor.

[0099] Thus, the graphene transistor according to this embodiment can have barrier properties to solutions and electrical insulation (stability). [Explanation of Symbols]

[0100] 1 circuit board 2 insulating film 3 channels 4 Source electrodes 5 Drain electrode 6 wiring metal 7. Contact layer 8. Stress relaxation layer 9 Protective layer 789 Passivation membrane 10 Receptive layer 11 Dam materials 12 solution 13 gates 14 Target substance 15 Non-target substances [Prior art documents] [Patent Documents]

[0101] [Patent Document 1] Japanese Patent Publication No. 2024-114337

Claims

1. In a solution-gate FET transistor having graphene in the channel, A first layer is formed on the outer periphery of the channel and on the source electrode and drain electrode, and a second layer is formed on the first layer. The first layer has better solution barrier properties than the second layer. A semiconductor device wherein the second layer has better adhesion to the channel than the first layer.

2. A first intermediate layer is formed between the first layer and the second layer. The semiconductor device according to claim 1, wherein the first intermediate layer has residual stress in the opposite direction to the residual stress of the first layer.

3. The semiconductor device according to claim 2, wherein the thermal expansion coefficient of the first intermediate layer is a value between the thermal expansion coefficient of the first layer and the thermal expansion coefficient of the second layer.

4. The semiconductor device according to claim 3, wherein the first layer, the second layer, and the first intermediate layer are formed of an insulating material.

5. The first layer is Al ２ O ３ A semiconductor device according to claim 1, formed by the above.

6. The second layer is Si ３ N ４ A semiconductor device according to claim 5, formed by the above.

7. The first layer is Al ２ O ３ Formed by, The second layer is Si ３ N ４ Formed by, The first intermediate layer is SiO ２ formed according to any one of claims 1 to 2, the semiconductor device according to claim 3.

8. The semiconductor device according to claim 1, wherein a protective layer is formed on the outer periphery of the channel and on the source electrode and drain electrode.

9. The semiconductor device according to claim 2, wherein a second intermediate layer is formed between the first layer and the first intermediate layer.

10. The semiconductor device according to claim 2, wherein the second layer and the first intermediate layer are alternately stacked on the first layer.

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