Semiconductor equipment

Abstract

To provide a semiconductor device with reduced on-resistance. [Solution] The semiconductor device of the embodiment comprises: a first transistor region including at least one transistor unit; a second transistor region including at least one transistor unit and provided in a first direction relative to the first transistor region; a first diode region provided between the first transistor region and the second transistor region and including at least one diode unit; a second diode region provided between the first diode region and the second transistor region and including at least one diode unit; and a third transistor region provided between the first diode region and the second diode region and including one transistor unit.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] A vertical metal oxide semiconductor field effect transistor (MOSFET) using silicon carbide incorporates a pn junction diode as an internal diode. For example, a MOSFET is used as a switching element connected to an inductive load. In this case, even when the MOSFET is off, the internal diode allows for freewheeling current to flow.

[0003] However, when a freewheel current is passed through using a body diode, stacking faults grow in the silicon carbide layer due to the carrier recombination energy, which increases the on-resistance of the MOSFET. This increase in on-resistance leads to a decrease in the reliability of the MOSFET. For example, by providing a unipolar Schottky Barrier Diode (SBD) as an internal diode in the MOSFET, it is possible to suppress the growth of stacking faults in the silicon carbide layer. By providing an SBD as an internal diode in the MOSFET, the reliability of the MOSFET is improved.

[0004] In some cases, a large surge current may flow through a MOSFET, momentarily exceeding its steady state. When a large surge current flows, a large surge voltage is applied, causing heat generation and potentially destroying the MOSFET. The maximum allowable peak current value (I) of the surge current that a MOSFET can handle is... FSM This is called surge current withstand capability. In MOSFETs equipped with SBDs, it is desirable to improve the surge current withstand capability.

[0005] For example, in order to allow a large surge current to flow, it is conceivable to intentionally provide a diode region containing a pn junction diode in a MOSFET, the diode region not performing transistor operation. However, providing a diode region that does not perform transistor operation may increase the on-resistance per unit area of the MOSFET.

Prior Art Document

Patent Document

[0006]

Patent Document 1

Summary of the Invention

Problem to be Solved by the Invention

[0007] The problem to be solved by the present invention is to provide a semiconductor device with reduced on-resistance.

Means for Solving the Problem

[0008] The semiconductor device of the embodiment comprises: a first transistor region including at least one transistor unit; a second transistor region including at least one transistor unit and provided in a first direction relative to the first transistor region; a first diode region provided between the first transistor region and the second transistor region and including at least one diode unit; a second diode region provided between the first diode region and the second transistor region and including at least one diode unit; and a third transistor region provided between the first diode region and the second diode region and including one transistor unit, wherein the transistor unit comprises: a first silicon carbide region of a first conductivity type including a first electrode; a second electrode; a first portion provided between the first electrode and the second electrode, in contact with the first electrode and extending in a second direction perpendicular to the first direction; and a second portion in contact with the first electrode, provided in the first direction relative to the first portion and extending in a second direction; and the first silicon carbide region and the first electrode A second silicon carbide region of a second conductivity type provided between the electrode and the first electrode, electrically connected to the first electrode, extending in the second direction, and provided between the first portion and the second portion in the first direction; a third silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first electrode, electrically connected to the first electrode, extending in the second direction, provided between the second silicon carbide region and the second portion in the first direction, and separated from the second silicon carbide region; and a second silicon carbide region provided between the second silicon carbide region and the first electrode, The diode unit includes a first electrode, a second electrode, a third portion in contact with the first electrode and extending in the second direction, and a fourth portion in contact with the first electrode and provided in the first direction relative to the third portion and extending in the second direction.the first silicon carbide region including; and a fifth silicon carbide region of a second conductivity type, which is provided between the first silicon carbide region and the first electrode, is electrically connected to the first electrode, extends in the second direction, and is continuously provided in the first direction between the third portion and the fourth portion, wherein a first distance in the first direction between the first portion and the second portion is equal to a second distance in the first direction between the third portion and the fourth portion. , [BRIEF DESCRIPTION OF THE DRAWINGS]

[0009] [Figure 1] A schematic top view of the semiconductor device according to the first embodiment. [Figure 2] A partial schematic top view of the semiconductor device according to the first embodiment. [Figure 3] A partial schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 4] A partial schematic top view of the semiconductor device according to the first embodiment. [Figure 5] A partial schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 6] A partial schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 7] An equivalent circuit diagram of the semiconductor device according to the first embodiment. [Figure 8] An explanatory diagram of the operation and effects of the semiconductor device according to the first embodiment. [Figure 9] An explanatory diagram of the operation and effects of the semiconductor device according to the first embodiment. [Figure 10] A partial schematic top view of the semiconductor device of a comparative example. [Figure 11] A partial schematic cross-sectional view of the semiconductor device of a comparative example. [Figure 12] A diagram illustrating problems of the semiconductor device of a comparative example. [Figure 13] An explanatory diagram of the operation and effects of the semiconductor device according to the first embodiment. [Figure 14] A partial schematic top view of the semiconductor device according to a first modification of the first embodiment. [Figure 15] A partial schematic cross-sectional view of the semiconductor device according to a first modification of the first embodiment. [Figure 16] A schematic top view of a part of the semiconductor device according to a second modification of the first embodiment. [Figure 17] A schematic cross-sectional view of a part of the semiconductor device according to the second embodiment. [Figure 18] A schematic cross-sectional view of a part of the semiconductor device according to the second embodiment. [Figure 19] A schematic cross-sectional view of a part of the semiconductor device according to the third embodiment. [Figure 20] A schematic cross-sectional view of a part of the semiconductor device according to the third embodiment. [Figure 21] A schematic cross-sectional view of a part of the semiconductor device according to the fourth embodiment. DESCRIPTION OF EMBODIMENTS

[0010] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, the same or similar members and the like are denoted by the same reference numerals, and the description of members and the like that have been described once may be omitted as appropriate.

[0011] Further, in the following description, n + , n, n - and p + , p, p - notations represent relative levels of impurity concentration in each conductivity type. That is, n + indicates that the n-type impurity concentration is relatively higher than that of n, and n - indicates that the n-type impurity concentration is relatively lower than that of n. Further, p + indicates that the p-type impurity concentration is relatively higher than that of p, and p - indicates that the p-type impurity concentration is relatively lower than that of p. Note that n + -type, n - -type may be simply referred to as n-type, and p + -type, p - -type may be simply referred to as p-type in some cases.

[0012] Impurity concentrations can be measured, for example, by SIMS (Secondary Ion Mass Spectrometry). Furthermore, the relative levels of impurity concentrations can be determined, for example, from the carrier concentrations obtained by SCM (Scanning Capacitance Microscopy). Additionally, distances such as the depth and thickness of impurity regions can be determined, for example, from images obtained by SEM (Scanning Electron Microscope) or by SIMS.

[0013] In this specification, unless otherwise specified, the impurity concentration in the semiconductor region refers to the maximum impurity concentration in that semiconductor region.

[0014] (First embodiment) The semiconductor device of the first embodiment comprises: a first transistor region including at least one transistor unit; a second transistor region including at least one transistor unit and provided in a first direction relative to the first transistor region; a first diode region provided between the first transistor region and the second transistor region and including at least one diode unit; a second diode region provided between the first diode region and the second transistor region and including at least one diode unit; and a third transistor region provided between the first diode region and the second diode region and including one transistor unit. The transistor unit comprises a first electrode, a second electrode, a first silicon carbide region of a first conductivity type including a first electrode, a first portion provided between the first electrode and the second electrode and in contact with the first electrode and extending in a second direction perpendicular to the first direction, and a second portion provided in contact with the first electrode and in a first direction relative to the first portion and extending in a second direction, a second silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first electrode, electrically connected to the first electrode and extending in a second direction and provided between the first portion and the second portion in the first direction, and the first silicon carbide region and the first The device includes: a third silicon carbide region of a second conductivity type provided between the electrodes and electrically connected to the first electrode, extending in a second direction, provided between the second silicon carbide region and the second portion in the first direction, and separated from the second silicon carbide region; a fourth silicon carbide region of a first conductivity type provided between the second silicon carbide region and the first electrode, and electrically connected to the first electrode; a first gate electrode facing the second silicon carbide region and the third silicon carbide region and extending in a second direction; and a gate insulating layer provided between the first gate electrode and the second silicon carbide region and the third silicon carbide region.The diode unit includes a first silicon carbide region comprising a first electrode, a second electrode, a third portion in contact with the first electrode and extending in a second direction, and a fourth portion in contact with the first electrode, provided in a first direction relative to the third portion and extending in a second direction; and a fifth silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first electrode, electrically connected to the first electrode, extending in a second direction, and continuously provided between the third portion and the fourth portion in the first direction. The first distance in the first direction between the first portion and the second portion is equal to the second distance in the first direction between the third portion and the fourth portion.

[0015] The semiconductor device of the first embodiment is a planar gate type vertical MOSFET 100 using silicon carbide. The MOSFET 100 of the first embodiment is a Double Implantation MOSFET (DIMOSFET) in which the base region and source region are formed by ion implantation, for example. The semiconductor device of the first embodiment also includes an SBD (Shottky Barrier Diode) as an internal diode.

[0016] In the first embodiment, the case where the first conductivity type is n-type and the second conductivity type is p-type will be described as an example. MOSFET 100 is a vertical n-channel MOSFET that uses electrons as carriers.

[0017] Figure 1 is a schematic top view of a semiconductor device according to the first embodiment. Figure 1 is a diagram showing the arrangement of each region of the MOSFET 100.

[0018] As shown in Figure 1, the MOSFET 100 comprises an element region 101 and a termination region 102. The element region 101 is provided with a MOSFET and an SBD. The termination region 102 surrounds the element region 101.

[0019] The termination region 102 is provided with a structure to improve the breakdown voltage of the MOSFET 100. Examples of structures that improve the breakdown voltage of the MOSFET 100 include a resurf and a guard ring.

[0020] The first direction is one direction parallel to the top surface of MOSFET 100. The second direction is another direction parallel to the top surface of MOSFET 100 and perpendicular to the first direction.

[0021] Figure 2 is a schematic top view of a part of the semiconductor device of the first embodiment. Figure 2 corresponds to region R in Figure 1.

[0022] The MOSFET 100 includes a first transistor region 10a, a second transistor region 10b, and a third transistor region 10c. The MOSFET 100 also includes a first diode region 20a and a second diode region 20b.

[0023] Hereinafter, the first transistor region 10a, the second transistor region 10b, and the third transistor region 10c may be referred to simply as transistor region 10, either individually or collectively. Similarly, the first diode region 20a and the second diode region 20b may be referred to simply as diode region 20, either individually or collectively.

[0024] The transistor region 10 includes transistor units 10x. The diode region 20 also includes diode units 20x.

[0025] The transistor unit 10x extends, for example, in a second direction. The transistor unit 10x is positioned, for example, in a first direction.

[0026] The diode unit 20x extends, for example, in a second direction. The diode unit 20x is positioned, for example, in a first direction.

[0027] The first transistor region 10a includes at least one transistor unit 10x. The first transistor region 10a includes, for example, multiple transistor units 10x.

[0028] The first transistor region 10a includes, for example, 10 transistor units 10x. The number of transistor units 10x included in the first transistor region 10a is not limited to 10.

[0029] The second transistor region 10b is provided in a first direction relative to the first transistor region 10a. The second transistor region 10b includes at least one transistor unit 10x. The second transistor region 10b includes, for example, multiple transistor units 10x.

[0030] The second transistor region 10b includes, for example, 10 transistor units 10x. The number of transistor units 10x included in the second transistor region 10b is not limited to 10.

[0031] The first diode region 20a is provided between the first transistor region 10a and the second transistor region 10b. The first diode region 20a includes at least one diode unit 20x. The first diode region 20a includes, for example, two to ten diode units 20x.

[0032] The first diode region 20a includes, for example, two diode units 20x. The number of diode units 20x included in the first diode region 20a is not limited to two.

[0033] The second diode region 20b is provided between the first diode region 20a and the second transistor region 10b. The second diode region 20b includes at least one diode unit 20x. The second diode region 20b includes, for example, two to ten diode units 20x.

[0034] The second diode region 20b includes, for example, two diode units 20x. The number of diode units 20x included in the second diode region 20b is not limited to two.

[0035] For example, the number of diode units 20x in the first diode region 20a is equal to the number of diode units 20x in the second diode region 20b. In MOSFET 100, the number of diode units 20x in the first diode region 20a and the number of diode units 20x in the second diode region 20b are both 2 and therefore equal.

[0036] The third transistor region 10c is located between the first diode region 20a and the second diode region 20b. The third transistor region 10c is in contact with the first diode region 20a and the second diode region 20b. The third transistor region 10c contains one transistor unit 10x. The third transistor region 10c does not contain two or more transistor units 10x. Only one transistor unit 10x is included in the third transistor region 10c.

[0037] Figure 3 is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment. Figure 4 is a schematic top view of a part of the semiconductor device of the first embodiment. Figure 3 is a diagram showing the AA' cross-section of Figures 1, 2, and 4.

[0038] The MOSFET 100 comprises a silicon carbide layer 30, a source electrode 41 (first electrode), a drain electrode 42 (second electrode), a first gate electrode 51, a second gate electrode 52, a gate insulating layer 54, and an interlayer insulating layer 55.

[0039] The silicon carbide layer 30 is n + Shape of drain region 31, n - The drift region 32 (first silicon carbide region) of the p-type transistor base region 33, n + It includes a source region 34 (fourth silicon carbide region) of the p-type diode and a base region 35 (fifth silicon carbide region) of the p-type diode.

[0040] The silicon carbide layer 30 is provided between the source electrode 41 and the drain electrode 42. The silicon carbide layer 30 is provided between the first gate electrode 51 and the drain electrode 42. The silicon carbide layer 30 is single crystal SiC. The silicon carbide layer 30 is, for example, 4H-SiC.

[0041] The silicon carbide layer 30 comprises a first surface ("F1" in Figure 3) and a second surface ("F2" in Figure 3). The first surface F1 is the surface of the silicon carbide layer. The second surface F2 is the back surface of the silicon carbide layer. Hereinafter, the first surface F1 may be referred to as the surface and the second surface F2 as the back surface. The first surface F1 is located on the source electrode 41 side of the silicon carbide layer 30. The second surface F2 is located on the drain electrode 42 side of the silicon carbide layer 30. The first surface F1 and the second surface F2 face each other. Hereinafter, "depth" refers to the depth in the direction toward the second surface with respect to the first surface. The "surfaces" of the first surface F1 and the second surface F2 refer to, for example, the interface between the silicon carbide layer and the insulating layer, or between the silicon carbide layer and the metal.

[0042] The first and second directions are parallel to the first surface F1.

[0043] The first surface F1 is, for example, a surface inclined at an angle of 0 to 8 degrees relative to the (0001) surface. The second surface F2 is, for example, a surface inclined at an angle of 0 to 8 degrees relative to the (000-1) surface. The (0001) surface is referred to as the silicon surface. The (000-1) surface is referred to as the carbon surface.

[0044] The thickness of the silicon carbide layer 30 is, for example, 5 μm to 350 μm.

[0045] n + The drain region 31 is provided between the source electrode 41 and the drain electrode 42. The drain region 31 is provided on the back side of the silicon carbide layer 30. The drain region 31 contains, for example, nitrogen (N) as an n-type impurity. The concentration of n-type impurities in the drain region 31 is, for example, 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0046] n - The drift region 32 is provided between the source electrode 41 and the drain electrode 42. The drift region 32 is provided between the drain region 31 and the source electrode 41. The drift region 32 is provided between the drain region 31 and the first surface F1. The drift region 32 is provided on the drain region 31.

[0047] The drift region 32 includes a portion that is in contact with the first surface F1. A further portion of the portion of the drift region 32 that is in contact with the first surface F1 is in contact with the source electrode 41.

[0048] The drift region 32 functions as a path for the on-current when the MOSFET 100 is in the ON state.

[0049] The drift region 32 contains, for example, nitrogen (N) as an n-type impurity. The concentration of n-type impurities in the drift region 32 is lower than the concentration of n-type impurities in the drain region 31. The concentration of n-type impurities in the drift region 32 is, for example, 4 × 10⁻⁶. 14 cm -3 The above 5 x 10 17 cm -3 The following applies: The thickness of the drift region 32 is, for example, between 3 μm and 100 μm.

[0050] The p-type transistor base region 33 is provided in the transistor region 10. The transistor base region 33 is provided between the drift region 32 and the source electrode 41. The transistor base region 33 is provided between the drift region 32 and the first surface F1. The transistor base region 33 is provided on the drift region 32.

[0051] The transistor base region 33 extends in a second direction. The transistor base region 33 is repeatedly arranged in a first direction.

[0052] A portion of the transistor base region 33 functions as the channel region of the MOSFET 100.

[0053] The transistor base region 33 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration in the transistor base region 33 is, for example, 5 × 10⁻⁶ 17 cm -3 The above 1 x 10 21 cm -3 The following applies. Note that the p-type impurity concentration in the transistor base region 33 is defined as the p-type impurity concentration at half the depth of the transistor base region 33.

[0054] The depth of the transistor base region 33 is, for example, 0.3 μm or more and 1.0 μm or less.

[0055] The transistor base region 33 is electrically connected to the source electrode 41. The transistor base region 33 is, for example, in contact with the source electrode 41. The transistor base region 33 is fixed at the potential of the source electrode 41.

[0056] n + The source region 34 is provided in the transistor region 10. The source region 34 is provided between the transistor base region 33 and the source electrode 41. The source region 34 is provided between the transistor base region 33 and the first surface F1. The source region 34 extends, for example, in a first direction.

[0057] Source region 34 contains, for example, phosphorus (P) as an n-type impurity. The concentration of n-type impurities in source region 34 is higher than the concentration of n-type impurities in drift region 32.

[0058] The n-type impurity concentration in source region 34 is, for example, 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 21 cm -3 The following applies: The depth of the source region 34 is shallower than the depth of the transistor base region 33. The depth of the source region 34 is, for example, between 0.1 μm and 0.3 μm.

[0059] The source region 34 is electrically connected to the source electrode 41. The source region 34, for example, is in contact with the source electrode 41. The source region 34 is fixed at the potential of the source electrode 41.

[0060] The p-type diode base region 35 is provided in the diode region 20. The diode base region 35 is provided between the drift region 32 and the source electrode 41. The diode base region 35 is provided between the drift region 32 and the first surface F1. The diode base region 35 is provided on the drift region 32.

[0061] The diode base region 35 extends in a second direction. The diode base region 35 is repeatedly arranged in a first direction.

[0062] The diode base region 35 functions as the p-type semiconductor region of the pn junction diode.

[0063] The diode base region 35 contains, for example, aluminum (Al) as a p-type impurity. The concentration of the p-type impurity in the diode base region 35 is, for example, 5 × 10⁻⁶ 17 cm -3 The above 1 x 10 21 cm -3 The following applies. Note that the p-type impurity concentration in the diode base region 35 is defined as the p-type impurity concentration at half the depth of the diode base region 35.

[0064] The depth of the diode base region 35 is, for example, 0.3 μm or more and 1.0 μm or less.

[0065] The p-type impurity concentration in the diode base region 35 is substantially equal to, for example, the p-type impurity concentration in the transistor base region 33. The depth of the diode base region 35 is substantially equal to, for example, the depth of the transistor base region 33.

[0066] The diode base region 35 is electrically connected to the source electrode 41. The diode base region 35 is, for example, in contact with the source electrode 41. The diode base region 35 is fixed at the potential of the source electrode 41.

[0067] The first gate electrode 51 and the second gate electrode 52 are provided on the side of the first surface F1 of the silicon carbide layer 30. The first gate electrode 51 and the second gate electrode 52 face the transistor base region 33. The first gate electrode 51 and the second gate electrode 52 face, for example, the portion of the transistor base region 33 that is in contact with the first surface F1. The first gate electrode 51 and the second gate electrode 52 extend in a second direction. The first gate electrode 51 and the second gate electrode 52 are arranged parallel to each other.

[0068] The first gate electrode 51 and the second gate electrode 52 are conductive layers. The first gate electrode 51 is, for example, polycrystalline silicon containing p-type or n-type impurities.

[0069] The gate insulating layer 54 is provided between the first gate electrode 51 and the silicon carbide layer 30, and between the second gate electrode 52 and the silicon carbide layer 30. The gate insulating layer 54 is provided between the first gate electrode 51 and the transistor base region 33, and between the second gate electrode 52 and the transistor base region 33. The gate insulating layer 54 is provided between the first gate electrode 51 and the drift region 32, and between the second gate electrode 52 and the drift region 32.

[0070] The gate insulating layer 54 is, for example, silicon oxide. For the gate insulating layer 54, for example, a high-k insulating material (high dielectric constant insulating material) can be applied.

[0071] The interlayer insulating layer 55 is provided on the first gate electrode 51, on the second gate electrode 52, and on the silicon carbide layer 30. The interlayer insulating layer 55 is provided between the first gate electrode 51 and the source electrode 41, and between the second gate electrode 52 and the source electrode 41. The interlayer insulating layer 55 is, for example, silicon oxide.

[0072] The interlayer insulating layer 55 has the function of electrically isolating the first gate electrode 51 from the source electrode 41, and the second gate electrode 52 from the source electrode 41.

[0073] The source electrode 41 is provided on the side of the first surface F1 of the silicon carbide layer 30. The source electrode 41 is in contact with the first surface F1.

[0074] The source electrode 41 is electrically connected to the drift region 32, the transistor base region 33, the source region 34, and the diode base region 35. For example, the source electrode 41 is in contact with the drift region 32, the transistor base region 33, the source region 34, and the diode base region 35.

[0075] The source electrode 41 contains a metal. The metal forming the source electrode 41 is, for example, a layered structure of titanium (Ti) and aluminum (Al).

[0076] The portion of the source electrode 41 that is in contact with the transistor base region 33, the source region 34, and the diode base region 35 is, for example, a metal silicide. The metal silicide is, for example, titanium silicide or nickel silicide.

[0077] For example, no metal silicide is provided in the portion of the source electrode 41 that is in contact with the drift region 32.

[0078] The junctions between the transistor base region 33, the source region 34, and the diode base region 35 and the source electrode 41 are, for example, ohmic junctions. The junction between the drift region 32 and the source electrode 41 is, for example, a Schottky junction.

[0079] The drain electrode 42 is provided on the side of the second surface F2 of the silicon carbide layer 30. The drain electrode 42 is in contact with the second surface F2. The drain electrode 42 is in contact with the drain region 31.

[0080] The drain electrode 42 is, for example, a metal or a metal-semiconductor compound. The drain electrode 42 includes, for example, at least one material selected from the group consisting of nickel silicide, titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).

[0081] The junction between the drain region 31 and the drain electrode 42 is, for example, an ohmic junction.

[0082] Figures 5 and 6 are schematic cross-sectional views of a part of the semiconductor device of the first embodiment. Figure 5 shows a cross-section of the transistor unit 10x. Figure 6 shows a cross-section of the diode unit 20x.

[0083] The transistor unit 10x comprises a silicon carbide layer 30, a source electrode 41 (first electrode), a drain electrode 42 (second electrode), a first gate electrode 51, a second gate electrode 52, a gate insulating layer 54, and an interlayer insulating layer 55.

[0084] The silicon carbide layer 30 of the transistor unit 10x is n + Shape of drain region 31, n - The drift region 32 of the p-shape (first silicon carbide region), the first transistor base region 33a of the p-shape (second silicon carbide region), the second transistor base region 33b of the p-shape (third silicon carbide region), the third transistor base region 33c of the p-shape (sixth silicon carbide region), n + It includes the source region 34 of the shape (the fourth silicon carbide region).

[0085] The drift region 32 includes a first portion 32a and a second portion 32b. The first transistor base region 33a, the second transistor base region 33b, and the third transistor base region 33c are one of the transistor base regions 33.

[0086] The first portion 32a and the second portion 32b are in contact with the source electrode 41. The first portion 32a and the second portion 32b are in contact with the first surface F1. The first portion 32a and the second portion 32b extend in a second direction on the first surface F1. The second portion 32b is provided in a first direction relative to the first portion 32a.

[0087] The first portion 32a and the second portion 32b are electrically connected to the source electrode 41. The junction between the first portion 32a and the second portion 32b and the source electrode 41 is, for example, a Schottky junction. The first portion 32a and the second portion 32b function as n-type semiconductor regions of the SBD.

[0088] The distance in the first direction between the first part 32a and the second part 32b is the first distance d1.

[0089] The first p-shaped transistor base region 33a is located between the first portion 32a and the second portion 32b. The first transistor base region 33a extends in the second direction.

[0090] The p-shaped second transistor base region 33b is provided between the first transistor base region 33a and the second portion 32b. The second transistor base region 33b extends in a second direction. The second transistor base region 33b is separated from the first transistor base region 33a.

[0091] The p-shaped third transistor base region 33c is located between the second transistor base region 33b and the second portion 32b. The third transistor base region 33c extends in the second direction. The third transistor base region 33c is separated from the second transistor base region 33b.

[0092] The transistor unit 10x includes a first gate electrode 51 and a second gate electrode 52. The first gate electrode 51 faces the first transistor base region 33a and the second transistor base region 33b. The second gate electrode 52 faces the second transistor base region 33b and the third transistor base region 33c.

[0093] A gate insulating layer 54 is provided between the first gate electrode 51 and the first transistor base region 33a and the second transistor base region 33b. A gate insulating layer 54 is provided between the second gate electrode 52 and the second transistor base region 33b and the third transistor base region 33c.

[0094] The first transistor base region 33a, the second transistor base region 33b, and a portion of the third transistor base region 33c function as the channel region of the MOSFET 100.

[0095] The transistor unit 10x is equipped with a MOSFET and an SBD.

[0096] The diode unit 20x comprises a silicon carbide layer 30, a source electrode 41 (first electrode), and a drain electrode 42 (second electrode).

[0097] The silicon carbide layer 30 of the diode unit 20x is n + Shape of drain region 31, n - It includes a p-type drift region 32 (first silicon carbide region) and a p-type diode base region 35 (fifth silicon carbide region).

[0098] The drift region 32 includes a third portion 32c and a fourth portion 32d.

[0099] The third portion 32c and the fourth portion 32d are in contact with the source electrode 41. The third portion 32c and the fourth portion 32d are in contact with the first surface F1. The third portion 32c and the fourth portion 32d extend in a second direction on the first surface F1. The fourth portion 32d is provided in a first direction relative to the third portion 32c.

[0100] The third portion 32c and the fourth portion 32d are electrically connected to the source electrode 41. The junction between the third portion 32c and the fourth portion 32d and the source electrode 41 is, for example, a Schottky junction. The third portion 32c and the fourth portion 32d function as n-type semiconductor regions of the SBD.

[0101] The distance in the first direction between the third part 32c and the fourth part 32d is the second distance d2. The second distance d2 is equal to the first distance d1.

[0102] The p-type diode base region 35 is located between the third portion 32c and the fourth portion 32d. The diode base region 35 extends in the second direction. The diode base region 35 functions as the p-type semiconductor region of the pn junction diode.

[0103] The diode unit 20x is provided with a pn junction diode and an SBD. The area occupied by the pn junction diode in the diode unit 20x projected onto the first surface F1 is larger than the area occupied by the pn junction diode in the transistor unit 10x projected onto the first surface F1.

[0104] In the diode unit 20x, the area in contact between the source electrode 41 and the silicon carbide layer 30 is larger than the area in contact between the source electrode 41 and the silicon carbide layer 30 in the transistor unit 10x. In the diode unit 20x, the area in contact between the source electrode 41 and the first surface F1 of the silicon carbide layer 30 is larger than the area in contact between the source electrode 41 and the first surface F1 of the silicon carbide layer 30 in the transistor unit 10x. In the diode unit 20x, the area in contact between the source electrode 41 and the diode base region 35 is larger than the area in contact between the source electrode 41 and the transistor base region 33 in the transistor unit 10x.

[0105] Next, the operation and effects of the MOSFET 100 of the first embodiment will be described.

[0106] The MOSFET 100 of the first embodiment is provided with a MOSFET and an SBD.

[0107] Figure 7 is an equivalent circuit diagram of the semiconductor device according to the first embodiment. A pn ​​junction diode and an SBD are connected in parallel with the transistor between the source electrode 41 and the drain electrode 42 as built-in diodes.

[0108] For example, consider the case where MOSFET 100 is used as a switching element connected to an inductive load. When MOSFET 100 is off, a load current caused by the inductive load may apply a voltage to the source electrode 41 relative to the drain electrode 42, resulting in a positive voltage. In this case, a forward current flows through the internal diode. This state is also called a reverse conduction state. The current flowing through the internal diode is called a freewheeling current.

[0109] The forward voltage (Vf) at which forward current begins to flow through an SBD is lower than the forward voltage (Vf) of a pn junction diode. Therefore, forward current flows through the SBD first.

[0110] The forward voltage (Vf) of an SBD is, for example, 1.0V. The forward voltage (Vf) of a pn junction diode is, for example, 2.5V.

[0111] If a MOSFET is not equipped with an SBD, a forward current will flow through the pn junction diode in the reverse conduction state. When a forward current flows through a pn junction diode, stacking faults grow in the silicon carbide layer due to the carrier recombination energy, which increases the on-resistance of the MOSFET. An increase in the on-resistance of the MOSFET leads to a decrease in the reliability of the MOSFET.

[0112] The SBD operates unipolar. Therefore, even when a forward current flows, stacking faults do not grow in the silicon carbide layer 30 due to carrier recombination energy. Consequently, the reliability of the MOSFET 100 is improved by incorporating an SBD as a built-in diode.

[0113] Figure 8 is an explanatory diagram of the operation and effects of the semiconductor device of the first embodiment. Figure 8 corresponds to Figure 3.

[0114] Figure 8 shows the current flowing through the built-in diode of the MOSFET 100 in the first embodiment. Figure 8 shows the state in which forward current flows only through the SBD. That is, Figure 8 shows the state in which the voltage applied across the pn junction of the pn junction diode is lower than the forward voltage (Vf) of the pn junction diode.

[0115] In Figure 8, the dotted arrows indicate the current flowing through the SBD. As shown in Figure 8, the current flowing through the SBD wraps around to the bottom of the transistor base region 33 and the diode base region 35. As a result, electrostatic potential wraps around to the drift region 32 opposite the bottom of the transistor base region 33 and the bottom of the diode base region 35. This electrostatic potential wraps around to the drift region 32, which is opposite the bottom of the transistor base region 33 and the diode base region 35, and reduces the voltage applied between the transistor base region 33 and the drift region 32, and between the diode base region 35 and the drift region 32.

[0116] Therefore, the forward voltage (Vf) of the pn junction diode is less likely to be exceeded at the bottom of the transistor base region 33 and the bottom of the diode base region 35. In other words, by providing an SBD, the forward voltage (Vf) of the pn junction diode of the MOSFET 100 can be made higher compared to when an SBD is not provided. As a result, the bipolar operation of the pn junction diode is suppressed, and the formation of stacking faults in the silicon carbide layer 30 due to carrier recombination energy is suppressed.

[0117] The forward voltage (Vf) of the pn junction diode in MOSFET100 depends on the distance between two adjacent SBDs in the first direction. In MOSFET100, the distance between two SBDs in transistor region 10 (first distance d1) is equal to the distance between two SBDs in diode region 20 (second distance d2). Therefore, the forward voltage (Vf) of the pn junction diode in transistor region 10 is equal to the forward voltage (Vf) of the pn junction diode in diode region 20.

[0118] In some cases, a surge voltage exceeding the steady state may be applied to the MOSFET instantaneously. A surge current flows along with the surge voltage. The surge current flows from the source electrode 41 to the drain electrode 42.

[0119] When a large surge current flows, the MOSFET overheats and is destroyed. The maximum allowable peak current value (I) of the surge current that can be tolerated by the MOSFET. FSM This is called surge current withstand capability. In MOSFETs equipped with SBDs, it is desirable to improve the surge current withstand capability.

[0120] Figure 9 is an explanatory diagram of the operation and effects of the semiconductor device of the first embodiment. Figure 9 corresponds to Figure 3.

[0121] Figure 9 shows the current flowing through the built-in diode of the MOSFET 100 in the first embodiment. Figure 9 shows the state in which forward current is flowing through the SBD and the pn junction diode. That is, Figure 9 shows the state in which the voltage applied across the pn junction of the pn junction diode is higher than the forward voltage (Vf) of the pn junction diode.

[0122] In Figure 9, the dotted arrows indicate the current flowing through the SBD, and the solid arrows indicate the current flowing through the pn junction diode.

[0123] When a large surge voltage is applied to MOSFET100, the voltage applied across the pn junction of the pn junction diode becomes higher than the forward voltage (Vf) of the pn junction diode. When the voltage applied across the pn junction of the pn junction diode becomes higher than the forward voltage (Vf) of the pn junction diode, current flows through the pn junction diode, as shown in Figure 9.

[0124] MOSFET 100 has diode regions 20 between transistor regions 10. As described above, the area occupied by the pn junction diode in diode unit 20x projected onto the first plane F1 is larger than the area occupied by the pn junction diode in transistor unit 10x projected onto the first plane F1. Therefore, by including the diode regions 20, MOSFET 100 increases the area occupied by the pn junction diode in the entire MOSFET 100. Consequently, the surge current that can flow when a large surge voltage is applied to MOSFET 100 is larger than when the diode regions 20 are not provided.

[0125] Furthermore, the area occupied by the pn junction diode in diode unit 20x is larger than the area occupied by the pn junction diode in transistor unit 10x. Therefore, when a large surge voltage is applied, conductivity modulation in diode unit 20x proceeds before conductivity modulation in transistor unit 10x. The conductivity modulation initiated in diode unit 20x propagates to transistor unit 10x, thereby accelerating conductivity modulation in transistor unit 10x. As a result, the rate of increase of surge current flowing through MOSFET 100 is larger than when diode region 20 is not provided. Consequently, the surge current that MOSFET 100 can handle when a large surge voltage is applied is larger than when diode region 20 is not provided.

[0126] Therefore, the surge current withstand capability of MOSFET100 is improved.

[0127] Figure 10 is a schematic top view of a part of the semiconductor device of the comparative example. Figure 10 corresponds to Figure 2 of the first embodiment.

[0128] Figure 11 is a schematic cross-sectional view of a part of a comparative example semiconductor device. Figure 11 is a view of the BB' cross-section in Figure 10. Figure 11 corresponds to Figure 3 of the first embodiment.

[0129] The comparative example MOSFET differs from the MOSFET 100 of the first embodiment in that it does not have a third transistor region 10c.

[0130] Figure 12 shows the problems of the comparative semiconductor device. Figure 12 corresponds to Figure 11.

[0131] Figure 12 shows the current flowing through the transistor of the comparative example MOSFET. Figure 12 shows the state in which on-current is flowing through the transistor in transistor region 10.

[0132] In Figure 12, the solid arrows indicate the on-current flowing through the transistor. Since there is no transistor in the diode region 20, the on-current per unit area is reduced compared to a MOSFET without the diode region 20. In other words, the on-resistance per unit area of ​​the MOSFET increases.

[0133] However, as shown in Figure 12, a portion of the on-current flows back from the transistor regions 10 on both sides of the diode region 20 to the drift region 32 of the diode region 20. Therefore, the increase in on-resistance per unit area caused by providing the diode region 20 is mitigated.

[0134] In the comparative example MOSFET, the inactive region 60 shown in Figure 12 is the region where no on-current flows through the transistor.

[0135] Figure 13 is an explanatory diagram of the operation and effects of the semiconductor device of the first embodiment. Figure 13 corresponds to Figure 3.

[0136] Figure 13 is a diagram showing the current flowing through the transistor of the MOSFET 100 in the first embodiment. Figure 13 shows the state in which an on-current is flowing through the transistor in the transistor region 10.

[0137] In the MOSFET 100 of the first embodiment, unlike the MOSFET of the comparative example, a third transistor region 10c is provided between the first diode region 20a and the second diode region. As a result, as shown in Figure 13, the total volume of the reactive region 60, through which the transistor's on-current does not flow, is reduced compared to the MOSFET of the comparative example. Therefore, the increase in on-resistance per unit area due to the provision of the diode region 20 is further mitigated compared to the MOSFET of the comparative example. Thus, a MOSFET with reduced on-resistance per unit area can be realized.

[0138] The third transistor region 10c contains one transistor unit 10x. If the number of transistor units 10x in the third transistor region 10c were two or more, the surge current withstand capability would decrease significantly.

[0139] When the distance between the first diode region 20a and the second diode region 20b is small, the conductivity modulation of the MOSFET is promoted by the interaction between the conductivity modulation occurring in the first diode region 20a and the conductivity modulation occurring in the second diode region 20b when a surge current flows. Therefore, the surge current that can flow when a large surge voltage is applied becomes larger, and the surge current withstand capability of the MOSFET is improved.

[0140] When the number of transistor units 10x included in the third transistor region 10c becomes two or more, the distance between the first diode region 20a and the second diode region 20b increases. As the distance between the first diode region 20a and the second diode region 20b increases, the conductivity modulation interaction between the first diode region 20a and the second diode region 20b when a surge current flows becomes less likely to occur. Therefore, the surge current that can flow when a large surge voltage is applied becomes smaller, and the surge current withstand capability of the MOSFET decreases.

[0141] In the MOSFET 100 of the first embodiment, by limiting the number of transistor units 10x included in the third transistor region 10c to one, the reduction in surge current withstand capability can be minimized even when the third transistor region 10c is provided.

[0142] According to the MOSFET 100 of the first embodiment, it is possible to improve surge current withstand capability and reduce on-resistance.

[0143] (First variation) The first modified semiconductor device differs from the semiconductor device of the first embodiment in that the first diode region includes three diode units and the second diode region includes three diode units.

[0144] Figure 14 is a schematic top view of a part of a semiconductor device of a first modification of the first embodiment. Figure 14 corresponds to Figure 2 of the first embodiment.

[0145] Figure 15 is a schematic cross-sectional view of a part of a semiconductor device of a first modification of the first embodiment. Figure 15 is a view of the CC' cross section of Figure 14.

[0146] The MOSFET of the first modified embodiment includes a first transistor region 10a, a second transistor region 10b, and a third transistor region 10c. The MOSFET of the first modified embodiment also includes a first diode region 20a and a second diode region 20b.

[0147] The transistor region 10 includes transistor units 10x. The diode region 20 also includes diode units 20x.

[0148] The first transistor region 10a includes, for example, nine transistor units 10x. The second transistor region 10b includes, for example, nine transistor units 10x.

[0149] The first diode region 20a includes three diode units 20x. The second diode region 20b includes three diode units 20x.

[0150] According to the MOSFET of the first modification of the first embodiment, similar to the first embodiment, improved surge current withstand capability and reduced on-resistance can be achieved.

[0151] (Second variation) The semiconductor device of the second modification differs from the semiconductor device of the first embodiment in that the first diode region includes one diode unit, and the second diode region also includes one diode unit.

[0152] Figure 16 is a schematic top view of a part of a semiconductor device of a second modification of the first embodiment. Figure 16 corresponds to Figure 2 of the first embodiment.

[0153] The MOSFET of the second modified embodiment includes a first transistor region 10a, a second transistor region 10b, a third transistor region 10c, a fourth transistor region 10d, and a fifth transistor region 10e. The MOSFET of the second modified embodiment also includes a first diode region 20a, a second diode region 20b, a third diode region 20c, and a fourth diode region 20d.

[0154] The transistor region 10 includes transistor units 10x. The diode region 20 also includes diode units 20x.

[0155] The fourth transistor region 10d is provided between the first transistor region 10a and the third transistor region 10c. The fifth transistor region 10e is provided between the third transistor region 10c and the second transistor region 10b.

[0156] The first diode region 20a is provided between the third transistor region 10c and the fourth transistor region 10d. The second diode region 20b is provided between the third transistor region 10c and the fifth transistor region 10e. The third diode region 20c is provided between the first transistor region 10a and the fourth transistor region 10d. The fourth diode region 20d is provided between the second transistor region 10b and the fifth transistor region 10e.

[0157] The first transistor region 10a includes, for example, nine transistor units 10x. The second transistor region 10b includes, for example, nine transistor units 10x. The third transistor region 10c, the fourth transistor region 10d, and the fifth transistor region 10e each include one transistor unit 10x.

[0158] The first diode region 20a, the second diode region 20b, the third diode region 20c, and the fourth diode region 20d each contain one diode unit 20x.

[0159] According to the MOSFET of the second modification of the first embodiment, similar to the first embodiment, improved surge current withstand capability and reduced on-resistance can be achieved.

[0160] As described above, according to the first embodiment and its modifications, a semiconductor device can be provided that has improved surge current withstand capability and reduced on-resistance.

[0161] (Second embodiment) The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the transistor unit does not include a second gate electrode and a sixth silicon carbide region. Some descriptions that overlap with the first embodiment may be omitted below.

[0162] Figures 17 and 18 are schematic cross-sectional views of a part of the semiconductor device of the second embodiment. Figure 17 shows a cross-section of the transistor unit 10x. Figure 18 shows a cross-section of the diode unit 20x. Figure 17 corresponds to Figure 5 of the first embodiment. Figure 18 corresponds to Figure 6 of the first embodiment.

[0163] The transistor unit 10x comprises a silicon carbide layer 30, a source electrode 41 (first electrode), a drain electrode 42 (second electrode), a first gate electrode 51, a gate insulating layer 54, and an interlayer insulating layer 55.

[0164] The silicon carbide layer 30 of the transistor unit 10x is n + Shape of drain region 31, n - The drift region 32 of the p-shape (first silicon carbide region), the first transistor base region 33a of the p-shape (second silicon carbide region), the second transistor base region 33b of the p-shape (third silicon carbide region), n + It includes the source region 34 of the shape (the fourth silicon carbide region).

[0165] The drift region 32 includes a first portion 32a and a second portion 32b. The distance between the first portion 32a and the second portion 32b in a first direction is the first distance d1.

[0166] The diode unit 20x comprises a silicon carbide layer 30, a source electrode 41 (first electrode), and a drain electrode 42 (second electrode).

[0167] The silicon carbide layer 30 of the diode unit 20x is n + Shape of drain region 31, n - It includes a p-type drift region 32 (first silicon carbide region) and a p-type diode base region 35 (fifth silicon carbide region).

[0168] The drift region 32 includes a third portion 32c and a fourth portion 32d. The distance in the first direction between the third portion 32c and the fourth portion 32d is the second distance d2. The second distance d2 is equal to the first distance d1.

[0169] As described above, the second embodiment provides a semiconductor device that, like the first embodiment, has improved surge current withstand capability and reduced on-resistance.

[0170] (Third embodiment) The semiconductor device of the third embodiment differs from the semiconductor device of the first embodiment in that the transistor region further includes a seventh silicon carbide region of second conductivity, provided between a first silicon carbide region and a first electrode, electrically connected to the first electrode, extending in a second direction, and provided between a sixth silicon carbide region and a second portion in the first direction, separated from the sixth silicon carbide region, and a third gate electrode, facing the sixth and seventh silicon carbide regions and extending in the second direction. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0171] Figures 19 and 20 are schematic cross-sectional views of a part of the semiconductor device of the third embodiment. Figure 19 is a cross-sectional view of the transistor unit 10x. Figure 20 is a cross-sectional view of the diode unit 20x. Figure 19 corresponds to Figure 5 of the first embodiment. Figure 20 corresponds to Figure 6 of the first embodiment.

[0172] The transistor unit 10x comprises a silicon carbide layer 30, a source electrode 41 (first electrode), a drain electrode 42 (second electrode), a first gate electrode 51, a second gate electrode 52, a third gate electrode 53, a gate insulating layer 54, and an interlayer insulating layer 55.

[0173] The silicon carbide layer 30 of the transistor unit 10x is n + Shape of drain region 31, n - The drift region 32 of the p-type (first silicon carbide region), the first transistor base region 33a of the p-type (second silicon carbide region), the second transistor base region 33b of the p-type (third silicon carbide region), the third transistor base region 33c of the p-type (sixth silicon carbide region), the fourth transistor base region 33d of the p-type (seventh silicon carbide region), n + It includes the source region 34 of the shape (the fourth silicon carbide region).

[0174] The p-shaped fourth transistor base region 33d is located between the third transistor base region 33c and the second portion 32b. The fourth transistor base region 33d extends in the second direction. The fourth transistor base region 33d is separated from the third transistor base region 33c.

[0175] The transistor unit 10x includes a first gate electrode 51, a second gate electrode 52, and a third gate electrode 53. The third gate electrode 53 faces a third transistor base region 33c and a fourth transistor base region 33d.

[0176] A gate insulating layer 54 is provided between the third gate electrode 53 and the third transistor base region 33c and the fourth transistor base region 33d.

[0177] The diode unit 20x comprises a silicon carbide layer 30, a source electrode 41 (first electrode), and a drain electrode 42 (second electrode).

[0178] The silicon carbide layer 30 of the diode unit 20x is n + Shape of drain region 31, n - It includes a p-type drift region 32 (first silicon carbide region) and a p-type diode base region 35 (fifth silicon carbide region).

[0179] The drift region 32 includes a third portion 32c and a fourth portion 32d. The distance in the first direction between the third portion 32c and the fourth portion 32d is the second distance d2. The second distance d2 is equal to the first distance d1.

[0180] As described above, the third embodiment provides a semiconductor device that, like the first embodiment, has improved surge current withstand capability and reduced on-resistance.

[0181] (Fourth embodiment) The semiconductor device of the fourth embodiment differs from the semiconductor device of the first embodiment in that the diode unit further includes a conductive layer facing the fifth silicon carbide region and extending in the second direction, and an insulating layer provided between the conductive layer and the fifth silicon carbide region. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0182] Figure 21 is a schematic cross-sectional view of a part of the semiconductor device of the fourth embodiment. Figure 21 is a cross-sectional view of the diode unit 20x. Figure 21 corresponds to Figure 6 of the first embodiment.

[0183] The MOSFET transistor unit 10x of the fourth embodiment has the same configuration as the MOSFET transistor unit 10x of the first embodiment shown in Figure 5.

[0184] The diode unit 20x comprises a silicon carbide layer 30, a source electrode 41 (first electrode), a drain electrode 42 (second electrode), a conductive layer 61, an insulating layer 64, and an interlayer insulating layer 55. It is equipped with.

[0185] The silicon carbide layer 30 of the diode unit 20x is n + Shape of drain region 31, n - It includes a p-type drift region 32 (first silicon carbide region) and a p-type diode base region 35 (fifth silicon carbide region).

[0186] The conductive layer 61 is provided on the side of the first surface F1 of the silicon carbide layer 30. The conductive layer 61 faces the diode base region 35. The conductive layer 61 extends in a second direction. The conductive layer 61 has a configuration similar to, for example, the first gate electrode 51 and the second gate electrode 52, and is formed simultaneously with the first gate electrode 51 and the second gate electrode 52.

[0187] The insulating layer 64 is provided between the conductive layer 61 and the silicon carbide layer 30. The insulating layer 64 is provided between the conductive layer 61 and the diode base region 35. The insulating layer 64 has a similar configuration to, for example, the gate insulating layer 54 and is formed at the same time as the gate insulating layer 54.

[0188] The interlayer insulating layer 55 is provided on the conductive layer 61 and the silicon carbide layer 30. The interlayer insulating layer 55 is provided between the conductive layer 61 and the source electrode 41.

[0189] The drift region 32 includes a third portion 32c and a fourth portion 32d. The distance in the first direction between the third portion 32c and the fourth portion 32d is the second distance d2. The second distance d2 is equal to the first distance d1.

[0190] As described above, the fourth embodiment provides a semiconductor device that, like the first embodiment, has improved surge current withstand capability and reduced on-resistance.

[0191] In the first to fourth embodiments, the case where the first conductivity type is n-type and the second conductivity type is p-type was explained as an example, but it is also possible to have the first conductivity type be p-type and the second conductivity type be n-type.

[0192] In the first to fourth embodiments, the case of 4H-SiC as the crystal structure of SiC was described as an example, but the present invention can also be applied to devices using SiC with other crystal structures such as 6H-SiC and 3C-SiC. Furthermore, it is possible to apply a plane other than the (0001) plane to the surface of the silicon carbide layer 30.

[0193] In the first to fourth embodiments, aluminum (Al) was exemplified as a p-type impurity, but boron (B) can also be used. Similarly, nitrogen (N) and phosphorus (P) were exemplified as n-type impurities, but arsenic (As), antimony (Sb), etc., can also be applied.

[0194] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0195] 10a First transistor region 10b Second transistor region 10c Third transistor region 10x Transistor Unit 20a First diode region 20b Second diode region 20x Diode Unit 30. Silicon carbide layer 32. Drift region (first silicon carbide region) 32a Part 1 32b Second part 32c Third part 32d Part 4 33a First transistor base region (second silicon carbide region) 33b Second transistor base region (third silicon carbide region) 33c Third transistor base region (sixth silicon carbide region) 33d Fourth transistor base region (seventh silicon carbide region) 34. Source region (fourth silicon carbide region) 35 Diode base region (5th silicon carbide region) 41 Source electrode (first electrode) 42 Drain electrode (second electrode) 51 First gate 52 Second gate electrode 53 Third gate 54 Gate Insulation Layer 61. Conductive layer 64 Insulating layer 100 MOSFETs (Semiconductor Devices) d1 First distance d2 Second distance

Claims

1. A first transistor region including at least one transistor unit, A second transistor region comprising at least one transistor unit and provided in a first direction relative to the first transistor region, A first diode region is provided between the first transistor region and the second transistor region and includes at least one diode unit, A second diode region is provided between the first diode region and the second transistor region, and includes at least one of the diode units, A third transistor region is provided between the first diode region and the second diode region and includes one transistor unit, The aforementioned transistor unit is The first electrode and The second electrode and A first silicon carbide region of a first conductivity type, provided between the first electrode and the second electrode, including a first portion that is in contact with the first electrode and extends in a second direction perpendicular to the first direction, and a second portion that is in contact with the first electrode, is provided in the first direction relative to the first portion and extends in the second direction, A second silicon carbide region of second conductivity is provided between the first silicon carbide region and the first electrode, electrically connected to the first electrode, extending in the second direction, and provided between the first portion and the second portion in the first direction. A third silicon carbide region of second conductivity is provided between the first silicon carbide region and the first electrode, electrically connected to the first electrode, extending in the second direction, provided between the second silicon carbide region and the second portion in the first direction, and separated from the second silicon carbide region. A fourth silicon carbide region of first conductivity type is provided between the second silicon carbide region and the first electrode and is electrically connected to the first electrode, A first gate electrode that faces the second silicon carbide region and the third silicon carbide region and extends in the second direction, A gate insulating layer is provided between the first gate electrode, the second silicon carbide region, and the third silicon carbide region, Includes, The diode unit is The first electrode and, The first electrode 2, The first silicon carbide region includes a third portion that is in contact with the first electrode and extends in the second direction, and a fourth portion that is in contact with the first electrode, is provided in the first direction relative to the third portion and extends in the second direction, A fifth silicon carbide region of second conductivity is provided between the first silicon carbide region and the first electrode, electrically connected to the first electrode, extending in the second direction and continuously provided between the third portion and the fourth portion in the first direction, Includes, A semiconductor device in which the first distance in the first direction between the first portion and the second portion is equal to the second distance in the first direction between the third portion and the fourth portion.

2. The semiconductor device according to claim 1, wherein the first diode region includes two to ten of the diode units, and the second diode region includes two to ten of the diode units.

3. The semiconductor device according to claim 1, wherein the first diode region includes two diode units, and the second diode region includes two diode units.

4. The semiconductor device according to claim 1, wherein the first diode region includes one diode unit, and the second diode region includes one diode unit.

5. The semiconductor device according to claim 1, wherein the number of diode units included in the first diode region is equal to the number of diode units included in the second diode region.

6. The semiconductor device according to claim 1, wherein the first transistor region and the second transistor region include a plurality of transistor units.

7. The transistor unit further includes a silicon carbide layer comprising the first silicon carbide region, the second silicon carbide region, the third silicon carbide region, and the fourth silicon carbide region. The diode unit further includes the silicon carbide layer, which includes the first silicon carbide region and the fifth silicon carbide region. The semiconductor device according to claim 1, wherein the area in which the first electrode and the silicon carbide layer are in contact in the diode unit is larger than the area in which the first electrode and the silicon carbide layer are in contact in the transistor unit.

8. The semiconductor device according to claim 1, wherein the third transistor region is in contact with the first diode region and the second diode region.

9. The aforementioned transistor unit is A sixth silicon carbide region of second conductivity, provided between the first silicon carbide region and the first electrode, electrically connected to the first electrode, extending in the second direction, provided between the third silicon carbide region and the second portion in the first direction, and separated from the third silicon carbide region, The semiconductor device according to claim 1, further comprising: a second gate electrode facing the third silicon carbide region and the sixth silicon carbide region and extending in the second direction.

10. The aforementioned transistor unit is A seventh silicon carbide region of second conductivity, provided between the first silicon carbide region and the first electrode, electrically connected to the first electrode, extending in the second direction, provided between the sixth silicon carbide region and the second portion in the first direction, and separated from the sixth silicon carbide region, The semiconductor device according to claim 9, further comprising: a third gate electrode facing the sixth silicon carbide region and the seventh silicon carbide region and extending in the second direction.

11. The semiconductor device according to claim 1, wherein the diode unit further includes a conductive layer facing the fifth silicon carbide region and extending in the second direction, and an insulating layer provided between the conductive layer and the fifth silicon carbide region.

12. The semiconductor device according to claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.

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