Semiconductor equipment

Abstract

To provide a semiconductor device that enables improved surge current withstand capability. [Solution] The semiconductor device of the embodiment has a silicon carbide layer having a first electrode, a second electrode, a first surface on the side of the first electrode, and a second surface on the side of the second electrode, comprising a first silicon carbide region of a first conductivity type including a first portion that is in contact with the first electrode and extends in a first direction parallel to the first surface, and second and third silicon carbide regions of a second conductivity type extending in a first direction between the first silicon carbide region and the first surface. The silicon carbide layer includes a fourth silicon carbide region, a fifth silicon carbide region of a first conductivity type between the second silicon carbide region and the first surface, and a sixth silicon carbide region of a second conductivity type between the second and third silicon carbide regions, in contact with the second and third silicon carbide regions; and a first gate electrode extending in a first direction and facing the second, third, and sixth silicon carbide regions.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] A vertical MOSFET using silicon carbide has a built-in pn junction diode. For example, a MOSFET is used as a switching element connected to an inductive load. In this case, even when the MOSFET is off, it is possible to pass a freewheeling current using the built-in diode.

[0003] However, when a freewheel current is passed through using a body diode, stacking faults grow in the silicon carbide layer due to the carrier recombination energy, which increases the on-resistance of the MOSFET. This increase in on-resistance leads to a decrease in the reliability of the MOSFET. For example, by providing a unipolar Schottky Barrier Diode (SBD) as an internal diode in the MOSFET, it is possible to suppress the growth of stacking faults in the silicon carbide layer. By providing an SBD as an internal diode in the MOSFET, the reliability of the MOSFET is improved.

[0004] A surge voltage exceeding the steady state may be instantaneously applied between the electrodes of a MOSFET, causing a surge current to flow. A large surge current can cause the MOSFET to overheat and eventually be destroyed. The maximum allowable peak current value (I) is the maximum surge current that a MOSFET can handle. FSM This is called surge current withstand capability. In MOSFETs equipped with SBDs, it is desirable to improve the surge current withstand capability. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] U.S. Patent Application Publication No. 2023 / 0163166 [Overview of the project] [Problems that the invention aims to solve]

[0006] The problem that this invention aims to solve is to provide a semiconductor device that enables improved surge current withstand capability. [Means for solving the problem]

[0007] The semiconductor device according to the embodiment includes: a first electrode; a second electrode; a silicon carbide layer provided between the first electrode and the second electrode, the silicon carbide layer having a first surface on the first electrode side and a second surface on the second electrode side, the silicon carbide layer comprising: a first silicon carbide region of a first conductivity type that is in contact with the first electrode and includes a first portion extending in a first direction parallel to the first surface; a second silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first surface, extending in the first direction, and electrically connected to the first electrode; a third silicon carbide region of the second conductivity type provided between the first silicon carbide region and the first surface, extending in the first direction, provided in a second direction parallel to the first surface and perpendicular to the first direction relative to the second silicon carbide region, and electrically connected to the first electrode; a fourth silicon carbide region of the second conductivity type provided between the first silicon carbide region and the first surface, extending in the first direction, provided in the second direction relative to the second silicon carbide region, wherein the second silicon carbide region is provided between the fourth silicon carbide region and the third silicon carbide region, and the first portion is provided between the fourth silicon carbide region and the second silicon carbide region, the fourth silicon carbide region being electrically connected to the first electrode; a fifth silicon carbide region of the first conductivity type provided between the second silicon carbide region and the first surface and electrically connected to the first electrode; and a sixth silicon carbide region of the second conductivity type provided between the first silicon carbide region and the first surface, provided between the second silicon carbide region and the third silicon carbide region, in contact with the second silicon carbide region and the third silicon carbide region, and electrically connected to the first electrode; a first gate electrode extending in the first direction and facing the second silicon carbide region, the third silicon carbide region, and the sixth silicon carbide region; and a gate insulating layer provided between the first gate electrode and the second silicon carbide region, between the first gate electrode and the third silicon carbide region, and between the first gate electrode and the sixth silicon carbide region. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] [Figure 1] A schematic top view of the semiconductor device according to the first embodiment. [Figure 2]A schematic cross-sectional view of a part of the semiconductor device according to the first embodiment. [Figure 3] A schematic top view of a part of the semiconductor device according to the first embodiment. [Figure 4] A schematic top view of a part of the semiconductor device according to the first embodiment. [Figure 5] A schematic cross-sectional view of a part of the semiconductor device according to the first embodiment. [Figure 6] A schematic cross-sectional view of a part of the semiconductor device according to the first embodiment. [Figure 7] A schematic cross-sectional view of a semiconductor device according to a comparative example. [Figure 8] An equivalent circuit diagram of a semiconductor device according to a comparative example. [Figure 9] An explanatory diagram of diode operation of a semiconductor device according to a comparative example. [Figure 10] An explanatory diagram of diode operation of a semiconductor device according to a comparative example. [Figure 11] An explanatory diagram of diode operation of the semiconductor device according to the first embodiment. [Figure 12] An explanatory diagram of diode operation of the semiconductor device according to the first embodiment. [Figure 13] A schematic cross-sectional view of a semiconductor device according to a first modification of the first embodiment. [Figure 14] A schematic cross-sectional view of a semiconductor device according to a second modification of the first embodiment. [Figure 15] A schematic cross-sectional view of a semiconductor device according to a second modification of the first embodiment. [Figure 16] A schematic cross-sectional view of a semiconductor device according to the second embodiment. [Figure 17] A schematic cross-sectional view of a part of the semiconductor device according to the third embodiment. [Figure 18] A schematic top view of a part of the semiconductor device according to the third embodiment. [Figure 19] A schematic top view of a part of the semiconductor device according to the third embodiment. [Figure 20] A schematic cross-sectional view of a part of the semiconductor device according to the third embodiment. [Figure 21] A schematic cross-sectional view of a part of the semiconductor device according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members and the like are denoted by the same reference numerals, and descriptions of members and the like that have already been described may be omitted as appropriate.

[0010] In addition, in the following description, n + , n, n - and p + , p, p - notations represent relative levels of impurity concentration in each conductivity type. That is, n + indicates that the n-type impurity concentration is relatively higher than that of n, and n - indicates that the n-type impurity concentration is relatively lower than that of n. Further, p + indicates that the p-type impurity concentration is relatively higher than that of p, and p - indicates that the p-type impurity concentration is relatively lower than that of p. Note that n + type, n - type may be simply referred to as n-type, and p + type, p - type may be simply referred to as p-type.

[0011] The impurity concentration can be measured, for example, by SIMS (Secondary Ion Mass Spectrometry). In addition, the relative level of impurity concentration can also be determined from, for example, the level of carrier concentration obtained by SCM (Scanning Capacitance Microscopy). Further, distances such as the depth and thickness of an impurity region can be obtained from, for example, an image obtained by SEM (Scanning Electron Microscope) or by SIMS.

[0012] In the present specification, the impurity concentration of a semiconductor region means the maximum impurity concentration of the semiconductor region, unless otherwise specified.

[0013] (First Embodiment) The semiconductor device of the first embodiment includes a first electrode, a second electrode, a silicon carbide layer provided between the first electrode and the second electrode, having a first surface on the side of the first electrode and a second surface on the side of the second electrode, a first silicon carbide region of a first conductivity type including a first portion that is in contact with the first electrode and extends in a first direction parallel to the first surface, and a second conductive layer provided between the first silicon carbide region and the first surface, extending in a first direction and electrically connected to the first electrode. A second silicon carbide region of the electrical type is provided between the first silicon carbide region and the first surface, extending in a first direction, and provided in a second direction parallel to the first surface and perpendicular to the first direction relative to the second silicon carbide region, and electrically connected to the first electrode. A third silicon carbide region of the second conductive type is provided between the first silicon carbide region and the first surface, extending in a first direction, and provided in a second direction relative to the second silicon carbide region, and between the second silicon carbide region and the third silicon carbide region. A silicon carbide region is provided, a first portion is provided between it and a second silicon carbide region, a fourth silicon carbide region of second conductivity type is electrically connected to the first electrode, a fifth silicon carbide region of first conductivity type is provided between the second silicon carbide region and the first surface and electrically connected to the first electrode, a silicon carbide region is provided between the first silicon carbide region and the first surface, a silicon carbide region is provided between the second silicon carbide region and the third silicon carbide region, and the second silicon carbide region and the third silicon carbide region The device comprises a silicon carbide layer including a sixth silicon carbide region of a second conductivity type that is in contact with an elementary region and electrically connected to a first electrode; a first gate electrode extending in a first direction and facing the second silicon carbide region, the third silicon carbide region, and the sixth silicon carbide region; and a first gate insulating layer provided between the first gate electrode and the second silicon carbide region, between the first gate electrode and the third silicon carbide region, and between the first gate electrode and the sixth silicon carbide region.

[0014] The semiconductor device of the first embodiment is a planar gate type vertical MOSFET 100 using silicon carbide. The MOSFET 100 of the first embodiment is a Double Implantation MOSFET (DIMOSFET) in which the base region and source region are formed by ion implantation, for example. The semiconductor device of the first embodiment also includes an SBD (Schottky Barrier Diode) as an internal diode. The MOSFET 100 is a vertical n-channel type MOSFET that uses electrons as carriers.

[0015] Figure 1 is a schematic top view of a semiconductor device according to the first embodiment. Figure 1 is a diagram showing the arrangement of each region of the MOSFET 100.

[0016] As shown in Figure 1, the MOSFET 100 includes an element region 101 and a termination region 102.

[0017] The element region 101 is provided with a MOSFET and an SBD. The termination region 102 surrounds the element region 101. The termination region 102 is provided with a structure to improve the breakdown voltage of the MOSFET 100. The structure to improve the breakdown voltage of the MOSFET 100 is, for example, a resurf or a guard ring.

[0018] Figure 2 is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment. Figure 2 is the AA' cross-section of Figures 1, 3, and 4.

[0019] Figure 3 is a schematic top view of a part of the semiconductor device of the first embodiment. Figure 3 shows the layout pattern of the gate electrode and silicon carbide region on the first surface side of the silicon carbide layer.

[0020] Figure 4 is a schematic top view of a part of the semiconductor device of the first embodiment. Figure 4 shows the layout pattern of the silicon carbide region on the first surface side of the silicon carbide layer. Figure 4 is a view of Figure 3 with the gate electrode removed.

[0021] Figure 5 is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment. Figure 5 is the BB' section of Figures 3 and 4.

[0022] Figure 6 is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment. Figure 6 is the CC' section of Figures 3 and 4.

[0023] The MOSFET 100 comprises a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a first gate electrode 18a, a second gate electrode 18b, a third gate electrode 18c, a fourth gate electrode 18d, and an interlayer insulating layer 20.

[0024] Hereinafter, the first gate electrode 18a, the second gate electrode 18b, the third gate electrode 18c, and the fourth gate electrode 18d may be referred to individually or collectively simply as gate electrode 18.

[0025] Within the silicon carbide layer 10, n + Drain area 30 of type n - The drift region 32 of type p (first silicon carbide region), the first base region 34a of type p (second silicon carbide region), the second base region 34b of type p (third silicon carbide region), the third base region 34c of type p (fourth silicon carbide region), the fourth base region 34d of type p, the fifth base region 34e of type p, the sixth base region 34f of type p, n + It includes a source region 36 of type p (the fifth silicon carbide region), a first intermediate region 38a of type p (the sixth silicon carbide region), a second intermediate region 38b of type p, a third intermediate region 38c of type p, and a fourth intermediate region 38d of type p.

[0026] The drift region 32 includes a first portion 32a, a second portion 32b, a third portion 32c, and a fifth portion 32e.

[0027] Hereinafter, the first base region 34a, the second base region 34b, the third base region 34c, the fourth base region 34d, the fifth base region 34e, and the sixth base region 34f may be referred to individually or collectively simply as base region 34. Also, the first intermediate region 38a, the second intermediate region 38b, the third intermediate region 38c, and the fourth intermediate region 38d may be referred to individually or collectively simply as intermediate region 38.

[0028] The silicon carbide layer 10 is provided between the source electrode 12 and the drain electrode 14. The silicon carbide layer 10 is provided between the gate electrode 18 and the drain electrode 14. The silicon carbide layer 10 is single-crystal SiC. The silicon carbide layer 10 is, for example, 4H-SiC.

[0029] The silicon carbide layer 10 comprises a first surface ("F1" in Figures 2, 5, and 6) and a second surface ("F2" in Figures 2, 5, and 6). The first surface F1 is the surface of the silicon carbide layer. The second surface F2 is the back surface of the silicon carbide layer. Hereinafter, the first surface F1 may be referred to as the surface and the second surface F2 as the back surface. The first surface F1 is located on the source electrode 12 side of the silicon carbide layer 10. The second surface F2 is located on the drain electrode 14 side of the silicon carbide layer 10. The first surface F1 and the second surface F2 face each other. Hereinafter, "depth" refers to the depth in the direction toward the second surface with respect to the first surface. The "surfaces" of the first surface F1 and the second surface F2 refer to, for example, the interface between the silicon carbide layer and the insulating layer, or between the silicon carbide layer and the metal.

[0030] We define the first direction as one direction parallel to the first plane. We also define the second direction as a direction parallel to the first plane and perpendicular to the first direction.

[0031] Figures 2 and 5 show cross-sections perpendicular to the first direction. Figure 6 shows a cross-section perpendicular to the second direction.

[0032] The first surface F1 is, for example, a surface inclined at an angle of 0 to 8 degrees relative to the (0001) surface. The second surface F2 is, for example, a surface inclined at an angle of 0 to 8 degrees relative to the (000-1) surface. The (0001) surface is referred to as the silicon surface. The (000-1) surface is referred to as the carbon surface.

[0033] The thickness of the silicon carbide layer 10 is, for example, 5 μm to 350 μm.

[0034] n + The drain region 30 is provided on the back side of the silicon carbide layer 10. The drain region 30 contains, for example, nitrogen (N) as an n-type impurity. The concentration of n-type impurities in the drain region 30 is, for example, 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0035] n - A drift region 32 of this type is provided between the drain region 30 and the first surface F1. A drift region 32 is provided between the source electrode 12 and the drain electrode 14. A drift region 32 is provided between the gate electrode 18 and the drain electrode 14.

[0036] The drift region 32 is provided between the drain region 30 and the first surface F1. The drift region 32 is provided on the drain region 30.

[0037] The drift region 32 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration in the drift region 32 is lower than the n-type impurity concentration in the drain region 30. The n-type impurity concentration in the drift region 32 is, for example, 4 × 10⁻⁶. 14 cm -3 The above 5 x 10 17 cm -3 The following applies: The thickness of the drift region 32 is, for example, between 3 μm and 100 μm.

[0038] The drift region 32 includes a portion tangent to the first surface F1. The drift region 32 includes, for example, a first portion 32a, a second portion 32b, a third portion 32c, and a fifth portion 32e tangent to the first surface F1.

[0039] The first portion 32a and the fifth portion 32e extend in the first direction. The first portion 32a and the fifth portion 32e are in contact with the source electrode 12.

[0040] The first portion 32a and the fifth portion 32e are provided between two adjacent base regions 34 in a second direction. For example, the first portion 32a is provided between the first base region 34a and the third base region 34c. For example, the fifth portion 32e is provided between the fifth base region 34e and the sixth base region 34f.

[0041] The first portion 32a and the fifth portion 32e function as n-type semiconductor regions of the SBD.

[0042] The second portion 32b and the third portion 32c are provided between two adjacent base regions 34 in the second direction. The second portion 32b and the third portion 32c are provided between the first base region 34a and the second base region 34b. The second portion 32b and the third portion 32c face the first gate electrode 18a.

[0043] The second portion 32b and the third portion 32c function as paths for the on-current when the MOSFET 100 is in the ON state.

[0044] The p-shaped base region 34 is provided between the drift region 32 and the first surface F1. The base region 34 extends in a first direction. The base region 34 is repeatedly arranged in a second direction.

[0045] The second base region 34b is provided in a second direction relative to the first base region 34a. The third base region 34c is provided in a second direction relative to the first base region 34a. The first base region 34a is provided between the third base region 34c and the second base region 34b. The first portion 32a is provided between the first base region 34a and the third base region 34c.

[0046] A portion of the base region 34 functions as the channel region of the MOSFET 100. The base region 34 functions as the p-type semiconductor region of the pn junction diode.

[0047] The base region 34 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration in the base region 34 is, for example, 5 × 10⁻⁶ 17 cm -3 The above 1 x 10 21 cm -3 The following applies. Note that the p-type impurity concentration in the base region 34 is defined as the p-type impurity concentration at half the depth of the base region 34.

[0048] The depth of the base region 34 is, for example, between 0.3 μm and 1.0 μm.

[0049] The base region 34 is electrically connected to the source electrode 12. The base region 34 is fixed at the potential of the source electrode 12.

[0050] n + The source region 36 of the mold is provided between the base region 34 and the first surface F1. The source region 36 is provided, for example, between the first base region 34a and the first surface F1. The source region 36 extends, for example, in a first direction.

[0051] Source region 36 contains, for example, phosphorus (P) as an n-type impurity. The concentration of n-type impurities in source region 36 is higher than the concentration of n-type impurities in drift region 32.

[0052] The n-type impurity concentration in source region 36 is, for example, 1 × 10⁻⁶. 18 cm-3 The above 1 x 10 21 cm -3 The following applies: The depth of the source region 36 is shallower than the depth of the base region 34. For example, the depth of the source region 36 is between 0.1 μm and 0.3 μm.

[0053] The source region 36 is electrically connected to the source electrode 12. The source region 36 is fixed at the potential of the source electrode 12.

[0054] The p-type intermediate region 38 is provided between the drift region 32 and the first surface F1. The intermediate region 38 faces the gate electrode 18. The intermediate region 38 is provided between two base regions 34 that face the same gate electrode 18. The intermediate region 38 is in contact with the two base regions 34.

[0055] For example, the first intermediate region 38a faces the first gate electrode 18a. For example, the first intermediate region 38a is provided between the first base region 34a and the second base region 34b. For example, the first intermediate region 38a is in contact with both the first base region 34a and the second base region 34b.

[0056] For example, the second intermediate region 38b faces the third gate electrode 18c. For example, the second intermediate region 38b is provided between the second base region 34b and the fifth base region 34e. For example, the second intermediate region 38b is in contact with the second base region 34b and the fifth base region 34e.

[0057] For example, the third intermediate region 38c faces the second gate electrode 18b. For example, the third intermediate region 38c is provided between the fourth base region 34d and the third base region 34c. For example, the third intermediate region 38c is in contact with both the fourth base region 34d and the third base region 34c.

[0058] The intermediate region 38 is provided between a part of the drift region 32 and another part in a first direction. The intermediate region 38 is in contact with a part of the drift region 32 and another part in a first direction.

[0059] For example, the first intermediate region 38a is provided between the second portion 32b of the drift region 32 and the third portion 32c of the drift region 32. For example, the first intermediate region 38a is in contact with the second portion 32b and the third portion 32c.

[0060] The intermediate region 38 functions as the p-type semiconductor region of the pn junction diode.

[0061] The intermediate region 38 contains, for example, aluminum (Al) as a p-type impurity. The concentration of p-type impurities in the intermediate region 38 is substantially equal to, for example, the concentration of p-type impurities in the base region 34. The concentration of p-type impurities in the intermediate region 38 is, for example, 5 × 10⁻⁶ 17 cm -3 The above 1 x 10 21 cm -3 The following applies. Note that the p-type impurity concentration in the intermediate region 38 is defined as the p-type impurity concentration at half the depth of the base region 34.

[0062] The depth of the intermediate region 38 is, for example, substantially the same as the depth of the base region 34. The depth of the intermediate region 38 is, for example, between 0.3 μm and 1.0 μm.

[0063] The intermediate region 38 is electrically connected to the source electrode 12. The intermediate region 38 is fixed at the potential of the source electrode 12.

[0064] The gate electrode 18 is provided on the side of the first surface F1 of the silicon carbide layer 10. The gate electrode 18 extends in a first direction. Multiple gate electrode 18s are arranged parallel to each other in a second direction. The gate electrode 18 has a so-called stripe shape.

[0065] The gate electrode 18 is a conductive layer. The gate electrode 18 is, for example, polycrystalline silicon containing p-type or n-type impurities.

[0066] The gate electrode 18 faces, for example, the portion of the base region 34 that is in contact with the first surface F1. The gate electrode 18 faces, for example, the portion of the intermediate region 38 that is in contact with the first surface F1. The gate electrode 18 faces, for example, the portion of the drift region 32 that is in contact with the first surface F1.

[0067] For example, the first gate electrode 18a faces the first base region 34a. For example, the first gate electrode 18a faces the second base region 34b. For example, the first gate electrode 18a faces the first intermediate region 38a. For example, the first gate electrode 18a faces the second portion 32b of the drift region 32. For example, the first gate electrode 18a faces the third portion 32c of the drift region 32.

[0068] The gate insulating layer 16 is provided between the gate electrode 18 and the silicon carbide layer 10. The gate insulating layer 16 is provided between the gate electrode 18 and the base region 34. The gate insulating layer 16 is provided between the gate electrode 18 and the drift region 32.

[0069] For example, the gate insulating layer 16 is provided between the first gate electrode 18a and the first base region 34a. For example, the gate insulating layer 16 is provided between the first gate electrode 18a and the second base region 34b. For example, the gate insulating layer 16 is provided between the first gate electrode 18a and the first intermediate region 38a. For example, the gate insulating layer 16 is provided between the first gate electrode 18a and the second portion 32b of the drift region 32. For example, the gate insulating layer 16 is provided between the first gate electrode 18a and the third portion 32c of the drift region 32.

[0070] The gate insulating layer 16 is, for example, silicon oxide. For the gate insulating layer 16, for example, a high-k insulating material (high dielectric constant insulating material) can be applied.

[0071] The interlayer insulating layer 20 is provided on the gate electrode 18 and the silicon carbide layer 10. The interlayer insulating layer 20 is provided between the gate electrode 18 and the source electrode 12. The interlayer insulating layer 20 is, for example, silicon oxide.

[0072] The interlayer insulating layer 20 has the function of electrically isolating the gate electrode 18 and the source electrode 12.

[0073] The source electrode 12 is provided on the side of the first surface F1 of the silicon carbide layer 10. The source electrode 12 is in contact with the first surface F1.

[0074] The source electrode 12 is electrically connected to the drift region 32, the base region 34, the source region 36, and the intermediate region 38. The source electrode 12 is in contact with, for example, the drift region 32, the base region 34, and the source region 36. The source electrode 12 is in contact with, for example, the first portion 32a and the fifth portion 32e of the drift region 32.

[0075] The source electrode 12 contains a metal. The metal forming the source electrode 12 is, for example, a layered structure of titanium (Ti) and aluminum (Al).

[0076] The portion of the source electrode 12 that is in contact with the base region 34 and the source region 36 is, for example, a metal silicide. The metal silicide is, for example, titanium silicide or nickel silicide.

[0077] For example, no metal silicide is provided in the portion of the source electrode 12 that is in contact with the drift region 32. For example, no metal silicide is provided in the portions of the source electrode 12 that are in contact with the first portion 32a and the fifth portion 32e.

[0078] The junction between the base region 34 and the source region 36 and the source electrode 12 is, for example, an ohmic junction. The junction between the drift region 32 and the source electrode 12 is, for example, a Schottky junction. The junction between the first portion 32a and the fifth portion 32e and the source electrode 12 is, for example, a Schottky junction.

[0079] The drain electrode 14 is provided on the side of the second surface F2 of the silicon carbide layer 10. The drain electrode 14 is in contact with the second surface F2. The drain electrode 14 is in contact with the drain region 30.

[0080] The drain electrode 14 is, for example, a metal or a metal-semiconductor compound. The drain electrode 14 includes, for example, at least one material selected from the group consisting of nickel silicide, titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).

[0081] The junction between the drain region 30 and the drain electrode 14 is, for example, an ohmic junction.

[0082] Next, the operation and effects of the MOSFET 100 of the first embodiment will be described.

[0083] Figure 7 is a schematic cross-sectional view of a comparative example semiconductor device. Figure 7 corresponds to Figure 2 of the first embodiment.

[0084] The semiconductor device in the comparative example is a MOSFET 900. The MOSFET 900 differs from the MOSFET 100 of the first embodiment in that the silicon carbide layer 10 does not have an intermediate region 38.

[0085] Since the MOSFET900 does not have an intermediate region 38, a drift region 32 is always provided between two adjacent base regions 34. In the MOSFET900, a drift region 32 is always provided between two base regions 34 facing the same gate electrode 18.

[0086] Figure 8 is an equivalent circuit diagram of a comparative example semiconductor device. Between the source electrode 12 and the drain electrode 14, a pn junction diode and an SBD are connected in parallel with the transistor as built-in diodes.

[0087] For example, consider the case where MOSFET900 is used as a switching element connected to an inductive load. When MOSFET900 is off, a load current caused by the inductive load may apply a voltage that makes the source electrode 12 positive relative to the drain electrode 14. In this case, a forward current flows through the built-in diode. This state is also called a reverse conduction state.

[0088] The forward voltage (Vf) at which forward current begins to flow through the SBD is lower than the forward voltage (Vf) at which forward current begins to flow through the pn junction diode. Therefore, forward current flows through the SBD first.

[0089] The forward voltage (Vf) of an SBD is, for example, 1.0V. The forward voltage (Vf) of a pn junction diode is, for example, 2.5V.

[0090] The SBD operates unipolar. Therefore, even when a forward current flows, stacking faults do not grow in the silicon carbide layer 10 due to carrier recombination energy.

[0091] Figures 9 and 10 are explanatory diagrams of the diode operation of the comparative semiconductor device. Figures 9 and 10 are schematic cross-sectional views of the comparative semiconductor device. Figures 9 and 10 correspond to Figure 7.

[0092] Figures 9 and 10 show the current flowing through the built-in diode of the comparative example MOSFET900. Figure 9 shows the state where forward current flows only through the SBD, and Figure 10 shows the state where forward current flows through both the SBD and the pn junction diode.

[0093] Specifically, Figure 9 shows a state where the voltage applied across the pn junctions of a pn junction diode is lower than the forward voltage (Vf) of the pn junction diode. Figure 10, on the other hand, shows a state where the voltage applied across the pn junctions of a pn junction diode is higher than the forward voltage (Vf) of the pn junction diode.

[0094] In Figures 9 and 10, the dotted arrows indicate the current flowing through the SBD. In Figure 10, the solid arrows indicate the current flowing through the pn junction diode.

[0095] As shown in Figure 9, the current flowing through the SBD wraps around to the bottom of the base region 34. As a result, electrostatic potential wraps around to the drift region 32 opposite the bottom of the base region 34. This wrap-around of electrostatic potential reduces the voltage applied between the base region 34 and the drift region 32.

[0096] Therefore, the forward voltage (Vf) of the pn junction diode is less likely to be exceeded at the bottom of the base region 34. In other words, the operating start voltage of the pn junction diode in the comparative example MOSFET 900 can be made higher compared to the case without an SBD. Consequently, the bipolar operation of the pn junction diode is suppressed, and the formation of stacking faults in the silicon carbide layer 10 due to carrier recombination energy is suppressed.

[0097] A surge voltage exceeding the steady state may be instantaneously applied between the electrodes of a MOSFET, causing a surge current to flow. For example, the surge current flows from the source electrode 12 to the drain electrode 14.

[0098] When a large surge current flows, the MOSFET overheats and can be destroyed. The maximum allowable peak current value (I) is the maximum surge current that the MOSFET can handle. FSM This is called surge current withstand capability. In MOSFETs equipped with SBDs, it is desirable to improve the surge current withstand capability.

[0099] When a large surge voltage is applied to the comparative example MOSFET900, the voltage applied across the pn junction of the pn junction diode becomes higher than the forward voltage (Vf) of the pn junction diode.

[0100] When the voltage applied across the pn junction of a pn junction diode becomes higher than the operating start voltage of the pn junction diode, current flows through the pn junction diode, as shown in Figure 10. By allowing current to flow through the pn junction diode, it becomes possible to supply a large current to the MOSFET 900, thereby improving its surge current withstand capability.

[0101] Figures 11 and 12 are explanatory diagrams of the diode operation of the semiconductor device of the first embodiment. Figures 11 and 12 are schematic cross-sectional views of the semiconductor device of the first embodiment. Figures 11 and 12 correspond to Figure 2. Also, Figures 11 and 12 correspond to Figures 9 and 10 of the comparative example.

[0102] Figures 11 and 12 show the currents flowing through the built-in diodes of the MOSFET 100 in the first embodiment. Figure 11 shows the state where forward current flows only through the SBD, and Figure 12 shows the state where forward current flows through both the SBD and the pn junction diode.

[0103] Figure 11 shows a state in which the voltage applied across the pn junction of the pn junction diode is lower than the forward voltage (Vf) of the pn junction diode. In this state, similar to the comparative example MOSFET 900, the voltage applied between the base region 34 and the drift region 32 is reduced due to the leakage of the electrostatic potential. Therefore, similar to the comparative example MOSFET 900, the bipolar operation of the pn junction diode is suppressed, and the formation of stacking faults in the silicon carbide layer 10 due to carrier recombination energy is suppressed.

[0104] Figure 12 shows a state in which the voltage applied across the pn junction of a pn junction diode is higher than the forward voltage (Vf) of the pn junction diode. The MOSFET 100 of the first embodiment includes an intermediate region 38. Therefore, the effective pn junction area is larger compared to the comparative example MOSFET 900. Consequently, as shown in Figure 12, the current flowing through the pn junction diode is larger compared to the comparative example MOSFET 900. Thus, the surge current withstand capability can be further improved.

[0105] According to the first embodiment, the surge current withstand capability can be improved in a MOSFET equipped with an SBD.

[0106] (First variation) The semiconductor device of the first modified embodiment differs from the semiconductor device of the first embodiment in that the concentration of the second conductivity type impurity in the sixth silicon carbide region is lower than the concentration of the second conductivity type impurity in the second silicon carbide region and the concentration of the second conductivity type impurity in the third silicon carbide region.

[0107] Figure 13 is a schematic cross-sectional view of a semiconductor device of a first modification of the first embodiment. Figure 13 corresponds to Figure 2 of the first embodiment.

[0108] The semiconductor device of the first modification of the first embodiment is a MOSFET 110.

[0109] In MOSFET110, the p-type impurity concentration in the intermediate region 38 is lower than that in the base region 34. For example, the p-type impurity concentration in the intermediate region 38 is between 20% and 90% of the p-type impurity concentration in the base region 34. The p-type impurity concentrations in the intermediate region 38 and the base region 34 are defined as the p-type impurity concentration at half the depth of the base region 34.

[0110] For example, the p-type impurity concentration in the first intermediate region 38a is between 20% and 90% of the p-type impurity concentration in the first base region 34a and the p-type impurity concentration in the second base region 34b.

[0111] According to the first modification of the first embodiment, as in the first embodiment, the surge current withstand capability can be improved in a MOSFET equipped with an SBD. Furthermore, by lowering the p-type impurity concentration in the intermediate region 38, for example, when forming the intermediate region 38 using an ion implantation method, the amount of defects caused by ion implantation damage in the silicon carbide layer 10 can be reduced. Therefore, the reliability of the gate insulating layer 16 provided on the intermediate region 38 is improved.

[0112] (Second variation) The semiconductor device of the second modification of the first embodiment differs from the semiconductor device of the first embodiment in that the silicon carbide layer further includes a seventh silicon carbide region of a first conductivity type provided between a sixth silicon carbide region and a first surface.

[0113] Figures 14 and 15 are schematic cross-sectional views of a semiconductor device of a second modification of the first embodiment. Figure 14 corresponds to Figure 2 of the first embodiment. Figure 15 corresponds to Figure 6 of the first embodiment.

[0114] The semiconductor device of the second modified example of the first embodiment is a MOSFET 120.

[0115] The silicon carbide layer 10 of MOSFET120 is n - It differs from the MOSFET 100 of the first embodiment in that it further includes a surface region 40 (the seventh silicon carbide region) of the shape.

[0116] n - The surface region 40 of the shape is provided between the intermediate region 38 and the first surface F1. The surface region 40 is provided, for example, between the second portion 32b and the third portion 32c of the drift region 32 in a first direction. The intermediate region 38 is in contact with, for example, the second portion 32b and the third portion 32c.

[0117] The surface region 40 functions as a path for the on-current when the MOSFET 120 is in the ON state.

[0118] The surface region 40 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration in the surface region 40 is, for example, 4 × 10⁻⁶ 14 cm -3 The above 5 x 10 17 cm -3 The following applies:

[0119] According to the second modification of the first embodiment, similar to the first embodiment, the surge current withstand capability can be improved in the MOSFET equipped with an SBD. Furthermore, by providing the surface region 40, the area directly above the intermediate region 38 also functions as a path for the on-current when the MOSFET 120 is in the ON state. Therefore, the on-resistance of the MOSFET 120 is reduced.

[0120] As described above, according to the first embodiment and its modifications, it is possible to improve the surge current withstand capability of a MOSFET equipped with an SBD.

[0121] (Second embodiment) The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the first depth of the sixth silicon carbide region relative to the first surface is shallower than the second depth of the second silicon carbide region relative to the first surface and the third depth of the third silicon carbide region relative to the first surface. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0122] Figure 16 is a schematic cross-sectional view of a semiconductor device according to the second embodiment. Figure 16 corresponds to Figure 2 of the first embodiment.

[0123] The semiconductor device of the second embodiment is a MOSFET 200. In the MOSFET 200, the depth of the intermediate region 38 relative to the first surface F1 is shallower than the depth of the base region 34 relative to the first surface F1. For example, the depth of the intermediate region 38 relative to the first surface F1 is between two-thirds and nine-tenths of the depth of the base region 34 relative to the first surface F1.

[0124] For example, the depth of the first intermediate region 38a relative to the first surface F1 (d1 in Figure 16) is shallower than the depth of the first base region 34a relative to the first surface F1 (d2 in Figure 16) and the depth of the second base region 34b relative to the first surface F1 (d3 in Figure 16). Also, for example, the depth d1 of the first intermediate region 38a relative to the first surface F1 is between two-thirds and nine-tenths of the depth d2 of the first base region 34a relative to the first surface F1 and the depth d3 of the second base region 34b relative to the first surface F1.

[0125] According to the second embodiment, similar to the first embodiment, it is possible to improve the surge current withstand capability in a MOSFET equipped with an SBD.

[0126] Furthermore, because the depth of the intermediate region 38 relative to the first surface F1 is shallower than the depth of the base region 34 relative to the first surface F1, irregularities are formed on the pn junction surface, increasing the effective area of ​​the pn junction. Consequently, the current flowing through the pn junction diode increases. Therefore, the surge current withstand capability can be further improved.

[0127] Furthermore, current concentrates in the uneven areas of the pn junction surface, increasing the current flowing through the pn junction diode. Therefore, the surge current withstand capability can be further improved.

[0128] As described above, according to the second embodiment, similar to the first embodiment, it is possible to improve the surge current withstand capability in a MOSFET equipped with an SBD.

[0129] Furthermore, it is also possible to combine the MOSFET200 of the second embodiment with the components of the MOSFET110 of the first modified example or the MOSFET120 of the second modified example of the first embodiment.

[0130] (Third embodiment) The semiconductor device of the third embodiment further comprises a second gate electrode extending in a first direction and facing a fourth silicon carbide region, the first silicon carbide region further includes a fourth portion touching the first surface and extending in the first direction, the fourth silicon carbide region is provided between the fourth portion and the first portion, and the second gate electrode faces the fourth portion, thus differing from the semiconductor device of the first embodiment. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0131] The semiconductor device of the third embodiment is a MOSFET300.

[0132] Figure 17 is a schematic cross-sectional view of a part of the semiconductor device of the third embodiment. Figure 17 is the DD' section of Figures 18 and 19.

[0133] Figure 18 is a schematic top view of a part of the semiconductor device of the third embodiment. Figure 18 shows the layout pattern of the gate electrode and silicon carbide region on the first surface side of the silicon carbide layer.

[0134] Figure 19 is a schematic top view of a part of the semiconductor device of the third embodiment. Figure 19 shows the layout pattern of the silicon carbide region on the first surface side of the silicon carbide layer. Figure 19 is the same as Figure 18 but with the gate electrode removed.

[0135] Figure 20 is a schematic cross-sectional view of a part of the semiconductor device of the third embodiment. Figure 20 is the EE' section of Figures 18 and 19.

[0136] Figure 21 is a schematic cross-sectional view of a part of the semiconductor device of the third embodiment. Figure 21 is the FF' cross-section of Figures 18 and 19.

[0137] Figures 17 and 20 show cross-sections perpendicular to the first direction. Figure 21 shows a cross-section perpendicular to the second direction.

[0138] The MOSFET 300 comprises a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a first gate electrode 18a, a second gate electrode 18b, a third gate electrode 18c, a fourth gate electrode 18d, and an interlayer insulating layer 20.

[0139] Hereinafter, the first gate electrode 18a, the second gate electrode 18b, the third gate electrode 18c, and the fourth gate electrode 18d may be referred to individually or collectively simply as gate electrode 18.

[0140] Within the silicon carbide layer 10, n + Drain area 30 of type n - The drift region 32 of type p (first silicon carbide region), the first base region 34a of type p (second silicon carbide region), the second base region 34b of type p (third silicon carbide region), the third base region 34c of type p (fourth silicon carbide region), the fourth base region 34d of type p, the fifth base region 34e of type p, the sixth base region 34f of type p, n + It includes a source region 36 of type p (the fifth silicon carbide region), a first intermediate region 38a of type p (the sixth silicon carbide region), and a second intermediate region 38b of type p.

[0141] The drift region 32 includes a first portion 32a, a fourth portion 32d, and a fifth portion 32e.

[0142] Hereinafter, the first base region 34a, the second base region 34b, the third base region 34c, the fourth base region 34d, the fifth base region 34e, and the sixth base region 34f may be referred to individually or collectively simply as base region 34. Also, the first intermediate region 38a and the second intermediate region 38b may be referred to individually or collectively simply as intermediate region 38.

[0143] The fourth portion 32d of the drift region 32 is tangent to the first surface F1. The fourth portion 32d extends in the first direction.

[0144] In the second direction, a third base region 34c is provided between the fourth portion 32d and the first portion 32a. In the second direction, the fourth portion 32d is provided between the third base region 34c and the fourth base region 34d.

[0145] No intermediate region 38 is provided between the third base region 34c and the fourth base region 34d.

[0146] The fourth portion 32d functions as a path for the on-current when MOSFET 300 is in the ON state.

[0147] A drift region 32 is not provided between the first base region 34a and the second base region 34b.

[0148] As described above, according to the third embodiment, similar to the first embodiment, it is possible to improve the surge current withstand capability in a MOSFET equipped with an SBD.

[0149] Furthermore, it is also possible to combine the MOSFET 300 of the third embodiment with the components of the MOSFET 110 of the first modified example, the MOSFET 120 of the second modified example, or the MOSFET 200 of the second embodiment.

[0150] In the first to third embodiments, the case where the first conductivity type is n-type and the second conductivity type is p-type was explained as an example, but it is also possible to have the first conductivity type be p-type and the second conductivity type be n-type.

[0151] In the first to third embodiments, the case of 4H-SiC as the crystal structure of SiC was described as an example, but the present invention can also be applied to devices using SiC with other crystal structures such as 6H-SiC and 3C-SiC. Furthermore, it is possible to apply a plane other than the (0001) plane to the surface of the silicon carbide layer 10.

[0152] In the first to third embodiments, aluminum (Al) was exemplified as a p-type impurity, but boron (B) can also be used. Similarly, while nitrogen (N) and phosphorus (P) were exemplified as n-type impurities, arsenic (As), antimony (Sb), etc., can also be applied.

[0153] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0154] 10. Silicon carbide layer 12 Source electrode (first electrode) 14. Drain electrode (second electrode) 16 Gate insulating layer 18a First gate electrode 18b Second gate electrode 32. Drift region (first silicon carbide region) 32a Part 1 32b Second part 32c Third part 32d Part 4 34a First base region (second silicon carbide region) 34b Second base region (third silicon carbide region) 34c Third base region (fourth silicon carbide region) 36. Source region (5th silicon carbide region) 38a First intermediate region (sixth silicon carbide region) 40. Surface region (7th silicon carbide region) 100 MOSFETs (Semiconductor Devices) 110 MOSFETs (Semiconductor Devices) 120 MOSFETs (Semiconductor Devices) 200 MOSFETs (Semiconductor Equipment) 300 MOSFETs (semiconductor equipment) F1 First Side F2 Second side d1 First depth d2 Second depth d3 Third depth

Claims

1. The first electrode and The second electrode and A silicon carbide layer provided between the first electrode and the second electrode, having a first surface on the side of the first electrode and a second surface on the side of the second electrode, A first silicon carbide region of a first conductivity type, including a first portion that is in contact with the first electrode and extends in a first direction parallel to the first surface, A second silicon carbide region of second conductivity type is provided between the first silicon carbide region and the first surface, extending in the first direction and electrically connected to the first electrode, A third silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, extending in the first direction, and provided in a second direction parallel to the first surface and perpendicular to the first direction with respect to the second silicon carbide region, and is electrically connected to the first electrode. A fourth silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, extending in the first direction, provided in the second direction with respect to the second silicon carbide region, providing a second silicon carbide region between it and the third silicon carbide region, providing a first portion between it and the second silicon carbide region, and electrically connected to the first electrode. A fifth silicon carbide region of first conductivity type is provided between the second silicon carbide region and the first surface and is electrically connected to the first electrode, A sixth silicon carbide region of second conductivity is provided between the first silicon carbide region and the first surface, and between the second silicon carbide region and the third silicon carbide region, and is in contact with the second silicon carbide region and the third silicon carbide region, and is electrically connected to the first electrode, A silicon carbide layer containing, A first gate electrode extending in the first direction and facing the second silicon carbide region, the third silicon carbide region, and the sixth silicon carbide region, A gate insulating layer is provided between the first gate electrode and the second silicon carbide region, between the first gate electrode and the third silicon carbide region, and between the first gate electrode and the sixth silicon carbide region. A semiconductor device equipped with the following features.

2. The semiconductor device according to claim 1, wherein the first depth of the sixth silicon carbide region with respect to the first surface is shallower than the second depth of the second silicon carbide region with respect to the first surface and the third depth of the third silicon carbide region with respect to the first surface.

3. The semiconductor device according to claim 2, wherein the first depth is two-thirds or more and nine-tenths or less of the second depth and the third depth.

4. The semiconductor device according to claim 1, wherein the concentration of the second conductivity type impurity in the sixth silicon carbide region is lower than the concentration of the second conductivity type impurity in the second silicon carbide region and the concentration of the second conductivity type impurity in the third silicon carbide region.

5. The first silicon carbide region further includes a second portion in contact with the first surface and a third portion in contact with the first surface. The second and third portions are provided between the second silicon carbide region and the third silicon carbide region, and the sixth silicon carbide region is provided between the second and third portions. The semiconductor device according to claim 1, wherein the first gate electrode faces the second portion and the third portion.

6. The present invention further comprises a second gate electrode extending in the first direction and facing the fourth silicon carbide region, The first silicon carbide region further includes a fourth portion that is in contact with the first surface and extends in the first direction. A fourth silicon carbide region is provided between the fourth portion and the first portion. The semiconductor device according to claim 1, wherein the gate electrode 2 faces the fourth portion.

7. The semiconductor device according to claim 1, wherein the sixth silicon carbide region is in contact with the first surface.

8. The semiconductor device according to claim 1, wherein the silicon carbide layer further includes a seventh silicon carbide region of a first conductivity type provided between the sixth silicon carbide region and the first surface.

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