SiC composite substrate and method for manufacturing the same

Abstract

The present invention provides a SiC composite substrate and a method for manufacturing the same, which suppresses warping of a single-crystal SiC layer formed by remote epitaxial growth. [Solution] The SiC composite substrate 1 comprises a single-crystal SiC layer 23 and a polycrystalline SiC substrate 11 formed directly on one main surface of the single-crystal SiC layer 23 by CVD. The stresses generated in the single-crystal SiC layer 23 and the polycrystalline SiC substrate 11 are matched in positive and negative terms, and the stress between the polycrystalline SiC substrate and the single-crystal SiC layer is relaxed. The manufacturing method of the SiC composite substrate 1 includes the steps of: providing a single-crystal SiC substrate 21 on which a graphene film 22 is formed on the main surface; epitaxially growing a single-crystal SiC layer 23 on the main surface of the single-crystal SiC substrate 21 via the graphene film 22; peeling the single-crystal SiC layer 23 from the graphene film 22; and forming a polycrystalline SiC substrate 11 directly on one main surface of the single-crystal SiC layer 23 by CVD.

Description

[Technical Field]

[0001] This disclosure relates to a SiC composite substrate and a method for manufacturing the same. [Background technology]

[0002] Conventionally, SiC-based devices such as Schottky barrier diodes (SBDs) and insulated-gate field-effect transistors (MOSFETs) have been provided for power control applications. Single-crystal SiC substrates on which such SiC-based devices are formed are generally manufactured using a sublimation-recrystallization method called the modified Lely method. However, this method suffers from low efficiency in crystal growth and wafer processing, resulting in high manufacturing costs.

[0003] Therefore, in order to reduce manufacturing costs, techniques have been provided for fabricating SiC composite substrates by growing a polycrystalline SiC substrate on a single-crystal SiC layer using chemical vapor deposition (CVD), or by bonding a single-crystal SiC layer manufactured by remote epitaxial growth to a polycrystalline SiC substrate (Patent Documents 1 and 2). On the other hand, a technique has been disclosed in which a tungsten film and a silicon film are sandwiched between the surfaces of two SiC semiconductor components and laminated, and a WSi2 mixture is formed by heat treatment (Patent Document 3).

[0004] Furthermore, a technique for suppressing warping by depositing wedge-shaped structures on both sides of a fine-grained SiC substrate has been disclosed (Patent Document 4). [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] International Publication No. 2021 / 020574 [Patent Document 2] International Publication No. 2017 / 047509 [Patent Document 3] Japanese National Publication of International Patent Application No. 2003-509843 [Patent Document 4] Japanese Unexamined Patent Publication No. 2003-113472

[0006] [Abstract] However, in the conventional remote epitaxial growth method, a single-crystal SiC layer is epitaxially grown on the main surface of a single-crystal SiC substrate via a graphene film, and the single-crystal SiC layer peeled off from the single-crystal SiC substrate warps when peeled off.

[0007] The present disclosure is proposed in view of the above circumstances, and an object of the present disclosure is to provide a SiC composite substrate and a method for manufacturing the same, which suppresses warpage of a single-crystal SiC layer formed by a remote epitaxial growth method.

[0008] In order to solve the above-mentioned problem, the SiC composite substrate of the present disclosure includes a single-crystal SiC layer and a polycrystalline SiC substrate formed directly by CVD on one main surface of the single-crystal SiC layer, wherein the signs of stress generated in the single-crystal SiC layer and the polycrystalline SiC substrate are matched, thereby relaxing the stress between the polycrystalline SiC substrate and the single-crystal SiC layer.

[0009] The method for manufacturing a SiC composite substrate of the present disclosure comprises: a step of providing a single-crystal SiC substrate having a graphene film formed on a main surface thereof; a step of epitaxially growing a single-crystal SiC layer on the main surface of the single-crystal SiC substrate via the graphene film; a step of peeling the single-crystal SiC layer from the graphene film; and a step of forming a polycrystalline SiC substrate on one main surface of the single-crystal SiC layer by CVD, wherein the signs of stress generated in the single-crystal SiC layer and the polycrystalline SiC substrate are matched, thereby relaxing the stress between the polycrystalline SiC substrate and the single-crystal SiC layer. [Brief Description of Drawings]

[0010] [Figure 1A] FIG. 1A is a schematic diagram of internal stress in a single-crystal SiC layer formed by remote epitaxial growth in the SiC composite substrate according to the embodiment. [Figure 1B] Figure 1B is a schematic diagram of the stresses on the surface and back sides of the exfoliated single-crystal SiC layer. [Figure 1C] Figure 1C is an explanatory diagram of a SiC composite substrate according to an embodiment in which a polycrystalline SiC substrate is directly formed on a single-crystal SiC layer by a CVD method to relieve stress on the single-crystal SiC layer. [Figure 2A] Figure 2A is an explanatory diagram illustrating the direct CVD method for forming polycrystalline SiC, which generates internal stress to alleviate the warping of a single-crystal SiC layer having an upward convex warp. [Figure 2B] Figure 2B is a cross-sectional view of the SiC composite substrate according to the embodiment obtained as a result of Figure 2A. [Figure 3A] Figure 3A is an explanatory diagram illustrating the direct CVD method for forming polycrystalline SiC, which generates internal stress to alleviate the warping of a single-crystal SiC layer having a downward convex warp. [Figure 3B] Figure 3B is a cross-sectional view of the SiC composite substrate according to the embodiment obtained as a result of Figure 3A. [Figure 4] Figure 4 is a cross-sectional view of a SiC composite substrate according to an embodiment. [Figure 5] Figure 5 is a cross-sectional view of a SiC composite substrate according to a modified example of the embodiment. [Figure 6A] Figure 6A is a process flow diagram (first half) of the manufacturing method of a SiC composite substrate according to the embodiment. [Figure 6B] Figure 6B is a process flow diagram (first half) of the manufacturing method of a SiC composite substrate according to the embodiment. [Figure 6C] Figure 6C is a process flow diagram (first half) of the manufacturing method of a SiC composite substrate according to the embodiment. [Figure 6D] Figure 6D is a process flow diagram (first half) of the manufacturing method for a SiC composite substrate according to the embodiment. [Figure 7A] Figure 7A is a process flow diagram (second half) of the manufacturing method for a SiC composite substrate according to the embodiment. [Figure 7B]Figure 7B is a cross-sectional view illustrating a method for manufacturing a SiC composite substrate according to an embodiment. [Figure 7C] Figure 7C is a diagram illustrating a method for manufacturing a SiC composite substrate according to an embodiment. [Figure 8] Figure 8 illustrates a method for manufacturing a SiC composite substrate according to a modified embodiment. [Figure 9] Figure 9 is a cross-sectional view of a Schottky barrier diode to which a SiC composite substrate according to an embodiment is applied. [Figure 10] Figure 10 is a cross-sectional view of a trench gate type MOSFET to which a SiC composite substrate according to an embodiment is applied.

[0011] [Detailed explanation] The embodiments of the SiC composite substrate and its manufacturing method described herein will be described in detail below with reference to the drawings. The embodiments are general or specific examples. The numerical values, shapes, materials, components, installation locations of components, and connection configurations shown in the embodiments are examples and are not intended to limit the scope of this disclosure. Furthermore, among the components in the following embodiments, those not described in the independent claim indicating the highest-level concept will be described as optional components. In addition, the dimensional ratios in the drawings are exaggerated for illustrative purposes and may differ from the actual ratios. Furthermore, the following embodiments and their modifications may include similar components, and similar components will be given the same reference numerals, and redundant descriptions will be omitted.

[0012] (Mechanism of stress relaxation) Figure 1A is a schematic diagram of the internal stress of a single-crystal SiC layer 23 formed by remote epitaxial growth in a SiC composite substrate according to an embodiment. Figure 1B is a schematic diagram of the stress on the surface and back sides of a peeled single-crystal SiC layer.

[0013] As shown in Figure 1A, the single-crystal SiC layer 23 is formed on the single-crystal SiC substrate 21 by remote epitaxial growth via a graphene film 22. Therefore, during epitaxial growth, internal stress is generated in the single-crystal SiC layer 23 in the direction indicated by the arrow in Figure 1A. Consequently, when the single-crystal SiC layer 23 is peeled from the single-crystal SiC substrate 21, warping occurs in the single-crystal SiC layer 23, for example, as shown in Figure 1B. In the example in Figure 1B, a downward convex warp occurs. As a result, in the example in Figure 1B, compressive stress CS is generated on the surface side of the single-crystal SiC layer 23 in the direction indicated by the arrow. On the other hand, tensile stress TS is generated on the back side of the single-crystal SiC layer 23 in the direction indicated by the arrow.

[0014] Figure 1C is an explanatory diagram of a SiC composite substrate in which a polycrystalline SiC substrate 11 is directly formed on a single-crystal SiC layer 23 by CVD to relieve stress on the single-crystal SiC layer 23.

[0015] When growing polycrystalline SiC directly onto a warped single-crystal SiC layer 23 using the CVD method, a SiC composite substrate with reduced warping of the single-crystal SiC layer 23 can be obtained by generating stress in a direction that cancels out the warping of the single-crystal SiC layer 23, as shown in Figure 1C. In the example shown in Figure 1C, the compressive stress CS generated on the surface side of the single-crystal SiC layer 23 is relieved by the compressive stress CS generated on the back side of the polycrystalline SiC substrate 11. As a result, as shown in Figure 1C, the stresses generated in the single-crystal SiC layer 23 and the polycrystalline SiC substrate 11 are matched in terms of positive and negative, and a SiC composite substrate with reduced stress between the single-crystal SiC layer 23 and the polycrystalline SiC substrate 11 can be obtained.

[0016] (Example of a single-crystal SiC layer with upward convex curvature) Figure 2A is an explanatory diagram illustrating the direct CVD method for forming polycrystalline SiC on a single-crystal SiC layer 23 having an upward convex curvature, which generates internal stress to alleviate the curvature of the single-crystal SiC layer 23. Figure 2B is a cross-sectional view of the SiC composite substrate according to the embodiment obtained as a result of Figure 2A.

[0017] When the single-crystal SiC layer 23 is peeled off from the single-crystal SiC substrate 21, the single-crystal SiC layer 23 exhibits warping, for example, as shown in Figure 2A. In the example in Figure 2A, upward convex warping occurs. As a result, in the example in Figure 2A, tensile stress TS is generated on the surface side of the single-crystal SiC layer 23 in the direction indicated by the arrow. On the other hand, compressive stress CS is generated on the back side of the single-crystal SiC layer 23 in the direction indicated by the arrow.

[0018] When growing polycrystalline SiC directly onto a warped single-crystal SiC layer 23 using the CVD method, stress is generated in a direction that cancels out the warping in the single-crystal SiC layer 23. In the example shown in Figure 2A, when growing the polycrystalline SiC, compressive stress CS is generated on the surface side in the direction indicated by the arrow, and tensile stress TS is generated on the back side in the direction indicated by the arrow. In the example shown in Figure 2B, the tensile stress TS generated on the surface side of the single-crystal SiC layer 23 is relaxed by the tensile stress TS generated on the back side of the polycrystalline SiC substrate 11. As a result, as shown in Figure 2B, the stresses generated in the single-crystal SiC layer 23 and the polycrystalline SiC substrate 11 are matched in positive and negative signs, and a SiC composite substrate can be obtained in which the stress between the single-crystal SiC layer 23 and the polycrystalline SiC substrate 11 is relaxed.

[0019] (Example of a single-crystal SiC layer with downward convex curvature) Figure 3A is an explanatory diagram illustrating the direct CVD method for forming polycrystalline SiC on a single-crystal SiC layer 23 having a downward convex curvature, which generates internal stress to alleviate the curvature of the single-crystal SiC layer 23. Figure 3B is a cross-sectional view of the SiC composite substrate according to the embodiment obtained as a result of Figure 3A.

[0020] When the single-crystal SiC layer 23 is peeled off from the single-crystal SiC substrate 21, the single-crystal SiC layer 23 exhibits warping, for example, as shown in Figure 3A. In the example in Figure 3A, a downward convex warp occurs. As a result, in the example in Figure 3A, compressive stress CS is generated on the surface side of the single-crystal SiC layer 23 in the direction indicated by the arrow. On the other hand, tensile stress TS is generated on the back side of the single-crystal SiC layer 23 in the direction indicated by the arrow.

[0021] When growing polycrystalline SiC directly onto a warped single-crystal SiC layer 23 using the CVD method, stress is generated in a direction that cancels out the warping in the single-crystal SiC layer 23. In the example shown in Figure 3A, when growing the polycrystalline SiC, tensile stress TS is generated on the surface side in the direction indicated by the arrow, and compressive stress CS is generated on the back side in the direction indicated by the arrow. In the example shown in Figure 3B, the compressive stress CS generated on the surface side of the single-crystal SiC layer 23 is relaxed by the compressive stress CS generated on the back side of the polycrystalline SiC substrate 11. As a result, as shown in Figure 3B, the stresses generated in the single-crystal SiC layer 23 and the polycrystalline SiC substrate 11 are matched in terms of positive and negative, and a SiC composite substrate can be obtained in which the stress between the single-crystal SiC layer 23 and the polycrystalline SiC substrate 11 is relaxed.

[0022] The SiC composite substrate according to this embodiment comprises a single-crystal SiC layer 23 formed by remote epitaxial growth technology and a polycrystalline SiC substrate 11 directly formed on one main surface of the single-crystal SiC layer 23 by CVD. The stresses generated in the single-crystal SiC layer 23 and the polycrystalline SiC substrate 11 are matched in terms of positive and negative, thereby relaxing the stress between the single-crystal SiC layer 23 and the polycrystalline SiC substrate 11.

[0023] The stresses generated in both the single-crystal SiC layer 23 and the polycrystalline SiC substrate 11 are either tensile or compressive stresses, with an absolute value of 30 MPa or more.

[0024] This explains why a SiC composite substrate with reduced warping of the single-crystal SiC layer 23 formed by remote epitaxial growth technology can be obtained.

[0025] When the stress generated in both the single-crystal SiC layer 23 and the polycrystalline SiC substrate 11 is a tensile stress TS, as shown in Figure 2A, by combining the single-crystal SiC layer 23 and the polycrystalline SiC substrate 11 back to back, the films exert tension on each other, thus mitigating warping. As a result, a flat shape is obtained, as shown in Figure 2B.

[0026] On the other hand, if the stress generated in both the single-crystal SiC layer 23 and the polycrystalline SiC substrate 11 is a compressive stress CS, as shown in Figure 3A, by combining the single-crystal SiC layer 23 and the polycrystalline SiC substrate 11 back to back, the films exert tension on each other, thus mitigating warping. As a result, a flat shape can be obtained, as shown in Figure 3B.

[0027] The stresses must have matching positive and negative signs. Furthermore, both stresses must be tensile stresses, or both must be compressive stresses, with an absolute value of 30 MPa or more.

[0028] A positive stress corresponds to tensile stress, and a negative stress corresponds to compressive stress. Based on the above explanation, the stresses generated in the single-crystal SiC layer 23 and the polycrystalline SiC substrate 11 must be in the same direction. If there is almost no stress, it is possible that sufficient warping has not occurred. Therefore, a value of 30 MPa or higher is specified to indicate a certain threshold. Furthermore, if the warping of a 4-inch wafer is 40 μm or less, the final radius of curvature of the composite substrate will be 30 μm or more.

[0029] In the manufacturing method of a SiC composite substrate according to the embodiment, warping can be mitigated by directly growing polycrystalline SiC on a warped single-crystal SiC layer using the CVD method, thereby generating stress in a direction that cancels out the warping that occurs in the single-crystal SiC layer. The direction of the stress can be determined from the warping of the single-crystal SiC layer, so stress is generated in the same direction. In addition, in order to equalize the stress values, it is necessary to measure the stress of the warped single-crystal SiC layer. The way stress is generated in the CVD method depends on the film deposition conditions. Based on the measurement results of the stress of the single-crystal SiC layer, the polycrystalline SiC substrate should be grown using CVD in such a way that the positive and negative signs of the stresses match.

[0030] (Evaluation of SiC composite substrates) The SiC composite substrate according to this embodiment allows for the measurement of crystal lattice strain by, for example, Raman spectroscopy. By irradiating the SiC composite substrate with excitation laser light for Raman measurement and measuring the Raman scattered light, the crystal lattice strain of the single-crystal SiC layer can be measured.

[0031] Furthermore, the SiC composite substrate according to this embodiment allows for the measurement of crystal orientation and crystal structure using, for example, X-ray diffraction (XRD). By incident X-rays for measurement onto the SiC composite substrate and measuring the reflected wave, the crystal orientation and crystal structure of the single-crystal SiC layer can be measured. Note that the X-rays for measurement may be incident on either the single-crystal SiC layer or the polycrystalline SiC substrate.

[0032] (SiC composite substrate) Figure 4 is a cross-sectional view of the SiC composite substrate 1 according to an embodiment.

[0033] As shown in Figure 4, the SiC composite substrate 1 according to the embodiment comprises a single-crystal SiC layer 13 and a polycrystalline SiC substrate 11 formed directly on one main surface of the single-crystal SiC layer 13 by CVD.

[0034] In the SiC composite substrate 1 according to the embodiment, the stresses generated in the single-crystal SiC layer 13 and the polycrystalline SiC substrate 11 are matched in terms of positive and negative values, thereby relaxing the stress between the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13.

[0035] In the SiC composite substrate 1 according to the embodiment, the stress generated in both the single-crystal SiC layer 13 and the polycrystalline SiC substrate 11 is either tensile stress or compressive stress, with an absolute value of 30 MPa or more.

[0036] The concentration of impurities added to the single-crystal SiC layer 13 is 1 × 10⁻⁶. 16 From 5x10 20 cm -3 It is within the range.

[0037] The polycrystalline SiC substrate 11 is formed by deposition using CVD. The crystalline polymorph of the polycrystalline SiC substrate 11 may be 4H, or it may be other crystalline polymorphs such as 6H or 3C.

[0038] As will be described later, the single-crystal SiC layer 13 is formed by epitaxial growth on the surface of a single-crystal SiC substrate 21 (FIG. 6A) via a thin graphene film 22 so as to transfer the crystal structure of the surface of the single-crystal SiC substrate 21. The crystal polytype of the single-crystal SiC layer 13 may be 4H, or may be other crystal polytypes such as 6H and 3C. The thickness of the single-crystal SiC layer 13 may be 2 μm or more. The defect density of basal plane dislocations in the single-crystal SiC layer 13 is 1×10 1 to 1×10 3 , and may be within this range.

[0039] Impurities may be added to the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13. The added impurities may be n-type impurities such as nitrogen (N) and phosphorus (P). The concentration of impurities added to the polycrystalline SiC substrate 11 is 1×10 19 cm -3 to 1×10 20 cm -3 , and may be within this range. The concentration of impurities added to the single-crystal SiC layer 13 is 1×10 16 cm -3 to 5×10 20 cm -3 , and may be within this range.

[0040] In the SiC composite substrate 1 according to the embodiment, by directly forming the polycrystalline SiC substrate 11 on one main surface of the single-crystal SiC layer 13 by CVD, the stresses generated in the single-crystal SiC layer 13 and the polycrystalline SiC substrate 11 are matched in positive and negative signs, thereby relaxing the stress between the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13. With such a SiC composite substrate 1, a high-quality single-crystal SiC layer 13 with few crystal defects can be obtained.

[0041] (Modification) FIG. 5 is a cross-sectional view of a SiC composite substrate 2 according to a modification of the embodiment.

[0042] The modified SiC composite substrate 2 is constructed by sequentially stacking a first single-crystal SiC layer 13a, in which an impurity is added at a first concentration, and a second single-crystal SiC layer 13b, in which an impurity is added at a second concentration lower than the first concentration. This differs from the SiC composite substrate 1 according to the first embodiment, which is composed of a single-crystal SiC layer 13 with a single impurity concentration. The other components of the SiC composite substrate 2 are the same as those of the SiC composite substrate 1 according to the embodiment. Therefore, redundant explanations are omitted.

[0043] In the modified SiC composite substrate 2, the impurity concentration in the first single crystal SiC layer 13a is, for example, 10 18 cm -3 In contrast to the base, the impurity concentration in the second single crystal SiC layer 13b is, for example, 10 16 cm -3 The impurity concentration of the second single-crystal SiC layer 13b may be an order of magnitude smaller than the impurity concentration of the first single-crystal SiC layer 13a. Although the single-crystal SiC layer 13 of the SiC composite substrate 2 is composed of two layers, the first single-crystal SiC layer 13a and the second single-crystal SiC layer 13b, it may be composed of three or more layers, each with a different concentration of added impurities. For example, the impurity concentration in each layer may gradually decrease from the bottom layer to the top layer.

[0044] When constructing a semiconductor device using a single-crystal SiC layer 13 of a SiC composite substrate 2 as a drift layer, it is possible to form two layers with different concentrations within the drift layer. For this reason, for example, the first single-crystal SiC layer 13a can be given a function such as a buffer layer.

[0045] (Manufacturing method for SiC composite substrate 1) A method for manufacturing the SiC composite substrate 1 will be described.

[0046] Figures 6A to 6D are process flow diagrams (first half) of the manufacturing method of the SiC composite substrate 1 according to the embodiment, and are diagrams that explain the process of fabricating the single crystal SiC layer 13 of the SiC composite substrate 1.

[0047] Figures 7A to 7C are process flow diagrams (second half) of the manufacturing method of the SiC composite substrate 1 according to the embodiment, illustrating the process of directly forming a polycrystalline SiC substrate 11 on a single-crystal SiC layer 13 by CVD.

[0048] The method for manufacturing the SiC composite substrate 1 according to the embodiment includes the steps of: providing a single-crystal SiC substrate 21 on which a graphene film 22 is formed on the main surface (Figure 6A); epitaxially growing a single-crystal SiC layer 23 on the main surface of the single-crystal SiC substrate 21 via the graphene film 22 (Figure 6B); peeling the single-crystal SiC layer 23 from the graphene film 22 (Figures 6C and 6D); and directly forming a polycrystalline SiC substrate 11 on one of the main surfaces of the single-crystal SiC layer 23 by CVD (Figures 7A to 7C).

[0049] —Remote epitaxial growth— (A) First, a single-crystal SiC substrate 21 is prepared, with a graphene film 22 formed on its main surface, as shown in Figure 6A. The single-crystal SiC substrate 21 may be formed by sublimation or a solution method. The single-crystal SiC substrate 21 may, for example, have a crystal polymorph of 4H and a main surface that is the (0001) plane, but it is not limited to this and may have other crystal polymorphs such as 6H or 3C, and the main surface may be any other crystal plane.

[0050] The graphene film 22 formed on the main surface of the single-crystal SiC substrate 21 may be a zero layer in which two-dimensionally extending graphene is covalently bonded to atoms on the main surface of the single-crystal SiC substrate 21. Alternatively, it may be formed from several layers of graphene. The graphene film 22 may be deposited by CVD or formed by thermal decomposition of the main surface of the single-crystal SiC substrate 21.

[0051] (B) Next, as shown in Figure 6B, a single-crystal SiC layer 23 is formed on the main surface of the single-crystal SiC substrate 21 via a graphene film 22 by epitaxial growth. Van der Waals forces are exerted on the single-crystal SiC layer 23 from the SiC atoms constituting the main surface of the single-crystal SiC substrate 21 via the graphene film 22. As a result, the crystal structure of the main surface of the single-crystal SiC substrate 21 is transferred to the single-crystal SiC layer 23. The single-crystal SiC layer 23 can be fabricated to a thickness of, for example, 2 μm or more by epitaxial growth. Furthermore, the defect density of basal plane dislocations in the single-crystal SiC layer 23 is 1 × 10⁻¹⁶. 1 From 1 x 10 3 It can be made to fall within this range. Impurities are added to the single-crystal SiC layer 23. The added impurities may be n-type impurities such as nitrogen (N) and phosphorus (P). The concentration of the impurities is 1 × 10⁻⁶. 16 cm -3 From 5x10 18 cm -3 It may be within the range up to that point.

[0052] (C) Next, as shown in Figure 6C, a stress layer 24 is formed on the single-crystal SiC layer 23, and a tape 25 is attached to the stress layer 24. For example, a nickel (Ni) layer is used for the stress layer 24. The stress layer 24 applies stress to the single-crystal SiC layer 23 so that it peels off from the graphene film 22. The Ni layer that becomes the stress layer 24 may be formed by vapor deposition or sputtering. Note that the stress layer 24 is not limited to Ni, but may be composed of other materials such as silicon nitride (SiN) or diamond-like carbon (DLC). The tape 25 may be a heat-release tape that peels off when heated.

[0053] (D) Next, as shown in Figure 6D, the single-crystal SiC layer 23 formed on the main surface of the single-crystal SiC substrate 21 via the graphene film 22 is peeled off. The two-dimensionally formed graphene film 22 and the single-crystal SiC layer 23 are bonded by van der Waals forces, and stress is applied to the single-crystal SiC layer 23 from the stress layer 24. Therefore, the single-crystal SiC layer 23 can be easily peeled off from the graphene film 22 by applying force to the tape 25 that supports it via the stress layer 24. The peeled single-crystal SiC layer 23 is supported by the tape 25 via the stress layer 24. The single-crystal SiC layer 23 corresponds to the single-crystal SiC layer 13 (Figure 1) of the SiC composite substrate 1.

[0054] —Method for forming SiC composite substrates— (E) First, a single-crystal SiC layer 23 supported by a tape 25 via a stress layer 24 is prepared, as shown in Figure 7A.

[0055] (F) Next, as shown in Figure 7B, a polycrystalline SiC substrate 11 is deposited directly onto one main surface of the single-crystal SiC layer 23 by CVD. The crystalline polymorph of the polycrystalline SiC substrate 11 may be 4H, or other crystalline polymorphs such as 6H or 3C. The polycrystalline SiC substrate 11 may contain impurities. The added impurities may be n-type impurities, similar to those in the single-crystal SiC layer 23. The impurity concentration is 1 × 10⁻⁶ 19 cm -3 From 5x10 20 cm -3 It may be within the range up to that point.

[0056] (G) Next, as shown in Figure 7C, remove the tape 25 to form the laminate 4. If the tape 25 is a heat-release tape, heat the tape 25 to remove it.

[0057] (H) Next, the stress layer 24 stacked on the single crystal SiC layer 23 is removed by etching or the like.

[0058] Through the above series of steps, the SiC composite substrate 1 (Figure 1) according to the embodiment is formed. The single-crystal SiC layer 23 of the laminate 4 corresponds to the single-crystal SiC layer 13 in the SiC composite substrate 1 (Figure 1) according to the embodiment.

[0059] In the embodiment, the SiC composite substrate 1 is formed by directly CVD on one main surface of a single-crystal SiC layer 23, forming a polycrystalline SiC substrate 11. By matching the positive and negative stresses generated in the single-crystal SiC layer 13 and the polycrystalline SiC substrate 11, it is possible to manufacture a SiC composite substrate 1 in which the stress between the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13 is relaxed.

[0060] (Manufacturing method for SiC composite substrate 2 according to modified example) Figure 8 is a cross-sectional view illustrating a modified example of a method for manufacturing a SiC composite substrate 2.

[0061] The modified method for manufacturing the SiC composite substrate 2 uses a single crystal SiC layer 23 in which a first single crystal SiC layer 23a containing impurities added at a first concentration and a second single crystal SiC layer 23b containing impurities added at a second concentration are stacked.

[0062] (I) First, a single-crystal SiC layer 23 supported by a tape 25 via a stress layer 24 is prepared, similar to Figure 7A.

[0063] (J) Next, similar to Figure 7B, a polycrystalline SiC substrate 11 is directly deposited onto one main surface of the single-crystal SiC layer 23 by CVD. The crystalline polymorph of the polycrystalline SiC substrate 11 may be 4H, or other crystalline polymorphs such as 6H or 3C. The polycrystalline SiC substrate 11 may contain impurities. The added impurities may be n-type impurities, similar to those in the single-crystal SiC layer 23. The impurity concentration is 1 × 10⁻⁶. 19 cm -3 From 5x10 20 cm -3 It may be within the range up to that point.

[0064] (K) Next, remove the tape 25 to form the laminate 4, similar to Figure 7C. If the tape 25 is a heat-release tape, heat the tape 25 to remove it.

[0065] (H) Next, the stress layer 24 stacked on the single crystal SiC layer 23 is removed by etching or the like. As a result, as shown in Figure 8, a SiC composite substrate 2 is obtained consisting of a single crystal SiC layer 23 and a polycrystalline SiC substrate 11 grown on the single crystal SiC layer 23 by CVD.

[0066] Through the above series of steps, the SiC composite substrate 1 (Figure 1) according to the embodiment is formed. The first single-crystal SiC layer 23a and the second single-crystal SiC layer 23b correspond to the first single-crystal SiC layer 13a and the second single-crystal SiC layer 13b in the SiC composite substrate 2 (Figure 5) according to the embodiment.

[0067] In the SiC composite substrate 2 according to this embodiment, a polycrystalline SiC substrate 11 is formed directly on one main surface of a single-crystal SiC layer 23 by CVD. By matching the positive and negative stresses generated in the single-crystal SiC layer 13 and the polycrystalline SiC substrate 11, it is possible to manufacture a SiC composite substrate 2 in which the stress between the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13 is relaxed.

[0068] (Examples of manufacturing methods for SiC composite substrates) An example of the manufacturing method for the SiC composite substrate 2 involves applying a single-crystal SiC layer 23 formed by stacking a first single-crystal SiC layer 23a and a second single-crystal SiC layer 23b, as shown in Figure 5.

[0069] A first single-crystal SiC layer 23a is grown on the main surface of a single-crystal SiC substrate 21 (Figure 6A) by epitaxial growth, with impurities added at a first concentration. Subsequently, a second single-crystal SiC layer 23b is grown with impurities added at a second concentration. Here, the first concentration of impurities in the first single-crystal SiC layer 23a is, for example, 10 18 cm -3 In contrast to the base, the second concentration of impurities in the second single-crystal SiC layer 23b is, for example, 10 16 cm -3As shown above, the second impurity concentration in the second single-crystal SiC layer 23b may be on the order of an order of magnitude smaller than the first impurity concentration in the first single-crystal SiC layer 23a. Other steps for fabricating the single-crystal SiC layer 23 are the same as those shown in Figures 6A to 6D.

[0070] Here, we will describe an example of a method for manufacturing a SiC composite substrate.

[0071] First, a 4H single-crystal SiC substrate 21 was heated to a high temperature of over 1500°C in an argon (Ar) atmosphere at atmospheric pressure, and a graphene film 22 consisting of 1 to 2 layers was grown on the main surface by pyrolysis. Subsequently, a 3 μm thick single-crystal SiC layer 23 was grown on the graphene film 22 by epitaxy using silane (SiH4) and propane (C3H8) as precursors. At this time, Ar was used as the carrier gas, and nitrogen gas (N2) was also flowed simultaneously as an n-type impurity gas. By appropriately controlling the flow rate, the concentration of impurities added to the single-crystal SiC layer 23 was adjusted according to the distance from the boundary with the graphene film 22, resulting in a concentration of 2 × 10⁻¹⁶ in the first single-crystal SiC layer 23a. 18 cm -3 and the 5 × 10 of the second single crystal SiC layer 23b 16 cm -3 It was manufactured to have a two-layer structure.

[0072] A 5 μm thick DLC film was deposited on a single-crystal SiC layer 23 as a stress layer 24 by plasma CVD. Then, an adhesive tape 25 was attached to the stress layer 24 to exfoliate the single-crystal SiC layer 23 from the graphene film 22. A polycrystalline SiC substrate 11 was grown by CVD on the first single-crystal SiC layer 23a of the exfoliated single-crystal SiC layer 23. After that, the tape 25 was removed, and finally, the DLC film was removed by combustion by heating at over 600°C in air to obtain a SiC composite substrate 2.

[0073] (Semiconductor devices) Next, an embodiment of the semiconductor device will be described. The semiconductor device according to this embodiment uses the SiC composite substrate 2 shown in Figure 5. The SiC composite substrate 2 is configured with a polycrystalline SiC substrate 11 as the substrate layer and a single-crystal SiC layer 13 as the drift layer. The SiC composite substrate 2 is formed by directly growing the polycrystalline SiC substrate 11 on the single-crystal SiC layer 13 using CVD. The SiC composite substrate 2 used here has its positive and negative stresses matched between the single-crystal SiC layer 13 and the polycrystalline SiC substrate 11, thereby relaxing the stress between the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13. Below, examples of electronic devices using the SiC composite substrate 2 will be described, including a Schottky barrier diode (SBD) and a trench-gate type MOSFET (Metal Oxide Field Effect Transistor). Although it is also applicable to other devices such as MEMS (Micro Electro Mechanical Systems), their explanation will be omitted here.

[0074] (SBD) Figure 9 is a cross-sectional view of SBD30. SBD30 was fabricated using the SiC composite substrate 2 shown in Figure 5. In SBD30, a polycrystalline SiC substrate 11 is formed by directly CVD growing a single-crystal SiC layer 13, and the stresses generated in the single-crystal SiC layer 13 and the polycrystalline SiC substrate 11 are matched in terms of positive and negative, thereby relaxing the stress between the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13.

[0075] The polycrystalline SiC substrate 11 is, for example, 10 19 cm -3 from 10 20 cm -3 High concentrations of n in the range + The substrate layer is doped into the mold. The bottom surface of the polycrystalline SiC substrate 11 is covered with a cathode electrode 41, and the cathode electrode 41 is connected to the cathode terminal K of the SBD 20.

[0076] The single-crystal SiC layer 13 is constructed by sequentially stacking a first single-crystal SiC layer 13a, which is doped with impurities at a first concentration, and a second single-crystal SiC layer 13b, which is doped with impurities at a second concentration lower than the first concentration. The impurity concentration in the first single-crystal SiC layer 13a is, for example, 10 18 cm -3 In contrast to the base, the impurity concentration in the second single crystal SiC layer 13b is, for example, 10 16 cm -3 This is the base. The single-crystal SiC layer 13 is a drift layer.

[0077] The top surface 13c of the single-crystal SiC layer 13 is provided with a contact hole 43 that exposes a portion of the single-crystal SiC layer 13 as a body region 42, and a field insulating film 45 is formed in the field region 44 surrounding the body region 42. The field insulating film 45 is made of SiO2 (silicon oxide), but may be made of other insulating materials such as silicon nitride (SiN). An anode electrode 46 is formed on this field insulating film 45, and the anode electrode 46 is connected to the anode terminal A of the SBD 20.

[0078] A p-type JTE (junction termination extension) structure 47 is formed near the top surface 13c (surface layer) of the single-crystal SiC layer 13, in contact with the anode electrode 46. The JTE structure 47 is formed along the contour of the contact hole 43, spanning both the inside and outside of the contact hole 43 of the field insulating film 45.

[0079] (Trench-gate MOSFET) Figure 10 is a cross-sectional view of a trench gate type MOSFET 40. The trench gate type MOSFET 40 was fabricated using the SiC composite substrate 2 shown in Figure 5. In the trench gate type MOSFET 40, the polycrystalline SiC substrate 11 of the SiC composite substrate 2 is used as the substrate layer, and the single-crystal SiC layer 13 is used as the drift layer. The SiC composite substrate 2 is formed by directly growing the polycrystalline SiC substrate 11 on the single-crystal SiC layer 13 using CVD. The SiC composite substrate 2 used is one in which the stresses generated in the single-crystal SiC layer 13 and the polycrystalline SiC substrate 11 are matched in terms of positive and negative, and the stress between the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13 is relaxed.

[0080] The polycrystalline SiC substrate 11 is, for example, 10 19 cm -3 from 10 20 cm -3 High concentrations of n in the range + The substrate layer is doped into the mold. The bottom surface of the polycrystalline SiC substrate 11 is covered with a drain electrode 31, which is connected to the drain terminal D of the trench gate type MOSFET 40.

[0081] The single-crystal SiC layer 13 is constructed by sequentially stacking a first single-crystal SiC layer 13a, which is doped with impurities at a first concentration, and a second single-crystal SiC layer 13b, which is doped with impurities at a second concentration lower than the first concentration. The impurity concentration in the first single-crystal SiC layer 13a is, for example, 10 18 cm -3 In contrast to the base, the impurity concentration in the second single crystal SiC layer 13b is, for example, 10 16 cm -3 This is the base. The single-crystal SiC layer 13 is a drift layer.

[0082] A p-type body region 32 is formed on the top surface 13c of the single-crystal SiC layer 13. A gate trench 34 is formed in the single-crystal SiC layer 13. The gate trench 34 penetrates the body region 32 from the top surface 13c of the single-crystal SiC layer 13, and its deepest part reaches the drain region 33.

[0083] A gate insulating film 35 is formed on the inner surface of the gate trench 34 and on the top surface 13c of the single-crystal SiC layer 13, covering the entire inner surface of the gate trench 34. A gate electrode 36 is embedded in the gate trench 34 by filling the inside of the gate insulating film 35 with, for example, polysilicon. A gate terminal G is connected to the gate electrode 36.

[0084] The surface layer of the body region 32 is made of highly doped n, which forms part of the side surface of the gate trench 34. + A type source region 37 is formed. In addition, the single crystal SiC layer 13 has a highly doped p that penetrates the source region 37 from its top surface 13c and connects to the body region 32. + A body contact area 38 of a certain type is formed.

[0085] An interlayer insulating film 51 made of SiO2 is formed on the single-crystal SiC layer 13. The source electrode 39 is connected to the source region 37 and the body contact region 38 via a contact hole 43 formed in the interlayer insulating film 51. A source terminal S is connected to the source electrode 39.

[0086] By generating a predetermined potential difference between the source electrode 39 and the drain electrode 31 (source-drain), and applying a predetermined voltage (a voltage greater than or equal to the gate threshold voltage) to the gate electrode 36, a channel can be formed near the interface between the gate insulating film 35 and the body region 32 by the electric field from the gate electrode 36. This allows current to flow between the source electrode 39 and the drain electrode 31, thereby turning on the trench gate type MOSFET 40.

[0087] The semiconductor device according to this embodiment is fabricated using a SiC composite substrate 2 in which the stresses generated in the single-crystal SiC layer 13 and the polycrystalline SiC substrate 11 are matched in terms of positive and negative, and the stress between the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13 is relaxed. As a result, substrate warping is reduced, crystal defects due to crystal strain are reduced, and a high-quality single-crystal SiC layer 13 is obtained. Therefore, even in semiconductor devices in which the drift layer is configured as a single-crystal SiC layer 13, quality degradation caused by lattice defects and the like is suppressed, and the characteristics are ensured.

[0088] In the above description of the embodiments, polycrystalline SiC substrates and single-crystal SiC layers were used as examples, but the method can be applied not only to SiC but also to GaN or GaAs, which are materials that can be remotely epitaxially grown.

[0089] Although the present disclosure has been described in detail above, it will be clear to those skilled in the art that the present disclosure is not limited to the embodiments described herein. One or more elements of one embodiment can be combined with one or more elements of another embodiment. The present disclosure can be implemented in modified and altered forms without departing from the spirit and scope of the present disclosure as defined by the claims. Therefore, the descriptions in the present disclosure are illustrative and not intended to be restrictive in any way.

[0090] (Note) The technical concepts that can be grasped from this disclosure are described below. Note that, not as an attempt to limit the scope but to aid understanding, the components described in the appendices are denoted by the corresponding reference numerals of the components in the embodiments. The reference numerals are provided as examples to aid understanding, and the components described in each appendice should not be limited to those indicated by the reference numerals.

[0091] (Note 1) The SiC composite substrate 1 comprises a single-crystal SiC layer 13 and a polycrystalline SiC substrate 11 directly formed on one main surface of the single-crystal SiC layer 13 by CVD. The stresses generated in the single-crystal SiC layer 13 and the polycrystalline SiC substrate 11 are matched in terms of positive and negative, and the stress between the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13 is relaxed. As a result, warping is reduced, crystal defects due to crystal strain are minimized, and a high-quality single-crystal SiC layer 13 can be obtained. Therefore, even in semiconductor devices where the drift layer is configured as a single-crystal SiC layer 13, quality degradation caused by lattice defects and the like is suppressed, and the properties are ensured.

[0092] (Note 2) In the SiC composite substrate 1 described in Appendix 1, the stresses generated in the single-crystal SiC layer 13 and the polycrystalline SiC substrate 11 may both be tensile or compressive stresses, and the absolute value of the stress may be 30 MPa or more. A SiC composite substrate 1 can be formed using a SiC wafer of 4 inches or larger.

[0093] (Note 3) In the SiC composite substrate 1 described in Appendix 1, the concentration of impurities added to the single-crystal SiC layer 13 is 1 × 10⁻⁶ 16 From 5x10 20 cm -3 It may also be within this range. The SiC composite substrate 1 can be used for SBDs and trench-type MOS devices.

[0094] (Note 4) The manufacturing method for the SiC composite substrate 1 includes the steps of: providing a single-crystal SiC substrate 21 with a graphene film formed on its main surface; epitaxially growing a single-crystal SiC layer 23 on the main surface of the single-crystal SiC substrate 21 via a graphene film 22; peeling the single-crystal SiC layer 23 from the graphene film 22; and directly forming a polycrystalline SiC substrate 11 on one main surface of the single-crystal SiC layer 23 by CVD. This method matches the positive and negative stresses generated in the single-crystal SiC layer 23 and the polycrystalline SiC substrate 11, thereby relaxing the stress between the polycrystalline SiC substrate 11 and the single-crystal SiC layer 23. As a result, substrate warping is reduced, crystal defects due to crystal distortion are minimized, and a high-quality single-crystal SiC layer 13 can be obtained. Therefore, even in semiconductor devices where the drift layer is configured as a single-crystal SiC layer 13, quality degradation caused by lattice defects and the like is suppressed, ensuring the performance characteristics.

[0095] (Note 5) In the manufacturing method of the SiC composite substrate 1 described in Appendix 4, the stress generated in the single-crystal SiC layer 13 and the polycrystalline SiC substrate 11 may both be tensile stress or compressive stress, and the absolute value of the stress may be 30 MPa or more. A SiC composite substrate 1 can be formed using a SiC wafer of 4 inches or larger.

[0096] (Note 6) The SiC composite substrate 2 may be configured such that, in the SiC composite substrate 1 described in Appendix 1, the single-crystal SiC layer 13 is formed by sequentially stacking a first single-crystal SiC layer 13a, in which impurities are added at a first concentration, and a second single-crystal SiC layer 13b, in which impurities are added at a second concentration lower than the first concentration. In this configuration, when the single-crystal SiC layer 13 is used as a drift layer to construct a semiconductor device, two layers with different concentrations can be formed within the drift layer. For this reason, for example, the first single-crystal SiC layer 13a can be given a function such as a buffer layer. The SiC composite substrate 2 can be used in SBDs and trench-type MOS devices.

[0097] (Note 7) In the SiC composite substrate 2 described in Appendix 6, the impurity concentration of the second single-crystal SiC layer 13b may be on the order of an order of magnitude smaller than the impurity concentration of the first single-crystal SiC layer 13a. A junction layer is formed by solid-phase diffusion, and high transmittance is obtained. When the single-crystal SiC layer 13 of the SiC composite substrate 2 is used as a drift layer to construct a semiconductor device, two layers with different concentrations can be formed within the drift layer. For this reason, for example, the first single-crystal SiC layer 13a can be given a function such as a buffer layer. The SiC composite substrate 2 can be used in SBDs and trench-type MOS devices.

[0098] (Note 8) In the SiC composite substrate 2 described in Appendix 6, the single-crystal SiC layer 13 of the SiC composite substrate 2 may be composed of three or more layers, each with a different concentration of added impurities. When the single-crystal SiC layer 13 of the SiC composite substrate 2 is used as a drift layer to construct a semiconductor device, two layers with different concentrations can be formed within the drift layer. For this reason, for example, the first single-crystal SiC layer 13a can be given a function such as a buffer layer. The SiC composite substrate 2 can be used in SBDs and trench-type MOS devices.

[0099] (Note 9) In the SiC composite substrate 2 described in Appendix 6, the concentration of impurities in each layer of the single-crystal SiC layer 13 of the SiC composite substrate 2 may gradually decrease from the lower layer to the upper layer. When the single-crystal SiC layer 13 of the SiC composite substrate 2 is used as a drift layer to construct a semiconductor device, two layers with different concentrations can be formed within the drift layer. For this reason, for example, the first single-crystal SiC layer 13a can be given a function such as a buffer layer. The SiC composite substrate 2 can be used in SBDs and trench-type MOS devices.

[0100] (Note 10) The semiconductor device is constructed using a single-crystal SiC layer 13 of a SiC composite substrate 2 as described in any one of appendices 6 to 9 as a drift layer. The single-crystal SiC layer 13 can be used to constitute the drift layer of the semiconductor device.

[0101] (Note 11) The semiconductor device described in Appendix 10 may include at least one of a Schottky barrier diode, a trench gate type MOS, and a plane gate type MOS. At least one of a Schottky barrier diode, a trench gate type MOS, and a plane gate type MOS can be constructed using the single crystal SiC layer 13 of the SiC composite substrate 2 as a drift layer. [Explanation of symbols]

[0102] 1, 2 SiC composite substrate 4 Laminate 11 Polycrystalline SiC substrate 13, 23 Single-crystal SiC layer 13a, 23a First single crystal SiC layer 13b, 23b Second single-crystal SiC layer 13c top surface 21 Single-crystal SiC substrate 22 Graphene membrane 24 Stress Layer 25 Tapes 30 Schottky barrier diodes (SBDs) 31 Drain electrode 32, 42 Body regions 33 Drain area 34 Gate Trench 35 Gate insulating film 36 Food Products 37 Source Area 38 Body Contact Area 39 Source electrodes 40 Trench-gate type MOSFETs 41 Cathode electrode 43, 52 Contact holes 44 Field Area 45 Field Insulating Film 46 Anode electrodes 47 JTE structure 51 Interlayer insulating film

Claims

1. A single-crystal SiC layer, A polycrystalline SiC substrate formed directly on one main surface of the single-crystal SiC layer by chemical vapor deposition, Equipped with, A SiC composite substrate in which the stresses generated in the single-crystal SiC layer and the polycrystalline SiC substrate are matched in terms of positive and negative values, and the stress between the polycrystalline SiC substrate and the single-crystal SiC layer is relaxed.

2. The SiC composite substrate according to claim 1, wherein the stress generated in the single-crystal SiC layer and the polycrystalline SiC substrate is either tensile stress or compressive stress, and the absolute value of the stress is 30 MPa or more.

3. The concentration of impurities added to the single-crystal SiC layer is 1 × 10⁻⁶ 16 From 5 x 10 20 cm -3 A SiC composite substrate according to claim 1, which is within the range of the specified area.

4. The SiC composite substrate according to claim 1, wherein the single-crystal SiC layer comprises a first single-crystal SiC layer in which an impurity is added at a first concentration, and a second single-crystal SiC layer in which an impurity is added at a second concentration lower than the first concentration, which are stacked in sequence.

5. The SiC composite substrate according to claim 4, wherein the impurity concentration of the second single-crystal SiC layer is on the order of an order of magnitude smaller than the impurity concentration of the first single-crystal SiC layer.

6. A step of providing a single-crystal SiC substrate on which a graphene film is formed on the main surface, A step of epitaxially growing a single-crystal SiC layer on the main surface of the single-crystal SiC substrate via the graphene film, The steps include peeling the single-crystal SiC layer from the graphene film, A step of forming a polycrystalline SiC substrate on one main surface of the single-crystal SiC layer by chemical vapor deposition. It has, A method for manufacturing a SiC composite substrate, wherein the stresses generated in the single-crystal SiC layer and the polycrystalline SiC substrate are matched in terms of positive and negative values, and the stress between the polycrystalline SiC substrate and the single-crystal SiC layer is relaxed.

7. The method for manufacturing a SiC composite substrate according to claim 4, wherein the stress generated in the single-crystal SiC layer and the polycrystalline SiC substrate is either tensile stress or compressive stress, and the absolute value of the stress is 30 MPa or more.

8. A semiconductor device comprising a single-crystal SiC layer of a SiC composite substrate according to any one of claims 1 to 5, configured as a drift layer.

9. The semiconductor device according to claim 8, comprising at least one of a Schottky barrier diode, a trench gate type MOS, and a plane gate type MOS.

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