Semiconductor memory devices

Abstract

This invention provides a semiconductor memory device and a method for manufacturing the same that reduce the bending of the capacitive structure and improve the performance of the semiconductor memory device. [Solution] The device comprises a substrate 10, a plurality of laminated structures, a bit line 30, a capacitive structure 40, and a support layer 60. The plurality of laminated structures are arranged on the substrate and isolated from each other in the vertical direction, and each comprises a semiconductor layer 20. The semiconductor layer comprises a first doping region 21, a groove region 22, and a second doping region 23. The bit line extends along the horizontal direction and is connected to the first doping region. The capacitive structure comprises a lower electrode 41 and an upper electrode 42, the lower electrode being connected to the second doping region. The support layer is installed between adjacent lower electrodes and is in direct contact with the first side wall 44, upper surface, and lower surface of the lower electrode. The device is used to achieve the effect of reducing the bending of the capacitive structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to a semiconductor memory device.

Background Art

[0002] With the development of semiconductor technology, semiconductor memory devices have been widely applied in various electronic devices. A semiconductor memory device includes word lines (abbreviated as WL), bit lines (abbreviated as BL), transistors and a capacitor structure. The gate electrode of a transistor is connected to a word line, the drain electrode of the transistor is connected to a bit line, and the source electrode of the transistor is connected to the capacitor structure. The word line controls the on / off of the transistor, and the bit line reads and writes data in the capacitor structure.

[0003] With the improvement of the integration degree of semiconductor memory devices, semiconductor memory devices have been developed into a three-dimensional structure in which capacitor structures are horizontally arranged. However, the capacitor structure is prone to bending, which affects the performance of the semiconductor memory device.

Summary of the Invention

Problem to be Solved by the Invention

[0004] Embodiments of the present application provide a semiconductor memory device that reduces bending of a capacitor structure and improves the performance of the semiconductor memory device.

Means for Solving the Problem

[0005] In a first embodiment, an embodiment of the present application provides a semiconductor memory device comprising a substrate, a plurality of stacked structures, a bit line, a capacitance structure, and a support layer, wherein the plurality of stacked structures are arranged on the substrate and are separated from each other in the vertical direction, the stacked structures comprise a semiconductor layer, the semiconductor layer comprises a first doping region, a groove region, and a second doping region, the bit line extends along the horizontal direction and is connected to the first doping region, the capacitance structure comprises a stacked lower electrode and an upper electrode, the lower electrode is connected to the second doping region, and the support layer is positioned around the lower electrode and is in direct contact with the side wall, top surface, and bottom surface of the lower electrode.

[0006] The semiconductor memory device in the embodiment of the present invention comprises a substrate, a plurality of stacked structures, a bit line, a capacitance structure, and a support layer. The plurality of stacked structures are arranged on the substrate and are separated from each other in the vertical direction, and each stacked structure comprises a semiconductor layer, which comprises a first doping region, a groove region, and a second doping region. The bit line extends along the horizontal direction and is connected to the first doping region. The capacitance structure comprises a lower electrode and an upper electrode that are stacked and installed, and the lower electrode is connected to the second doping region. The support layer is installed around the lower electrode and is in direct contact with the side wall, top surface, and bottom surface of the lower electrode. By directly contacting the lower electrode with the support layer, the end of the lower electrode opposite to the semiconductor layer is supported, bending of the lower electrode and bridging connections between the lower electrodes can be avoided, and the performance of the semiconductor memory device is ensured.

[0007] In a second aspect, embodiments of the present application provide a semiconductor memory device comprising a substrate, a plurality of stacked structures, bit lines, a capacitance structure, an insulating layer, and a support layer, wherein the plurality of stacked structures are arranged on the substrate and are separated from each other in the vertical direction, the stacked structures comprise a semiconductor layer, the semiconductor layer comprises a first doping region, a groove region, and a second doping region, the bit lines extend along the horizontal direction and are connected to the first doping region, the capacitance structure comprises a stacked lower electrode and an upper electrode, the lower electrode is connected to the second doping region, the insulating layer is arranged between adjacent capacitance structures, and the support layer is arranged between the insulating layers and is in direct contact with the side walls, top surface, and bottom surface of the insulating layer. [Effects of the Invention]

[0008] The semiconductor memory device in the embodiment of the present invention comprises a substrate, a plurality of stacked structures, a bit line, a capacitance structure, an insulating layer, and a support layer. The plurality of stacked structures are arranged on the substrate and are isolated from each other in the vertical direction. Each stacked structure comprises a semiconductor layer, which comprises a first doping region, a groove region, and a second doping region. The bit line extends along the horizontal direction and is connected to the first doping region. The capacitance structure comprises a lower electrode and an upper electrode that are stacked and installed, with the lower electrode connected to the second doping region. The insulating layer is arranged between adjacent capacitance structures, and the support layer is arranged between the insulating layers and is in direct contact with the side walls, top surface, and bottom surface of the insulating layer. In this way, one end of the insulating layer extends into the support layer, and the support layer provides support to the insulating layer, thereby ensuring the stability of the insulating layer and preventing bending of the insulating layer. This prevents the capacitance structure subsequently formed on the insulating layer from bending and bridging, thereby ensuring the performance of the semiconductor memory device. [Brief explanation of the drawing]

[0009] The accompanying drawings of this specification are incorporated herein and constitute part of this specification, illustrating embodiments consistent with this application and are used together with this specification to illustrate the principles of this application. [Figure 1]This is a schematic diagram of a semiconductor memory device provided by this application. [Figure 2] This is a schematic diagram with the isolation layer in Figure 1 hidden. [Figure 3] This is a schematic diagram of the support layer after it has been formed, as provided by this invention. [Figure 4] This is a schematic diagram after removing a portion of the insulating layer provided by this application. [Figure 5] Figure 4 is a schematic diagram showing the isolation layer. [Figure 6] A schematic diagram of the upper electrode after formation, provided by this application. [Figure 7] A plan view of a semiconductor memory device provided by this application. [Figure 8] This is a cross-sectional view of a semiconductor memory device provided by this application. [Figure 9] Another schematic diagram after the lower electrode has been formed, as provided by this application. [Figure 10] Another schematic diagram after the formation of the upper electrode provided by this application. [Figure 11] This is another cross-sectional view of the semiconductor memory device provided by this application. [Modes for carrying out the invention]

[0010] Herein, exemplary embodiments shown in the accompanying drawings will be described in detail. Where the following description relates to the accompanying drawings, unless otherwise noted, the same numbers in different drawings represent the same or similar elements. The embodiments described below in the exemplary embodiments do not represent all embodiments consistent with this specification. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application described in detail in the accompanying claims.

[0011] The semiconductor memory device provided by this invention reduces bending of the lower electrode by providing a support layer to directly support the lower electrode or by providing support to an insulating layer directly used for deposition of the lower electrode. As a result, bridging of the lower electrode is avoided, and the performance of the semiconductor memory device is improved.

[0012] The following describes in detail the technical means of the present application and how they solve the above technical problems, using specific examples. The following specific examples can be combined and implemented, and the same or similar concepts or processes may not be described repeatedly in some examples. The following describes the examples of the present application with reference to the drawings.

[0013] Please refer to Figures 6, 7, and 8. Embodiments of the present invention provide a semiconductor memory device, such as a dynamic random access memory (DRAM). The semiconductor memory device comprises a substrate 10, a plurality of stacked structures, bit lines 30, a capacitive structure 40, and a support layer 60. The substrate 10 provides support to the structures on it, such as the stacked structures and the support layer 60. Examples of the substrate 10 include a silicon substrate, a silicon-containing (e.g., silicon germanium) substrate, or a silicon-on-insulator (e.g., SOI) substrate.

[0014] Multiple stacked structures are arranged on a substrate 10 and are isolated from each other in the vertical direction. Each stacked structure comprises a semiconductor layer 20, which includes a first doping region 21, a groove region 22, and a second doping region 23. The multiple stacked structures are arranged on the substrate 10 at intervals, and the arrangement direction of the multiple stacked structures is shown in D3 of Figure 6. At least adjacent stacked structures are filled with isolation layers 90, and the isolation layers 90 achieve mutual isolation between each stacked structure.

[0015] Illustratively, the isolation layer 90 is disposed on the substrate 10 (shown in FIGS. 6 to 9) and extends along the vertical direction, thereby ensuring that the stacked structures are not electrically connected to each other in the vertical direction. The top surface of the isolation layer 90 may be higher than or coplanar with the top surface of the stacked structure. As shown by D2 in FIG. 6, the top surface refers to the surface opposite to the substrate 10, and the vertical direction refers to a direction perpendicular to the top surface of the substrate 10. Materials of the isolation layer 90 include, for example, insulating materials including silicon oxide, silicon nitride, silicon carbide-silicon nitride, etc.

[0016] Each stacked structure includes at least one semiconductor layer 20, and these semiconductor layers 20 are arranged at intervals in the vertical direction. The semiconductor layer 20 in each stacked structure may be in contact with the substrate 10, or may be disposed at an interval from the substrate 10 (shown in FIG. 8). Materials of the semiconductor layer 20 include, for example, semiconductor materials such as single crystal silicon, polycrystalline silicon, and amorphous silicon.

[0017] Each semiconductor layer 20 includes a first doped region 21, a trench region 22 and a second doped region 23 which are sequentially arranged, that is, the first doped region 21 and the second doped region 23 are respectively connected to two sides of the trench region 22. The first doped region 21, the trench region 22 and the second doped region 23 are sequentially adjacent to each other and parallel to the top surface of the substrate 10. The arrangement direction of the first doped region 21, the trench region 22 and the second doped region 23 is the D1 direction shown in FIG. 6 and FIG. 8, and this direction may also be regarded as the extending direction of the semiconductor layer 20.

[0018] The mutually corresponding surfaces of the first doping region 21 and the trench region 22 overlap each other, for example, completely overlap each other, and the mutually corresponding surfaces of the second doping region 23 and the trench region 22 overlap each other, for example, can be completely overlapped. Both the first doping region 21 and the second doping region 23 can be heavily doped regions where doping is achieved, for example, by ion implantation. The first doping region 21 can function as a drain region and is connected to the bit line 30, and the second doping region 23 can function as a source region and is connected to the capacitor structure 40.

[0019] In order to achieve mutual isolation between adjacent semiconductor layers 20 in the same stacked structure, the stacked structure further comprises an insulating layer 50, and the insulating layer 50 is disposed between adjacent semiconductor layers 20. The insulating layer 50 is filled at least between adjacent semiconductor layers 20 and completely contacts the mutually corresponding surfaces of two adjacent semiconductor layers 20, thereby ensuring the isolation effect between each semiconductor layer 20. The material of the insulating layer 50 includes, for example, silicon oxide, silicon nitride, phosphosilicate glass and the like.

[0020] Next, please refer to Figures 7 and 8. The bit line 30 is positioned on the substrate 10 and extends horizontally, with the horizontal direction parallel to the top surface of the substrate 10. The bit line 30 is electrically connected to the first doping region 21, that is, there is electrical conductivity between the bit line 30 and the first doping region 21. In some possible mounting configurations, the bit line 30 and the semiconductor layer 20 are height-matched, such that the top surface of the bit line 30 is higher than the bottom surface of the connected semiconductor layer 20 and lower than or coplanar with the top surface of the connected semiconductor layer 20, or the bottom surface of the bit line 30 is higher than or coplanar with the bottom surface of the connected semiconductor layer 20 and lower than the top surface of the connected semiconductor layer 20. Specifically, by making the top surface of the bit line 30 coplanar with the top surface of the connected semiconductor layer 20 and the bottom surface of the bit line 30 coplanar with the bottom surface of the connected semiconductor layer 20, the fabrication of the bit line 30 can be facilitated and the transmission performance between the bit line 30 and the corresponding semiconductor layer 20 can be improved.

[0021] In some possible examples, the direction of extension of the bit line 30 is parallel to the arrangement direction of multiple stacked structures, so that multiple semiconductor layers 20 can be connected to the bit line 30, and by arranging these semiconductor layers 20 in different stacked structures, the structure of the semiconductor memory device is simplified and the memory density is increased. The direction of extension of the bit line 30 is the D3 direction shown in Figure 6. The bit line 30 can be a single-layer structure or a stacked structure, and exemplary, the bit line 30 comprises a first conductor layer, the material of which the first conductor layer includes, for example, a low-resistance metallic material such as tungsten, aluminum, or copper. The specific structure of the bit line 30 is not limited in the embodiments of the present application. There can be multiple bit lines 30, and the multiple bit lines 30 are arranged at intervals along the vertical direction, thereby avoiding connections between adjacent bit lines 30. The number of bit lines 30 can match the number of semiconductor layers 20 in the stacked structure, so that each stacked structure can draw out each internal semiconductor layer 20 through the multiple bit lines 30.

[0022] Next, please refer to Figures 6 to 8. The capacitive structure 40 is capable of storing data and comprises a stacked lower electrode 41 and an upper electrode 42, which are spaced apart from each other. The lower electrode 41 is connected to the second doping region 23, and exemplary, the lower electrode 41 is positioned on the surface of the second doping region 23 away from the groove region 22, that is, the first doping region 21, the groove region 22, the second doping region 23 and the lower electrode 41 are arranged sequentially. The corresponding surfaces of the lower electrode 41 and the second doping region 23 are in close contact, for example, completely overlapping.

[0023] The material of the lower electrode 41 is made the same as the material of the semiconductor layer 20, so that the lower electrode 41 and the semiconductor layer 20 become one, that is, the lower electrode 41 can function as part of the semiconductor layer 20, and the synchronous fabrication of the lower electrode 41 and the semiconductor layer 20 is made easy. The upper and lower surfaces of the lower electrode 41 are arranged facing each other along the vertical direction, and the end of the lower electrode 41 opposite the second doping region 23 is located within the support layer 60. The support layer provides support to the capacitive structure 40, thereby preventing the collapse of the capacitive structure 40 and ensuring the performance of the semiconductor memory device. Exemplarily, the lower electrode 41 has a first side wall 44 and a second side wall 45 arranged facing each other, with the first side wall 44 in direct contact with the support layer 60 and the second side wall 45 in direct contact with the second doping region 23.

[0024] The upper electrode 42 is positioned between adjacent lower electrodes 41, and is offset from the semiconductor layer 20 along the vertical direction. The upper electrode 42 is positioned on the surface of the insulating layer 50 facing the support layer 60, and furthermore, the upper electrode 42 is positioned centered on the outer circumferential surface of the lower electrode 41, that is, the upper electrode 42 is positioned to fit the lower electrode 41 and is positioned at a distance from the lower electrode 41. The upper electrode 42 is a single structure, meaning that multiple lower electrodes 41 can share one upper electrode 42, and the upper electrode 42 is formed, for example, by a deposition process to facilitate the fabrication of the upper electrode 42. The material of the upper electrode 42 may include low-resistance metallic materials such as titanium nitride, aluminum, titanium, copper, or tungsten, semiconductor materials such as silicon germanium, or combinations of these materials.

[0025] Please refer to Figures 6 to 8. The electrode structure further comprises a dielectric layer 43, which is positioned between the lower electrode 41 and the upper electrode 42, and between the support layer 60 and the upper electrode 42, and the dielectric layer 43 covers a portion of the surface of the lower electrode 41. For example, the dielectric layer 43 covers a portion of the outer circumferential surface of one end of the lower electrode 41 adjacent to the second doping region 23, while the end of the lower electrode 41 opposite the second doping region 23 extends into the support layer 60, and this end is not covered by the dielectric layer 43. The dielectric layer 43 isolates the upper electrode 42 from the lower electrode 41, and the upper electrode 42 from the support layer 60, for example, by covering the upper electrode 42. Examples of materials for the dielectric layer 43 include silicon oxide, zirconium oxide, and aluminum oxide.

[0026] The support layer 60 can be configured to extend vertically, so that it directly contacts the sidewalls, top surface, and bottom surface of the lower electrode 41. The upper and bottom surfaces of the lower electrode 41 are positioned opposite each other vertically, and the sidewalls of the lower electrode 41 are connected to the upper and bottom surfaces of the lower electrode 41. By directly contacting the lower electrode 41, the support layer 60 supports the end of the lower electrode 41 opposite to the semiconductor layer 20, preventing bending of the lower electrode 41 and bridging connections between the lower electrodes 41, thereby ensuring the performance of the semiconductor memory device. The material of the support layer 60 includes, for example, a highly hard insulating material such as silicon nitride or silicon carbide nitride. The laminated structure may be positioned opposite each other on both sides of the support layer 60, i.e., the laminated structure may be positioned along the D1 direction shown in Figure 8. Then the support layer 60 can provide support to the laminated structure on both sides, improving the memory density of the semiconductor memory device.

[0027] In the example where the lower electrode 41 has a first side wall 44 and a second side wall 45 facing each other, the support layer 60 covers the end of the lower electrode 41 opposite the second doping region 23, specifically the first side wall 44 of the lower electrode 41, as well as a portion of the upper and lower surfaces adjacent to the first side wall 44. As shown in Figure 8, the support layer 60 is further in direct contact with the surface of the dielectric layer 43 opposite the insulating layer 50. It should be understood that by having the end of the lower electrode 41 opposite the second doping region 23 protrude beyond the end of the dielectric layer 43 opposite the insulating layer 50, the support layer 60 covers this end and supports the lower electrode 41.

[0028] In some possible embodiments, the orthographic projections of the upper electrode 42 and the lower electrode 41 in the support layer 60 are both within the contours of the corresponding surfaces of the support layer 60. As shown in Figures 7 and 8, the orthographic projection of the lower electrode 41 in the support layer 60 is within the contours of the corresponding surfaces of the support layer 60, and the orthographic projections of the upper electrode 42 in the support layer 60 are both within the contours of the corresponding surfaces of the support layer 60. This increases the extent of the support layer 60 both vertically and horizontally, allowing the support layer 60 to support all of the lower electrodes 41 and to be in complete contact with the first sidewalls 44 of the lower electrodes 41, thereby improving the support effect. At the same time, the contact area between the support layer 60 and the dielectric layer 43 is increased, further improving the support effect of the support layer 60.

[0029] Please refer to Figures 6 to 8. The semiconductor memory device further includes a word line, which extends vertically and is adjacent to the groove region 22. Specifically, the word line is configured to extend in a direction opposite to the upper surface of the substrate 10. The word line is configured to be adjacent to the groove region 22 so that a gate electrode is formed and the opening and closing of the groove region 22 is controlled. The word line can be configured to face the groove regions 22 of multiple semiconductor layers 20 in the same stacked structure so that the opening and closing of multiple groove regions 22 are controlled simultaneously.

[0030] In some possible embodiments, the word line comprises a first word line 71 and a second word line 72, where the first word line 71 is adjacent to the first side of the groove region 22, and the second word line 72 is adjacent to the second side of the groove region 22, with the second and first sides of the groove region 22 facing each other along the extending direction of the bit line 30. As shown in Figure 6, the first word line 71 and the second word line 72 are located on the first and second sides of the groove region 22, respectively, with the first word line 71 being close to the first side of the groove region 22 and facing at least a portion of the groove region 22, and the second word line 72 being close to the second side of the groove region 22 and facing at least a portion of the groove region 22. By having the first and second sides of the groove region 22 face each other along the extending direction of the bit line 30, the groove region 22 can be controlled by the two word lines.

[0031] It should be understood that in the first word line 71 and the second word line 72, gate electrodes are formed in the region directly opposite the groove region 22 along the extending direction of the bit line 30. The structures of the first word line 71 and the second word line 72 may be the same or different. The first word line 71 and the second word line 72 may be single-layer or multi-layer, for example, comprising a second conductor layer. The material of the second conductor layer may include semiconductor materials such as doped polycrystalline silicon or doped amorphous silicon, or low-resistance metallic materials such as tungsten, aluminum, or copper, and the embodiments of this application are not limited thereto.

[0032] To realize the control functions of the first word line 71 and the second word line 72, the semiconductor memory device further includes a gate oxide layer 73, which is located at least between the first word line 71 and the groove region 22, and between the second word line 72 and the groove region 22. Exemplarily, the gate oxide layer 73 extends along the vertical direction, i.e., it is located further between the first word line 71 and the insulating layer 50, and between the second word line 72 and the insulating layer 50. The material of the gate oxide layer 73 may include silicon oxide, hafnium oxide, and the like.

[0033] The semiconductor memory device in the embodiment of the present invention comprises a substrate 10, a plurality of stacked structures, a bit line 30, a capacitance structure 40, and a support layer 60. The plurality of stacked structures are arranged on the substrate 10 and are separated from each other in the vertical direction. Each stacked structure comprises a semiconductor layer 20, which comprises a first doping region 21, a groove region 22, and a second doping region 23. The bit line 30 extends horizontally and is connected to the first doping region 21. The capacitance structure 40 comprises a lower electrode 41 and an upper electrode 42 that are stacked and installed, with the lower electrode 41 connected to the second doping region 23. The support layer 60 is centered on the lower electrode 41 and is in direct contact with the side walls, top surface, and bottom surface of the lower electrode 41. By directly contacting the lower electrode 41 with the support layer 60, the end of the lower electrode 41 opposite to the semiconductor layer 20 is supported, bending of the lower electrode 41 and bridging connections between the lower electrodes 41 are avoided, and the performance of the semiconductor memory device is ensured.

[0034] Embodiments of the present invention further provide a semiconductor memory device, such as a dynamic random access memory. Referring to Figures 10 and 11, the semiconductor memory device comprises a substrate 10, a plurality of stacked structures, bit lines 30, a capacitive structure 40, an insulating layer 50, and a support layer 60. The substrate 10 provides support to the structures on it, such as the stacked structures and the support layer 60. Examples of the substrate 10 include a silicon substrate, a silicon-containing (e.g., silicon-germanium) substrate, or a silicon-on-insulator (e.g., SOI) substrate.

[0035] Multiple stacked structures are arranged on a substrate 10 and are isolated from each other in the vertical direction. Each stacked structure comprises a semiconductor layer 20, which includes a first doping region 21, a groove region 22, and a second doping region 23. The multiple stacked structures are arranged on the substrate 10 at intervals, and the arrangement direction of the multiple stacked structures is shown in D3 of Figure 10. At least adjacent stacked structures are filled with isolation layers 90, which enable mutual isolation between each stacked structure.

[0036] Exemplary, the isolation layer 90 is positioned on the substrate 10 and extends along the vertical direction, thereby ensuring that there is no electrical conductivity between the stacked structures in the vertical direction. The upper surface of the isolation layer 90 can be higher than or coplanar with the upper surface of the stacked structures. As shown in D2 of Figure 10, the upper surface refers to the surface opposite to the surface of the substrate 10, and the vertical direction refers to the direction perpendicular to the upper surface of the substrate 10. The material of the isolation layer 90 includes, for example, insulating materials such as silicon oxide, silicon nitride, and silicon carbide-silicon nitride.

[0037] Each stacked structure includes at least one semiconductor layer 20, which are arranged with spacing in the vertical direction. The semiconductor layers 20 in each stacked structure may be in contact with the substrate 10, or they may be spaced apart from the substrate 10. The material of the semiconductor layer 20 may include, for example, single-crystal silicon, polycrystalline silicon, amorphous silicon, and other semiconductor materials.

[0038] Each semiconductor layer 20 comprises sequentially arranged first doping regions 21, groove regions 22, and second doping regions 23, that is, the first doping regions 21 and second doping regions 23 are connected to both sides of the groove region 22, respectively. The first doping regions 21, groove regions 22, and second doping regions 23 are sequentially adjacent and parallel to the upper surface of the substrate 10. The arrangement direction of the first doping regions 21, groove regions 22, and second doping regions 23 is the D1 direction shown in Figures 10 and 11, and this direction may also be considered as the extension direction of the semiconductor layer 20.

[0039] The corresponding surfaces of the first doping region 21 and the groove region 22 overlap each other, for example, completely, and the corresponding surfaces of the second doping region 23 and the groove region 22 overlap each other, for example, completely. Both the first doping region 21 and the second doping region 23 can be high-concentration doping regions, for example, achieved by ion implantation. The first doping region 21 can function as a drain region and is connected to the bit line 30, and the second doping region 23 can function as a source region and is connected to the volume structure 40.

[0040] The bit line 30 is positioned on the substrate 10 and extends horizontally, with the horizontal direction parallel to the top surface of the substrate 10. The bit line 30 is electrically connected to the first doping region 21, i.e., electrically conductive between the bit line 30 and the first doping region 21. In some possible mounting configurations, the heights of the bit line 30 and the semiconductor layer 20 are matched, with the top surface of the bit line 30 being higher than the bottom surface of the connected semiconductor layer 20 and lower than or coplanar with the top surface of the connected semiconductor layer 20, or the bottom surface of the bit line 30 being higher than or coplanar with the bottom surface of the connected semiconductor layer 20 and lower than the top surface of the connected semiconductor layer 20. Specifically, by arranging the bit line 30 so that its upper surface is on the same plane as the upper surface of the connected semiconductor layer 20, and its lower surface is on the same plane as the connected semiconductor layer 20, the bit line 30 and the semiconductor layer 20 are placed on the same layer, making it easier to manufacture the bit line 30 and improving the transmission performance between the bit line 30 and the corresponding semiconductor layer 20.

[0041] In some possible examples, the direction of extension of the bit line 30 is parallel to the arrangement direction of multiple stacked structures, so that multiple semiconductor layers 20 can be connected to the bit line 30, and by arranging these semiconductor layers 20 in different stacked structures, the structure of the semiconductor memory device is simplified and the memory density is increased. The direction of extension of the bit line 30 is the D3 direction shown in Figure 10. The bit line 30 can be a single-layer structure or a stacked structure, and exemplary, the bit line 30 comprises a first conductor layer, the material of which the first conductor layer may include a low-resistance metallic material such as tungsten, aluminum, or copper. The specific structure of the bit line 30 is not limited in the embodiments of this application. There may be multiple bit lines 30, and the multiple bit lines 30 may be arranged at intervals along the vertical direction, thereby avoiding connections between adjacent bit lines 30. The number of bit lines 30 may correspond to the number of semiconductor layers 20 in the stacked structure, so that each stacked structure can draw out each internal semiconductor layer 20 through the multiple bit lines 30.

[0042] Next, please refer to Figures 10 and 11. The capacitive structure 40 is capable of storing data and comprises a stacked lower electrode 41 and an upper electrode 42, which are spaced apart from each other. The lower electrode 41 is connected to the second doping region 23, and exemplary, the lower electrode 41 is located on the surface of the second doping region 23 away from the groove region 22, i.e., the first doping region 21, groove region 22, second doping region 23 and lower electrode 41 are arranged in sequence. The corresponding surfaces of the lower electrode 41 and the second doping region 23 are in close contact, for example, completely overlapping.

[0043] Exemplary, the lower electrode 41 comprises a first side wall 44 and a second side wall 45 arranged opposite each other, with the first side wall 44 in direct contact with the support layer 60 and the second side wall 45 in direct contact with the second doping region 23. The surface of the lower electrode 41 that is separated from the second doping region 23 is in close contact with the support layer 60. The material of the lower electrode 41 may include low-resistance metallic materials such as titanium nitride, aluminum, titanium, copper, or tungsten, semiconductor materials such as silicon germanium, or combinations thereof.

[0044] The upper electrode 42 is positioned partially inside the lower electrode 41, meaning the lower electrode 41 surrounds a portion of the upper electrode 42. The upper electrode 42 faces the lower electrode 41 and is positioned at a distance from it. The upper electrode 42 is a single, integrated structure, meaning multiple lower electrodes 41 can share one upper electrode 42. The upper electrode 42 is formed, for example, by a deposition process to facilitate its fabrication. The material of the upper electrode 42 may include low-resistance metallic materials such as titanium nitride, aluminum, titanium, copper, or tungsten, semiconductor materials such as silicon germanium, or combinations of these materials.

[0045] In some possible embodiments, the orthographic projections of the upper electrode 42 and the lower electrode 41 in the support layer 60 are both within the contours of the corresponding surfaces of the support layer 60. As shown in Figures 10 and 11, the orthographic projection of the lower electrode 41 in the support layer 60 is within the contours of the corresponding surfaces of the support layer 60, and the orthographic projections of the upper electrode 42 in the support layer 60 are both within the contours of the corresponding surfaces of the support layer 60. This increases the extent of the support layer 60 both vertically and horizontally, allowing the support layer 60 to support all of the lower electrodes 41 and to be in complete contact with the first sidewalls 44 of the lower electrodes 41, thereby improving the support effect. At the same time, the contact area between the support layer 60 and the dielectric layer 43 is increased, further improving the support effect of the support layer 60.

[0046] The semiconductor memory device further includes a dielectric layer 43, which is positioned between the lower electrode 41 and the upper electrode 42. Examples of materials for the dielectric layer 43 include silicon oxide, zirconium oxide, and aluminum oxide. To achieve mutual isolation along the vertical direction between the capacitive structures 40, an insulating layer 50 is positioned between adjacent capacitive structures 40, specifically between adjacent lower electrodes 41. Examples of materials for the insulating layer 50 include silicon oxide, silicon nitride, and phosphate glass.

[0047] The insulating layer 50 is further positioned between adjacent semiconductor layers 20, thereby enabling mutual isolation along the vertical direction between adjacent semiconductor layers 20. Furthermore, the insulating layer 50 extends between even more adjacent bit lines 30 to achieve mutual isolation along the vertical direction between adjacent bit lines 30. As shown in Figure 11, the lower electrode 41 covers a portion of the surface of the insulating layer 50, the semiconductor layer 20 covers a portion of the surface of the insulating layer 50, and the bit line 30 covers a portion of the surface of the insulating layer 50.

[0048] In some possible examples, the insulating layer 50 has a first and second end that are opposite each other, with the first end of the insulating layer 50 protruding beyond the end of the bit line 30 opposite the first doping region 21, or it may be coplanar with the end of the bit line 30 opposite the first doping region 21, and the second end of the insulating layer 50 protruding beyond the end of the lower electrode 41 opposite the second doping region 23. The first and second ends of the insulating layer 50 are positioned opposite each other along the alignment direction of the semiconductor layer 20 and the capacitive structure 40.

[0049] Please refer to Figures 10 and 11. The support layer 60 is positioned between the insulating layers 50 and in direct contact with the sidewalls, top surface, and bottom surface of the insulating layer 50. In this case, one end of the insulating layer 50 extends into the support layer 60, and the support layer 60 provides support to the insulating layer 50, thereby maintaining the stability of the insulating layer 50 and preventing bending of the insulating layer 50. This prevents the capacitive structure 40 that is subsequently formed on the insulating layer 50 from bending and bridging, thus ensuring the performance of the semiconductor memory device. The top and bottom surfaces of the insulating layer 50 are spaced apart along the vertical direction, and the sidewalls of the insulating layer 50 are the surfaces opposite the bit lines 30 of the insulating layer 50. The laminated structure can also be positioned opposite each other on both sides of the support layer 60, that is, the laminated structure can be positioned along the D1 direction shown in Figures 10 and 11. In this case, the support layer 60 can provide support to the laminated structures on both sides, improving the memory density of the semiconductor memory device.

[0050] In some possible embodiments, the bit line 30 and the support layer 60 are positioned on opposite sides of the semiconductor layer 20. The bit line 30 is positioned on one side of the semiconductor layer 20, the capacitive structure 40 is positioned on the other side of the semiconductor layer 20, and the support layer 60 is positioned on the side of the capacitive structure 40 opposite to the semiconductor layer 20. Specifically, the support layer 60 is in direct contact with the surface of the lower electrode 41 opposite to the second doping region 23, and at the same time, it is in direct contact with the side wall, part of the upper surface and part of the lower surface of the insulating layer 50 opposite to the bit line 30.

[0051] Please refer to Figures 10 and 11. The semiconductor memory device further includes a word line, which extends vertically and is adjacent to the groove region 22. Specifically, the word line extends in the direction opposite to the top surface of the substrate 10. The word line is adjacent to the groove region 22 so that a gate electrode is formed and the opening and closing of the groove region 22 is controlled. The word line can be positioned to face the groove regions 22 of multiple semiconductor layers 20 in the same stacked structure so that the opening and closing of multiple groove regions 22 is controlled.

[0052] In some possible embodiments, the word line comprises a first word line 71 and a second word line 72, where the first word line 71 is adjacent to the first side of the groove region 22, and the second word line 72 is adjacent to the second side of the groove region 22, with the second and first sides of the groove region 22 facing each other along the extending direction of the bit line 30. As shown in the figure, the first word line 71 and the second word line 72 are positioned on the first and second sides of the groove region 22, respectively, with the first word line 71 being close to the first side of the groove region 22 and facing at least a portion of the groove region 22, and the second word line 72 being close to the second side of the groove region 22 and facing at least a portion of the groove region 22. By having the first and second sides of the groove region 22 face each other along the extending direction of the bit line 30, the groove region 22 can be controlled by the two word lines.

[0053] It should be understood that in the first word line 71 and the second word line 72, gate electrodes are formed in the region directly opposite the groove region 22 along the extending direction of the bit line 30. The structures of the first word line 71 and the second word line 72 may be the same or different. The first word line 71 and the second word line 72 may be single-layer or multi-layer, for example, comprising a second conductor layer, the material of which may include semiconductor materials such as doped polycrystalline silicon or doped amorphous silicon, or low-resistance metallic materials such as tungsten, aluminum, or copper, and the embodiments of this application are not limited thereto.

[0054] To realize the control functions of the first word line 71 and the second word line 72, the semiconductor memory device further includes a gate oxide layer 73, which is located at least between the first word line 71 and the groove region 22, and between the second word line 72 and the groove region 22. Exemplarily, the gate oxide layer 73 extends along the vertical direction, i.e., it is located further between the first word line 71 and the insulating layer 50, and between the second word line 72 and the insulating layer 50. The material of the gate oxide layer 73 includes silicon oxide, hafnium oxide, and the like.

[0055] The semiconductor memory device in the embodiment of the present invention comprises a substrate 10, a plurality of stacked structures, a bit line 30, a capacitance structure 40, an insulating layer 50, and a support layer 60. The plurality of stacked structures are arranged on the substrate 10 and are separated from each other in the vertical direction, and each stacked structure comprises a semiconductor layer 20, which comprises a first doping region 21, a groove region 22, and a second doping region 23. The bit line 30 extends along the horizontal direction and is connected to the first doping region 21. The capacitance structure 40 comprises a lower electrode 41 and an upper electrode 42 that are stacked and installed, with the lower electrode 41 connected to the second doping region 23. The insulating layer 50 is arranged between adjacent capacitance structures 40, and the support layer 60 is arranged between the insulating layers 50 and is in direct contact with the side walls, top surface, and bottom surface of the insulating layers 50. As a result, one end of the insulating layer 50 extends into the support layer 60, and the support layer 60 provides support to the insulating layer 50, maintaining the stability of the insulating layer 50 and preventing bending of the insulating layer 50. This prevents the capacitive structure 40 that is subsequently formed on the insulating layer 50 from bending and bridging, thereby ensuring the performance of the semiconductor memory device.

[0056] Embodiments of the present invention further provide a method for manufacturing a semiconductor memory device, referring to Figures 1 to 11, the manufacturing method specifically includes the steps of providing a substrate 10, and forming a plurality of stacked structures, bit lines 30, capacitance structures 40, and support layers 60, wherein the plurality of stacked structures are arranged on the substrate 10 and are separated from each other in the vertical direction, the stacked structures comprise a semiconductor layer 20, the semiconductor layer 20 comprises a first doping region 21, a groove region 22, and a second doping region 23, the bit lines 30 extend along the horizontal direction and are connected to the first doping region 21, the capacitance structure 40 comprises a stacked lower electrode 41 and an upper electrode 42, the lower electrode 41 is connected to the second doping region 23, and the support layer 60 is in contact with the side wall of the capacitance structure 40.

[0057] The substrate 10 provides support, and examples of substrates 10 include silicon substrates, silicon-containing (e.g., silicon-germanium) substrates, or silicon-on-insulator (e.g., SOI) substrates. Multiple laminated structures, bit lines 30, capacitive structures 40, and support layers 60 are formed on the substrate 10. The multiple laminated structures are arranged on the substrate 10 with spacing between them so that mutual isolation between each laminated structure can be easily achieved. The arrangement direction of the multiple laminated structures is shown in Figure 6 and D3 in Figure 10. At least between adjacent laminated structures, isolation layers 90 are filled, and the isolation layers 90 achieve mutual isolation between each laminated structure.

[0058] Exemplary, the isolation layer 90 is positioned on the substrate 10 and extends along the vertical direction, thereby ensuring that there is no electrical conductivity between the stacked structures in the vertical direction. The upper surface of the isolation layer 90 can be higher than or coplanar with the upper surface of the stacked structures. As shown in Figures 6 and 10, D2, the upper surface refers to the surface opposite to the substrate 10, and the vertical direction refers to the direction perpendicular to the upper surface of the substrate 10. The material of the isolation layer 90 includes, for example, insulating materials such as silicon oxide, silicon nitride, and silicon carbide-silicon nitride.

[0059] Each stacked structure includes at least one semiconductor layer 20, which are arranged with spacing in the vertical direction. The semiconductor layers 20 in each stacked structure may be in contact with the substrate 10, or they may be spaced apart from the substrate 10. The material of the semiconductor layer 20 may include, for example, single-crystal silicon, polycrystalline silicon, amorphous silicon, and other semiconductor materials.

[0060] Each semiconductor layer 20 comprises a sequentially arranged first doping region 21, groove region 22, and second doping region 23, that is, the first doping region 21 and the second doping region 23 are connected to both sides of the groove region 22, respectively. The first doping region 21, groove region 22, and second doping region 23 are sequentially adjacent and parallel to the upper surface of the substrate 10. The arrangement direction of the first doping region 21, groove region 22, and second doping region 23 is the D1 direction shown in Figures 6 and 10, and this direction may also be considered as the extension direction of the semiconductor layer 20.

[0061] The corresponding surfaces of the first doping region 21 and the groove region 22 can overlap, for example, completely, and the corresponding surfaces of the second doping region 23 and the groove region 22 can overlap, for example, completely. Both the first doping region 21 and the second doping region 23 can be high-concentration doping regions, for example, by ion implantation. The first doping region 21 can function as a drain region and is connected to the bit line 30, and the second doping region 23 can function as a source region and is connected to the volume structure 40.

[0062] Next, please refer to Figure 2. The manufacturing method further includes a step of forming a word line, the word line extending along the vertical direction and adjacent to the groove region 22. Specifically, the word line extends along the direction opposite to the upper surface of the substrate 10. The word line is adjacent to the groove region 22 so that a gate electrode is formed and the opening and closing of the groove region 22 is controlled. The word line can be positioned to face the groove regions 22 of multiple semiconductor layers 20 in the same stacked structure so that the opening and closing of multiple groove regions 22 are controlled simultaneously.

[0063] In some possible embodiments, the word line comprises a first word line 71 and a second word line 72, where the first word line 71 is adjacent to the first side of the groove region 22, and the second word line 72 is adjacent to the second side of the groove region 22, with the second and first sides of the groove region 22 facing each other along the extending direction of the bit line 30. As shown in the figure, the first word line 71 and the second word line 72 are positioned on the first and second sides of the groove region 22, respectively, with the first word line 71 being close to the first side of the groove region 22 and facing at least a portion of the groove region 22, and the second word line 72 being close to the second side of the groove region 22 and facing at least a portion of the groove region 22. By having the first and second sides of the groove region 22 face each other along the extending direction of the bit line 30, the groove region 22 can be controlled by the two word lines.

[0064] It should be understood that in the first word line 71 and the second word line 72, gate electrodes are formed in the region directly opposite the groove region 22 along the extending direction of the bit line 30. The structures of the first word line 71 and the second word line 72 may be the same or different. The first word line 71 and the second word line 72 may be single-layer or multi-layer, for example, comprising a second conductor layer. The material of the second conductor layer may include semiconductor materials such as doped polycrystalline silicon or doped amorphous silicon, or low-resistance metallic materials such as tungsten, aluminum, or copper, and the embodiments of this application are not limited thereto.

[0065] To realize the control functions of the first word line 71 and the second word line 72, the semiconductor memory device further includes a gate oxide layer 73, which is located at least between the first word line 71 and the groove region 22, and between the second word line 72 and the groove region 22. Exemplarily, the gate oxide layer 73 extends along the vertical direction, i.e., it is located further between the first word line 71 and the insulating layer 50, and between the second word line 72 and the insulating layer 50. The material of the gate oxide layer 73 includes silicon oxide, hafnium oxide, and the like.

[0066] The bit line 30 is positioned on the substrate 10 and extends horizontally, with the horizontal direction parallel to the top surface of the substrate 10. The bit line 30 is electrically connected to the first doping region 21, i.e., electrically conductive between the bit line 30 and the first doping region 21. In some possible mounting configurations, the heights of the bit line 30 and the semiconductor layer 20 are matched, such that the top surface of the bit line 30 is higher than the bottom surface of the connected semiconductor layer 20 and lower than or coplanar with the top surface of the connected semiconductor layer 20, or the bottom surface of the bit line 30 is higher than or coplanar with the bottom surface of the connected semiconductor layer 20 and lower than the top surface of the connected semiconductor layer 20. Specifically, by arranging the bit line 30 so that its upper surface is on the same plane as the upper surface of the connected semiconductor layer 20, and its lower surface is on the same plane as the connected semiconductor layer 20, the bit line 30 and the semiconductor layer 20 are placed on the same layer, making it easier to manufacture the bit line 30 and improving the transmission performance between the bit line 30 and the corresponding semiconductor layer 20.

[0067] In some possible examples, the direction of extension of the bit line 30 is parallel to the arrangement direction of multiple stacked structures, so that multiple semiconductor layers 20 can be connected to the bit line 30, and by arranging these semiconductor layers 20 in different stacked structures, the structure of the semiconductor memory device is simplified and the memory density is increased. The direction of extension of the bit line 30 is the D3 direction shown in Figures 6 and 10. The bit line 30 can be a single-layer structure or a stacked structure, and exemplary, the bit line 30 comprises a first conductor layer, the material of which the first conductor layer may include, for example, a low-resistance metallic material such as tungsten, aluminum, or copper. The specific structure of the bit line 30 is not limited in the embodiments of this application. There may be multiple bit lines 30, and the multiple bit lines 30 may be arranged at intervals along the vertical direction, thereby avoiding connections between adjacent bit lines 30. The number of bit lines 30 may correspond to the number of semiconductor layers 20 in the stacked structure, so that each stacked structure can draw out each internal semiconductor layer 20 by multiple bit lines 30.

[0068] Next, please refer to Figures 1 to 11. The capacitive structure 40 can store data and comprises a stacked lower electrode 41 and an upper electrode 42, with the lower electrode 41 and upper electrode 42 spaced apart from each other. The lower electrode 41 is further connected to a second doping region 23, for example, the lower electrode 41 is positioned on a surface away from the groove region 22 of the second doping region 23, i.e., the first doping region 21, groove region 22, second doping region 23 and lower electrode 41 are arranged sequentially. The corresponding surfaces of the lower electrode 41 and the second doping region 23 are in close contact, for example, completely overlapping. The materials for the lower electrode 41 and upper electrode 42 include, for example, low-resistance metallic materials such as titanium nitride, aluminum, titanium, copper or tungsten, semiconductor materials such as silicon germanium, or combinations of these materials. To realize the memory function of the capacitive structure 40, a dielectric layer 43 is formed between the upper electrode 42 and the lower electrode 41. The material of the dielectric layer 43 includes, for example, silicon oxide, zirconium oxide, and aluminum oxide.

[0069] The support layer 60 is positioned on the side of the semiconductor layer 20 opposite to the bit line 30, i.e., the support layer 60 and the bit line 30 are positioned on opposite sides of the semiconductor layer 20, and the capacitive structure 40 is further formed between the support layer 60 and the semiconductor layer 20. The support layer 60 can extend along the vertical direction and contact the side wall of the capacitive structure 40, for example, so that the support layer 60 directly contacts at least the surface opposite to the second doping region 23 of the lower electrode 41, thereby providing support to the capacitive structure 40, preventing bending of the capacitive structure 40, and improving the performance of the formed semiconductor memory device. The material of the support layer 60 includes, for example, a highly hard insulating material such as silicon nitride or silicon carbide nitride. Laminated structures can be formed on both sides of the support layer 60, i.e., the laminated structures can be positioned along the D1 direction as shown in Figures 8 and 11. The support layer 60 provides support to the laminated structures on both sides, improving the memory density of the semiconductor memory device.

[0070] In some possible embodiments, referring to Figures 1 to 8, the support layer 60 is centered on the lower electrode 41 and is in direct contact with the side walls, top surface, and bottom surface of the lower electrode 41. The top and bottom surfaces of the lower electrode 41 are positioned opposite each other along the vertical direction. By providing support to the capacitive structure 40 by the support layer 60 such that the end of the lower electrode 41 opposite the second doping region 23 is within the support layer 60, bending of the lower electrode 41 and bridging connections between the lower electrodes 41 can be avoided, thereby ensuring the performance of the semiconductor memory device.

[0071] For example, the lower electrode 41 comprises a first side wall 44 and a second side wall 45 arranged opposite each other, with the first side wall 44 in direct contact with the support layer 60 and the second side wall 45 in direct contact with the second doping region 23. By making the material of the lower electrode 41 the same as the material of the semiconductor layer 20, the lower electrode 41 and the semiconductor layer 20 become one unit, facilitating the synchronous fabrication of the lower electrode 41 and the semiconductor layer 20. The lower electrode 41 and the semiconductor layer 20 are arranged in the same layer, and the lower electrode 41 can function as part of the semiconductor layer 20. The upper electrode 42 is positioned between adjacent lower electrodes 41, and along the vertical direction, the upper electrode 42 is offset from the semiconductor layer 20.

[0072] In this embodiment, the method for fabricating a semiconductor memory device further includes the step of forming an insulating layer 50, which is positioned between adjacent semiconductor layers 20 such that mutual isolation between adjacent semiconductor layers 20 in the same stacked structure is achieved. The insulating layer 50 fills at least the space between adjacent semiconductor layers 20 and is in complete contact with the corresponding surfaces of two adjacent semiconductor layers 20, thereby ensuring the isolation effect between each semiconductor layer 20. Examples of materials for the insulating layer 50 include silicon oxide, silicon nitride, and phosphate glass. The upper electrode 42 is specifically formed on the surface of the insulating layer 50 facing the support layer 60. The upper electrode 42 is positioned centered on the outer circumferential surface of the lower electrode 41, that is, the upper electrode 42 is positioned to fit the lower electrode 41 and is positioned at a distance from the lower electrode 41. The upper electrode 42 is an integral structure, that is, multiple lower electrodes 41 can share one upper electrode 42, and the upper electrode 42 is formed, for example, in a deposition process to facilitate the fabrication of the upper electrode 42.

[0073] In this embodiment, the dielectric layer 43 is positioned between the lower electrode 41 and the upper electrode 42, and between the support layer 60 and the upper electrode 42, with the dielectric layer 43 covering a portion of the surface of the lower electrode 41. For example, the dielectric layer 43 covers a portion of the outer circumferential surface of one end of the lower electrode 41 adjacent to the second doping region 23, while the end of the lower electrode 41 opposite the second doping region 23 extends into the support layer 60, and the dielectric layer 43 is not formed on this end. Specifically, the lower electrode 41 and the dielectric layer 43 are in contact with the support layer 60, and the dielectric layer covers the surface of the portion where the lower electrode 41 and the upper electrode 42 face each other, with the upper electrode 42 positioned at a distance from the support layer 60.

[0074] As one possible implementation, the specific process of the manufacturing method in the embodiment of this application is as follows:

[0075] Refer to Figures 1 and 2. A laminated initial structure is formed, which comprises alternating insulating initial layers and semiconductor initial layers, and a mask layer 80 is formed on the laminated initial structure. The insulating initial layer and semiconductor initial layer are formed as an insulating layer 50 and a semiconductor layer 20, respectively, in a subsequent process. The insulating initial layer, semiconductor initial layer, and mask layer 80 can all be formed in the deposition process and are all complete film layers.

[0076] A mask layer 80 is patterned, and the patterned mask layer 80 is used as a mask to etch the initial laminated structure, forming a laminated structure and isolation grooves that separate each laminated structure. A predetermined pattern is formed on the mask layer 80 by photolithography etching, and this pattern is transferred downwards. The formed laminated structure comprises alternatingly arranged insulating layers 50 and semiconductor layers 20. The mask layer 80 may be consumed when etching the initial laminated structure, may be removed after the formation of the laminated structure, or may be removed after the formation of the capacitive structure. After the formation of the laminated structure, isolation layers 90 may be formed in the isolation grooves so that each laminated structure is independent of the others.

[0077] As shown in Figures 1 and 2, a bit line 30 is formed on one side of the semiconductor layer 20, and the bit line 30 is connected to the semiconductor layer 20. The bit line 30 may be formed by removing a portion of the semiconductor layer 20 and then depositing the bit line material, or the bit line 30 may be formed by depositing the bit line material adjacent to another film layer of the semiconductor layer 20.

[0078] Referring to Figures 3 and 9, the insulating layer 50 on the end opposite the bit line 30 is partially removed to form the support layer 60. Before partially removing the insulating layer 50, the isolation layer 90 opposite the bit line 30 may be partially removed, which increases the exposed area of ​​the insulating layer 50 and makes it easier to remove part of the insulating layer 50. The support layer 60 may be formed by deposition, and the support layer 60 is filled between adjacent semiconductor layers 20 and is also formed on the side of the semiconductor layer 20 opposite the bit line 30. Before or after the formation of the support layer 60, gate oxide layers 73 are formed on both sides of the laminated structure, and a first word line 71 and a second word line 72 are formed corresponding to the side of the gate oxide layer 73 away from the laminated structure. Exemplarily, after the formation of the support layer 60, the isolation layer 90 is partially removed to expose at least a portion of the semiconductor layer 20, and gate oxide material and word line material are sequentially deposited in that position to form the gate oxide layer 73, the first word line 71 and the second word line 72.

[0079] Referring to Figures 4 to 7, the insulating layer 50 adjacent to the support layer 60 is partially removed, and the dielectric layer 43 and upper electrode 42 are sequentially deposited, filling the gap between adjacent semiconductor layers 20 with the dielectric layer 43 and upper electrode 42, that is, making a part of the semiconductor layer 20 function as the lower electrode 41. As shown in Figures 4 and 5, before partially removing the insulating layer 50, the isolation layer 90 opposite the support layer 60 may be partially removed, which increases the exposed area of ​​the insulating layer 50 and makes it easier to remove a part of the insulating layer 50. As shown in Figures 6 and 7, on the surface of the exposed semiconductor layer 20, the dielectric layer 43 is deposited such that the gap between adjacent semiconductor layers 20 along the vertical direction is not filled with the dielectric layer 43, and then on the surface of the dielectric layer 43, the upper electrode 42 is deposited such that the remaining gap between adjacent semiconductor layers 20 along the vertical direction is filled with the upper electrode 42.

[0080] In several other possible embodiments, referring to Figures 9 to 11, the manufacturing method further includes the step of forming an insulating layer 50, which is positioned between adjacent capacitive structures 40, and a support layer 60 is positioned between the insulating layers 50 and in direct contact with the side walls, top surface, and bottom surface of the insulating layers 50. Specifically, the insulating layer 50 is formed between adjacent lower electrodes 41, and the material of the insulating layer 50 includes, for example, silicon oxide, silicon nitride, or phosphate glass. The insulating layer 50 has a first end and a second end that are positioned opposite each other, and the first end of the insulating layer 50 may protrude from the end opposite the first doping region 21 of the bit line 30, or it may be coplanar with the end opposite the first doping region 21 of the bit line 30 and the second end of the insulating layer 50 protrude from the end opposite the second doping region 23 of the lower electrode 41. The first and second ends of the insulating layer 50 are positioned opposite each other along the alignment direction of the semiconductor layer 20 and the capacitive structure 40.

[0081] The support layer 60 covers one end of the insulating layer 50, providing support to the insulating layer 50 and maintaining its stability, thereby preventing bending of the insulating layer 50. This prevents the capacitive structure 40 subsequently formed on the insulating layer 50 from bending and bridging, thus ensuring the performance of the semiconductor memory device. The upper and lower surfaces of the insulating layer 50 are spaced apart along the vertical direction, and the sidewalls of the insulating layer 50 are the surfaces opposite to the bit line 30 of the insulating layer 50. Specifically, the lower electrode 41 is in contact with the support layer 60, the dielectric layer covers all surfaces of the lower electrode 41 that are directly facing the upper electrode 42, and both the dielectric layer 43 and the upper electrode 42 are spaced apart from the support layer 60.

[0082] In this embodiment, the insulating layer 50 is further positioned between adjacent semiconductor layers 20, thereby enabling the insulating layer 50 to achieve mutual isolation along the vertical direction between adjacent semiconductor layers 20. Furthermore, the insulating layer 50 extends between even more adjacent bit lines 30 to achieve mutual isolation along the vertical direction between adjacent bit lines 30. As shown in Figure 11, the lower electrode 41 covers a portion of the surface of the insulating layer 50, the semiconductor layer 20 covers a portion of the surface of the insulating layer 50, and the bit line 30 covers a portion of the surface of the insulating layer 50.

[0083] Referring to Figures 1 to 3 and Figures 9 to 11, one possible implementation is a specific process of the manufacturing method in the embodiment of this application, which is as follows.

[0084] A laminated initial structure is formed, which comprises alternatingly arranged insulating initial layers and semiconductor initial layers, and a mask layer 80 is formed on the laminated initial structure. The insulating initial layer and semiconductor initial layer are formed as an insulating layer 50 and a semiconductor layer 20, respectively, in a subsequent process, and the insulating initial layer, semiconductor initial layer and mask layer 80 can all be formed in the deposition process and are all complete film layers.

[0085] A mask layer 80 is patterned, and the patterned mask layer 80 is used as a mask to etch the initial laminated structure, forming a laminated structure and isolation grooves that separate each laminated structure. A predetermined pattern is formed on the mask layer 80 by photolithography etching, and this pattern is transferred downwards. The formed laminated structure comprises alternatingly arranged insulating layers 50 and semiconductor layers 20. The mask layer 80 may be consumed when etching the initial laminated structure, may be removed after the formation of the laminated structure, or may be removed after the formation of the capacitive structure. After the formation of the laminated structure, isolation layers 90 may be formed in the isolation grooves so that each laminated structure is independent of the others.

[0086] A bit line 30 is formed on one side of the semiconductor layer 20, and the bit line 30 is connected to a first doping region 21 in the semiconductor layer 20. The bit line 30 may be formed by removing a portion of the semiconductor layer 20 and then depositing the bit line material, or the bit line 30 may be formed by depositing the bit line material adjacent to another film layer of the semiconductor layer 20.

[0087] The semiconductor layer 20 opposite the bit line 30 is partially removed to form a support layer 60. Before partially removing the insulating layer 50, the isolation layer 90 opposite the bit line 30 may be partially removed, which increases the exposed area of ​​the insulating layer 50 and makes it easier to remove part of the insulating layer 50. The support layer 60 may be formed by deposition, and the support layer 60 is filled between adjacent semiconductor layers 20 and formed on the side of the semiconductor layer 20 opposite the bit line 30. Before or after the formation of the support layer 60, gate oxide layers 73 are formed on both sides of the laminated structure, and a first word line 71 and a second word line 72 are formed corresponding to the side of the gate oxide layer 73 away from the laminated structure. Exemplarily, after the formation of the support layer 60, the isolation layer 90 is partially removed to expose at least a portion of the semiconductor layer 20, and gate oxide material and word line material are sequentially deposited in that position to form the gate oxide layer 73, the first word line 71 and the second word line 72.

[0088] The semiconductor layer 20 adjacent to the support layer 60 is partially removed, and the lower electrode 41, dielectric layer 43, and upper electrode 42 are sequentially deposited to form a capacitive structure 40, where the lower electrode 41, dielectric layer 43, and upper electrode 42 fill the gaps between adjacent insulating layers 50. As shown in Figure 9, before partially removing the semiconductor layer 20, the isolation layer 90 opposite the support layer 60 may be partially removed, which increases the exposed area of ​​the semiconductor layer 20, making it easier to partially remove the semiconductor layer 20 and partially exposing the insulating layer 50. On the surface of the exposed insulating layer 50, the lower electrode 41 is deposited such that the gaps between adjacent insulating layers 50 in the vertical direction are not filled with the lower electrode 41, then the dielectric layer 43 is deposited such that the gaps between adjacent insulating layers 50 in the vertical direction are not filled with the dielectric layer 43, and on the surface of the dielectric layer 43, the upper electrode 42 is deposited such that the remaining gaps between adjacent insulating layers 50 in the vertical direction are filled with the upper electrode 42.

[0089] In the two embodiments described above and other possible embodiments, the orthographic projections of the upper electrode 42 and the lower electrode 41 in the support layer 60 are both within the contours of the corresponding surfaces of the support layer 60. As shown in Figures 7 and 8, the orthographic projection of the lower electrode 41 in the support layer 60 is within the contours of the corresponding surfaces of the support layer 60, and the orthographic projections of the upper electrode 42 in the support layer 60 are both within the contours of the corresponding surfaces of the support layer 60. This increases the area of ​​the support layer 60 both vertically and horizontally, allowing the support layer 60 to support all of the lower electrodes 41 while simultaneously being able to make complete contact with the first sidewalls 44 of the lower electrodes 41, thereby improving the support effect. At the same time, the contact area between the support layer 60 and the dielectric layer 43 is increased, further improving the support effect of the support layer 60.

[0090] A method for fabricating a semiconductor memory device provided by an embodiment of the present invention includes the steps of providing a substrate 10 and forming a plurality of stacked structures, bit lines 30, a capacitance structure 40, and a support layer 60, wherein the plurality of stacked structures are arranged on the substrate 10 and are separated from each other in the vertical direction, the stacked structures comprise a semiconductor layer 20 which comprises a first doping region 21, a groove region 22, and a second doping region 23, the bit lines 30 extend along the horizontal direction and are connected to the first doping region 21, the capacitance structure 40 comprises a stacked lower electrode 41 and an upper electrode 42 which are connected to the second doping region 23, and the support layer 60 is in contact with the side wall of the capacitance structure 40. The support layer 60 can perform a support function when forming the capacitance structure 40, thereby avoiding bending of the capacitance structure 40 and improving the performance of the formed semiconductor memory device.

[0091] Finally, it should be noted that those skilled in the art, upon reviewing this specification and practicing the invention disclosed herein, should readily conceive of other embodiments of the invention. The invention is intended to encompass any variations, uses, or adaptive changes of the invention, including common or ordinary technical means known in the art but not disclosed herein, in accordance with the general principles of the invention, and is not limited to the exact structures described above and shown in the drawings, but can be modified and altered in any way that does not depart from that scope. The scope of the invention is limited only by the appended claims. [Explanation of Symbols]

[0092] 10. Circuit board 20. Semiconductor layer 21. Doping Area 1 22, groove area 23. Second Doping Area 30, bit line 40, capacity structure 41. Lower electrode 42, upper electrode 43. Dielectric layer 44. First side wall 45. Second side wall 50. Insulating layer 60, support layer 71. First Wordline 72. Second Wordline 73. Gate oxide layer 80, Mask layer 90, isolation layer

Claims

1. A semiconductor memory device comprising a substrate, multiple stacked structures, bit lines, a capacitive structure, and a support layer, The plurality of stacked structures are arranged on the substrate and are separated from each other in the vertical direction, and each stacked structure comprises a semiconductor layer, the semiconductor layer comprises a first doping region, a groove region and a second doping region, The bit line extends horizontally and is connected to the first doping area. The aforementioned capacitive structure comprises a lower electrode and an upper electrode, the lower electrode being connected to the second doping region, The semiconductor memory device is characterized in that the support layer is installed between adjacent lower electrodes and is in direct contact with the side walls, top surface, and bottom surface of the lower electrodes.

2. The semiconductor memory device according to claim 1, characterized in that the lower electrode comprises a first side wall and a second side wall arranged opposite to each other, the first side wall in direct contact with the support layer and the second side wall in direct contact with the second doping region.

3. The semiconductor memory device according to claim 2, characterized in that the orthographic projections of the upper electrode and the lower electrode are both located within the contour of the corresponding surface of the support layer.

4. The semiconductor memory device according to any one of claims 1 to 3, further comprising a word line, wherein the word line extends along the vertical direction and is adjacent to the groove region.

5. The semiconductor further comprises an insulating layer and a dielectric layer, wherein the insulating layer is disposed between adjacent semiconductor layers. The semiconductor memory device according to any one of claims 1 to 3, characterized in that the dielectric layer is disposed between the lower electrode and the upper electrode, and between the support layer and the upper electrode, and the dielectric layer covers a portion of the surface of the lower electrode.

6. A semiconductor memory device comprising a substrate, multiple stacked structures, bit lines, capacitive structures, insulating layers, and support layers, The plurality of stacked structures are arranged on the substrate and are separated from each other in the vertical direction, and each stacked structure comprises a semiconductor layer, the semiconductor layer comprises a first doping region, a groove region and a second doping region, The bit line extends horizontally and is connected to the first doping area. The aforementioned capacitance structure comprises a lower electrode and an upper electrode that are stacked and installed, and the lower electrode is connected to the second doping region. The insulating layer is placed between adjacent capacitive structures. The semiconductor memory device is characterized in that the support layer is disposed between the insulating layers and is in direct contact with the side walls, top surface, and bottom surface of the insulating layers.

7. The semiconductor memory device according to claim 6, characterized in that the lower electrode comprises a first side wall and a second side wall arranged opposite to each other, the first side wall in direct contact with the support layer and the second side wall in direct contact with the second doping region.

8. The semiconductor memory device according to claim 7, characterized in that the orthographic projections of the upper electrode and the lower electrode are both located within the contour of the corresponding surface of the support layer.

9. The semiconductor memory device according to any one of claims 6-8, further comprising a word line, wherein the word line extends along the vertical direction and is adjacent to the groove region.

10. The semiconductor memory device according to any one of claims 6-8, characterized in that the bit line and the support layer are each arranged on opposite sides of the semiconductor layer.

11. The insulating layer is further disposed between adjacent semiconductor layers. The semiconductor memory device according to any one of claims 6-8, further comprising a dielectric layer, wherein the dielectric layer is disposed between the lower electrode and the upper electrode, and the lower electrode covers a portion of the surface of the insulating layer.

Images